msm_serial_hs_lite: Don't set UART clock to zero always
Setting UART clock rate to zero is causing multiple issues
and leading to more confusion with other stability issues.
Setting UART clock rate to zero is invalid operation on
recent platforms and throws multiple error messages. Hence
add platform data set_uart_clk_zero to enable setting uart
clock rate to zero operation on required platform for
specific use case.
Also set set_uart_clk_zero for GSBI9 shared between different
processor.
CRs-Fixed: 455466
Change-Id: Iba04d4cf094885b0eae6a9c49ed06f750bcc1024
Signed-off-by: Mayank Rana <mrana@codeaurora.org>
diff --git a/drivers/tty/serial/msm_serial_hs_lite.c b/drivers/tty/serial/msm_serial_hs_lite.c
index c9f4199..8069b35 100644
--- a/drivers/tty/serial/msm_serial_hs_lite.c
+++ b/drivers/tty/serial/msm_serial_hs_lite.c
@@ -2,7 +2,7 @@
* drivers/serial/msm_serial.c - driver for msm7k serial device and console
*
* Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2010-2012, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2010-2013, The Linux Foundation. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
@@ -1257,6 +1257,9 @@
{
int ret;
struct msm_hsl_port *msm_hsl_port = UART_TO_MSM(port);
+ struct platform_device *pdev = to_platform_device(port->dev);
+ const struct msm_serial_hslite_platform_data *pdata =
+ pdev->dev.platform_data;
switch (state) {
case 0:
@@ -1268,9 +1271,11 @@
break;
case 3:
clk_en(port, 0);
- ret = clk_set_rate(msm_hsl_port->clk, 0);
- if (ret)
- pr_err("Error setting UART clock rate to zero.\n");
+ if (pdata && pdata->set_uart_clk_zero) {
+ ret = clk_set_rate(msm_hsl_port->clk, 0);
+ if (ret)
+ pr_err("Error setting UART clock rate to zero.\n");
+ }
break;
default:
pr_err("Unknown PM state %d\n", state);