| commit | 9a561f74e89414fdb4bb2edfabf8ae308c3ff502 | [log] [tgz] |
|---|---|---|
| author | Matt Wagantall <mattw@codeaurora.org> | Thu Jan 19 16:13:12 2012 -0800 |
| committer | Matt Wagantall <mattw@codeaurora.org> | Thu Jan 26 19:17:10 2012 -0800 |
| tree | 422869809c036e7342566a4d4a012462162c179f | |
| parent | 76a59b96976dd70485ecf1e10f1d306b5ddb688c [diff] |
msm: clock: Respect voltage constraints for 9615 and 8960 UART dividers The 16-bit fractional dividers used for these clocks should have a clock rate no greater than 300MHz applied to their inputs when running in low voltage mode. Increase the pre-dividers for rates that previously violated this rule. Change-Id: Ia7177c8643f8c8051ec9cef6cedcb2a7051d936c Signed-off-by: Matt Wagantall <mattw@codeaurora.org>