Merge "msm: mdss: Add rotator sync point support in mdss"
diff --git a/Documentation/devicetree/bindings/fb/mdss-dsi-ctrl.txt b/Documentation/devicetree/bindings/fb/mdss-dsi-ctrl.txt
index 7187908..cda437a 100644
--- a/Documentation/devicetree/bindings/fb/mdss-dsi-ctrl.txt
+++ b/Documentation/devicetree/bindings/fb/mdss-dsi-ctrl.txt
@@ -46,12 +46,6 @@
- qcom,platform-te-gpio: Specifies the gpio used for TE.
- qcom,platform-mode-gpio: Select video/command mode of panel through gpio when it supports
both modes.
-- qcom,platform-reset-sequence: An array that lists the
- sequence of reset gpio values and sleeps
- Each command will have the format defined
- as below:
- --> Reset GPIO value
- --> Sleep value (in ms)
Example:
mdss_dsi0: qcom,mdss_dsi@fd922800 {
@@ -77,7 +71,6 @@
qcom,platform-te-gpio = <&msmgpio 24 0>;
qcom,platform-enable-gpio = <&msmgpio 58 1>;
qcom,platform-mode-gpio = <&msmgpio 7 0>;
- qcom,platform-reset-sequence = <1 25 0 20 1 10>;
qcom,platform-supply-entry1 {
qcom,supply-name = "vdd";
qcom,supply-min-voltage = <2800000>;
diff --git a/Documentation/devicetree/bindings/fb/mdss-dsi-panel.txt b/Documentation/devicetree/bindings/fb/mdss-dsi-panel.txt
index 9b30b39..1a44f5a 100644
--- a/Documentation/devicetree/bindings/fb/mdss-dsi-panel.txt
+++ b/Documentation/devicetree/bindings/fb/mdss-dsi-panel.txt
@@ -244,6 +244,13 @@
"low" = Set GPIO to LOW
- qcom,partial-update-enabled: Boolean used to enable partial
panel update for command mode panels.
+- qcom,mdss-dsi-reset-sequence: An array that lists the
+ sequence of reset gpio values and sleeps
+ Each command will have the format defined
+ as below:
+ --> Reset GPIO value
+ --> Sleep value (in ms)
+
Note, if a given optional qcom,* binding is not present, then the driver will configure
the default values specified.
@@ -335,5 +342,6 @@
qcom,mdss-pan-physical-height-dimension = <140>;
qcom,mdss-dsi-panel-mode-gpio-state = "low";
qcom,partial-update-enabled;
+ qcom,mdss-dsi-reset-sequence = <1 2>, <0 10>, <1 10>;
};
};
diff --git a/Documentation/devicetree/bindings/nfc/nfc-nci.txt b/Documentation/devicetree/bindings/nfc/nfc-nci.txt
index f70d90f..cdd1e68 100644
--- a/Documentation/devicetree/bindings/nfc/nfc-nci.txt
+++ b/Documentation/devicetree/bindings/nfc/nfc-nci.txt
@@ -8,6 +8,8 @@
- reg: NCI i2c slave address.
- qcom,dis-gpio: specific gpio for hardware reset.
- qcom,irq-gpio: specific gpio for read interrupt.
+- qcom,clk-src: nfc clock source ("BBCLK2", "RFCLK3", "GPCLK", ...)
+- qcom,clk-en-gpio: msm gpio clock,used ony if clock source is msm gpio
- interrupt-parent: Should be phandle for the interrupt controller
that services interrupts for this device.
- interrupts: should contain the NFC interrupt. NFC has one read interrupt.
@@ -21,6 +23,8 @@
reg = <0x0e>;
qcom,irq-gpio = <&msmgpio 21 0x00>;
qcom,dis-gpio = <&msmgpio 20 0x00>;
+ qcom,clk-src = "BBCLK2";
+ qcom,clk-en-gpio = <&msmgpio 0 0x00>;
interrupt-parent = <&msmgpio>;
interrupts = <21 0>;
qcom,clk-gpio = <&pm8226_gpios 3 0>;
diff --git a/Documentation/sysctl/kernel.txt b/Documentation/sysctl/kernel.txt
index a419f5e..8a20b47 100644
--- a/Documentation/sysctl/kernel.txt
+++ b/Documentation/sysctl/kernel.txt
@@ -26,6 +26,7 @@
- boot_reason [ ARM only ]
- callhome [ S390 only ]
- cap_last_cap
+- cold_boot [ ARM only ]
- core_pattern
- core_pipe_limit
- core_uses_pid
@@ -176,6 +177,16 @@
Highest valid capability of the running kernel. Exports
CAP_LAST_CAP from the kernel.
+===============================================================
+
+cold_boot
+
+ARM -- indicator for system cold boot
+
+A single bit will be set in the unsigned integer value to identify
+whether the device was booted from a cold or warm state. Zero
+indicating a warm boot and one indicating a cold boot.
+
==============================================================
core_pattern:
diff --git a/arch/arm/boot/dts/dsi-panel-generic-720p-cmd.dtsi b/arch/arm/boot/dts/dsi-panel-generic-720p-cmd.dtsi
index 23091f0..2963d15 100644
--- a/arch/arm/boot/dts/dsi-panel-generic-720p-cmd.dtsi
+++ b/arch/arm/boot/dts/dsi-panel-generic-720p-cmd.dtsi
@@ -76,5 +76,6 @@
qcom,mdss-dsi-dma-trigger = <4>;
qcom,mdss-dsi-mdp-trigger = <0>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm";
+ qcom,mdss-dsi-reset-sequence = <1 20>, <0 200>, <1 20>;
};
};
diff --git a/arch/arm/boot/dts/dsi-panel-hx8379a-wvga-video.dtsi b/arch/arm/boot/dts/dsi-panel-hx8379a-wvga-video.dtsi
index 4230018..23b65f3 100644
--- a/arch/arm/boot/dts/dsi-panel-hx8379a-wvga-video.dtsi
+++ b/arch/arm/boot/dts/dsi-panel-hx8379a-wvga-video.dtsi
@@ -118,6 +118,7 @@
qcom,mdss-dsi-dma-trigger = <4>;
qcom,mdss-dsi-mdp-trigger = <0>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-reset-sequence = <1 20>, <0 2>, <1 20>;
};
};
diff --git a/arch/arm/boot/dts/dsi-panel-hx8394a-720p-video.dtsi b/arch/arm/boot/dts/dsi-panel-hx8394a-720p-video.dtsi
index c9d887b..83351ca 100644
--- a/arch/arm/boot/dts/dsi-panel-hx8394a-720p-video.dtsi
+++ b/arch/arm/boot/dts/dsi-panel-hx8394a-720p-video.dtsi
@@ -78,6 +78,7 @@
qcom,mdss-dsi-dma-trigger = <4>;
qcom,mdss-dsi-mdp-trigger = <0>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-reset-sequence = <1 20>, <0 1>, <1 20>;
};
};
diff --git a/arch/arm/boot/dts/dsi-panel-nt35521-720p-video.dtsi b/arch/arm/boot/dts/dsi-panel-nt35521-720p-video.dtsi
index 829197a..9bb11da 100644
--- a/arch/arm/boot/dts/dsi-panel-nt35521-720p-video.dtsi
+++ b/arch/arm/boot/dts/dsi-panel-nt35521-720p-video.dtsi
@@ -268,6 +268,7 @@
qcom,mdss-dsi-dma-trigger = <4>;
qcom,mdss-dsi-mdp-trigger = <0>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-reset-sequence = <1 20>, <0 1>, <1 20>;
};
};
diff --git a/arch/arm/boot/dts/dsi-panel-nt35590-720p-cmd.dtsi b/arch/arm/boot/dts/dsi-panel-nt35590-720p-cmd.dtsi
index 0918cf4..a24cb58 100644
--- a/arch/arm/boot/dts/dsi-panel-nt35590-720p-cmd.dtsi
+++ b/arch/arm/boot/dts/dsi-panel-nt35590-720p-cmd.dtsi
@@ -531,6 +531,9 @@
qcom,mdss-dsi-dma-trigger = <4>;
qcom,mdss-dsi-mdp-trigger = <0>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-reset-sequence = <1 20>, <0 1>, <1 20>;
+ qcom,mdss-pan-physical-width-dimension = <59>;
+ qcom,mdss-pan-physical-height-dimension = <104>;
};
};
diff --git a/arch/arm/boot/dts/dsi-panel-nt35590-720p-video.dtsi b/arch/arm/boot/dts/dsi-panel-nt35590-720p-video.dtsi
index 6d68a3e..79618b9 100644
--- a/arch/arm/boot/dts/dsi-panel-nt35590-720p-video.dtsi
+++ b/arch/arm/boot/dts/dsi-panel-nt35590-720p-video.dtsi
@@ -527,6 +527,9 @@
qcom,mdss-dsi-dma-trigger = <4>;
qcom,mdss-dsi-mdp-trigger = <0>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-reset-sequence = <1 20>, <0 1>, <1 20>;
+ qcom,mdss-pan-physical-width-dimension = <59>;
+ qcom,mdss-pan-physical-height-dimension = <104>;
};
};
diff --git a/arch/arm/boot/dts/dsi-panel-nt35596-1080p-video.dtsi b/arch/arm/boot/dts/dsi-panel-nt35596-1080p-video.dtsi
index 49aef24..2312b37 100644
--- a/arch/arm/boot/dts/dsi-panel-nt35596-1080p-video.dtsi
+++ b/arch/arm/boot/dts/dsi-panel-nt35596-1080p-video.dtsi
@@ -582,6 +582,7 @@
qcom,mdss-dsi-dma-trigger = <4>;
qcom,mdss-dsi-mdp-trigger = <0>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-reset-sequence = <1 20>, <0 1>, <1 20>;
};
};
diff --git a/arch/arm/boot/dts/dsi-panel-otm8018b-fwvga-video.dtsi b/arch/arm/boot/dts/dsi-panel-otm8018b-fwvga-video.dtsi
index 89a5063..9477c56 100644
--- a/arch/arm/boot/dts/dsi-panel-otm8018b-fwvga-video.dtsi
+++ b/arch/arm/boot/dts/dsi-panel-otm8018b-fwvga-video.dtsi
@@ -261,6 +261,7 @@
qcom,mdss-dsi-dma-trigger = <4>;
qcom,mdss-dsi-mdp-trigger = <0>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-reset-sequence = <1 20>, <0 2>, <1 20>;
};
};
diff --git a/arch/arm/boot/dts/dsi-panel-sharp-qhd-video.dtsi b/arch/arm/boot/dts/dsi-panel-sharp-qhd-video.dtsi
index c627e7a..285d8fc 100644
--- a/arch/arm/boot/dts/dsi-panel-sharp-qhd-video.dtsi
+++ b/arch/arm/boot/dts/dsi-panel-sharp-qhd-video.dtsi
@@ -67,6 +67,7 @@
qcom,mdss-dsi-dma-trigger = <4>;
qcom,mdss-dsi-mdp-trigger = <4>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-reset-sequence = <1 20>, <0 200>, <1 20>;
};
};
diff --git a/arch/arm/boot/dts/dsi-panel-sim-video.dtsi b/arch/arm/boot/dts/dsi-panel-sim-video.dtsi
index ccbb659..501fdde 100644
--- a/arch/arm/boot/dts/dsi-panel-sim-video.dtsi
+++ b/arch/arm/boot/dts/dsi-panel-sim-video.dtsi
@@ -39,5 +39,6 @@
qcom,on-cmds-dsi-state = "DSI_LP_MODE";
qcom,panel-off-cmds = [22 01 00 00 00 00 02 00 00];
qcom,off-cmds-dsi-state = "DSI_LP_MODE";
+ qcom,mdss-dsi-reset-sequence = <1 20>, <0 200>, <1 20>;
};
};
diff --git a/arch/arm/boot/dts/dsi-panel-ssd2080m-720p-video.dtsi b/arch/arm/boot/dts/dsi-panel-ssd2080m-720p-video.dtsi
index 7bb414a..bb8389f 100644
--- a/arch/arm/boot/dts/dsi-panel-ssd2080m-720p-video.dtsi
+++ b/arch/arm/boot/dts/dsi-panel-ssd2080m-720p-video.dtsi
@@ -115,5 +115,6 @@
qcom,mdss-dsi-dma-trigger = <4>;
qcom,mdss-dsi-mdp-trigger = <0>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-reset-sequence = <1 20>, <0 1>, <1 20>;
};
};
diff --git a/arch/arm/boot/dts/dsi-panel-toshiba-720p-video.dtsi b/arch/arm/boot/dts/dsi-panel-toshiba-720p-video.dtsi
index 021ddef..f7de416 100644
--- a/arch/arm/boot/dts/dsi-panel-toshiba-720p-video.dtsi
+++ b/arch/arm/boot/dts/dsi-panel-toshiba-720p-video.dtsi
@@ -92,5 +92,6 @@
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
qcom,mdss-dsi-pan-enable-dynamic-fps;
qcom,mdss-dsi-pan-fps-update = "dfps_suspend_resume_mode";
+ qcom,mdss-dsi-reset-sequence = <1 20>, <0 200>, <1 20>;
};
};
diff --git a/arch/arm/boot/dts/dsi-panel-truly-wvga-cmd.dtsi b/arch/arm/boot/dts/dsi-panel-truly-wvga-cmd.dtsi
index f6e6df8..d170833 100644
--- a/arch/arm/boot/dts/dsi-panel-truly-wvga-cmd.dtsi
+++ b/arch/arm/boot/dts/dsi-panel-truly-wvga-cmd.dtsi
@@ -166,5 +166,6 @@
qcom,mdss-dsi-dma-trigger = <4>;
qcom,mdss-dsi-mdp-trigger = <2>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-reset-sequence = <1 20>, <0 2>, <1 20>;
};
};
diff --git a/arch/arm/boot/dts/dsi-panel-truly-wvga-video.dtsi b/arch/arm/boot/dts/dsi-panel-truly-wvga-video.dtsi
index fae4834..546a90f 100644
--- a/arch/arm/boot/dts/dsi-panel-truly-wvga-video.dtsi
+++ b/arch/arm/boot/dts/dsi-panel-truly-wvga-video.dtsi
@@ -164,5 +164,6 @@
qcom,mdss-dsi-dma-trigger = <4>;
qcom,mdss-dsi-mdp-trigger = <0>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-reset-sequence = <1 20>, <0 2>, <1 20>;
};
};
diff --git a/arch/arm/boot/dts/msm8226-mdss.dtsi b/arch/arm/boot/dts/msm8226-mdss.dtsi
index c7a4eee..d5c3811 100644
--- a/arch/arm/boot/dts/msm8226-mdss.dtsi
+++ b/arch/arm/boot/dts/msm8226-mdss.dtsi
@@ -78,7 +78,6 @@
00 00 00 00 0a 00 00 01 97
00 00 00 00 0f 00 00 01 97
00 c0 00 00 00 00 00 01 bb];
- qcom,platform-reset-sequence = <1 20 0 1 1 20>;
qcom,platform-supply-entry1 {
qcom,supply-name = "vdd";
qcom,supply-min-voltage = <2800000>;
diff --git a/arch/arm/boot/dts/msm8226-mtp.dtsi b/arch/arm/boot/dts/msm8226-mtp.dtsi
index 318d4fc..5d98271 100644
--- a/arch/arm/boot/dts/msm8226-mtp.dtsi
+++ b/arch/arm/boot/dts/msm8226-mtp.dtsi
@@ -40,6 +40,8 @@
reg = <0x0e>;
qcom,irq-gpio = <&msmgpio 21 0x00>;
qcom,dis-gpio = <&msmgpio 20 0x00>;
+ qcom,clk-src = "BBCLK2";
+ qcom,clk-en-gpio = <&msmgpio 0 0x00>;
interrupt-parent = <&msmgpio>;
interrupts = <21 0>;
qcom,clk-gpio = <&pm8226_gpios 3 0>;
diff --git a/arch/arm/boot/dts/msm8226-v1-pm.dtsi b/arch/arm/boot/dts/msm8226-v1-pm.dtsi
index dcf46e6..1530074 100644
--- a/arch/arm/boot/dts/msm8226-v1-pm.dtsi
+++ b/arch/arm/boot/dts/msm8226-v1-pm.dtsi
@@ -266,6 +266,7 @@
<38 108>,
<39 109>,
<40 110>,
+ <41 115>,
<54 111>,
<55 113>;
};
diff --git a/arch/arm/boot/dts/msm8226-v2-cdp.dts b/arch/arm/boot/dts/msm8226-v2-cdp.dts
index 3d40180..3302d26 100644
--- a/arch/arm/boot/dts/msm8226-v2-cdp.dts
+++ b/arch/arm/boot/dts/msm8226-v2-cdp.dts
@@ -20,3 +20,7 @@
compatible = "qcom,msm8226-cdp", "qcom,msm8226", "qcom,cdp";
qcom,board-id = <1 0>;
};
+
+&hsic_host {
+ status = "ok";
+};
diff --git a/arch/arm/boot/dts/msm8226-v2-pm.dtsi b/arch/arm/boot/dts/msm8226-v2-pm.dtsi
index 9ee47e2..9104cba 100644
--- a/arch/arm/boot/dts/msm8226-v2-pm.dtsi
+++ b/arch/arm/boot/dts/msm8226-v2-pm.dtsi
@@ -268,6 +268,7 @@
<38 108>,
<39 109>,
<40 110>,
+ <41 115>,
<54 111>,
<55 113>;
};
diff --git a/arch/arm/boot/dts/msm8226.dtsi b/arch/arm/boot/dts/msm8226.dtsi
index cfb6bed..852a71c 100644
--- a/arch/arm/boot/dts/msm8226.dtsi
+++ b/arch/arm/boot/dts/msm8226.dtsi
@@ -299,6 +299,37 @@
qcom,android-usb-swfi-latency = <1>;
};
+ hsic_host: hsic@f9a00000 {
+ status = "disabled";
+ compatible = "qcom,hsic-host";
+ reg = <0xf9a00000 0x400>;
+ #address-cells = <0>;
+ interrupt-parent = <&hsic_host>;
+ interrupts = <0 1 2>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xffffffff>;
+ interrupt-map = <0 &intc 0 136 0
+ 1 &intc 0 148 0
+ 2 &msmgpio 115 0x8>;
+ interrupt-names = "core_irq", "async_irq", "wakeup";
+ hsic_vdd_dig-supply = <&pm8226_s1_corner>;
+ HSIC_GDSC-supply = <&gdsc_usb_hsic>;
+ hsic,strobe-gpio = <&msmgpio 115 0x00>;
+ hsic,data-gpio = <&msmgpio 116 0x00>;
+ hsic,ignore-cal-pad-config;
+ hsic,strobe-pad-offset = <0x2050>;
+ hsic,data-pad-offset = <0x2054>;
+ qcom,phy-susp-sof-workaround;
+ hsic,vdd-voltage-level = <1 5 7>;
+
+ qcom,msm-bus,name = "hsic";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <85 512 0 0>,
+ <85 512 40000 160000>;
+ };
+
wcd9xxx_intc: wcd9xxx-irq {
compatible = "qcom,wcd9xxx-irq";
interrupt-controller;
diff --git a/arch/arm/boot/dts/msm8610-mdss.dtsi b/arch/arm/boot/dts/msm8610-mdss.dtsi
index de74e52..929659e 100644
--- a/arch/arm/boot/dts/msm8610-mdss.dtsi
+++ b/arch/arm/boot/dts/msm8610-mdss.dtsi
@@ -38,9 +38,6 @@
qcom,platform-reset-gpio = <&msmgpio 41 0>;
qcom,platform-te-gpio = <&msmgpio 12 0>;
qcom,platform-mode-gpio = <&msmgpio 7 0>;
-
- qcom,platform-reset-sequence = <1 20 0 2 1 20 2>;
-
qcom,platform-strength-ctrl = [ff 06];
qcom,platform-bist-ctrl = [03 03 00 00 0f 00];
qcom,platform-regulator-settings = [02 08 05 00 20 03];
diff --git a/arch/arm/boot/dts/msm8926-cdp.dts b/arch/arm/boot/dts/msm8926-cdp.dts
index 7d8d6cf..d6e70e6 100644
--- a/arch/arm/boot/dts/msm8926-cdp.dts
+++ b/arch/arm/boot/dts/msm8926-cdp.dts
@@ -32,3 +32,7 @@
};
};
+
+&hsic_host {
+ status = "ok";
+};
diff --git a/arch/arm/boot/dts/msm8926-qrd-skug.dts b/arch/arm/boot/dts/msm8926-qrd-skug.dts
index a366205..9a21aac 100644
--- a/arch/arm/boot/dts/msm8926-qrd-skug.dts
+++ b/arch/arm/boot/dts/msm8926-qrd-skug.dts
@@ -79,6 +79,23 @@
qcom,key-codes = <139 172 158>;
qcom,y-offset = <0>;
};
+
+ gpio-leds {
+ compatible = "gpio-leds";
+ keypad-backlight {
+ gpios = <&msmgpio 34 0>;
+ label = "button-backlight";
+ linux,default-trigger = "none";
+ };
+ };
+};
+
+&spmi_bus {
+ qcom,pm8226@0 {
+ qcom,leds@a100 {
+ status = "disable";
+ };
+ };
};
&mdss_dsi0 {
diff --git a/arch/arm/boot/dts/msm8926.dtsi b/arch/arm/boot/dts/msm8926.dtsi
index 2ab272a..2eaca4c 100644
--- a/arch/arm/boot/dts/msm8926.dtsi
+++ b/arch/arm/boot/dts/msm8926.dtsi
@@ -89,10 +89,18 @@
};
&msmgpio {
- ngpio = <120>;
+ ngpio = <121>;
};
&memory_hole {
qcom,memblock-remove = <0x08000000 0x7500000
0x0fa00000 0x500000>; /* Address and size of the hole */
};
+
+&hsic_host {
+ interrupt-map = <0 &intc 0 136 0
+ 1 &intc 0 148 0
+ 2 &msmgpio 119 0x8>;
+ hsic,strobe-gpio = <&msmgpio 119 0x00>;
+ hsic,data-gpio = <&msmgpio 120 0x00>;
+};
diff --git a/arch/arm/boot/dts/msm8974-mdss.dtsi b/arch/arm/boot/dts/msm8974-mdss.dtsi
index 7181db2..6d5000f 100644
--- a/arch/arm/boot/dts/msm8974-mdss.dtsi
+++ b/arch/arm/boot/dts/msm8974-mdss.dtsi
@@ -90,7 +90,6 @@
qcom,mdss-mdp = <&mdss_mdp>;
qcom,platform-reset-gpio = <&pm8941_gpios 19 0>;
qcom,platform-enable-gpio = <&msmgpio 58 0>;
- qcom,platform-reset-sequence = <1 20 0 200 1 20 2>;
qcom,platform-te-gpio = <&msmgpio 12 0>;
qcom,platform-strength-ctrl = [ff 06];
qcom,platform-bist-ctrl = [00 00 b1 ff 00 00];
diff --git a/arch/arm/boot/dts/msm8974pro-ab-mtp.dts b/arch/arm/boot/dts/msm8974pro-ab-mtp.dts
index 002baf7..f61b4a6 100644
--- a/arch/arm/boot/dts/msm8974pro-ab-mtp.dts
+++ b/arch/arm/boot/dts/msm8974pro-ab-mtp.dts
@@ -26,3 +26,7 @@
<217 8 0x10000>,
<218 8 0x10000>;
};
+
+&sdhc_1 {
+ qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */
+};
diff --git a/arch/arm/boot/dts/msm8974pro-ab.dtsi b/arch/arm/boot/dts/msm8974pro-ab.dtsi
index 5809069..0f37584 100644
--- a/arch/arm/boot/dts/msm8974pro-ab.dtsi
+++ b/arch/arm/boot/dts/msm8974pro-ab.dtsi
@@ -36,6 +36,22 @@
qcom,use-phase-switching;
};
+&krait0_vreg {
+ regulator-max-microvolt = <1120000>;
+};
+
+&krait1_vreg {
+ regulator-max-microvolt = <1120000>;
+};
+
+&krait2_vreg {
+ regulator-max-microvolt = <1120000>;
+};
+
+&krait3_vreg {
+ regulator-max-microvolt = <1120000>;
+};
+
&tspp {
vdd_cx-supply = <&pm8841_s2_corner>;
};
diff --git a/arch/arm/boot/dts/msm8974pro-ac-regulator.dtsi b/arch/arm/boot/dts/msm8974pro-ac-regulator.dtsi
index e0473b7..c38c9e1 100644
--- a/arch/arm/boot/dts/msm8974pro-ac-regulator.dtsi
+++ b/arch/arm/boot/dts/msm8974pro-ac-regulator.dtsi
@@ -488,7 +488,7 @@
<0xf908a800 0x1000>; /* APCS_ALIAS0_KPSS_MDD */
reg-names = "acs", "mdd";
regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1100000>;
+ regulator-max-microvolt = <1120000>;
qcom,headroom-voltage = <150000>;
qcom,retention-voltage = <675000>;
qcom,ldo-default-voltage = <750000>;
@@ -504,7 +504,7 @@
<0xf909a800 0x1000>; /* APCS_ALIAS1_KPSS_MDD */
reg-names = "acs", "mdd";
regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1100000>;
+ regulator-max-microvolt = <1120000>;
qcom,headroom-voltage = <150000>;
qcom,retention-voltage = <675000>;
qcom,ldo-default-voltage = <750000>;
@@ -520,7 +520,7 @@
<0xf90aa800 0x1000>; /* APCS_ALIAS2_KPSS_MDD */
reg-names = "acs", "mdd";
regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1100000>;
+ regulator-max-microvolt = <1120000>;
qcom,headroom-voltage = <150000>;
qcom,retention-voltage = <675000>;
qcom,ldo-default-voltage = <750000>;
@@ -536,7 +536,7 @@
<0xf90ba800 0x1000>; /* APCS_ALIAS3_KPSS_MDD */
reg-names = "acs", "mdd";
regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1100000>;
+ regulator-max-microvolt = <1120000>;
qcom,headroom-voltage = <150000>;
qcom,retention-voltage = <675000>;
qcom,ldo-default-voltage = <750000>;
diff --git a/arch/arm/configs/msm8226-perf_defconfig b/arch/arm/configs/msm8226-perf_defconfig
index f8369a9..b822288 100644
--- a/arch/arm/configs/msm8226-perf_defconfig
+++ b/arch/arm/configs/msm8226-perf_defconfig
@@ -387,6 +387,7 @@
CONFIG_MMC_MSM_SPS_SUPPORT=y
CONFIG_LEDS_QPNP=y
CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_GPIO=y
CONFIG_SWITCH=y
CONFIG_RTC_CLASS=y
# CONFIG_RTC_DRV_MSM is not set
diff --git a/arch/arm/configs/msm8226_defconfig b/arch/arm/configs/msm8226_defconfig
index 816b020..546b6b9 100644
--- a/arch/arm/configs/msm8226_defconfig
+++ b/arch/arm/configs/msm8226_defconfig
@@ -413,6 +413,7 @@
CONFIG_MMC_MSM_SPS_SUPPORT=y
CONFIG_LEDS_QPNP=y
CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_GPIO=y
CONFIG_SWITCH=y
CONFIG_RTC_CLASS=y
# CONFIG_RTC_DRV_MSM is not set
diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h
index 07209d7..3a2cd22 100644
--- a/arch/arm/include/asm/processor.h
+++ b/arch/arm/include/asm/processor.h
@@ -30,6 +30,7 @@
#endif
extern unsigned int boot_reason;
+extern unsigned int cold_boot;
struct debug_info {
#ifdef CONFIG_HAVE_HW_BREAKPOINT
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 28b114f..7298f9a 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -107,6 +107,9 @@
unsigned int boot_reason;
EXPORT_SYMBOL(boot_reason);
+unsigned int cold_boot;
+EXPORT_SYMBOL(cold_boot);
+
#ifdef MULTI_CPU
struct processor processor __read_mostly;
#endif
diff --git a/arch/arm/mach-msm/acpuclock-8974.c b/arch/arm/mach-msm/acpuclock-8974.c
index 8410019..3e488e3 100644
--- a/arch/arm/mach-msm/acpuclock-8974.c
+++ b/arch/arm/mach-msm/acpuclock-8974.c
@@ -899,7 +899,7 @@
{ 0, { 0 } }
};
-static struct acpu_level acpu_ftbl_pro_2p3g_pvs0[] __initdata = {
+static struct acpu_level pro_rev0_2p3g_pvs0[] __initdata = {
{ 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 72 },
{ 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 83 },
{ 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 101 },
@@ -930,38 +930,38 @@
{ 0, { 0 } }
};
-static struct acpu_level acpu_ftbl_pro_2p3g_pvs1[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 72},
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 83},
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 101},
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 120},
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 139},
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 785000, 159},
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 795000, 180},
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 805000, 200},
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 815000, 221},
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 825000, 242},
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 835000, 264},
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 850000, 287},
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 860000, 308},
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 870000, 333},
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 885000, 356},
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 895000, 380},
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 905000, 404},
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 920000, 430},
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 935000, 456},
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 950000, 482},
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 965000, 510},
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 980000, 538},
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 995000, 565},
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1005000, 596},
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1020000, 627},
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1035000, 659},
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1050000, 691},
+static struct acpu_level pro_rev0_2p3g_pvs1[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 72 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 83 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 101 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 120 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 139 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 785000, 159 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 795000, 180 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 805000, 200 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 815000, 221 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 825000, 242 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 835000, 264 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 850000, 287 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 860000, 308 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 870000, 333 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 885000, 356 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 895000, 380 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 905000, 404 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 920000, 430 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 935000, 456 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 950000, 482 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 965000, 510 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 980000, 538 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 995000, 565 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1005000, 596 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1020000, 627 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1035000, 659 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1050000, 691 },
{ 0, { 0 } }
};
-static struct acpu_level acpu_ftbl_pro_2p3g_pvs2[] __initdata = {
+static struct acpu_level pro_rev0_2p3g_pvs2[] __initdata = {
{ 1, { 300000, PLL_0, 0, 0 }, L2(0), 750000, 72 },
{ 0, { 345600, HFPLL, 2, 36 }, L2(1), 750000, 83 },
{ 1, { 422400, HFPLL, 2, 44 }, L2(2), 750000, 101 },
@@ -992,449 +992,1525 @@
{ 0, { 0 } }
};
-static struct acpu_level acpu_ftbl_pro_2p3g_pvs3[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 750000, 72},
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 750000, 83},
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 750000, 101},
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 750000, 120},
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 750000, 139},
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 755000, 159},
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 765000, 180},
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 775000, 200},
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 785000, 221},
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 795000, 242},
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 805000, 264},
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 815000, 287},
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 825000, 308},
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 835000, 333},
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 850000, 356},
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 860000, 380},
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 870000, 404},
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 885000, 430},
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 900000, 456},
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 910000, 482},
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 925000, 510},
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 935000, 538},
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 945000, 565},
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 960000, 596},
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 970000, 627},
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 985000, 659},
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1000000, 691},
+static struct acpu_level pro_rev0_2p3g_pvs3[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 750000, 72 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 750000, 83 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 750000, 101 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 750000, 120 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 750000, 139 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 755000, 159 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 765000, 180 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 775000, 200 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 785000, 221 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 795000, 242 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 805000, 264 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 815000, 287 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 825000, 308 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 835000, 333 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 850000, 356 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 860000, 380 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 870000, 404 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 885000, 430 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 900000, 456 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 910000, 482 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 925000, 510 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 935000, 538 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 945000, 565 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 960000, 596 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 970000, 627 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 985000, 659 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1000000, 691 },
{ 0, { 0 } }
};
-static struct acpu_level acpu_ftbl_pro_2p3g_pvs4[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 750000, 72},
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 750000, 83},
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 750000, 101},
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 750000, 120},
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 750000, 139},
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 750000, 159},
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 755000, 180},
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 765000, 200},
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 775000, 221},
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 785000, 242},
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 795000, 264},
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 805000, 287},
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 815000, 308},
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 825000, 333},
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 835000, 356},
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 845000, 380},
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 855000, 404},
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 870000, 430},
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 885000, 456},
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 895000, 482},
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 905000, 510},
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 915000, 538},
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 925000, 565},
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 935000, 596},
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 950000, 627},
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 960000, 659},
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 975000, 691},
+static struct acpu_level pro_rev0_2p3g_pvs4[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 750000, 72 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 750000, 83 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 750000, 101 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 750000, 120 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 750000, 139 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 750000, 159 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 755000, 180 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 765000, 200 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 775000, 221 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 785000, 242 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 795000, 264 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 805000, 287 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 815000, 308 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 825000, 333 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 835000, 356 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 845000, 380 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 855000, 404 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 870000, 430 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 885000, 456 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 895000, 482 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 905000, 510 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 915000, 538 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 925000, 565 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 935000, 596 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 950000, 627 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 960000, 659 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 975000, 691 },
{ 0, { 0 } }
};
-static struct acpu_level acpu_ftbl_pro_2p3g_pvs5[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 725000, 72},
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 725000, 83},
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 725000, 101},
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 725000, 120},
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 725000, 139},
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 735000, 159},
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 745000, 180},
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 755000, 200},
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 765000, 221},
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 775000, 242},
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 785000, 264},
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 795000, 287},
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 805000, 308},
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 815000, 333},
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 825000, 356},
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 835000, 380},
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 845000, 404},
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 855000, 430},
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 865000, 456},
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 875000, 482},
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 885000, 510},
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 895000, 538},
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 905000, 565},
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 915000, 596},
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 930000, 627},
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 940000, 659},
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 950000, 691},
+static struct acpu_level pro_rev0_2p3g_pvs5[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 725000, 72 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 725000, 83 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 725000, 101 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 725000, 120 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 725000, 139 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 735000, 159 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 745000, 180 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 755000, 200 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 765000, 221 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 775000, 242 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 785000, 264 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 795000, 287 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 805000, 308 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 815000, 333 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 825000, 356 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 835000, 380 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 845000, 404 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 855000, 430 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 865000, 456 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 875000, 482 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 885000, 510 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 895000, 538 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 905000, 565 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 915000, 596 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 930000, 627 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 940000, 659 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 950000, 691 },
{ 0, { 0 } }
};
-static struct acpu_level acpu_ftbl_pro_2p3g_pvs6[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 725000, 72},
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 725000, 83},
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 725000, 101},
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 725000, 120},
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 725000, 139},
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 725000, 159},
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 735000, 180},
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 745000, 200},
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 755000, 221},
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 765000, 242},
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 775000, 264},
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 785000, 287},
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 795000, 308},
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 805000, 333},
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 815000, 356},
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 825000, 380},
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 835000, 404},
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 845000, 430},
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 850000, 456},
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 860000, 482},
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 870000, 510},
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 880000, 538},
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 890000, 565},
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 895000, 596},
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 905000, 627},
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 915000, 659},
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 925000, 691},
+static struct acpu_level pro_rev0_2p3g_pvs6[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 725000, 72 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 725000, 83 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 725000, 101 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 725000, 120 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 725000, 139 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 725000, 159 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 735000, 180 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 745000, 200 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 755000, 221 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 765000, 242 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 775000, 264 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 785000, 287 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 795000, 308 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 805000, 333 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 815000, 356 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 825000, 380 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 835000, 404 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 845000, 430 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 850000, 456 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 860000, 482 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 870000, 510 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 880000, 538 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 890000, 565 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 895000, 596 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 905000, 627 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 915000, 659 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 925000, 691 },
{ 0, { 0 } }
};
-static struct acpu_level acpu_ftbl_pro_2p5g_pvs0[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 800000, 76},
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 800000, 87},
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 800000, 106},
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 800000, 125},
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 800000, 145},
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 800000, 164},
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 800000, 183},
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 800000, 202},
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 800000, 222},
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 800000, 241},
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 805000, 261},
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 815000, 282},
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 825000, 305},
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 835000, 327},
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 845000, 350},
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 855000, 373},
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 870000, 398},
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 885000, 424},
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 900000, 449},
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 915000, 476},
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 930000, 503},
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 945000, 530},
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 960000, 559},
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 980000, 590},
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1000000, 621},
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1020000, 654},
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1040000, 686},
- { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1060000, 723},
- { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 1080000, 761},
- { 1, { 2496000, HFPLL, 1, 130 }, L2(19), 1100000, 800},
+static struct acpu_level pro_rev0_2p5g_pvs0[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 800000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 800000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 800000, 106 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 800000, 125 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 800000, 145 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 800000, 164 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 800000, 183 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 800000, 202 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 800000, 222 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 800000, 241 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 805000, 261 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 815000, 282 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 825000, 305 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 835000, 327 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 845000, 350 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 855000, 373 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 870000, 398 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 885000, 424 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 900000, 449 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 915000, 476 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 930000, 503 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 945000, 530 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 960000, 559 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 980000, 590 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1000000, 621 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1020000, 654 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1040000, 686 },
+ { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1060000, 723 },
+ { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 1080000, 761 },
+ { 1, { 2496000, HFPLL, 1, 130 }, L2(19), 1100000, 800 },
{ 0, { 0 } }
};
-static struct acpu_level acpu_ftbl_pro_2p5g_pvs1[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 800000, 76},
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 800000, 87},
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 800000, 106},
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 800000, 125},
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 800000, 145},
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 800000, 164},
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 800000, 183},
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 800000, 202},
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 800000, 222},
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 800000, 241},
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 800000, 261},
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 805000, 282},
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 815000, 305},
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 825000, 327},
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 835000, 350},
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 845000, 373},
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 855000, 398},
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 870000, 424},
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 885000, 449},
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 900000, 476},
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 915000, 503},
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 930000, 530},
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 945000, 559},
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 960000, 590},
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 975000, 621},
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 995000, 654},
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1015000, 686},
- { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1035000, 723},
- { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 1055000, 761},
- { 1, { 2496000, HFPLL, 1, 130 }, L2(19), 1075000, 800},
+static struct acpu_level pro_rev0_2p5g_pvs1[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 800000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 800000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 800000, 106 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 800000, 125 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 800000, 145 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 800000, 164 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 800000, 183 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 800000, 202 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 800000, 222 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 800000, 241 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 800000, 261 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 805000, 282 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 815000, 305 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 825000, 327 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 835000, 350 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 845000, 373 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 855000, 398 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 870000, 424 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 885000, 449 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 900000, 476 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 915000, 503 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 930000, 530 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 945000, 559 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 960000, 590 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 975000, 621 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 995000, 654 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1015000, 686 },
+ { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1035000, 723 },
+ { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 1055000, 761 },
+ { 1, { 2496000, HFPLL, 1, 130 }, L2(19), 1075000, 800 },
{ 0, { 0 } }
};
-static struct acpu_level acpu_ftbl_pro_2p5g_pvs2[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 76},
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 87},
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 106},
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 125},
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 145},
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 775000, 164},
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 775000, 183},
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 775000, 202},
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 775000, 222},
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 775000, 241},
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 780000, 261},
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 790000, 282},
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 800000, 305},
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 810000, 327},
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 820000, 350},
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 830000, 373},
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 840000, 398},
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 850000, 424},
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 865000, 449},
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 880000, 476},
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 895000, 503},
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 910000, 530},
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 925000, 559},
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 940000, 590},
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 955000, 621},
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 970000, 654},
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 990000, 686},
- { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1010000, 723},
- { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 1030000, 761},
- { 1, { 2496000, HFPLL, 1, 130 }, L2(19), 1050000, 800},
+static struct acpu_level pro_rev0_2p5g_pvs2[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 106 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 125 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 145 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 775000, 164 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 775000, 183 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 775000, 202 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 775000, 222 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 775000, 241 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 780000, 261 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 790000, 282 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 800000, 305 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 810000, 327 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 820000, 350 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 830000, 373 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 840000, 398 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 850000, 424 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 865000, 449 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 880000, 476 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 895000, 503 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 910000, 530 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 925000, 559 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 940000, 590 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 955000, 621 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 970000, 654 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 990000, 686 },
+ { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1010000, 723 },
+ { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 1030000, 761 },
+ { 1, { 2496000, HFPLL, 1, 130 }, L2(19), 1050000, 800 },
{ 0, { 0 } }
};
-static struct acpu_level acpu_ftbl_pro_2p5g_pvs3[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 76},
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 87},
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 106},
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 125},
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 145},
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 775000, 164},
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 775000, 183},
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 775000, 202},
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 775000, 222},
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 775000, 241},
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 775000, 261},
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 780000, 282},
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 790000, 305},
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 800000, 327},
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 810000, 350},
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 820000, 373},
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 830000, 398},
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 840000, 424},
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 850000, 449},
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 865000, 476},
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 880000, 503},
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 895000, 530},
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 910000, 559},
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 925000, 590},
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 940000, 621},
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 955000, 654},
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 970000, 686},
- { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 985000, 723},
- { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 1005000, 761},
- { 1, { 2496000, HFPLL, 1, 130 }, L2(19), 1025000, 800},
+static struct acpu_level pro_rev0_2p5g_pvs3[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 106 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 125 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 145 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 775000, 164 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 775000, 183 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 775000, 202 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 775000, 222 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 775000, 241 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 775000, 261 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 780000, 282 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 790000, 305 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 800000, 327 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 810000, 350 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 820000, 373 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 830000, 398 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 840000, 424 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 850000, 449 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 865000, 476 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 880000, 503 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 895000, 530 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 910000, 559 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 925000, 590 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 940000, 621 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 955000, 654 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 970000, 686 },
+ { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 985000, 723 },
+ { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 1005000, 761 },
+ { 1, { 2496000, HFPLL, 1, 130 }, L2(19), 1025000, 800 },
{ 0, { 0 } }
};
-static struct acpu_level acpu_ftbl_pro_2p5g_pvs4[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 750000, 76},
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 750000, 87},
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 750000, 106},
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 750000, 125},
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 750000, 145},
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 750000, 164},
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 750000, 183},
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 750000, 202},
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 750000, 222},
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 750000, 241},
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 760000, 261},
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 770000, 282},
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 780000, 305},
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 790000, 327},
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 800000, 350},
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 810000, 373},
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 820000, 398},
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 830000, 424},
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 840000, 449},
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 850000, 476},
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 865000, 503},
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 880000, 530},
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 895000, 559},
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 910000, 590},
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 925000, 621},
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 940000, 654},
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 955000, 686},
- { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 970000, 723},
- { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 985000, 761},
- { 1, { 2496000, HFPLL, 1, 130 }, L2(19), 1000000, 800},
+static struct acpu_level pro_rev0_2p5g_pvs4[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 750000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 750000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 750000, 106 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 750000, 125 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 750000, 145 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 750000, 164 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 750000, 183 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 750000, 202 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 750000, 222 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 750000, 241 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 760000, 261 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 770000, 282 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 780000, 305 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 790000, 327 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 800000, 350 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 810000, 373 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 820000, 398 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 830000, 424 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 840000, 449 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 850000, 476 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 865000, 503 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 880000, 530 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 895000, 559 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 910000, 590 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 925000, 621 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 940000, 654 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 955000, 686 },
+ { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 970000, 723 },
+ { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 985000, 761 },
+ { 1, { 2496000, HFPLL, 1, 130 }, L2(19), 1000000, 800 },
{ 0, { 0 } }
};
-static struct acpu_level acpu_ftbl_pro_2p5g_pvs5[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 750000, 76},
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 750000, 87},
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 750000, 106},
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 750000, 125},
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 750000, 145},
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 750000, 164},
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 750000, 183},
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 750000, 202},
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 750000, 222},
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 750000, 241},
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 750000, 261},
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 760000, 282},
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 770000, 305},
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 780000, 327},
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 790000, 350},
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 800000, 373},
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 810000, 398},
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 820000, 424},
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 830000, 449},
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 840000, 476},
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 850000, 503},
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 860000, 530},
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 870000, 559},
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 885000, 590},
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 900000, 621},
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 915000, 654},
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 930000, 686},
- { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 945000, 723},
- { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 960000, 761},
- { 1, { 2496000, HFPLL, 1, 130 }, L2(19), 975000, 800},
+static struct acpu_level pro_rev0_2p5g_pvs5[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 750000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 750000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 750000, 106 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 750000, 125 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 750000, 145 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 750000, 164 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 750000, 183 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 750000, 202 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 750000, 222 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 750000, 241 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 750000, 261 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 760000, 282 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 770000, 305 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 780000, 327 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 790000, 350 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 800000, 373 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 810000, 398 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 820000, 424 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 830000, 449 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 840000, 476 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 850000, 503 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 860000, 530 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 870000, 559 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 885000, 590 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 900000, 621 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 915000, 654 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 930000, 686 },
+ { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 945000, 723 },
+ { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 960000, 761 },
+ { 1, { 2496000, HFPLL, 1, 130 }, L2(19), 975000, 800 },
{ 0, { 0 } }
};
-static struct acpu_level acpu_ftbl_pro_2p5g_pvs6[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 725000, 76},
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 725000, 87},
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 725000, 106},
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 725000, 125},
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 725000, 145},
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 725000, 164},
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 725000, 183},
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 725000, 202},
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 725000, 222},
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 725000, 241},
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 735000, 261},
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 745000, 282},
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 755000, 305},
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 765000, 327},
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 775000, 350},
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 785000, 373},
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 795000, 398},
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 805000, 424},
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 815000, 449},
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 825000, 476},
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 835000, 503},
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 845000, 530},
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 855000, 559},
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 865000, 590},
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 875000, 621},
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 890000, 654},
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 905000, 686},
- { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 920000, 723},
- { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 935000, 761},
- { 1, { 2496000, HFPLL, 1, 130 }, L2(19), 950000, 800},
+static struct acpu_level pro_rev0_2p5g_pvs6[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 725000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 725000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 725000, 106 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 725000, 125 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 725000, 145 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 725000, 164 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 725000, 183 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 725000, 202 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 725000, 222 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 725000, 241 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 735000, 261 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 745000, 282 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 755000, 305 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 765000, 327 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 775000, 350 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 785000, 373 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 795000, 398 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 805000, 424 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 815000, 449 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 825000, 476 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 835000, 503 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 845000, 530 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 855000, 559 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 865000, 590 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 875000, 621 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 890000, 654 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 905000, 686 },
+ { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 920000, 723 },
+ { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 935000, 761 },
+ { 1, { 2496000, HFPLL, 1, 130 }, L2(19), 950000, 800 },
{ 0, { 0 } }
};
-static struct pvs_table pvs_v1[NUM_SPEED_BINS][NUM_PVS] __initdata = {
+static struct acpu_level pro_rev1_2p5g_pvs0[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 800000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 800000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 800000, 106 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 810000, 126 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 820000, 147 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 830000, 168 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 840000, 189 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 850000, 211 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 860000, 233 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 870000, 256 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 880000, 278 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 890000, 301 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 900000, 324 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 910000, 348 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 920000, 372 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 930000, 396 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 940000, 421 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 950000, 446 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 965000, 473 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 980000, 501 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 995000, 529 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 1010000, 558 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1025000, 588 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1040000, 617 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1055000, 649 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1070000, 682 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1085000, 716 },
+ { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1100000, 751 },
+ { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 1115000, 786 },
+ { 1, { 2457600, HFPLL, 1, 128 }, L2(19), 1120000, 802 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level pro_rev1_2p5g_pvs1[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 800000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 800000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 800000, 106 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 800000, 126 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 810000, 147 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 820000, 168 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 830000, 189 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 840000, 211 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 850000, 233 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 860000, 256 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 870000, 278 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 880000, 301 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 890000, 324 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 900000, 348 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 910000, 372 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 920000, 396 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 930000, 421 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 940000, 446 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 955000, 473 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 970000, 501 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 985000, 529 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 1000000, 558 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1015000, 588 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1030000, 617 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1045000, 649 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1060000, 682 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1075000, 716 },
+ { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1090000, 751 },
+ { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 1105000, 786 },
+ { 1, { 2457600, HFPLL, 1, 128 }, L2(19), 1110000, 802 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level pro_rev1_2p5g_pvs2[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 800000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 800000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 800000, 106 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 800000, 126 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 800000, 147 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 810000, 168 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 820000, 189 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 830000, 211 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 840000, 233 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 850000, 256 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 860000, 278 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 870000, 301 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 880000, 324 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 890000, 348 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 900000, 372 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 910000, 396 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 920000, 421 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 930000, 446 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 945000, 473 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 960000, 501 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 975000, 529 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 990000, 558 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1005000, 588 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1020000, 617 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1035000, 649 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1050000, 682 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1065000, 716 },
+ { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1080000, 751 },
+ { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 1095000, 786 },
+ { 1, { 2457600, HFPLL, 1, 128 }, L2(19), 1100000, 802 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level pro_rev1_2p5g_pvs3[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 800000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 800000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 800000, 106 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 800000, 126 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 800000, 147 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 800000, 168 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 810000, 189 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 820000, 211 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 830000, 233 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 840000, 256 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 850000, 278 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 860000, 301 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 870000, 324 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 880000, 348 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 890000, 372 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 900000, 396 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 910000, 421 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 920000, 446 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 935000, 473 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 950000, 501 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 965000, 529 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 980000, 558 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 995000, 588 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1010000, 617 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1025000, 649 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1040000, 682 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1055000, 716 },
+ { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1070000, 751 },
+ { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 1085000, 786 },
+ { 1, { 2457600, HFPLL, 1, 128 }, L2(19), 1090000, 802 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level pro_rev1_2p5g_pvs4[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 800000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 800000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 800000, 106 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 800000, 126 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 800000, 147 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 800000, 168 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 800000, 189 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 810000, 211 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 820000, 233 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 830000, 256 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 840000, 278 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 850000, 301 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 860000, 324 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 870000, 348 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 880000, 372 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 890000, 396 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 900000, 421 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 910000, 446 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 925000, 473 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 940000, 501 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 955000, 529 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 970000, 558 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 985000, 588 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1000000, 617 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1015000, 649 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1030000, 682 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1045000, 716 },
+ { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1060000, 751 },
+ { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 1075000, 786 },
+ { 1, { 2457600, HFPLL, 1, 128 }, L2(19), 1080000, 802 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level pro_rev1_2p5g_pvs5[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 800000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 800000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 800000, 106 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 800000, 126 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 800000, 147 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 800000, 168 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 800000, 189 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 800000, 211 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 810000, 233 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 820000, 256 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 830000, 278 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 840000, 301 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 850000, 324 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 860000, 348 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 870000, 372 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 880000, 396 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 890000, 421 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 900000, 446 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 915000, 473 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 930000, 501 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 945000, 529 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 960000, 558 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 975000, 588 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 990000, 617 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1005000, 649 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1020000, 682 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1035000, 716 },
+ { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1050000, 751 },
+ { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 1065000, 786 },
+ { 1, { 2457600, HFPLL, 1, 128 }, L2(19), 1070000, 802 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level pro_rev1_2p5g_pvs6[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 106 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 126 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 147 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 775000, 168 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 780000, 189 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 790000, 211 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 800000, 233 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 810000, 256 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 820000, 278 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 830000, 301 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 840000, 324 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 850000, 348 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 860000, 372 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 870000, 396 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 880000, 421 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 890000, 446 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 905000, 473 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 920000, 501 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 935000, 529 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 950000, 558 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 965000, 588 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 980000, 617 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 995000, 649 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1010000, 682 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1025000, 716 },
+ { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1040000, 751 },
+ { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 1055000, 786 },
+ { 1, { 2457600, HFPLL, 1, 128 }, L2(19), 1060000, 802 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level pro_rev1_2p5g_pvs7[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 106 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 126 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 147 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 775000, 168 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 775000, 189 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 780000, 211 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 790000, 233 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 800000, 256 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 810000, 278 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 820000, 301 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 830000, 324 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 840000, 348 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 850000, 372 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 860000, 396 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 870000, 421 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 880000, 446 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 895000, 473 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 910000, 501 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 925000, 529 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 940000, 558 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 955000, 588 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 970000, 617 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 985000, 649 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1000000, 682 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1015000, 716 },
+ { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1030000, 751 },
+ { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 1045000, 786 },
+ { 1, { 2457600, HFPLL, 1, 128 }, L2(19), 1050000, 802 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level pro_rev1_2p5g_pvs8[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 106 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 126 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 147 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 775000, 168 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 775000, 189 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 775000, 211 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 780000, 233 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 790000, 256 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 800000, 278 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 810000, 301 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 820000, 324 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 830000, 348 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 840000, 372 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 850000, 396 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 860000, 421 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 870000, 446 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 885000, 473 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 900000, 501 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 915000, 529 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 930000, 558 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 945000, 588 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 960000, 617 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 975000, 649 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 990000, 682 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1005000, 716 },
+ { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1020000, 751 },
+ { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 1035000, 786 },
+ { 1, { 2457600, HFPLL, 1, 128 }, L2(19), 1040000, 802 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level pro_rev1_2p5g_pvs9[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 106 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 126 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 147 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 775000, 168 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 775000, 189 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 775000, 211 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 775000, 233 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 780000, 256 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 790000, 278 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 800000, 301 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 810000, 324 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 820000, 348 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 830000, 372 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 840000, 396 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 850000, 421 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 860000, 446 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 875000, 473 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 890000, 501 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 905000, 529 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 920000, 558 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 935000, 588 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 950000, 617 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 965000, 649 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 980000, 682 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 995000, 716 },
+ { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1010000, 751 },
+ { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 1025000, 786 },
+ { 1, { 2457600, HFPLL, 1, 128 }, L2(19), 1030000, 802 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level pro_rev1_2p5g_pvs10[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 106 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 126 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 147 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 775000, 168 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 775000, 189 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 775000, 211 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 775000, 233 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 775000, 256 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 780000, 278 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 790000, 301 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 800000, 324 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 810000, 348 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 820000, 372 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 830000, 396 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 840000, 421 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 850000, 446 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 865000, 473 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 880000, 501 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 895000, 529 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 910000, 558 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 925000, 588 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 940000, 617 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 955000, 649 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 970000, 682 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 985000, 716 },
+ { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1000000, 751 },
+ { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 1015000, 786 },
+ { 1, { 2457600, HFPLL, 1, 128 }, L2(19), 1020000, 802 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level pro_rev1_2p5g_pvs11[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 106 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 126 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 147 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 775000, 168 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 775000, 189 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 775000, 211 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 775000, 233 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 775000, 256 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 775000, 278 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 780000, 301 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 790000, 324 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 800000, 348 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 810000, 372 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 820000, 396 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 830000, 421 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 840000, 446 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 855000, 473 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 870000, 501 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 885000, 529 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 900000, 558 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 915000, 588 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 930000, 617 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 945000, 649 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 960000, 682 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 975000, 716 },
+ { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 990000, 751 },
+ { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 1005000, 786 },
+ { 1, { 2457600, HFPLL, 1, 128 }, L2(19), 1010000, 802 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level pro_rev1_2p5g_pvs12[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 106 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 126 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 147 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 775000, 168 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 775000, 189 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 775000, 211 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 775000, 233 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 775000, 256 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 775000, 278 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 775000, 301 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 780000, 324 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 790000, 348 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 800000, 372 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 810000, 396 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 820000, 421 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 830000, 446 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 845000, 473 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 860000, 501 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 875000, 529 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 890000, 558 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 905000, 588 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 920000, 617 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 935000, 649 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 950000, 682 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 965000, 716 },
+ { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 980000, 751 },
+ { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 995000, 786 },
+ { 1, { 2457600, HFPLL, 1, 128 }, L2(19), 1000000, 802 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level pro_rev1_2p5g_pvs13[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 106 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 126 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 147 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 775000, 168 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 775000, 189 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 775000, 211 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 775000, 233 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 775000, 256 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 775000, 278 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 775000, 301 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 775000, 324 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 780000, 348 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 790000, 372 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 800000, 396 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 810000, 421 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 820000, 446 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 835000, 473 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 850000, 501 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 865000, 529 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 880000, 558 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 895000, 588 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 910000, 617 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 925000, 649 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 940000, 682 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 955000, 716 },
+ { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 970000, 751 },
+ { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 985000, 786 },
+ { 1, { 2457600, HFPLL, 1, 128 }, L2(19), 990000, 802 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level pro_rev1_2p5g_pvs14[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 750000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 750000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 750000, 106 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 750000, 126 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 750000, 147 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 750000, 168 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 750000, 189 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 750000, 211 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 750000, 233 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 750000, 256 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 750000, 278 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 750000, 301 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 760000, 324 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 770000, 348 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 780000, 372 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 790000, 396 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 800000, 421 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 810000, 446 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 825000, 473 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 840000, 501 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 855000, 529 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 870000, 558 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 885000, 588 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 900000, 617 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 915000, 649 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 930000, 682 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 945000, 716 },
+ { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 960000, 751 },
+ { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 975000, 786 },
+ { 1, { 2457600, HFPLL, 1, 128 }, L2(19), 980000, 802 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level pro_rev1_2p5g_pvs15[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 750000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 750000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 750000, 106 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 750000, 126 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 750000, 147 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 750000, 168 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 750000, 189 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 750000, 211 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 750000, 233 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 750000, 256 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 750000, 278 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 750000, 301 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 750000, 324 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 760000, 348 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 770000, 372 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 780000, 396 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 790000, 421 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 800000, 446 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 815000, 473 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 830000, 501 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 845000, 529 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 860000, 558 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 875000, 588 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 890000, 617 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 905000, 649 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 920000, 682 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 935000, 716 },
+ { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 950000, 751 },
+ { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 965000, 786 },
+ { 1, { 2457600, HFPLL, 1, 128 }, L2(19), 970000, 802 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level pro_rev1_2p3g_pvs0[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 800000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 810000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 820000, 108 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 830000, 129 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 840000, 150 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 850000, 171 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 860000, 193 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 870000, 215 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 880000, 237 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 890000, 260 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 900000, 282 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 910000, 306 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 920000, 330 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 930000, 354 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 940000, 378 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 955000, 404 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 970000, 431 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 985000, 458 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 1000000, 486 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 1015000, 515 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 1030000, 543 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 1045000, 572 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1060000, 604 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1075000, 636 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1090000, 669 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1105000, 703 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1120000, 738 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level pro_rev1_2p3g_pvs1[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 800000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 800000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 810000, 108 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 820000, 129 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 830000, 150 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 840000, 171 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 850000, 193 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 860000, 215 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 870000, 237 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 880000, 260 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 890000, 282 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 900000, 306 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 910000, 330 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 920000, 354 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 930000, 378 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 945000, 404 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 960000, 431 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 975000, 458 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 990000, 486 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 1005000, 515 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 1020000, 543 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 1035000, 572 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1050000, 604 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1065000, 636 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1080000, 669 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1095000, 703 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1110000, 738 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level pro_rev1_2p3g_pvs2[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 800000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 800000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 800000, 108 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 810000, 129 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 820000, 150 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 830000, 171 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 840000, 193 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 850000, 215 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 860000, 237 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 870000, 260 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 880000, 282 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 890000, 306 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 900000, 330 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 910000, 354 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 920000, 378 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 935000, 404 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 950000, 431 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 965000, 458 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 980000, 486 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 995000, 515 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 1010000, 543 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 1025000, 572 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1040000, 604 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1055000, 636 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1070000, 669 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1085000, 703 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1100000, 738 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level pro_rev1_2p3g_pvs3[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 800000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 800000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 800000, 108 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 800000, 129 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 810000, 150 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 820000, 171 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 830000, 193 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 840000, 215 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 850000, 237 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 860000, 260 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 870000, 282 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 880000, 306 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 890000, 330 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 900000, 354 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 910000, 378 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 925000, 404 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 940000, 431 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 955000, 458 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 970000, 486 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 985000, 515 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 1000000, 543 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 1015000, 572 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1030000, 604 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1045000, 636 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1060000, 669 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1075000, 703 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1090000, 738 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level pro_rev1_2p3g_pvs4[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 800000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 800000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 800000, 108 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 800000, 129 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 800000, 150 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 810000, 171 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 820000, 193 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 830000, 215 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 840000, 237 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 850000, 260 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 860000, 282 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 870000, 306 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 880000, 330 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 890000, 354 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 900000, 378 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 915000, 404 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 930000, 431 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 945000, 458 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 960000, 486 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 975000, 515 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 990000, 543 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 1005000, 572 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1020000, 604 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1035000, 636 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1050000, 669 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1065000, 703 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1080000, 738 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level pro_rev1_2p3g_pvs5[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 800000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 800000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 800000, 108 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 800000, 129 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 800000, 150 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 800000, 171 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 810000, 193 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 820000, 215 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 830000, 237 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 840000, 260 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 850000, 282 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 860000, 306 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 870000, 330 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 880000, 354 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 890000, 378 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 905000, 404 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 920000, 431 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 935000, 458 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 950000, 486 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 965000, 515 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 980000, 543 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 995000, 572 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1010000, 604 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1025000, 636 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1040000, 669 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1055000, 703 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1070000, 738 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level pro_rev1_2p3g_pvs6[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 108 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 129 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 780000, 150 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 790000, 171 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 800000, 193 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 810000, 215 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 820000, 237 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 830000, 260 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 840000, 282 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 850000, 306 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 860000, 330 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 870000, 354 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 880000, 378 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 895000, 404 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 910000, 431 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 925000, 458 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 940000, 486 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 955000, 515 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 970000, 543 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 985000, 572 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1000000, 604 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1015000, 636 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1030000, 669 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1045000, 703 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1060000, 738 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level pro_rev1_2p3g_pvs7[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 108 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 129 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 150 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 780000, 171 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 790000, 193 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 800000, 215 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 810000, 237 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 820000, 260 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 830000, 282 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 840000, 306 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 850000, 330 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 860000, 354 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 870000, 378 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 885000, 404 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 900000, 431 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 915000, 458 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 930000, 486 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 945000, 515 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 960000, 543 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 975000, 572 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 990000, 604 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1005000, 636 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1020000, 669 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1035000, 703 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1050000, 738 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level pro_rev1_2p3g_pvs8[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 108 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 129 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 150 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 775000, 171 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 780000, 193 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 790000, 215 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 800000, 237 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 810000, 260 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 820000, 282 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 830000, 306 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 840000, 330 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 850000, 354 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 860000, 378 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 875000, 404 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 890000, 431 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 905000, 458 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 920000, 486 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 935000, 515 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 950000, 543 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 965000, 572 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 980000, 604 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 995000, 636 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1010000, 669 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1025000, 703 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1040000, 738 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level pro_rev1_2p3g_pvs9[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 108 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 129 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 150 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 775000, 171 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 775000, 193 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 780000, 215 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 790000, 237 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 800000, 260 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 810000, 282 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 820000, 306 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 830000, 330 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 840000, 354 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 850000, 378 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 865000, 404 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 880000, 431 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 895000, 458 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 910000, 486 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 925000, 515 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 940000, 543 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 955000, 572 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 970000, 604 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 985000, 636 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1000000, 669 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1015000, 703 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1030000, 738 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level pro_rev1_2p3g_pvs10[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 108 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 129 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 150 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 775000, 171 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 775000, 193 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 775000, 215 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 780000, 237 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 790000, 260 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 800000, 282 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 810000, 306 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 820000, 330 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 830000, 354 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 840000, 378 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 855000, 404 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 870000, 431 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 885000, 458 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 900000, 486 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 915000, 515 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 930000, 543 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 945000, 572 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 960000, 604 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 975000, 636 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 990000, 669 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1005000, 703 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1020000, 738 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level pro_rev1_2p3g_pvs11[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 108 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 129 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 150 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 775000, 171 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 775000, 193 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 775000, 215 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 775000, 237 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 780000, 260 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 790000, 282 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 800000, 306 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 810000, 330 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 820000, 354 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 830000, 378 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 845000, 404 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 860000, 431 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 875000, 458 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 890000, 486 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 905000, 515 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 920000, 543 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 935000, 572 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 950000, 604 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 965000, 636 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 980000, 669 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 995000, 703 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1010000, 738 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level pro_rev1_2p3g_pvs12[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 108 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 129 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 150 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 775000, 171 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 775000, 193 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 775000, 215 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 775000, 237 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 775000, 260 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 780000, 282 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 790000, 306 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 800000, 330 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 810000, 354 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 820000, 378 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 835000, 404 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 850000, 431 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 865000, 458 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 880000, 486 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 895000, 515 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 910000, 543 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 925000, 572 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 940000, 604 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 955000, 636 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 970000, 669 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 985000, 703 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1000000, 738 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level pro_rev1_2p3g_pvs13[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 108 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 129 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 150 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 775000, 171 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 775000, 193 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 775000, 215 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 775000, 237 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 775000, 260 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 775000, 282 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 780000, 306 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 790000, 330 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 800000, 354 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 810000, 378 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 825000, 404 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 840000, 431 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 855000, 458 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 870000, 486 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 885000, 515 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 900000, 543 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 915000, 572 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 930000, 604 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 945000, 636 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 960000, 669 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 975000, 703 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 990000, 738 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level pro_rev1_2p3g_pvs14[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 750000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 750000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 750000, 108 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 750000, 129 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 750000, 150 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 750000, 171 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 750000, 193 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 750000, 215 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 750000, 237 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 750000, 260 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 760000, 282 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 770000, 306 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 780000, 330 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 790000, 354 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 800000, 378 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 815000, 404 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 830000, 431 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 845000, 458 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 860000, 486 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 875000, 515 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 890000, 543 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 905000, 572 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 920000, 604 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 935000, 636 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 950000, 669 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 965000, 703 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 980000, 738 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level pro_rev1_2p3g_pvs15[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 750000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 750000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 750000, 108 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 750000, 129 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 750000, 150 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 750000, 171 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 750000, 193 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 750000, 215 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 750000, 237 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 750000, 260 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 750000, 282 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 760000, 306 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 770000, 330 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 780000, 354 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 790000, 378 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 805000, 404 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 820000, 431 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 835000, 458 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 850000, 486 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 865000, 515 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 880000, 543 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 895000, 572 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 910000, 604 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 925000, 636 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 940000, 669 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 955000, 703 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 970000, 738 },
+ { 0, { 0 } }
+};
+
+static struct pvs_table pvs_v1[NUM_PVS_REVS][NUM_SPEED_BINS][NUM_PVS] __initdata = {
/* 8974v1 1.7GHz Parts */
- [0][0] = { acpu_freq_tbl_v1_pvs0, sizeof(acpu_freq_tbl_v1_pvs0) },
- [0][1] = { acpu_freq_tbl_v1_pvs1, sizeof(acpu_freq_tbl_v1_pvs1) },
- [0][2] = { acpu_freq_tbl_v1_pvs2, sizeof(acpu_freq_tbl_v1_pvs2) },
- [0][3] = { acpu_freq_tbl_v1_pvs3, sizeof(acpu_freq_tbl_v1_pvs3) },
- [0][4] = { acpu_freq_tbl_v1_pvs4, sizeof(acpu_freq_tbl_v1_pvs4) },
+ [0][0][0] = { acpu_freq_tbl_v1_pvs0, sizeof(acpu_freq_tbl_v1_pvs0) },
+ [0][0][1] = { acpu_freq_tbl_v1_pvs1, sizeof(acpu_freq_tbl_v1_pvs1) },
+ [0][0][2] = { acpu_freq_tbl_v1_pvs2, sizeof(acpu_freq_tbl_v1_pvs2) },
+ [0][0][3] = { acpu_freq_tbl_v1_pvs3, sizeof(acpu_freq_tbl_v1_pvs3) },
+ [0][0][4] = { acpu_freq_tbl_v1_pvs4, sizeof(acpu_freq_tbl_v1_pvs4) },
};
-static struct pvs_table pvs_v2[NUM_SPEED_BINS][NUM_PVS] __initdata = {
+static struct pvs_table pvs_v2[NUM_PVS_REVS][NUM_SPEED_BINS][NUM_PVS] __initdata = {
/* 8974v2 2.0GHz Parts */
- [0][0] = { acpu_freq_tbl_2g_pvs0, sizeof(acpu_freq_tbl_2g_pvs0) },
- [0][1] = { acpu_freq_tbl_2g_pvs1, sizeof(acpu_freq_tbl_2g_pvs1) },
- [0][2] = { acpu_freq_tbl_2g_pvs2, sizeof(acpu_freq_tbl_2g_pvs2) },
- [0][3] = { acpu_freq_tbl_2g_pvs3, sizeof(acpu_freq_tbl_2g_pvs3) },
- [0][4] = { acpu_freq_tbl_2g_pvs4, sizeof(acpu_freq_tbl_2g_pvs4) },
- [0][5] = { acpu_freq_tbl_2g_pvs5, sizeof(acpu_freq_tbl_2g_pvs5) },
- [0][6] = { acpu_freq_tbl_2g_pvs6, sizeof(acpu_freq_tbl_2g_pvs6) },
- [0][7] = { acpu_freq_tbl_2g_pvs6, sizeof(acpu_freq_tbl_2g_pvs6) },
+ [0][0][0] = { acpu_freq_tbl_2g_pvs0, sizeof(acpu_freq_tbl_2g_pvs0) },
+ [0][0][1] = { acpu_freq_tbl_2g_pvs1, sizeof(acpu_freq_tbl_2g_pvs1) },
+ [0][0][2] = { acpu_freq_tbl_2g_pvs2, sizeof(acpu_freq_tbl_2g_pvs2) },
+ [0][0][3] = { acpu_freq_tbl_2g_pvs3, sizeof(acpu_freq_tbl_2g_pvs3) },
+ [0][0][4] = { acpu_freq_tbl_2g_pvs4, sizeof(acpu_freq_tbl_2g_pvs4) },
+ [0][0][5] = { acpu_freq_tbl_2g_pvs5, sizeof(acpu_freq_tbl_2g_pvs5) },
+ [0][0][6] = { acpu_freq_tbl_2g_pvs6, sizeof(acpu_freq_tbl_2g_pvs6) },
+ [0][0][7] = { acpu_freq_tbl_2g_pvs6, sizeof(acpu_freq_tbl_2g_pvs6) },
/* 8974v2 2.3GHz Parts */
- [1][0] = { acpu_freq_tbl_2p3g_pvs0, sizeof(acpu_freq_tbl_2p3g_pvs0) },
- [1][1] = { acpu_freq_tbl_2p3g_pvs1, sizeof(acpu_freq_tbl_2p3g_pvs1) },
- [1][2] = { acpu_freq_tbl_2p3g_pvs2, sizeof(acpu_freq_tbl_2p3g_pvs2) },
- [1][3] = { acpu_freq_tbl_2p3g_pvs3, sizeof(acpu_freq_tbl_2p3g_pvs3) },
- [1][4] = { acpu_freq_tbl_2p3g_pvs4, sizeof(acpu_freq_tbl_2p3g_pvs4) },
- [1][5] = { acpu_freq_tbl_2p3g_pvs5, sizeof(acpu_freq_tbl_2p3g_pvs5) },
- [1][6] = { acpu_freq_tbl_2p3g_pvs6, sizeof(acpu_freq_tbl_2p3g_pvs6) },
- [1][7] = { acpu_freq_tbl_2p3g_pvs6, sizeof(acpu_freq_tbl_2p3g_pvs6) },
+ [0][1][0] = { acpu_freq_tbl_2p3g_pvs0, sizeof(acpu_freq_tbl_2p3g_pvs0) },
+ [0][1][1] = { acpu_freq_tbl_2p3g_pvs1, sizeof(acpu_freq_tbl_2p3g_pvs1) },
+ [0][1][2] = { acpu_freq_tbl_2p3g_pvs2, sizeof(acpu_freq_tbl_2p3g_pvs2) },
+ [0][1][3] = { acpu_freq_tbl_2p3g_pvs3, sizeof(acpu_freq_tbl_2p3g_pvs3) },
+ [0][1][4] = { acpu_freq_tbl_2p3g_pvs4, sizeof(acpu_freq_tbl_2p3g_pvs4) },
+ [0][1][5] = { acpu_freq_tbl_2p3g_pvs5, sizeof(acpu_freq_tbl_2p3g_pvs5) },
+ [0][1][6] = { acpu_freq_tbl_2p3g_pvs6, sizeof(acpu_freq_tbl_2p3g_pvs6) },
+ [0][1][7] = { acpu_freq_tbl_2p3g_pvs6, sizeof(acpu_freq_tbl_2p3g_pvs6) },
/* 8974v2 2.2GHz Parts */
- [2][0] = { acpu_freq_tbl_2p2g_pvs0, sizeof(acpu_freq_tbl_2p2g_pvs0) },
- [2][1] = { acpu_freq_tbl_2p2g_pvs1, sizeof(acpu_freq_tbl_2p2g_pvs1) },
- [2][2] = { acpu_freq_tbl_2p2g_pvs2, sizeof(acpu_freq_tbl_2p2g_pvs2) },
- [2][3] = { acpu_freq_tbl_2p2g_pvs3, sizeof(acpu_freq_tbl_2p2g_pvs3) },
- [2][4] = { acpu_freq_tbl_2p2g_pvs4, sizeof(acpu_freq_tbl_2p2g_pvs4) },
- [2][5] = { acpu_freq_tbl_2p2g_pvs5, sizeof(acpu_freq_tbl_2p2g_pvs5) },
- [2][6] = { acpu_freq_tbl_2p2g_pvs6, sizeof(acpu_freq_tbl_2p2g_pvs6) },
- [2][7] = { acpu_freq_tbl_2p2g_pvs6, sizeof(acpu_freq_tbl_2p2g_pvs6) },
+ [0][2][0] = { acpu_freq_tbl_2p2g_pvs0, sizeof(acpu_freq_tbl_2p2g_pvs0) },
+ [0][2][1] = { acpu_freq_tbl_2p2g_pvs1, sizeof(acpu_freq_tbl_2p2g_pvs1) },
+ [0][2][2] = { acpu_freq_tbl_2p2g_pvs2, sizeof(acpu_freq_tbl_2p2g_pvs2) },
+ [0][2][3] = { acpu_freq_tbl_2p2g_pvs3, sizeof(acpu_freq_tbl_2p2g_pvs3) },
+ [0][2][4] = { acpu_freq_tbl_2p2g_pvs4, sizeof(acpu_freq_tbl_2p2g_pvs4) },
+ [0][2][5] = { acpu_freq_tbl_2p2g_pvs5, sizeof(acpu_freq_tbl_2p2g_pvs5) },
+ [0][2][6] = { acpu_freq_tbl_2p2g_pvs6, sizeof(acpu_freq_tbl_2p2g_pvs6) },
+ [0][2][7] = { acpu_freq_tbl_2p2g_pvs6, sizeof(acpu_freq_tbl_2p2g_pvs6) },
};
-static struct pvs_table pvs_pro[NUM_SPEED_BINS][NUM_PVS] __initdata = {
+static struct pvs_table pvs_pro[NUM_PVS_REVS][NUM_SPEED_BINS][NUM_PVS] __initdata = {
/* 2.0 GHz is not used on 8974Pro */
- [0][0] = { acpu_freq_tbl_2g_pvs0, sizeof(acpu_freq_tbl_2g_pvs0) },
- [0][1] = { acpu_freq_tbl_2g_pvs1, sizeof(acpu_freq_tbl_2g_pvs1) },
- [0][2] = { acpu_freq_tbl_2g_pvs2, sizeof(acpu_freq_tbl_2g_pvs2) },
- [0][3] = { acpu_freq_tbl_2g_pvs3, sizeof(acpu_freq_tbl_2g_pvs3) },
- [0][4] = { acpu_freq_tbl_2g_pvs4, sizeof(acpu_freq_tbl_2g_pvs4) },
- [0][5] = { acpu_freq_tbl_2g_pvs5, sizeof(acpu_freq_tbl_2g_pvs5) },
- [0][6] = { acpu_freq_tbl_2g_pvs6, sizeof(acpu_freq_tbl_2g_pvs6) },
- [0][7] = { acpu_freq_tbl_2g_pvs6, sizeof(acpu_freq_tbl_2g_pvs6) },
+ [0][0][0] = { acpu_freq_tbl_2g_pvs0, sizeof(acpu_freq_tbl_2g_pvs0) },
+ [0][0][1] = { acpu_freq_tbl_2g_pvs1, sizeof(acpu_freq_tbl_2g_pvs1) },
+ [0][0][2] = { acpu_freq_tbl_2g_pvs2, sizeof(acpu_freq_tbl_2g_pvs2) },
+ [0][0][3] = { acpu_freq_tbl_2g_pvs3, sizeof(acpu_freq_tbl_2g_pvs3) },
+ [0][0][4] = { acpu_freq_tbl_2g_pvs4, sizeof(acpu_freq_tbl_2g_pvs4) },
+ [0][0][5] = { acpu_freq_tbl_2g_pvs5, sizeof(acpu_freq_tbl_2g_pvs5) },
+ [0][0][6] = { acpu_freq_tbl_2g_pvs6, sizeof(acpu_freq_tbl_2g_pvs6) },
+ [0][0][7] = { acpu_freq_tbl_2g_pvs6, sizeof(acpu_freq_tbl_2g_pvs6) },
/* 8974Pro AB 2.3GHz */
- [1][0] = { acpu_ftbl_pro_2p3g_pvs0, sizeof(acpu_ftbl_pro_2p3g_pvs0) },
- [1][1] = { acpu_ftbl_pro_2p3g_pvs1, sizeof(acpu_ftbl_pro_2p3g_pvs1) },
- [1][2] = { acpu_ftbl_pro_2p3g_pvs2, sizeof(acpu_ftbl_pro_2p3g_pvs2) },
- [1][3] = { acpu_ftbl_pro_2p3g_pvs3, sizeof(acpu_ftbl_pro_2p3g_pvs3) },
- [1][4] = { acpu_ftbl_pro_2p3g_pvs4, sizeof(acpu_ftbl_pro_2p3g_pvs4) },
- [1][5] = { acpu_ftbl_pro_2p3g_pvs5, sizeof(acpu_ftbl_pro_2p3g_pvs5) },
- [1][6] = { acpu_ftbl_pro_2p3g_pvs6, sizeof(acpu_ftbl_pro_2p3g_pvs6) },
- [1][7] = { acpu_ftbl_pro_2p3g_pvs6, sizeof(acpu_ftbl_pro_2p3g_pvs6) },
+ [0][1][0] = { pro_rev0_2p3g_pvs0, sizeof(pro_rev0_2p3g_pvs0) },
+ [0][1][1] = { pro_rev0_2p3g_pvs1, sizeof(pro_rev0_2p3g_pvs1) },
+ [0][1][2] = { pro_rev0_2p3g_pvs2, sizeof(pro_rev0_2p3g_pvs2) },
+ [0][1][3] = { pro_rev0_2p3g_pvs3, sizeof(pro_rev0_2p3g_pvs3) },
+ [0][1][4] = { pro_rev0_2p3g_pvs4, sizeof(pro_rev0_2p3g_pvs4) },
+ [0][1][5] = { pro_rev0_2p3g_pvs5, sizeof(pro_rev0_2p3g_pvs5) },
+ [0][1][6] = { pro_rev0_2p3g_pvs6, sizeof(pro_rev0_2p3g_pvs6) },
+ [0][1][7] = { pro_rev0_2p3g_pvs6, sizeof(pro_rev0_2p3g_pvs6) },
/* 2.2GHz is not used on 8974Pro */
- [2][0] = { acpu_freq_tbl_2p2g_pvs0, sizeof(acpu_freq_tbl_2p2g_pvs0) },
- [2][1] = { acpu_freq_tbl_2p2g_pvs1, sizeof(acpu_freq_tbl_2p2g_pvs1) },
- [2][2] = { acpu_freq_tbl_2p2g_pvs2, sizeof(acpu_freq_tbl_2p2g_pvs2) },
- [2][3] = { acpu_freq_tbl_2p2g_pvs3, sizeof(acpu_freq_tbl_2p2g_pvs3) },
- [2][4] = { acpu_freq_tbl_2p2g_pvs4, sizeof(acpu_freq_tbl_2p2g_pvs4) },
- [2][5] = { acpu_freq_tbl_2p2g_pvs5, sizeof(acpu_freq_tbl_2p2g_pvs5) },
- [2][6] = { acpu_freq_tbl_2p2g_pvs6, sizeof(acpu_freq_tbl_2p2g_pvs6) },
- [2][7] = { acpu_freq_tbl_2p2g_pvs6, sizeof(acpu_freq_tbl_2p2g_pvs6) },
+ [0][2][0] = { acpu_freq_tbl_2p2g_pvs0, sizeof(acpu_freq_tbl_2p2g_pvs0) },
+ [0][2][1] = { acpu_freq_tbl_2p2g_pvs1, sizeof(acpu_freq_tbl_2p2g_pvs1) },
+ [0][2][2] = { acpu_freq_tbl_2p2g_pvs2, sizeof(acpu_freq_tbl_2p2g_pvs2) },
+ [0][2][3] = { acpu_freq_tbl_2p2g_pvs3, sizeof(acpu_freq_tbl_2p2g_pvs3) },
+ [0][2][4] = { acpu_freq_tbl_2p2g_pvs4, sizeof(acpu_freq_tbl_2p2g_pvs4) },
+ [0][2][5] = { acpu_freq_tbl_2p2g_pvs5, sizeof(acpu_freq_tbl_2p2g_pvs5) },
+ [0][2][6] = { acpu_freq_tbl_2p2g_pvs6, sizeof(acpu_freq_tbl_2p2g_pvs6) },
+ [0][2][7] = { acpu_freq_tbl_2p2g_pvs6, sizeof(acpu_freq_tbl_2p2g_pvs6) },
/* 8974Pro AC 2.5GHz */
- [3][0] = { acpu_ftbl_pro_2p5g_pvs0, sizeof(acpu_ftbl_pro_2p5g_pvs0) },
- [3][1] = { acpu_ftbl_pro_2p5g_pvs1, sizeof(acpu_ftbl_pro_2p5g_pvs1) },
- [3][2] = { acpu_ftbl_pro_2p5g_pvs2, sizeof(acpu_ftbl_pro_2p5g_pvs2) },
- [3][3] = { acpu_ftbl_pro_2p5g_pvs3, sizeof(acpu_ftbl_pro_2p5g_pvs3) },
- [3][4] = { acpu_ftbl_pro_2p5g_pvs4, sizeof(acpu_ftbl_pro_2p5g_pvs4) },
- [3][5] = { acpu_ftbl_pro_2p5g_pvs5, sizeof(acpu_ftbl_pro_2p5g_pvs5) },
- [3][6] = { acpu_ftbl_pro_2p5g_pvs6, sizeof(acpu_ftbl_pro_2p5g_pvs6) },
- [3][7] = { acpu_ftbl_pro_2p5g_pvs6, sizeof(acpu_ftbl_pro_2p5g_pvs6) },
+ [0][3][0] = { pro_rev0_2p5g_pvs0, sizeof(pro_rev0_2p5g_pvs0) },
+ [0][3][1] = { pro_rev0_2p5g_pvs1, sizeof(pro_rev0_2p5g_pvs1) },
+ [0][3][2] = { pro_rev0_2p5g_pvs2, sizeof(pro_rev0_2p5g_pvs2) },
+ [0][3][3] = { pro_rev0_2p5g_pvs3, sizeof(pro_rev0_2p5g_pvs3) },
+ [0][3][4] = { pro_rev0_2p5g_pvs4, sizeof(pro_rev0_2p5g_pvs4) },
+ [0][3][5] = { pro_rev0_2p5g_pvs5, sizeof(pro_rev0_2p5g_pvs5) },
+ [0][3][6] = { pro_rev0_2p5g_pvs6, sizeof(pro_rev0_2p5g_pvs6) },
+ [0][3][7] = { pro_rev0_2p5g_pvs6, sizeof(pro_rev0_2p5g_pvs6) },
+
+ /* 8974Pro AB 2.3GHz */
+ [1][1][0] = { pro_rev1_2p3g_pvs0, sizeof(pro_rev1_2p3g_pvs0) },
+ [1][1][1] = { pro_rev1_2p3g_pvs1, sizeof(pro_rev1_2p3g_pvs1) },
+ [1][1][2] = { pro_rev1_2p3g_pvs2, sizeof(pro_rev1_2p3g_pvs2) },
+ [1][1][3] = { pro_rev1_2p3g_pvs3, sizeof(pro_rev1_2p3g_pvs3) },
+ [1][1][4] = { pro_rev1_2p3g_pvs4, sizeof(pro_rev1_2p3g_pvs4) },
+ [1][1][5] = { pro_rev1_2p3g_pvs5, sizeof(pro_rev1_2p3g_pvs5) },
+ [1][1][6] = { pro_rev1_2p3g_pvs6, sizeof(pro_rev1_2p3g_pvs6) },
+ [1][1][7] = { pro_rev1_2p3g_pvs7, sizeof(pro_rev1_2p3g_pvs7) },
+ [1][1][8] = { pro_rev1_2p3g_pvs8, sizeof(pro_rev1_2p3g_pvs8) },
+ [1][1][9] = { pro_rev1_2p3g_pvs9, sizeof(pro_rev1_2p3g_pvs9) },
+ [1][1][10] = { pro_rev1_2p3g_pvs10, sizeof(pro_rev1_2p3g_pvs10) },
+ [1][1][11] = { pro_rev1_2p3g_pvs11, sizeof(pro_rev1_2p3g_pvs11) },
+ [1][1][12] = { pro_rev1_2p3g_pvs12, sizeof(pro_rev1_2p3g_pvs12) },
+ [1][1][13] = { pro_rev1_2p3g_pvs13, sizeof(pro_rev1_2p3g_pvs13) },
+ [1][1][14] = { pro_rev1_2p3g_pvs14, sizeof(pro_rev1_2p3g_pvs14) },
+ [1][1][15] = { pro_rev1_2p3g_pvs15, sizeof(pro_rev1_2p3g_pvs15) },
+
+ /* 8974Pro AC 2.5GHz */
+ [1][3][0] = { pro_rev1_2p5g_pvs0, sizeof(pro_rev1_2p5g_pvs0) },
+ [1][3][1] = { pro_rev1_2p5g_pvs1, sizeof(pro_rev1_2p5g_pvs1) },
+ [1][3][2] = { pro_rev1_2p5g_pvs2, sizeof(pro_rev1_2p5g_pvs2) },
+ [1][3][3] = { pro_rev1_2p5g_pvs3, sizeof(pro_rev1_2p5g_pvs3) },
+ [1][3][4] = { pro_rev1_2p5g_pvs4, sizeof(pro_rev1_2p5g_pvs4) },
+ [1][3][5] = { pro_rev1_2p5g_pvs5, sizeof(pro_rev1_2p5g_pvs5) },
+ [1][3][6] = { pro_rev1_2p5g_pvs6, sizeof(pro_rev1_2p5g_pvs6) },
+ [1][3][7] = { pro_rev1_2p5g_pvs7, sizeof(pro_rev1_2p5g_pvs7) },
+ [1][3][8] = { pro_rev1_2p5g_pvs8, sizeof(pro_rev1_2p5g_pvs8) },
+ [1][3][9] = { pro_rev1_2p5g_pvs9, sizeof(pro_rev1_2p5g_pvs9) },
+ [1][3][10] = { pro_rev1_2p5g_pvs10, sizeof(pro_rev1_2p5g_pvs10) },
+ [1][3][11] = { pro_rev1_2p5g_pvs11, sizeof(pro_rev1_2p5g_pvs11) },
+ [1][3][12] = { pro_rev1_2p5g_pvs12, sizeof(pro_rev1_2p5g_pvs12) },
+ [1][3][13] = { pro_rev1_2p5g_pvs13, sizeof(pro_rev1_2p5g_pvs13) },
+ [1][3][14] = { pro_rev1_2p5g_pvs14, sizeof(pro_rev1_2p5g_pvs14) },
+ [1][3][15] = { pro_rev1_2p5g_pvs15, sizeof(pro_rev1_2p5g_pvs15) },
};
static struct msm_bus_scale_pdata bus_scale_data __initdata = {
@@ -1470,12 +2546,15 @@
{ }
};
struct acpu_level *l;
- int s, p;
+ int s, p, r;
- for (s = 0; s < NUM_SPEED_BINS; s++)
- for (p = 0; p < NUM_PVS; p++)
- for (l = pvs_v1[s][p].table; l && l->speed.khz; l++)
- l->l2_level = l->l2_level > 5 ? 1 : 0;
+ for (r = 0; r < NUM_PVS_REVS; r++)
+ for (s = 0; s < NUM_SPEED_BINS; s++)
+ for (p = 0; p < NUM_PVS; p++) {
+ l = pvs_v1[r][s][p].table;
+ for (; l && l->speed.khz; l++)
+ l->l2_level = l->l2_level > 5 ? 1 : 0;
+ }
acpuclk_8974_params.l2_freq_tbl = resticted_l2_tbl;
acpuclk_8974_params.l2_freq_tbl_size = sizeof(resticted_l2_tbl);
diff --git a/arch/arm/mach-msm/acpuclock-krait.c b/arch/arm/mach-msm/acpuclock-krait.c
index 0479844..cf3fac0 100644
--- a/arch/arm/mach-msm/acpuclock-krait.c
+++ b/arch/arm/mach-msm/acpuclock-krait.c
@@ -1092,15 +1092,17 @@
pte_efuse = readl_relaxed(base);
redundant_sel = (pte_efuse >> 24) & 0x7;
+ bin->pvs_rev = (pte_efuse >> 4) & 0x3;
bin->speed = pte_efuse & 0x7;
- bin->pvs = (pte_efuse >> 6) & 0x7;
+ /* PVS number is in bits 31, 8, 7, 6 */
+ bin->pvs = ((pte_efuse >> 28) & 0x8) | ((pte_efuse >> 6) & 0x7);
switch (redundant_sel) {
case 1:
- bin->speed = (pte_efuse >> 27) & 0x7;
+ bin->speed = (pte_efuse >> 27) & 0xF;
break;
case 2:
- bin->pvs = (pte_efuse >> 27) & 0x7;
+ bin->pvs = (pte_efuse >> 27) & 0xF;
break;
}
bin->speed_valid = true;
@@ -1136,13 +1138,15 @@
if (bin.pvs_valid) {
drv.pvs_bin = bin.pvs;
dev_info(drv.dev, "ACPU PVS: %d\n", drv.pvs_bin);
+ drv.pvs_rev = bin.pvs_rev;
+ dev_info(drv.dev, "ACPU PVS REVISION: %d\n", drv.pvs_rev);
} else {
drv.pvs_bin = 0;
dev_warn(drv.dev, "ACPU PVS: Defaulting to %d\n",
drv.pvs_bin);
}
- return ¶ms->pvs_tables[drv.speed_bin][drv.pvs_bin];
+ return ¶ms->pvs_tables[drv.pvs_rev][drv.speed_bin][drv.pvs_bin];
}
static void __init drv_data_init(struct device *dev,
diff --git a/arch/arm/mach-msm/acpuclock-krait.h b/arch/arm/mach-msm/acpuclock-krait.h
index f02af98..4eff45d 100644
--- a/arch/arm/mach-msm/acpuclock-krait.h
+++ b/arch/arm/mach-msm/acpuclock-krait.h
@@ -50,10 +50,15 @@
PVS_NOMINAL = 1,
PVS_FAST = 3,
PVS_FASTER = 4,
- NUM_PVS = 8
+ NUM_PVS = 16
};
/**
+ * The maximum number of PVS revisions.
+ */
+#define NUM_PVS_REVS (4)
+
+/**
* The maximum number of speed bins.
*/
#define NUM_SPEED_BINS (16)
@@ -236,12 +241,14 @@
* @pvs_valid: @pvs field is valid
* @speed: Speed bin ID
* @pvs: PVS bin ID
+ * @pvs_rev: PVS revision ID
*/
struct bin_info {
bool speed_valid;
bool pvs_valid;
int speed;
int pvs;
+ int pvs_rev;
};
/**
@@ -273,7 +280,7 @@
struct scalable *scalable;
size_t scalable_size;
struct hfpll_data *hfpll_data;
- struct pvs_table (*pvs_tables)[NUM_PVS];
+ struct pvs_table (*pvs_tables)[NUM_SPEED_BINS][NUM_PVS];
struct l2_level *l2_freq_tbl;
size_t l2_freq_tbl_size;
phys_addr_t pte_efuse_phys;
@@ -293,6 +300,7 @@
* @boost_uv: Voltage boost amount
* @speed_bin: Speed bin ID.
* @pvs_bin: PVS bin ID.
+ * @pvs_bin: PVS revision ID.
* @dev: Device.
*/
struct drv_data {
@@ -305,6 +313,7 @@
int boost_uv;
int speed_bin;
int pvs_bin;
+ int pvs_rev;
struct device *dev;
};
diff --git a/arch/arm/mach-msm/board-8226-gpiomux.c b/arch/arm/mach-msm/board-8226-gpiomux.c
index 5dd9bab..4dcbc3a 100644
--- a/arch/arm/mach-msm/board-8226-gpiomux.c
+++ b/arch/arm/mach-msm/board-8226-gpiomux.c
@@ -18,6 +18,38 @@
#include <mach/gpiomux.h>
#include <mach/socinfo.h>
+#ifdef CONFIG_USB_EHCI_MSM_HSIC
+static struct gpiomux_setting hsic_sus_cfg = {
+ .func = GPIOMUX_FUNC_GPIO,
+ .drv = GPIOMUX_DRV_2MA,
+ .pull = GPIOMUX_PULL_DOWN,
+ .dir = GPIOMUX_OUT_LOW,
+};
+
+static struct gpiomux_setting hsic_act_cfg = {
+ .func = GPIOMUX_FUNC_1,
+ .drv = GPIOMUX_DRV_16MA,
+ .pull = GPIOMUX_PULL_NONE,
+};
+
+static struct msm_gpiomux_config msm_hsic_configs[] = {
+ {
+ .gpio = 115, /* HSIC_STROBE */
+ .settings = {
+ [GPIOMUX_ACTIVE] = &hsic_act_cfg,
+ [GPIOMUX_SUSPENDED] = &hsic_sus_cfg,
+ },
+ },
+ {
+ .gpio = 116, /* HSIC_DATA */
+ .settings = {
+ [GPIOMUX_ACTIVE] = &hsic_act_cfg,
+ [GPIOMUX_SUSPENDED] = &hsic_sus_cfg,
+ },
+ },
+};
+#endif
+
#define KS8851_IRQ_GPIO 115
#if defined(CONFIG_KS8851) || defined(CONFIG_KS8851_MODULE)
@@ -824,4 +856,17 @@
ARRAY_SIZE(usb_otg_sw_configs));
msm_gpiomux_sdc3_install();
+
+ /*
+ * HSIC STROBE gpio is also used by the ethernet. Install HSIC
+ * gpio mux config only when HSIC is enabled. HSIC config will
+ * be disabled when ethernet config is enabled.
+ */
+#ifdef CONFIG_USB_EHCI_MSM_HSIC
+ if (machine_is_msm8926()) {
+ msm_hsic_configs[0].gpio = 119; /* STROBE */
+ msm_hsic_configs[1].gpio = 120; /* DATA */
+ }
+ msm_gpiomux_install(msm_hsic_configs, ARRAY_SIZE(msm_hsic_configs));
+#endif
}
diff --git a/arch/arm/mach-msm/include/mach/gpiomux.h b/arch/arm/mach-msm/include/mach/gpiomux.h
index bd1a4a2..122ffaa 100644
--- a/arch/arm/mach-msm/include/mach/gpiomux.h
+++ b/arch/arm/mach-msm/include/mach/gpiomux.h
@@ -114,6 +114,8 @@
TLMM_ETM_MODE_REG = 0x2014,
TLMM_SDC2_HDRV_PULL_CTL = 0x2048,
TLMM_SPARE_REG = 0x2024,
+ TLMM_CDC_HDRV_CTL = 0x2054,
+ TLMM_CDC_HDRV_PULL_CTL = 0x2058,
};
void msm_tlmm_misc_reg_write(enum msm_tlmm_misc_reg misc_reg, int val);
diff --git a/arch/arm/mach-msm/include/mach/socinfo.h b/arch/arm/mach-msm/include/mach/socinfo.h
index b06189f..6b3d590 100644
--- a/arch/arm/mach-msm/include/mach/socinfo.h
+++ b/arch/arm/mach-msm/include/mach/socinfo.h
@@ -50,6 +50,7 @@
#define machine_is_msm8610() of_machine_is_compatible("qcom,msm8610")
#define machine_is_msm8226() of_machine_is_compatible("qcom,msm8226")
#define machine_is_apq8074() of_machine_is_compatible("qcom,apq8074")
+#define machine_is_msm8926() of_machine_is_compatible("qcom,msm8926")
#define early_machine_is_msm8610() \
of_flat_dt_is_compatible(of_get_flat_dt_root(), "qcom,msm8610")
@@ -80,6 +81,7 @@
#define machine_is_msm8610() 0
#define machine_is_msm8226() 0
#define machine_is_apq8074() 0
+#define machine_is_msm8926() 0
#define early_machine_is_msm8610() 0
#define early_machine_is_mpq8092() 0
diff --git a/drivers/gpu/msm/adreno.h b/drivers/gpu/msm/adreno.h
index 6507852..a837574 100644
--- a/drivers/gpu/msm/adreno.h
+++ b/drivers/gpu/msm/adreno.h
@@ -63,7 +63,6 @@
#define ADRENO_DEFAULT_PWRSCALE_POLICY NULL
#endif
-void adreno_debugfs_init(struct kgsl_device *device);
#define ADRENO_ISTORE_START 0x5000 /* Istore offset */
@@ -749,4 +748,11 @@
return ADRENO_REG_REGISTER_MAX;
return adreno_dev->gpudev->reg_offsets->offsets[offset_name];
}
+
+#ifdef CONFIG_DEBUG_FS
+void adreno_debugfs_init(struct kgsl_device *device);
+#else
+static inline void adreno_debugfs_init(struct kgsl_device *device) { }
+#endif
+
#endif /*__ADRENO_H */
diff --git a/drivers/gpu/msm/adreno_debugfs.c b/drivers/gpu/msm/adreno_debugfs.c
index fc98d86..a7d1b7f 100644
--- a/drivers/gpu/msm/adreno_debugfs.c
+++ b/drivers/gpu/msm/adreno_debugfs.c
@@ -23,8 +23,6 @@
#include "a2xx_reg.h"
-unsigned int kgsl_cff_dump_enable;
-
DEFINE_SIMPLE_ATTRIBUTE(kgsl_cff_dump_enable_fops, kgsl_cff_dump_enable_get,
kgsl_cff_dump_enable_set, "%llu\n");
diff --git a/drivers/gpu/msm/adreno_profile.h b/drivers/gpu/msm/adreno_profile.h
index d91b09b..7e1ccb2 100644
--- a/drivers/gpu/msm/adreno_profile.h
+++ b/drivers/gpu/msm/adreno_profile.h
@@ -61,6 +61,7 @@
#define ADRENO_PROFILE_LOG_BUF_SIZE_DWORDS (ADRENO_PROFILE_LOG_BUF_SIZE / \
sizeof(unsigned int))
+#ifdef CONFIG_DEBUG_FS
void adreno_profile_init(struct kgsl_device *device);
void adreno_profile_close(struct kgsl_device *device);
int adreno_profile_process_results(struct kgsl_device *device);
@@ -70,6 +71,22 @@
void adreno_profile_postib_processing(struct kgsl_device *device,
unsigned int *cmd_flags, unsigned int **rbptr,
unsigned int *cmds_gpu);
+#else
+static inline void adreno_profile_init(struct kgsl_device *device) { }
+static inline void adreno_profile_close(struct kgsl_device *device) { }
+static inline int adreno_profile_process_results(struct kgsl_device *device)
+{
+ return 0;
+}
+
+static inline void adreno_profile_preib_processing(struct kgsl_device *device,
+ unsigned int context_id, unsigned int *cmd_flags,
+ unsigned int **rbptr, unsigned int *cmds_gpu) { }
+
+static inline void adreno_profile_postib_processing(struct kgsl_device *device,
+ unsigned int *cmd_flags, unsigned int **rbptr,
+ unsigned int *cmds_gpu) { }
+#endif
static inline bool adreno_profile_enabled(struct adreno_profile *profile)
{
diff --git a/drivers/gpu/msm/kgsl_log.h b/drivers/gpu/msm/kgsl_log.h
index a7832e4..94649bd 100644
--- a/drivers/gpu/msm/kgsl_log.h
+++ b/drivers/gpu/msm/kgsl_log.h
@@ -13,8 +13,6 @@
#ifndef __KGSL_LOG_H
#define __KGSL_LOG_H
-extern unsigned int kgsl_cff_dump_enable;
-
#define KGSL_LOG_INFO(dev, lvl, fmt, args...) \
do { \
if ((lvl) >= 6) \
diff --git a/drivers/nfc/nfc-nci.c b/drivers/nfc/nfc-nci.c
index 87c7c30..67b057c 100644
--- a/drivers/nfc/nfc-nci.c
+++ b/drivers/nfc/nfc-nci.c
@@ -26,12 +26,15 @@
#include <linux/of_device.h>
#include <linux/regulator/consumer.h>
#include "nfc-nci.h"
+#include <mach/gpiomux.h>
struct qca199x_platform_data {
unsigned int irq_gpio;
unsigned int dis_gpio;
unsigned int ven_gpio;
unsigned int reg;
+ const char *clk_src;
+ unsigned int clk_src_gpio;
};
static struct of_device_id msm_match_table[] = {
@@ -397,7 +400,9 @@
gpio_set_value(qca199x_dev->dis_gpio, 1);
usleep(1000);
} else if (arg == 2) {
+ mutex_lock(&qca199x_dev->read_mutex);
r = nfcc_initialise(qca199x_dev->client, 0xE);
+ mutex_unlock(&qca199x_dev->read_mutex);
if (r) {
dev_err(&qca199x_dev->client->dev,
"nfc-nci probe: request nfcc initialise failed\n");
@@ -419,7 +424,6 @@
return r;
}
-
/*
* Inside nfc_ioctl_nfcc_mode
*
@@ -477,6 +481,64 @@
}
/*
+ * Inside nfc_ioctl_nfcc_version
+ *
+ * @brief nfc_ioctl_nfcc_version
+ *
+ *
+ */
+int nfc_ioctl_nfcc_version(struct file *filp, unsigned int cmd,
+ unsigned long arg)
+{
+ int r = 0;
+ unsigned short slave_addr = 0xE;
+ unsigned short curr_addr;
+
+ unsigned char raw_chip_version_addr = 0x00;
+ unsigned char raw_chip_rev_id_addr = 0x9C;
+ unsigned char raw_chip_version = 0xFF;
+
+ struct qca199x_dev *qca199x_dev = filp->private_data;
+ struct qca199x_platform_data *platform_data;
+
+ platform_data = qca199x_dev->client->dev.platform_data;
+
+ if (arg == 0) {
+ curr_addr = qca199x_dev->client->addr;
+ qca199x_dev->client->addr = slave_addr;
+ r = nfc_i2c_write(qca199x_dev->client,
+ &raw_chip_version_addr, 1);
+ if (r < 0)
+ goto invalid_wr;
+ usleep(10);
+ r = i2c_master_recv(qca199x_dev->client, &raw_chip_version, 1);
+ /* Restore original NFCC slave I2C address */
+ qca199x_dev->client->addr = curr_addr;
+ }
+ if (arg == 1) {
+ curr_addr = qca199x_dev->client->addr;
+ qca199x_dev->client->addr = slave_addr;
+ r = nfc_i2c_write(qca199x_dev->client,
+ &raw_chip_rev_id_addr, 1);
+ if (r < 0)
+ goto invalid_wr;
+ usleep(10);
+ r = i2c_master_recv(qca199x_dev->client, &raw_chip_version, 1);
+ /* Restore original NFCC slave I2C address */
+ qca199x_dev->client->addr = curr_addr;
+ }
+
+ return raw_chip_version;
+invalid_wr:
+ raw_chip_version = 0xFF;
+ dev_err(&qca199x_dev->client->dev,
+ "\nNFCC_INVALID_CHIP_VERSION = %d\n", raw_chip_version);
+ return raw_chip_version;
+}
+
+
+
+/*
* Inside nfc_ioctl_kernel_logging
*
* @brief nfc_ioctl_kernel_logging
@@ -522,6 +584,9 @@
case NFCC_MODE:
nfc_ioctl_nfcc_mode(pfile, cmd, arg);
break;
+ case NFCC_VERSION:
+ r = nfc_ioctl_nfcc_version(pfile, cmd, arg);
+ break;
case NFC_KERNEL_LOGGING_MODE:
nfc_ioctl_kernel_logging(arg, pfile);
break;
@@ -690,6 +755,14 @@
if ((!gpio_is_valid(pdata->irq_gpio)))
return -EINVAL;
+ r = of_property_read_string(np, "qcom,clk-src", &pdata->clk_src);
+
+ if (!strcmp(pdata->clk_src, "GPCLK"))
+ pdata->clk_src_gpio = of_get_named_gpio(np,
+ "qcom,clk-en-gpio", 0);
+
+ if (r)
+ return -EINVAL;
return r;
}
@@ -698,7 +771,7 @@
{
int r = 0;
int irqn = 0;
- struct clk *nfc_clk;
+ struct clk *nfc_clk = NULL;
struct device_node *node = client->dev.of_node;
struct qca199x_platform_data *platform_data;
struct qca199x_dev *qca199x_dev;
@@ -769,7 +842,7 @@
dev_err(&client->dev,
"NFC: unable to request gpio [%d]\n",
platform_data->dis_gpio);
- goto err_dis_gpio;
+ goto err_free_dev;
}
r = gpio_direction_output(platform_data->dis_gpio, 1);
if (r) {
@@ -785,15 +858,28 @@
gpio_set_value(platform_data->dis_gpio, 1);/* HPD */
msleep(20);
gpio_set_value(platform_data->dis_gpio, 0);/* ULPM */
-
- nfc_clk = clk_get(&client->dev, "ref_clk");
-
- if (nfc_clk == NULL)
- goto err_dis_gpio;
-
+ if (!strcmp(platform_data->clk_src, "BBCLK2")) {
+ nfc_clk = clk_get(&client->dev, "ref_clk");
+ if (nfc_clk == NULL)
+ goto err_dis_gpio;
+ } else if (!strcmp(platform_data->clk_src, "RFCLK3")) {
+ nfc_clk = clk_get(&client->dev, "ref_clk_rf");
+ if (nfc_clk == NULL)
+ goto err_dis_gpio;
+ } else if (!strcmp(platform_data->clk_src, "GPCLK")) {
+ if (gpio_is_valid(platform_data->clk_src_gpio)) {
+ nfc_clk = clk_get(&client->dev, "core_clk");
+ if (nfc_clk == NULL)
+ goto err_dis_gpio;
+ } else {
+ goto err_dis_gpio;
+ }
+ } else {
+ nfc_clk = NULL;
+ }
r = clk_prepare_enable(nfc_clk);
if (r)
- goto err_dis_gpio;
+ goto err_clk;
platform_data->ven_gpio = of_get_named_gpio(node,
"qcom,clk-gpio", 0);
@@ -813,11 +899,9 @@
platform_data->ven_gpio);
goto err_ven_gpio;
}
-
} else {
-
dev_err(&client->dev, "ven gpio not provided\n");
- goto err_dis_gpio;
+ goto err_clk;
}
qca199x_dev->dis_gpio = platform_data->dis_gpio;
qca199x_dev->irq_gpio = platform_data->irq_gpio;
@@ -871,7 +955,18 @@
mutex_destroy(&qca199x_dev->read_mutex);
err_ven_gpio:
gpio_free(platform_data->ven_gpio);
+err_clk:
+ clk_disable_unprepare(nfc_clk);
err_dis_gpio:
+ r = gpio_direction_input(platform_data->dis_gpio);
+ if (r)
+ dev_err(&client->dev, "nfc-nci probe: Unable to set direction\n");
+ if (!strcmp(platform_data->clk_src, "GPCLK")) {
+ r = gpio_direction_input(platform_data->clk_src_gpio);
+ if (r)
+ dev_err(&client->dev, "nfc-nci probe: Unable to set direction\n");
+ gpio_free(platform_data->clk_src_gpio);
+ }
gpio_free(platform_data->dis_gpio);
err_irq:
gpio_free(platform_data->irq_gpio);
diff --git a/drivers/nfc/nfc-nci.h b/drivers/nfc/nfc-nci.h
index c3cabc2..81f2521 100644
--- a/drivers/nfc/nfc-nci.h
+++ b/drivers/nfc/nfc-nci.h
@@ -49,26 +49,27 @@
enum ehandler_mode handle_flavour;
} tdevicemode;
-#define NFC_DRIVER_NAME "nfc-nci"
+#define NFC_DRIVER_NAME "nfc-nci"
#define NFC_I2C_DRIVER_NAME "NCI NFC I2C Interface",
-#define NCI_I2C_SLAVE (0x2C)
-#define NFC_I2C_BUS 3 /* 6, 10, 4, 5 */
-#define NFC_SET_PWR _IOW(0xE9, 0x01, unsigned int)
-#define NFCC_MODE _IOW(0xE9, 0x02, unsigned int)
+#define NCI_I2C_SLAVE (0x2C)
+#define NFC_I2C_BUS 3 /* 6, 10, 4, 5 */
+#define NFC_SET_PWR _IOW(0xE9, 0x01, unsigned int)
+#define NFCC_MODE _IOW(0xE9, 0x02, unsigned int)
#define NFC_KERNEL_LOGGING_MODE _IOW(0xE9, 0x03, unsigned int)
-#define SET_RX_BLOCK _IOW(0xE9, 0x04, unsigned int)
+#define SET_RX_BLOCK _IOW(0xE9, 0x04, unsigned int)
#define SET_EMULATOR_TEST_POINT _IOW(0xE9, 0x05, unsigned int)
+#define NFCC_VERSION _IOW(0xE9, 0x08, unsigned int)
-#define NFC_MAX_I2C_TRANSFER (0x0400)
-#define NFC_MSG_MAX_SIZE (0x21)
+#define NFC_MAX_I2C_TRANSFER (0x0400)
+#define NFC_MSG_MAX_SIZE (0x21)
#define NFC_RX_BUFFER_CNT_START (0x0)
-#define NFC_RX_BUFFER_BLOCK_SIZE (0x120) /* Bytes per Block */
+#define NFC_RX_BUFFER_BLOCK_SIZE (0x120) /* Bytes per Block */
#define NFC_RX_BUFFER_PAGE_SIZE (0x1000) /* Page size Bytes */
#define NFC_RX_BUFFER_PAGES (0x8)
-#define NFC_RX_ORDER_FREE_PAGES (0x3) /* Free 8 Pages */
+#define NFC_RX_ORDER_FREE_PAGES (0x3) /* Free 8 Pages */
/* The total no. of Blocks */
#define NFC_RX_BUFFER_CNT_LIMIT (unsigned short)( \
@@ -86,10 +87,10 @@
/** Power Management Related **/
-#define NFCC_WAKE (0x01)
-#define NFCC_SLEEP (0x00)
+#define NFCC_WAKE (0x01)
+#define NFCC_SLEEP (0x00)
-#define XTAL_CLOCK (0X00)
+#define XTAL_CLOCK (0X00)
#define REFERENCE_CLOCK (0X01)
/* LDO Trim Settings */
@@ -122,8 +123,8 @@
#define LOCALBIASXTAL (0x20)
#define BIAS2X_FORCE (0x10)
#define BIAS2X (0x08)
-#define LBIAS2X (0x04)
-#define SMALLRF (0x02)
+#define LBIAS2X (0x04)
+#define SMALLRF (0x02)
#define SMALLRBIAS (0x01)
/* Select as appropriate */
diff --git a/drivers/platform/msm/qpnp-power-on.c b/drivers/platform/msm/qpnp-power-on.c
index b4edce8..c0371a5 100644
--- a/drivers/platform/msm/qpnp-power-on.c
+++ b/drivers/platform/msm/qpnp-power-on.c
@@ -1031,8 +1031,11 @@
index = ffs(pon_sts);
if ((index > PON_REASON_MAX) || (index < 0))
index = 0;
- pr_info("PMIC@SID%d Power-on reason: %s\n", pon->spmi->sid,
- index ? qpnp_pon_reason[index - 1] : "Unknown");
+
+ cold_boot = !qpnp_pon_is_warm_reset();
+ pr_info("PMIC@SID%d Power-on reason: %s and '%s' boot\n",
+ pon->spmi->sid, index ? qpnp_pon_reason[index - 1] :
+ "Unknown", cold_boot ? "cold" : "warm");
rc = of_property_read_u32(pon->spmi->dev.of_node,
"qcom,pon-dbc-delay", &delay);
diff --git a/drivers/usb/dwc3/dwc3_otg.c b/drivers/usb/dwc3/dwc3_otg.c
index 5348eb5..9599936 100644
--- a/drivers/usb/dwc3/dwc3_otg.c
+++ b/drivers/usb/dwc3/dwc3_otg.c
@@ -24,7 +24,7 @@
#include "io.h"
#include "xhci.h"
-#define VBUS_REG_CHECK_DELAY (jiffies + msecs_to_jiffies(1000))
+#define VBUS_REG_CHECK_DELAY (msecs_to_jiffies(1000))
#define MAX_INVALID_CHRGR_RETRY 3
static int max_chgr_retry_count = MAX_INVALID_CHRGR_RETRY;
module_param(max_chgr_retry_count, int, S_IRUGO | S_IWUSR);
@@ -678,7 +678,7 @@
struct dwc3_charger *charger = dotg->charger;
bool work = 0;
int ret = 0;
- int delay = 0;
+ unsigned long delay = 0;
pm_runtime_resume(phy->dev);
dev_dbg(phy->dev, "%s state\n", otg_state_string(phy->state));
diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
index 8fa4774..8588ffb 100644
--- a/drivers/usb/dwc3/gadget.c
+++ b/drivers/usb/dwc3/gadget.c
@@ -2617,10 +2617,13 @@
}
}
+ /*
+ * Notify suspend only to gadget driver, but not resume. Resume is
+ * notified as part of wakeup event in dwc3_gadget_wakeup_interrupt().
+ */
if (next == DWC3_LINK_STATE_U0) {
if (dwc->link_state == DWC3_LINK_STATE_U3) {
dbg_event(0xFF, "RESUME", 0);
- dwc->gadget_driver->resume(&dwc->gadget);
}
} else if (next == DWC3_LINK_STATE_U3) {
dbg_event(0xFF, "SUSPEND", 0);
diff --git a/drivers/usb/gadget/android.c b/drivers/usb/gadget/android.c
index bbb206d..6765078 100644
--- a/drivers/usb/gadget/android.c
+++ b/drivers/usb/gadget/android.c
@@ -1478,7 +1478,11 @@
rndis->ethaddr[0], rndis->ethaddr[1], rndis->ethaddr[2],
rndis->ethaddr[3], rndis->ethaddr[4], rndis->ethaddr[5]);
- ret = gether_setup_name(c->cdev->gadget, rndis->ethaddr, "rndis");
+ if (rndis->ethaddr[0])
+ ret = gether_setup_name(c->cdev->gadget, NULL, "rndis");
+ else
+ ret = gether_setup_name(c->cdev->gadget, rndis->ethaddr,
+ "rndis");
if (ret) {
pr_err("%s: gether_setup failed\n", __func__);
return ret;
diff --git a/drivers/video/msm/mdss/dsi_v2.c b/drivers/video/msm/mdss/dsi_v2.c
index 531c814..65cca0e 100644
--- a/drivers/video/msm/mdss/dsi_v2.c
+++ b/drivers/video/msm/mdss/dsi_v2.c
@@ -141,8 +141,6 @@
struct mdss_dsi_ctrl_pdata *ctrl_pdata)
{
struct device_node *np = pdev->dev.of_node;
- int rc = 0, i = 0;
- u32 tmp[9];
ctrl_pdata->disp_en_gpio = of_get_named_gpio(np,
"qcom,platform-enable-gpio", 0);
@@ -160,15 +158,6 @@
__func__, __LINE__);
}
- rc = of_property_read_u32_array(np,
- "qcom,platform-reset-sequence", tmp, MDSS_DSI_RST_SEQ_LEN);
- if (rc)
- pr_err("%s:%d, unable to read gpio reset sequence\n",
- __func__, __LINE__);
- else
- for (i = 0; i < MDSS_DSI_RST_SEQ_LEN; ++i)
- ctrl_pdata->rst_seq[i] = tmp[i];
-
ctrl_pdata->rst_gpio = of_get_named_gpio(np,
"qcom,platform-reset-gpio", 0);
if (!gpio_is_valid(ctrl_pdata->rst_gpio))
diff --git a/drivers/video/msm/mdss/mdp3_ppp.c b/drivers/video/msm/mdss/mdp3_ppp.c
index 6e62cc7..1b1ddf1 100644
--- a/drivers/video/msm/mdss/mdp3_ppp.c
+++ b/drivers/video/msm/mdss/mdp3_ppp.c
@@ -495,6 +495,9 @@
{
int dst_h, src_w, i;
uint32_t mdp_op = blit_op->mdp_op;
+ void *src_p0 = blit_op->src.p0;
+ void *src_p1 = blit_op->src.p1;
+ void *dst_p0 = blit_op->dst.p0;
src_w = req->src_rect.w;
dst_h = blit_op->dst.roi.height;
@@ -527,8 +530,11 @@
/* this is for a remainder update */
dst_h -= 16;
src_w -= blit_op->src.roi.width;
- /* restore mdp_op since MDPOP_ASCALE have been cleared */
+ /* restore parameters that may have been overwritten */
blit_op->mdp_op = mdp_op;
+ blit_op->src.p0 = src_p0;
+ blit_op->src.p1 = src_p1;
+ blit_op->dst.p0 = dst_p0;
}
if ((dst_h < 0) || (src_w < 0))
diff --git a/drivers/video/msm/mdss/mdp3_ppp_data.c b/drivers/video/msm/mdss/mdp3_ppp_data.c
index e1c0f27..ba2a369 100644
--- a/drivers/video/msm/mdss/mdp3_ppp_data.c
+++ b/drivers/video/msm/mdss/mdp3_ppp_data.c
@@ -16,6 +16,8 @@
#include "mdss_fb.h"
#include "mdp3_ppp.h"
+#define MDP_IS_IMGTYPE_BAD(x) ((x) >= MDP_IMGTYPE_LIMIT)
+
/* bg_config_lut not needed since it is same as src */
const uint32_t src_cfg_lut[MDP_IMGTYPE_LIMIT] = {
[MDP_RGB_565] = MDP_RGB_565_SRC_REG,
@@ -1504,56 +1506,56 @@
uint32_t ppp_bpp(uint32_t type)
{
- if (type > MDP_IMGTYPE_LIMIT)
+ if (MDP_IS_IMGTYPE_BAD(type))
return 0;
return bytes_per_pixel[type];
}
uint32_t ppp_src_config(uint32_t type)
{
- if (type > MDP_IMGTYPE_LIMIT)
+ if (MDP_IS_IMGTYPE_BAD(type))
return 0;
return src_cfg_lut[type];
}
uint32_t ppp_out_config(uint32_t type)
{
- if (type > MDP_IMGTYPE_LIMIT)
+ if (MDP_IS_IMGTYPE_BAD(type))
return 0;
return out_cfg_lut[type];
}
uint32_t ppp_pack_pattern(uint32_t type)
{
- if (type > MDP_IMGTYPE_LIMIT)
+ if (MDP_IS_IMGTYPE_BAD(type))
return 0;
return pack_patt_lut[type];
}
uint32_t ppp_dst_op_reg(uint32_t type)
{
- if (type > MDP_IMGTYPE_LIMIT)
+ if (MDP_IS_IMGTYPE_BAD(type))
return 0;
return dst_op_reg[type];
}
uint32_t ppp_src_op_reg(uint32_t type)
{
- if (type > MDP_IMGTYPE_LIMIT)
+ if (MDP_IS_IMGTYPE_BAD(type))
return 0;
return src_op_reg[type];
}
bool ppp_per_p_alpha(uint32_t type)
{
- if (type > MDP_IMGTYPE_LIMIT)
+ if (MDP_IS_IMGTYPE_BAD(type))
return 0;
return per_pixel_alpha[type];
}
bool ppp_multi_plane(uint32_t type)
{
- if (type > MDP_IMGTYPE_LIMIT)
+ if (MDP_IS_IMGTYPE_BAD(type))
return 0;
return multi_plane[type];
}
diff --git a/drivers/video/msm/mdss/mdss_dsi.c b/drivers/video/msm/mdss/mdss_dsi.c
index b794ac4..b353c96 100644
--- a/drivers/video/msm/mdss/mdss_dsi.c
+++ b/drivers/video/msm/mdss/mdss_dsi.c
@@ -1069,7 +1069,6 @@
{
struct mipi_panel_info *mipi;
int rc, i, len;
- u32 tmp[9];
struct device_node *dsi_ctrl_np = NULL;
struct platform_device *ctrl_pdev = NULL;
bool dynamic_fps;
@@ -1248,15 +1247,6 @@
ctrl_pdata->disp_te_gpio);
}
- rc = of_property_read_u32_array(ctrl_pdev->dev.of_node,
- "qcom,platform-reset-sequence", tmp, MDSS_DSI_RST_SEQ_LEN);
- if (rc)
- pr_err("%s:%d, unable to read gpio reset sequence\n",
- __func__, __LINE__);
- else
- for (i = 0; i < MDSS_DSI_RST_SEQ_LEN; ++i)
- ctrl_pdata->rst_seq[i] = tmp[i];
-
ctrl_pdata->rst_gpio = of_get_named_gpio(ctrl_pdev->dev.of_node,
"qcom,platform-reset-gpio", 0);
if (!gpio_is_valid(ctrl_pdata->rst_gpio)) {
diff --git a/drivers/video/msm/mdss/mdss_dsi.h b/drivers/video/msm/mdss/mdss_dsi.h
index b2b20f2..121d6ff 100644
--- a/drivers/video/msm/mdss/mdss_dsi.h
+++ b/drivers/video/msm/mdss/mdss_dsi.h
@@ -194,8 +194,6 @@
#define MDSS_DSI_LEN 8 /* 4 x 4 - 6 - 2, bytes dcs header+crc-align */
-#define MDSS_DSI_RST_SEQ_LEN 6
-
struct dsi_buf {
u32 *hdr; /* dsi host header */
char *start; /* buffer start addr */
@@ -346,7 +344,6 @@
u32 pclk_rate;
u32 byte_clk_rate;
struct dss_module_power power_data;
- int rst_seq[MDSS_DSI_RST_SEQ_LEN];
u32 dsi_irq_mask;
struct mdss_hw *dsi_hw;
diff --git a/drivers/video/msm/mdss/mdss_dsi_panel.c b/drivers/video/msm/mdss/mdss_dsi_panel.c
index f37a6cc..262b7bd 100644
--- a/drivers/video/msm/mdss/mdss_dsi_panel.c
+++ b/drivers/video/msm/mdss/mdss_dsi_panel.c
@@ -182,10 +182,11 @@
pinfo = &(ctrl_pdata->panel_data.panel_info);
if (enable) {
- for (i = 0; i < MDSS_DSI_RST_SEQ_LEN; ++i) {
+ for (i = 0; i < pdata->panel_info.rst_seq_len; ++i) {
gpio_set_value((ctrl_pdata->rst_gpio),
- ctrl_pdata->rst_seq[i]);
- msleep(ctrl_pdata->rst_seq[++i]);
+ pdata->panel_info.rst_seq[i]);
+ if (pdata->panel_info.rst_seq[++i])
+ usleep(pdata->panel_info.rst_seq[i] * 1000);
}
if (gpio_is_valid(ctrl_pdata->disp_en_gpio))
gpio_set_value((ctrl_pdata->disp_en_gpio), 1);
@@ -547,6 +548,35 @@
}
+static int mdss_dsi_parse_reset_seq(struct device_node *np,
+ u32 rst_seq[MDSS_DSI_RST_SEQ_LEN], u32 *rst_len,
+ const char *name)
+{
+ int num = 0, i;
+ int rc;
+ struct property *data;
+ u32 tmp[MDSS_DSI_RST_SEQ_LEN];
+ *rst_len = 0;
+ data = of_find_property(np, name, &num);
+ num /= sizeof(u32);
+ if (!data || !num || num > MDSS_DSI_RST_SEQ_LEN || num % 2) {
+ pr_debug("%s:%d, error reading %s, length found = %d\n",
+ __func__, __LINE__, name, num);
+ } else {
+ rc = of_property_read_u32_array(np, name, tmp, num);
+ if (rc)
+ pr_debug("%s:%d, error reading %s, rc = %d\n",
+ __func__, __LINE__, name, rc);
+ else {
+ for (i = 0; i < num; ++i)
+ rst_seq[i] = tmp[i];
+ *rst_len = num;
+ }
+ }
+ return 0;
+}
+
+
static int mdss_panel_parse_dt(struct device_node *np,
struct mdss_dsi_ctrl_pdata *ctrl_pdata)
{
@@ -795,6 +825,9 @@
mdss_dsi_parse_fbc_params(np, pinfo);
+ mdss_dsi_parse_reset_seq(np, pinfo->rst_seq, &(pinfo->rst_seq_len),
+ "qcom,mdss-dsi-reset-sequence");
+
mdss_dsi_parse_dcs_cmds(np, &ctrl_pdata->on_cmds,
"qcom,mdss-dsi-on-command", "qcom,mdss-dsi-on-command-state");
diff --git a/drivers/video/msm/mdss/mdss_hdmi_edid.c b/drivers/video/msm/mdss/mdss_hdmi_edid.c
index 65dc19c..488bc11 100644
--- a/drivers/video/msm/mdss/mdss_hdmi_edid.c
+++ b/drivers/video/msm/mdss/mdss_hdmi_edid.c
@@ -27,6 +27,8 @@
#define MAX_AUDIO_DATA_BLOCK_SIZE 30
#define MAX_SPKR_ALLOC_DATA_BLOCK_SIZE 3
+#define BUFF_SIZE_3D 128
+
struct hdmi_edid_sink_data {
u32 disp_mode_list[HDMI_VFRMT_MAX];
u32 disp_3d_mode_list[HDMI_VFRMT_MAX];
@@ -249,19 +251,19 @@
if (!hdmi_get_supported_mode(*video_mode))
continue;
if (ret > 0)
- ret += snprintf(buf+ret, PAGE_SIZE-ret, ",%d",
- *video_mode++);
+ ret += scnprintf(buf + ret, PAGE_SIZE - ret,
+ ",%d", *video_mode++);
else
- ret += snprintf(buf+ret, PAGE_SIZE-ret, "%d",
- *video_mode++);
+ ret += scnprintf(buf + ret, PAGE_SIZE - ret,
+ "%d", *video_mode++);
}
} else {
- ret += snprintf(buf+ret, PAGE_SIZE-ret, "%d",
+ ret += scnprintf(buf + ret, PAGE_SIZE - ret, "%d",
edid_ctrl->video_resolution);
}
DEV_DBG("%s: '%s'\n", __func__, buf);
- ret += snprintf(buf+ret, PAGE_SIZE-ret, "\n");
+ ret += scnprintf(buf + ret, PAGE_SIZE - ret, "\n");
return ret;
} /* hdmi_edid_sysfs_rda_modes */
@@ -279,7 +281,7 @@
return -EINVAL;
}
- ret = snprintf(buf, PAGE_SIZE, "%d\n", edid_ctrl->physical_address);
+ ret = scnprintf(buf, PAGE_SIZE, "%d\n", edid_ctrl->physical_address);
DEV_DBG("%s: '%d'\n", __func__, edid_ctrl->physical_address);
return ret;
@@ -298,7 +300,7 @@
return -EINVAL;
}
- ret = snprintf(buf, PAGE_SIZE, "%d, %d, %d\n", edid_ctrl->pt_scan_info,
+ ret = scnprintf(buf, PAGE_SIZE, "%d, %d, %d\n", edid_ctrl->pt_scan_info,
edid_ctrl->it_scan_info, edid_ctrl->ce_scan_info);
DEV_DBG("%s: '%s'\n", __func__, buf);
@@ -311,7 +313,8 @@
{
ssize_t ret = 0;
int i;
- char buff_3d[128];
+ char buff_3d[BUFF_SIZE_3D];
+
struct hdmi_edid_ctrl *edid_ctrl =
hdmi_get_featuredata_from_sysfs_dev(dev, HDMI_TX_FEAT_EDID);
@@ -327,23 +330,23 @@
for (i = 0; i < edid_ctrl->sink_data.num_of_elements; ++i) {
ret = hdmi_get_video_3d_fmt_2string(*video_3d_mode++,
- buff_3d);
+ buff_3d, sizeof(buff_3d));
if (ret > 0)
- ret += snprintf(buf+ret, PAGE_SIZE-ret,
+ ret += scnprintf(buf + ret, PAGE_SIZE - ret,
",%d=%s", *video_mode++,
buff_3d);
else
- ret += snprintf(buf+ret, PAGE_SIZE-ret,
+ ret += scnprintf(buf + ret, PAGE_SIZE - ret,
"%d=%s", *video_mode++,
buff_3d);
}
} else {
- ret += snprintf(buf+ret, PAGE_SIZE-ret, "%d",
+ ret += scnprintf(buf + ret, PAGE_SIZE - ret, "%d",
edid_ctrl->video_resolution);
}
DEV_DBG("%s: '%s'\n", __func__, buf);
- ret += snprintf(buf+ret, PAGE_SIZE-ret, "\n");
+ ret += scnprintf(buf + ret, PAGE_SIZE - ret, "\n");
return ret;
} /* hdmi_edid_sysfs_rda_3d_modes */
@@ -816,7 +819,7 @@
static void hdmi_edid_add_sink_3d_format(struct hdmi_edid_sink_data *sink_data,
u32 video_format, u32 video_3d_format)
{
- char string[128];
+ char string[BUFF_SIZE_3D];
u32 added = false;
int i;
@@ -828,7 +831,7 @@
}
}
- hdmi_get_video_3d_fmt_2string(video_3d_format, string);
+ hdmi_get_video_3d_fmt_2string(video_3d_format, string, sizeof(string));
DEV_DBG("%s: EDID[3D]: format: %d [%s], %s %s\n", __func__,
video_format, msm_hdmi_mode_2string(video_format),
diff --git a/drivers/video/msm/mdss/mdss_hdmi_util.c b/drivers/video/msm/mdss/mdss_hdmi_util.c
index 53dfc71..711ec68 100644
--- a/drivers/video/msm/mdss/mdss_hdmi_util.c
+++ b/drivers/video/msm/mdss/mdss_hdmi_util.c
@@ -123,30 +123,30 @@
return "";
} /* hdmi_get_single_video_3d_fmt_2string */
-ssize_t hdmi_get_video_3d_fmt_2string(u32 format, char *buf)
+ssize_t hdmi_get_video_3d_fmt_2string(u32 format, char *buf, u32 size)
{
ssize_t ret, len = 0;
- ret = snprintf(buf, PAGE_SIZE, "%s",
+ ret = scnprintf(buf, size, "%s",
hdmi_get_single_video_3d_fmt_2string(
format & FRAME_PACKING));
len += ret;
if (len && (format & TOP_AND_BOTTOM))
- ret = snprintf(buf + len, PAGE_SIZE, ":%s",
+ ret = scnprintf(buf + len, size - len, ":%s",
hdmi_get_single_video_3d_fmt_2string(
format & TOP_AND_BOTTOM));
else
- ret = snprintf(buf + len, PAGE_SIZE, "%s",
+ ret = scnprintf(buf + len, size - len, "%s",
hdmi_get_single_video_3d_fmt_2string(
format & TOP_AND_BOTTOM));
len += ret;
if (len && (format & SIDE_BY_SIDE_HALF))
- ret = snprintf(buf + len, PAGE_SIZE, ":%s",
+ ret = scnprintf(buf + len, size - len, ":%s",
hdmi_get_single_video_3d_fmt_2string(
format & SIDE_BY_SIDE_HALF));
else
- ret = snprintf(buf + len, PAGE_SIZE, "%s",
+ ret = scnprintf(buf + len, size - len, "%s",
hdmi_get_single_video_3d_fmt_2string(
format & SIDE_BY_SIDE_HALF));
len += ret;
diff --git a/drivers/video/msm/mdss/mdss_hdmi_util.h b/drivers/video/msm/mdss/mdss_hdmi_util.h
index e99e549..5f7878b 100644
--- a/drivers/video/msm/mdss/mdss_hdmi_util.h
+++ b/drivers/video/msm/mdss/mdss_hdmi_util.h
@@ -256,7 +256,7 @@
int hdmi_get_video_id_code(struct msm_hdmi_mode_timing_info *timing_in);
const struct msm_hdmi_mode_timing_info *hdmi_get_supported_mode(u32 mode);
void hdmi_del_supported_mode(u32 mode);
-ssize_t hdmi_get_video_3d_fmt_2string(u32 format, char *buf);
+ssize_t hdmi_get_video_3d_fmt_2string(u32 format, char *buf, u32 size);
/* todo: Fix this. Right now this is defined in mdss_hdmi_tx.c */
void *hdmi_get_featuredata_from_sysfs_dev(struct device *device, u32 type);
diff --git a/drivers/video/msm/mdss/mdss_mdp.h b/drivers/video/msm/mdss/mdss_mdp.h
index 7338d85..f9db498 100644
--- a/drivers/video/msm/mdss/mdss_mdp.h
+++ b/drivers/video/msm/mdss/mdss_mdp.h
@@ -513,33 +513,18 @@
int mdss_hw_init(struct mdss_data_type *mdata);
-int mdss_mdp_pa_config(struct mdss_mdp_ctl *ctl,
- struct mdp_pa_cfg_data *config,
- u32 *copyback);
-int mdss_mdp_pcc_config(struct mdss_mdp_ctl *ctl,
- struct mdp_pcc_cfg_data *cfg_ptr,
- u32 *copyback);
-int mdss_mdp_igc_lut_config(struct mdss_mdp_ctl *ctl,
- struct mdp_igc_lut_data *config,
- u32 *copyback, u32 copy_from_kernel);
-int mdss_mdp_argc_config(struct mdss_mdp_ctl *ctl,
- struct mdp_pgc_lut_data *config,
- u32 *copyback);
-int mdss_mdp_hist_lut_config(struct mdss_mdp_ctl *ctl,
- struct mdp_hist_lut_data *config,
- u32 *copyback);
-int mdss_mdp_dither_config(struct mdss_mdp_ctl *ctl,
- struct mdp_dither_cfg_data *config,
- u32 *copyback);
-int mdss_mdp_gamut_config(struct mdss_mdp_ctl *ctl,
- struct mdp_gamut_cfg_data *config,
- u32 *copyback);
+int mdss_mdp_pa_config(struct mdp_pa_cfg_data *config, u32 *copyback);
+int mdss_mdp_pcc_config(struct mdp_pcc_cfg_data *cfg_ptr, u32 *copyback);
+int mdss_mdp_igc_lut_config(struct mdp_igc_lut_data *config, u32 *copyback,
+ u32 copy_from_kernel);
+int mdss_mdp_argc_config(struct mdp_pgc_lut_data *config, u32 *copyback);
+int mdss_mdp_hist_lut_config(struct mdp_hist_lut_data *config, u32 *copyback);
+int mdss_mdp_dither_config(struct mdp_dither_cfg_data *config, u32 *copyback);
+int mdss_mdp_gamut_config(struct mdp_gamut_cfg_data *config, u32 *copyback);
-int mdss_mdp_histogram_start(struct mdss_mdp_ctl *ctl,
- struct mdp_histogram_start_req *req);
-int mdss_mdp_histogram_stop(struct mdss_mdp_ctl *ctl, u32 block);
-int mdss_mdp_hist_collect(struct mdss_mdp_ctl *ctl,
- struct mdp_histogram_data *hist);
+int mdss_mdp_histogram_start(struct mdp_histogram_start_req *req);
+int mdss_mdp_histogram_stop(u32 block);
+int mdss_mdp_hist_collect(struct mdp_histogram_data *hist);
void mdss_mdp_hist_intr_done(u32 isr);
int mdss_mdp_ad_config(struct msm_fb_data_type *mfd,
diff --git a/drivers/video/msm/mdss/mdss_mdp_ctl.c b/drivers/video/msm/mdss/mdss_mdp_ctl.c
index 503effa..8b90942 100644
--- a/drivers/video/msm/mdss/mdss_mdp_ctl.c
+++ b/drivers/video/msm/mdss/mdss_mdp_ctl.c
@@ -910,7 +910,7 @@
ctl->dst_format = MDSS_MDP_PANEL_FORMAT_RGB888;
break;
}
- mdss_mdp_dither_config(ctl, &dither, NULL);
+ mdss_mdp_dither_config(&dither, NULL);
}
return ctl;
diff --git a/drivers/video/msm/mdss/mdss_mdp_overlay.c b/drivers/video/msm/mdss/mdss_mdp_overlay.c
index 1998113..e3e4509 100644
--- a/drivers/video/msm/mdss/mdss_mdp_overlay.c
+++ b/drivers/video/msm/mdss/mdss_mdp_overlay.c
@@ -547,12 +547,11 @@
pipe->pp_cfg.hist_cfg.frame_cnt;
hist.bit_mask = pipe->pp_cfg.hist_cfg.bit_mask;
hist.num_bins = pipe->pp_cfg.hist_cfg.num_bins;
- mdss_mdp_histogram_start(pipe->mixer->ctl,
- &hist);
+ mdss_mdp_histogram_start(&hist);
} else if (pipe->pp_cfg.hist_cfg.ops &
MDP_PP_OPS_DISABLE) {
- mdss_mdp_histogram_stop(pipe->mixer->ctl,
- pipe->pp_cfg.hist_cfg.block);
+ mdss_mdp_histogram_stop(
+ pipe->pp_cfg.hist_cfg.block);
}
}
len = pipe->pp_cfg.hist_lut_cfg.len;
@@ -1822,7 +1821,6 @@
struct msmfb_mdp_pp mdp_pp;
u32 copyback = 0;
u32 copy_from_kernel = 0;
- struct mdss_overlay_private *mdp5_data = mfd_to_mdp5_data(mfd);
ret = copy_from_user(&mdp_pp, argp, sizeof(mdp_pp));
if (ret)
@@ -1837,14 +1835,12 @@
switch (mdp_pp.op) {
case mdp_op_pa_cfg:
- ret = mdss_mdp_pa_config(mdp5_data->ctl,
- &mdp_pp.data.pa_cfg_data,
+ ret = mdss_mdp_pa_config(&mdp_pp.data.pa_cfg_data,
©back);
break;
case mdp_op_pcc_cfg:
- ret = mdss_mdp_pcc_config(mdp5_data->ctl,
- &mdp_pp.data.pcc_cfg_data,
+ ret = mdss_mdp_pcc_config(&mdp_pp.data.pcc_cfg_data,
©back);
break;
@@ -1852,7 +1848,6 @@
switch (mdp_pp.data.lut_cfg_data.lut_type) {
case mdp_lut_igc:
ret = mdss_mdp_igc_lut_config(
- mdp5_data->ctl,
(struct mdp_igc_lut_data *)
&mdp_pp.data.lut_cfg_data.data,
©back, copy_from_kernel);
@@ -1860,14 +1855,12 @@
case mdp_lut_pgc:
ret = mdss_mdp_argc_config(
- mdp5_data->ctl,
&mdp_pp.data.lut_cfg_data.data.pgc_lut_data,
©back);
break;
case mdp_lut_hist:
ret = mdss_mdp_hist_lut_config(
- mdp5_data->ctl,
(struct mdp_hist_lut_data *)
&mdp_pp.data.lut_cfg_data.data, ©back);
break;
@@ -1879,13 +1872,11 @@
break;
case mdp_op_dither_cfg:
ret = mdss_mdp_dither_config(
- mdp5_data->ctl,
&mdp_pp.data.dither_cfg_data,
©back);
break;
case mdp_op_gamut_cfg:
ret = mdss_mdp_gamut_config(
- mdp5_data->ctl,
&mdp_pp.data.gamut_cfg_data,
©back);
break;
@@ -1936,7 +1927,6 @@
struct mdp_histogram_data hist;
struct mdp_histogram_start_req hist_req;
u32 block;
- struct mdss_overlay_private *mdp5_data = mfd_to_mdp5_data(mfd);
u32 pp_bus_handle;
static int req = -1;
@@ -1955,7 +1945,7 @@
if (ret)
return ret;
- ret = mdss_mdp_histogram_start(mdp5_data->ctl, &hist_req);
+ ret = mdss_mdp_histogram_start(&hist_req);
break;
case MSMFB_HISTOGRAM_STOP:
@@ -1963,7 +1953,7 @@
if (ret)
return ret;
- ret = mdss_mdp_histogram_stop(mdp5_data->ctl, block);
+ ret = mdss_mdp_histogram_stop(block);
if (ret)
return ret;
@@ -1985,7 +1975,7 @@
if (ret)
return ret;
- ret = mdss_mdp_hist_collect(mdp5_data->ctl, &hist);
+ ret = mdss_mdp_hist_collect(&hist);
if (!ret)
ret = copy_to_user(argp, &hist, sizeof(hist));
break;
diff --git a/drivers/video/msm/mdss/mdss_mdp_pipe.c b/drivers/video/msm/mdss/mdss_mdp_pipe.c
index 8920fe1..79549a1 100644
--- a/drivers/video/msm/mdss/mdss_mdp_pipe.c
+++ b/drivers/video/msm/mdss/mdss_mdp_pipe.c
@@ -501,12 +501,14 @@
}
}
-static int mdss_mdp_image_setup(struct mdss_mdp_pipe *pipe)
+static int mdss_mdp_image_setup(struct mdss_mdp_pipe *pipe,
+ struct mdss_mdp_data *data)
{
u32 img_size, src_size, src_xy, dst_size, dst_xy, ystride0, ystride1;
u32 width, height;
u32 decimation;
struct mdss_mdp_img_rect sci, dst, src;
+ int ret = 0;
pr_debug("pnum=%d wh=%dx%d src={%d,%d,%d,%d} dst={%d,%d,%d,%d}\n",
pipe->num, pipe->img_width, pipe->img_height,
@@ -518,6 +520,12 @@
mdss_mdp_get_plane_sizes(pipe->src_fmt->format, width, height,
&pipe->src_planes, pipe->bwc_mode);
+ if (data != NULL) {
+ ret = mdss_mdp_data_check(data, &pipe->src_planes);
+ if (ret)
+ return ret;
+ }
+
if ((pipe->flags & MDP_DEINTERLACE) &&
!(pipe->flags & MDP_SOURCE_ROTATED_90)) {
int i;
@@ -690,7 +698,7 @@
pr_debug("solid fill setup on pnum=%d\n", pipe->num);
- ret = mdss_mdp_image_setup(pipe);
+ ret = mdss_mdp_image_setup(pipe, NULL);
if (ret) {
pr_err("image setup error for pnum=%d\n", pipe->num);
return ret;
@@ -751,7 +759,7 @@
goto done;
}
- ret = mdss_mdp_image_setup(pipe);
+ ret = mdss_mdp_image_setup(pipe, src_data);
if (ret) {
pr_err("image setup error for pnum=%d\n", pipe->num);
goto done;
diff --git a/drivers/video/msm/mdss/mdss_mdp_pp.c b/drivers/video/msm/mdss/mdss_mdp_pp.c
index 09b789b..64d0bca 100644
--- a/drivers/video/msm/mdss/mdss_mdp_pp.c
+++ b/drivers/video/msm/mdss/mdss_mdp_pp.c
@@ -1133,7 +1133,7 @@
flush_exit:
writel_relaxed(opmode, basel + MDSS_MDP_REG_DSPP_OP_MODE);
- mdss_mdp_ctl_write(ctl, MDSS_MDP_REG_CTL_FLUSH, BIT(13 + dspp_num));
+ ctl->flush_bits |= BIT(13 + dspp_num);
wmb();
dspp_exit:
mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_OFF, false);
@@ -1369,15 +1369,12 @@
return 0;
}
-int mdss_mdp_pa_config(struct mdss_mdp_ctl *ctl, struct mdp_pa_cfg_data *config,
+int mdss_mdp_pa_config(struct mdp_pa_cfg_data *config,
u32 *copyback)
{
int ret = 0;
u32 pa_offset, disp_num, dspp_num = 0;
- if (!ctl)
- return -EINVAL;
-
if ((config->block < MDP_LOGICAL_BLOCK_DISP_0) ||
(config->block >= MDP_BLOCK_MAX))
return -EINVAL;
@@ -1411,8 +1408,6 @@
pa_config_exit:
mutex_unlock(&mdss_pp_mutex);
- if (!ret)
- mdss_mdp_pp_setup(ctl);
return ret;
}
@@ -1542,16 +1537,12 @@
MDSS_MDP_REG_WRITE(offset + 8, cfg_ptr->b.rgb_1);
}
-int mdss_mdp_pcc_config(struct mdss_mdp_ctl *ctl,
- struct mdp_pcc_cfg_data *config,
+int mdss_mdp_pcc_config(struct mdp_pcc_cfg_data *config,
u32 *copyback)
{
int ret = 0;
u32 base, disp_num, dspp_num = 0;
- if (!ctl)
- return -EINVAL;
-
if ((config->block < MDP_LOGICAL_BLOCK_DISP_0) ||
(config->block >= MDP_BLOCK_MAX))
return -EINVAL;
@@ -1581,8 +1572,6 @@
pcc_config_exit:
mutex_unlock(&mdss_pp_mutex);
- if (!ret)
- mdss_mdp_pp_setup(ctl);
return ret;
}
@@ -1656,22 +1645,18 @@
config.c0_c1_data = igc_limited;
config.c2_data = igc_limited;
- ret = mdss_mdp_igc_lut_config(ctl, &config, ©back,
+ ret = mdss_mdp_igc_lut_config(&config, ©back,
copy_from_kernel);
return ret;
}
-int mdss_mdp_igc_lut_config(struct mdss_mdp_ctl *ctl,
- struct mdp_igc_lut_data *config,
+int mdss_mdp_igc_lut_config(struct mdp_igc_lut_data *config,
u32 *copyback, u32 copy_from_kernel)
{
int ret = 0;
u32 tbl_idx, igc_offset, disp_num, dspp_num = 0;
struct mdp_igc_lut_data local_cfg;
- if (!ctl)
- return -EINVAL;
-
if ((config->block < MDP_LOGICAL_BLOCK_DISP_0) ||
(config->block >= MDP_BLOCK_MAX))
return -EINVAL;
@@ -1748,8 +1733,6 @@
igc_config_exit:
mutex_unlock(&mdss_pp_mutex);
- if (!ret)
- mdss_mdp_pp_setup(ctl);
return ret;
}
static void pp_update_gc_one_lut(u32 offset,
@@ -1864,8 +1847,7 @@
writel_relaxed(1, offset + 16);
}
-int mdss_mdp_argc_config(struct mdss_mdp_ctl *ctl,
- struct mdp_pgc_lut_data *config,
+int mdss_mdp_argc_config(struct mdp_pgc_lut_data *config,
u32 *copyback)
{
int ret = 0;
@@ -1874,9 +1856,6 @@
struct mdp_pgc_lut_data *pgc_ptr;
u32 tbl_size, r_size, g_size, b_size;
- if (!ctl)
- return -EINVAL;
-
if ((PP_BLOCK(config->block) < MDP_LOGICAL_BLOCK_DISP_0) ||
(PP_BLOCK(config->block) >= MDP_BLOCK_MAX))
return -EINVAL;
@@ -1986,20 +1965,14 @@
}
argc_config_exit:
mutex_unlock(&mdss_pp_mutex);
- if (!ret)
- mdss_mdp_pp_setup(ctl);
return ret;
}
-int mdss_mdp_hist_lut_config(struct mdss_mdp_ctl *ctl,
- struct mdp_hist_lut_data *config,
+int mdss_mdp_hist_lut_config(struct mdp_hist_lut_data *config,
u32 *copyback)
{
int i, ret = 0;
u32 hist_offset, disp_num, dspp_num = 0;
- if (!ctl)
- return -EINVAL;
-
if ((PP_BLOCK(config->block) < MDP_LOGICAL_BLOCK_DISP_0) ||
(PP_BLOCK(config->block) >= MDP_BLOCK_MAX))
return -EINVAL;
@@ -2043,18 +2016,13 @@
}
enhist_config_exit:
mutex_unlock(&mdss_pp_mutex);
- if (!ret)
- mdss_mdp_pp_setup(ctl);
return ret;
}
-int mdss_mdp_dither_config(struct mdss_mdp_ctl *ctl,
- struct mdp_dither_cfg_data *config,
+int mdss_mdp_dither_config(struct mdp_dither_cfg_data *config,
u32 *copyback)
{
u32 disp_num;
- if (!ctl)
- return -EINVAL;
if ((config->block < MDP_LOGICAL_BLOCK_DISP_0) ||
(config->block >= MDP_BLOCK_MAX))
@@ -2067,12 +2035,10 @@
mdss_pp_res->dither_disp_cfg[disp_num] = *config;
mdss_pp_res->pp_disp_flags[disp_num] |= PP_FLAGS_DIRTY_DITHER;
mutex_unlock(&mdss_pp_mutex);
- mdss_mdp_pp_setup(ctl);
return 0;
}
-int mdss_mdp_gamut_config(struct mdss_mdp_ctl *ctl,
- struct mdp_gamut_cfg_data *config,
+int mdss_mdp_gamut_config(struct mdp_gamut_cfg_data *config,
u32 *copyback)
{
int i, j, size_total = 0, ret = 0;
@@ -2084,9 +2050,6 @@
uint16_t *b_tbl[MDP_GAMUT_TABLE_NUM];
- if (!ctl)
- return -EINVAL;
-
if ((config->block < MDP_LOGICAL_BLOCK_DISP_0) ||
(config->block >= MDP_BLOCK_MAX))
return -EINVAL;
@@ -2209,8 +2172,6 @@
}
gamut_config_exit:
mutex_unlock(&mdss_pp_mutex);
- if (!ret)
- mdss_mdp_pp_setup(ctl);
return ret;
}
static void pp_hist_read(char __iomem *v_base,
@@ -2253,7 +2214,7 @@
hist_info->col_state = HIST_RESET;
hist_info->col_en = true;
spin_unlock_irqrestore(&hist_info->hist_lock, flag);
- hist_info->is_kick_ready = false;
+ hist_info->is_kick_ready = true;
mdss_mdp_hist_irq_enable(3 << shift_bit);
writel_relaxed(req->frame_cnt, ctl_base + 8);
/* Kick out reset start */
@@ -2263,8 +2224,7 @@
return ret;
}
-int mdss_mdp_histogram_start(struct mdss_mdp_ctl *ctl,
- struct mdp_histogram_start_req *req)
+int mdss_mdp_histogram_start(struct mdp_histogram_start_req *req)
{
u32 done_shift_bit;
char __iomem *ctl_base;
@@ -2274,8 +2234,6 @@
u32 mixer_cnt, mixer_id[MDSS_MDP_INTF_MAX_LAYERMIXER];
struct mdss_mdp_pipe *pipe;
struct mdss_data_type *mdata = mdss_mdp_get_mdata();
- if (!ctl)
- return -EINVAL;
if ((PP_BLOCK(req->block) < MDP_LOGICAL_BLOCK_DISP_0) ||
(PP_BLOCK(req->block) >= MDP_BLOCK_MAX))
@@ -2342,31 +2300,6 @@
mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_OFF, false);
hist_exit:
- if (!ret && (PP_LOCAT(req->block) == MDSS_PP_DSPP_CFG)) {
- mdss_mdp_pp_setup(ctl);
- /* wait for a frame to let histrogram enable itself */
- /* TODO add hysteresis value to be able to remove this sleep */
- usleep(41666);
- for (i = 0; i < mixer_cnt; i++) {
- dspp_num = mixer_id[i];
- hist_info = &mdss_pp_res->dspp_hist[dspp_num];
- mutex_lock(&hist_info->hist_mutex);
- hist_info->is_kick_ready = true;
- mutex_unlock(&hist_info->hist_mutex);
- }
- } else if (!ret) {
- for (i = 0; i < MDSS_PP_ARG_NUM; i++) {
- if (!PP_ARG(i, req->block))
- continue;
- pr_info("PP_ARG(%d) = %d", i, PP_ARG(i, req->block));
- pipe = mdss_mdp_pipe_get(mdata, BIT(i));
- if (IS_ERR_OR_NULL(pipe))
- continue;
- hist_info = &pipe->pp_res.hist;
- hist_info->is_kick_ready = true;
- mdss_mdp_pipe_unmap(pipe);
- }
- }
return ret;
}
@@ -2395,7 +2328,7 @@
return ret;
}
-int mdss_mdp_histogram_stop(struct mdss_mdp_ctl *ctl, u32 block)
+int mdss_mdp_histogram_stop(u32 block)
{
int i, ret = 0;
char __iomem *ctl_base;
@@ -2405,9 +2338,6 @@
struct mdss_mdp_pipe *pipe;
struct mdss_data_type *mdata = mdss_mdp_get_mdata();
- if (!ctl)
- return -EINVAL;
-
if ((PP_BLOCK(block) < MDP_LOGICAL_BLOCK_DISP_0) ||
(PP_BLOCK(block) >= MDP_BLOCK_MAX))
return -EINVAL;
@@ -2472,13 +2402,10 @@
hist_stop_clk:
mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_OFF, false);
hist_stop_exit:
- if (!ret && (PP_LOCAT(block) == MDSS_PP_DSPP_CFG))
- mdss_mdp_pp_setup(ctl);
return ret;
}
-static int pp_hist_collect(struct mdss_mdp_ctl *ctl,
- struct mdp_histogram_data *hist,
+static int pp_hist_collect(struct mdp_histogram_data *hist,
struct pp_hist_col_info *hist_info,
char __iomem *ctl_base)
{
@@ -2502,9 +2429,6 @@
spin_unlock_irqrestore(&hist_info->hist_lock, flag);
timeout = HIST_WAIT_TIMEOUT(hist_info->frame_cnt);
mutex_unlock(&hist_info->hist_mutex);
- /* flush updates before wait*/
- if (PP_LOCAT(hist->block) == MDSS_PP_DSPP_CFG)
- mdss_mdp_pp_setup(ctl);
if (PP_LOCAT(hist->block) == MDSS_PP_SSPP_CFG) {
res = container_of(hist_info, struct mdss_pipe_pp_res,
hist);
@@ -2565,8 +2489,7 @@
return ret;
}
-int mdss_mdp_hist_collect(struct mdss_mdp_ctl *ctl,
- struct mdp_histogram_data *hist)
+int mdss_mdp_hist_collect(struct mdp_histogram_data *hist)
{
int i, j, off, ret = 0;
struct pp_hist_col_info *hist_info;
@@ -2580,9 +2503,6 @@
struct mdss_mdp_pipe *pipe;
struct mdss_data_type *mdata = mdss_mdp_get_mdata();
- if (!ctl)
- return -EINVAL;
-
if ((PP_BLOCK(hist->block) < MDP_LOGICAL_BLOCK_DISP_0) ||
(PP_BLOCK(hist->block) >= MDP_BLOCK_MAX))
return -EINVAL;
@@ -2609,7 +2529,7 @@
hist_info = &mdss_pp_res->dspp_hist[dspp_num];
ctl_base = mdss_mdp_get_dspp_addr_off(dspp_num) +
MDSS_MDP_REG_DSPP_HIST_CTL_BASE;
- ret = pp_hist_collect(ctl, hist, hist_info, ctl_base);
+ ret = pp_hist_collect(hist, hist_info, ctl_base);
if (ret)
goto hist_collect_exit;
}
@@ -2678,7 +2598,7 @@
hist_info = &pipe->pp_res.hist;
ctl_base = pipe->base +
MDSS_MDP_REG_VIG_HIST_CTL_BASE;
- ret = pp_hist_collect(ctl, hist, hist_info, ctl_base);
+ ret = pp_hist_collect(hist, hist_info, ctl_base);
mdss_mdp_pipe_unmap(pipe);
if (ret)
goto hist_collect_exit;
@@ -2971,8 +2891,6 @@
}
mutex_unlock(&ad->lock);
ctl = mfd_to_ctl(mfd);
- if (!ret)
- mdss_mdp_pp_setup(ctl);
return ret;
}
@@ -2980,7 +2898,6 @@
struct mdss_ad_input *input, int wait) {
int ret = 0;
struct mdss_ad_info *ad;
- struct mdss_mdp_ctl *ctl;
u32 bl;
ret = mdss_mdp_get_ad(mfd, &ad);
@@ -3056,8 +2973,6 @@
init_completion(&ad->comp);
mutex_unlock(&ad->lock);
}
- ctl = mfd_to_ctl(mfd);
- mdss_mdp_pp_setup(ctl);
if (wait) {
ret = wait_for_completion_interruptible_timeout(
&ad->comp, HIST_WAIT_TIMEOUT(1));
@@ -3415,7 +3330,7 @@
}
mutex_unlock(&ad->lock);
mutex_lock(&mfd->lock);
- mdss_mdp_ctl_write(ctl, MDSS_MDP_REG_CTL_FLUSH, BIT(13 + ad->num));
+ ctl->flush_bits |= BIT(13 + ad->num);
mutex_unlock(&mfd->lock);
/* Trigger update notify to wake up those waiting for display updates */
diff --git a/drivers/video/msm/mdss/mdss_panel.h b/drivers/video/msm/mdss/mdss_panel.h
index d5b6ec7..25f1e7c 100644
--- a/drivers/video/msm/mdss/mdss_panel.h
+++ b/drivers/video/msm/mdss/mdss_panel.h
@@ -24,6 +24,7 @@
};
#define DEFAULT_FRAME_RATE 60
+#define MDSS_DSI_RST_SEQ_LEN 10
/* panel type list */
#define NO_PANEL 0xffff /* No Panel */
@@ -272,6 +273,8 @@
u32 frame_count;
u32 is_3d_panel;
u32 out_format;
+ u32 rst_seq[MDSS_DSI_RST_SEQ_LEN];
+ u32 rst_seq_len;
u32 vic; /* video identification code */
u32 roi_x;
u32 roi_y;
diff --git a/include/linux/sysctl.h b/include/linux/sysctl.h
index 84c59dc..d950b5c 100644
--- a/include/linux/sysctl.h
+++ b/include/linux/sysctl.h
@@ -154,6 +154,7 @@
KERN_NMI_WATCHDOG=75, /* int: enable/disable nmi watchdog */
KERN_PANIC_ON_NMI=76, /* int: whether we will panic on an unrecovered */
KERN_BOOT_REASON = 77, /* int: identify reason system was booted */
+ KERN_COLD_BOOT = 78, /* int: identify if system cold booted */
};
diff --git a/kernel/sysctl.c b/kernel/sysctl.c
index b390dad..d16a59ec 100644
--- a/kernel/sysctl.c
+++ b/kernel/sysctl.c
@@ -1009,7 +1009,15 @@
.maxlen = sizeof(int),
.mode = 0444,
.proc_handler = proc_dointvec,
-},
+ },
+
+ {
+ .procname = "cold_boot",
+ .data = &cold_boot,
+ .maxlen = sizeof(int),
+ .mode = 0444,
+ .proc_handler = proc_dointvec,
+ },
#endif
/*
* NOTE: do not add new entries to this table unless you have read
diff --git a/kernel/sysctl_binary.c b/kernel/sysctl_binary.c
index acb60be..6170f45 100644
--- a/kernel/sysctl_binary.c
+++ b/kernel/sysctl_binary.c
@@ -138,6 +138,7 @@
{ CTL_INT, KERN_MAX_LOCK_DEPTH, "max_lock_depth" },
{ CTL_INT, KERN_PANIC_ON_NMI, "panic_on_unrecovered_nmi" },
{ CTL_INT, KERN_BOOT_REASON, "boot_reason" },
+ { CTL_INT, KERN_COLD_BOOT, "cold_boot" },
{}
};
diff --git a/mm/debug-pagealloc.c b/mm/debug-pagealloc.c
index 789ff70..bc91cba 100644
--- a/mm/debug-pagealloc.c
+++ b/mm/debug-pagealloc.c
@@ -69,6 +69,7 @@
print_hex_dump(KERN_ERR, "", DUMP_PREFIX_ADDRESS, 16, 1, start,
end - start + 1, 1);
+ BUG_ON(PANIC_CORRUPTION);
dump_stack();
}
diff --git a/sound/soc/codecs/wcd9306.c b/sound/soc/codecs/wcd9306.c
index 4e07d7f..577c1ed 100644
--- a/sound/soc/codecs/wcd9306.c
+++ b/sound/soc/codecs/wcd9306.c
@@ -1063,6 +1063,25 @@
static const struct snd_kcontrol_new class_h_dsm_mux =
SOC_DAPM_ENUM("CLASS_H_DSM MUX Mux", class_h_dsm_enum);
+static int tapan_hph_impedance_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ uint32_t zl, zr;
+ bool hphr;
+ struct soc_multi_mixer_control *mc;
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+ struct tapan_priv *priv = snd_soc_codec_get_drvdata(codec);
+
+ mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
+
+ hphr = mc->shift;
+ wcd9xxx_mbhc_get_impedance(&priv->mbhc, &zl, &zr);
+ pr_debug("%s: zl %u, zr %u\n", __func__, zl, zr);
+ ucontrol->value.integer.value[0] = hphr ? zr : zl;
+
+ return 0;
+}
+
static const struct snd_kcontrol_new tapan_common_snd_controls[] = {
SOC_ENUM_EXT("EAR PA Gain", tapan_ear_pa_gain_enum[0],
@@ -1165,6 +1184,11 @@
tapan_get_iir_band_audio_mixer, tapan_put_iir_band_audio_mixer),
SOC_SINGLE_MULTI_EXT("IIR2 Band5", IIR2, BAND5, 255, 0, 5,
tapan_get_iir_band_audio_mixer, tapan_put_iir_band_audio_mixer),
+
+ SOC_SINGLE_EXT("HPHL Impedance", 0, 0, UINT_MAX, 0,
+ tapan_hph_impedance_get, NULL),
+ SOC_SINGLE_EXT("HPHR Impedance", 0, 1, UINT_MAX, 0,
+ tapan_hph_impedance_get, NULL),
};
static const struct snd_kcontrol_new tapan_9306_snd_controls[] = {
diff --git a/sound/soc/codecs/wcd9xxx-mbhc.c b/sound/soc/codecs/wcd9xxx-mbhc.c
index c2d626b..88f46fa 100644
--- a/sound/soc/codecs/wcd9xxx-mbhc.c
+++ b/sound/soc/codecs/wcd9xxx-mbhc.c
@@ -125,6 +125,11 @@
#define WCD9XXX_MB_MEAS_DELTA_MAX_MV 80
#define WCD9XXX_CS_MEAS_DELTA_MAX_MV 10
+static int impedance_detect_en;
+module_param(impedance_detect_en, int,
+ S_IRUGO | S_IWUSR | S_IWGRP);
+MODULE_PARM_DESC(impedance_detect_en, "enable/disable impedance detect");
+
static bool detect_use_vddio_switch = true;
struct wcd9xxx_mbhc_detect {
@@ -863,7 +868,7 @@
mbhc->micbias_enable_cb(mbhc->codec, true);
}
- if (mbhc->impedance_detect)
+ if (mbhc->impedance_detect && impedance_detect_en)
wcd9xxx_detect_impedance(mbhc, &mbhc->zl, &mbhc->zr);
pr_debug("%s: Reporting insertion %d(%x)\n", __func__,
@@ -1077,6 +1082,18 @@
mbhc->mbhc_cb->enable_mb_source(codec, true);
/*
+ * setup internal micbias if codec uses internal micbias for
+ * headset detection
+ */
+ if (mbhc->mbhc_cfg->use_int_rbias) {
+ if (mbhc->mbhc_cb && mbhc->mbhc_cb->setup_int_rbias)
+ mbhc->mbhc_cb->setup_int_rbias(codec, true);
+ else
+ pr_err("%s: internal bias is requested but codec did not provide callback\n",
+ __func__);
+ }
+
+ /*
* Request BG and clock.
* These will be released by wcd9xxx_cleanup_hs_polling
*/
@@ -1406,7 +1423,7 @@
(dgnd->_vdces + WCD9XXX_CS_GM_SWAP_THRES_MAX_MV >
maxv))
type = PLUG_TYPE_GND_MIC_SWAP;
- else if (dgnd->_type != PLUG_TYPE_HEADSET) {
+ else if (dgnd->_type != PLUG_TYPE_HEADSET && !dmicbias) {
pr_debug("%s: Invalid, inconsistent types\n", __func__);
type = PLUG_TYPE_INVALID;
}
@@ -2257,8 +2274,11 @@
usleep_range(generic->t_shutdown_plug_rem,
generic->t_shutdown_plug_rem);
- cs_enable = ((mbhc->mbhc_cfg->cs_enable_flags &
- (1 << MBHC_CS_ENABLE_REMOVAL)) != 0);
+ /* If micbias is enabled, don't enable current source */
+ cs_enable = (((mbhc->mbhc_cfg->cs_enable_flags &
+ (1 << MBHC_CS_ENABLE_REMOVAL)) != 0) &&
+ (!(snd_soc_read(codec,
+ mbhc->mbhc_bias_regs.ctl_reg) & 0x80)));
if (cs_enable)
wcd9xxx_turn_onoff_current_source(mbhc, true, false);
@@ -3030,13 +3050,14 @@
change = snd_soc_update_bits(codec, WCD9XXX_A_MAD_ANA_CTRL, 1 << 4,
1 << 0);
usleep_range(1000, 1000 + 1000);
- if (sta_z)
+ if (sta_z) {
*sta_z = wcd9xxx_codec_sta_dce(mbhc, 0, false);
- if (dce_z)
+ pr_debug("%s: sta_z 0x%x\n", __func__, *sta_z & 0xFFFF);
+ }
+ if (dce_z) {
*dce_z = wcd9xxx_codec_sta_dce(mbhc, 1, false);
-
- pr_debug("%s: sta_z 0x%x, dce_z 0x%x\n", __func__, *sta_z & 0xFFFF,
- *dce_z & 0xFFFF);
+ pr_debug("%s: dce_z 0x%x\n", __func__, *dce_z & 0xFFFF);
+ }
/* Connect override from micbias */
if (change)
@@ -4450,6 +4471,7 @@
mbhc->rco_clk_rate = rco_clk_rate;
mbhc->mbhc_cb = mbhc_cb;
mbhc->impedance_detect = impedance_det_en;
+ impedance_detect_en = impedance_det_en ? 1 : 0;
if (mbhc->headset_jack.jack == NULL) {
ret = snd_soc_jack_new(codec, "Headset Jack", WCD9XXX_JACK_MASK,
diff --git a/sound/soc/codecs/wcd9xxx-resmgr.c b/sound/soc/codecs/wcd9xxx-resmgr.c
index 95244c0..cb76342 100644
--- a/sound/soc/codecs/wcd9xxx-resmgr.c
+++ b/sound/soc/codecs/wcd9xxx-resmgr.c
@@ -199,12 +199,17 @@
usleep_range(50, 50);
}
/* Notify */
- if (resmgr->clk_type == WCD9XXX_CLK_RCO)
+ if (resmgr->clk_type == WCD9XXX_CLK_RCO) {
wcd9xxx_resmgr_notifier_call(resmgr,
WCD9XXX_EVENT_POST_RCO_OFF);
- else
+ } else {
+ if (resmgr->codec_type == WCD9XXX_CDC_TYPE_HELICON)
+ snd_soc_update_bits(codec,
+ MSM8X10_WCD_A_CDC_CLK_PDM_CTL, 0x03, 0x00);
+
wcd9xxx_resmgr_notifier_call(resmgr,
WCD9XXX_EVENT_POST_MCLK_OFF);
+ }
pr_debug("%s: leave\n", __func__);
}
diff --git a/sound/soc/msm/msm8x10.c b/sound/soc/msm/msm8x10.c
index 4b61db6..c318849 100644
--- a/sound/soc/msm/msm8x10.c
+++ b/sound/soc/msm/msm8x10.c
@@ -29,6 +29,7 @@
#include <qdsp6v2/msm-pcm-routing-v2.h>
#include <sound/q6afe-v2.h>
#include <linux/module.h>
+#include <mach/gpiomux.h>
#include "../codecs/msm8x10-wcd.h"
#define DRV_NAME "msm8x10-asoc-wcd"
#define BTSCO_RATE_8KHZ 8000
@@ -186,6 +187,10 @@
static int msm_config_mclk(u16 port_id, struct afe_digital_clk_cfg *cfg)
{
+ /* set the drive strength on the clock */
+ msm_tlmm_misc_reg_write(TLMM_CDC_HDRV_CTL, 0x00);
+ msm_tlmm_misc_reg_write(TLMM_CDC_HDRV_PULL_CTL, 0x0006db6d);
+
iowrite32(0x1, pcbcr);
/* Set the update bit to make the settings go through */
iowrite32(0x1, prcgr);