tree fe5e792226548270df57aa5da1eaea72058f4372
parent 1289deb9b5c151876feb594cd82984f3932982e8
author Will Deacon <will.deacon@arm.com> 1317663053 +0100
committer Greg Kroah-Hartman <gregkh@suse.de> 1319519413 +0200

ARM: 7117/1: perf: fix HW_CACHE_* events on Cortex-A9

commit 29a541f6c1f6e4a85628bb86071b9e72c9f8be2c upstream.

Using COHERENT_LINE_{MISS,HIT} for cache misses and references
respectively is completely wrong. Instead, use the L1D events which
are a better and more useful approximation despite ignoring instruction
traffic.

Reported-by: Alasdair Grant <alasdair.grant@arm.com>
Reported-by: Matt Horsnell <matt.horsnell@arm.com>
Reported-by: Michael Williams <michael.williams@arm.com>
Cc: Jean Pihet <j-pihet@ti.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>