tree e1c06b90d161bc81e8d2c819da3b676f75527dda
parent 7465378fd7c681f6cf2b74b3494c4f0991d8c8ac
author Chris Wilson <chris@chris-wilson.co.uk> 1285359347 +0100
committer Chris Wilson <chris@chris-wilson.co.uk> 1288347307 +0100

drm/i915: Only enforce fence limits inside the GTT.

So long as we adhere to the fence registers rules for alignment and no
overlaps (including with unfenced accesses to linear memory) and account
for the tiled access in our size allocation, we do not have to allocate
the full fenced region for the object. This allows us to fight the bloat
tiling imposed on pre-i965 chipsets and frees up RAM for real use. [Inside
the GTT we still suffer the additional alignment constraints, so it doesn't
magic allow us to render larger scenes without stalls -- we need the
expanded GTT and fence pipelining to overcome those...]

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>