msm: pil-riva: Simplify and fix CXO voting
Determining when CXO should be used as the source for the RIVA
PLL relies on reading the RIVA PMU registers which themselves are
clocked by CXO. A recent patch to consolidate the proxy voting to
the core moved this check up before CXO is turned on by the
driver, thus leading to a possible situation where if CXO is off
reading the PMU registers would hang.
Instead of worrying about turning on CXO to access the PMU
registers, unconditionally turn on CXO in the proxy vote callback
and turn it off after the timeout expires. This should ensure
that CXO is on whenever the PMU registers are accessed in
addition to properly handling the PLL configuration. It also
ensures that the RIVA processor can access the PMU registers
early on during boot before it places its own CXO vote.
Change-Id: I0289ca2646dd07a981254e35ee183ac44b9faed6
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
1 file changed