Merge "msm: pil-venus: Fix iommu programming order in reset and shutdown" into msm-3.4
diff --git a/arch/arm/mach-msm/pil-venus.c b/arch/arm/mach-msm/pil-venus.c
index 6a0aeaa..49c39ec 100644
--- a/arch/arm/mach-msm/pil-venus.c
+++ b/arch/arm/mach-msm/pil-venus.c
@@ -228,12 +228,6 @@
writel_relaxed(drv->fw_sz, wrapper_base +
VENUS_WRAPPER_VBIF_SS_SEC_FW_END_ADDR);
- rc = iommu_attach_device(drv->iommu_fw_domain, drv->iommu_fw_ctx);
- if (rc) {
- dev_err(pil->dev, "venus fw iommu attach failed\n");
- goto err_iommu_attach;
- }
-
/* Enable all Venus internal clocks */
writel_relaxed(0, wrapper_base + VENUS_WRAPPER_CLOCK_CONFIG);
writel_relaxed(0, wrapper_base + VENUS_WRAPPER_CPU_CLOCK_CONFIG);
@@ -247,6 +241,12 @@
*/
udelay(1);
+ rc = iommu_attach_device(drv->iommu_fw_domain, drv->iommu_fw_ctx);
+ if (rc) {
+ dev_err(pil->dev, "venus fw iommu attach failed\n");
+ goto err_iommu_attach;
+ }
+
/* Map virtual addr space 0 - fw_sz to firmware physical addr space */
rc = msm_iommu_map_contig_buffer(pa, drv->venus_domain_num, 0,
drv->fw_sz, SZ_4K, 0, &iova);
@@ -285,19 +285,6 @@
venus_clock_prepare_enable(pil->dev);
- /* Halt AXI and AXI OCMEM VBIF Access */
- reg = readl_relaxed(vbif_base + VENUS_VBIF_AXI_HALT_CTRL0);
- reg |= VENUS_VBIF_AXI_HALT_CTRL0_HALT_REQ;
- writel_relaxed(reg, vbif_base + VENUS_VBIF_AXI_HALT_CTRL0);
-
- /* Request for AXI bus port halt */
- rc = readl_poll_timeout(vbif_base + VENUS_VBIF_AXI_HALT_CTRL1,
- reg, reg & VENUS_VBIF_AXI_HALT_CTRL1_HALT_ACK,
- POLL_INTERVAL_US,
- VENUS_VBIF_AXI_HALT_ACK_TIMEOUT_US);
- if (rc)
- dev_err(pil->dev, "Port halt timeout\n");
-
/* Assert the reset to ARM9 */
reg = readl_relaxed(wrapper_base + VENUS_WRAPPER_SW_RESET);
reg |= BIT(4);
@@ -311,6 +298,19 @@
iommu_detach_device(drv->iommu_fw_domain, drv->iommu_fw_ctx);
+ /* Halt AXI and AXI OCMEM VBIF Access */
+ reg = readl_relaxed(vbif_base + VENUS_VBIF_AXI_HALT_CTRL0);
+ reg |= VENUS_VBIF_AXI_HALT_CTRL0_HALT_REQ;
+ writel_relaxed(reg, vbif_base + VENUS_VBIF_AXI_HALT_CTRL0);
+
+ /* Request for AXI bus port halt */
+ rc = readl_poll_timeout(vbif_base + VENUS_VBIF_AXI_HALT_CTRL1,
+ reg, reg & VENUS_VBIF_AXI_HALT_CTRL1_HALT_ACK,
+ POLL_INTERVAL_US,
+ VENUS_VBIF_AXI_HALT_ACK_TIMEOUT_US);
+ if (rc)
+ dev_err(pil->dev, "Port halt timeout\n");
+
venus_clock_disable_unprepare(pil->dev);
regulator_disable(drv->gdsc);