Merge "devices-8064: Enable Content Protection for 8064." into msm-3.0
diff --git a/arch/arm/configs/msm9615_defconfig b/arch/arm/configs/msm9615_defconfig
index 0419929..e6b7b79 100644
--- a/arch/arm/configs/msm9615_defconfig
+++ b/arch/arm/configs/msm9615_defconfig
@@ -180,10 +180,8 @@
CONFIG_SERIAL_MSM_HSL=y
CONFIG_SERIAL_MSM_HSL_CONSOLE=y
CONFIG_DIAG_CHAR=y
-CONFIG_HVC_DCC=y
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_MSM=y
-CONFIG_DCC_TTY=y
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
# CONFIG_I2C_MSM is not set
diff --git a/arch/arm/mach-msm/bam_dmux.c b/arch/arm/mach-msm/bam_dmux.c
index befa5bb..d53e471 100644
--- a/arch/arm/mach-msm/bam_dmux.c
+++ b/arch/arm/mach-msm/bam_dmux.c
@@ -1595,6 +1595,7 @@
static void ul_wakeup(void)
{
int ret;
+ int do_vote_dfab = 0;
mutex_lock(&wakeup_lock);
if (bam_is_connected) { /* bam got connected before lock grabbed */
@@ -1621,16 +1622,19 @@
* don't grab the wakelock the first time because it is
* already grabbed when a2 powers on
*/
- if (likely(a2_pc_disabled_wakelock_skipped))
+ if (likely(a2_pc_disabled_wakelock_skipped)) {
grab_wakelock();
- else
+ do_vote_dfab = 1; /* vote must occur after wait */
+ } else {
a2_pc_disabled_wakelock_skipped = 1;
+ }
if (wait_for_dfab) {
ret = wait_for_completion_timeout(
&dfab_unvote_completion, HZ);
BUG_ON(ret == 0);
}
- vote_dfab();
+ if (likely(do_vote_dfab))
+ vote_dfab();
schedule_delayed_work(&ul_timeout_work,
msecs_to_jiffies(UL_TIMEOUT_DELAY));
bam_is_connected = 1;
diff --git a/arch/arm/mach-msm/board-8064.c b/arch/arm/mach-msm/board-8064.c
index df041f0..be539d0 100644
--- a/arch/arm/mach-msm/board-8064.c
+++ b/arch/arm/mach-msm/board-8064.c
@@ -1260,7 +1260,6 @@
0,
};
-#ifndef CONFIG_MSM_VCAP
#define MXT_TS_GPIO_IRQ 6
#define MXT_TS_PWR_EN_GPIO PM8921_GPIO_PM_TO_SYS(23)
#define MXT_TS_RESET_GPIO 33
@@ -1312,7 +1311,6 @@
.irq = MSM_GPIO_TO_INT(MXT_TS_GPIO_IRQ),
},
};
-#endif
#define CYTTSP_TS_GPIO_IRQ 6
#define CYTTSP_TS_GPIO_SLEEP 33
@@ -2055,13 +2053,14 @@
},
};
-static struct platform_device *common_devices[] __initdata = {
- &apq8064_device_dmov,
-#ifndef CONFIG_MSM_VCAP
+static struct platform_device *common_not_mpq_devices[] __initdata = {
&apq8064_device_qup_i2c_gsbi1,
&apq8064_device_qup_i2c_gsbi3,
&apq8064_device_qup_i2c_gsbi4,
-#endif
+};
+
+static struct platform_device *common_devices[] __initdata = {
+ &apq8064_device_dmov,
&apq8064_device_qup_spi_gsbi5,
&apq8064_device_ext_5v_vreg,
&apq8064_device_ext_mpp8_vreg,
@@ -2603,14 +2602,12 @@
smb349_charger_i2c_info,
ARRAY_SIZE(smb349_charger_i2c_info)
},
-#ifndef CONFIG_MSM_VCAP
{
I2C_SURF | I2C_LIQUID,
APQ_8064_GSBI3_QUP_I2C_BUS_ID,
mxt_device_info,
ARRAY_SIZE(mxt_device_info),
},
-#endif
{
I2C_FFA,
APQ_8064_GSBI3_QUP_I2C_BUS_ID,
@@ -2813,6 +2810,10 @@
apq8064_ehci_host_init();
apq8064_init_buses();
platform_add_devices(common_devices, ARRAY_SIZE(common_devices));
+ if (!(machine_is_mpq8064_cdp() || machine_is_mpq8064_hrd() ||
+ machine_is_mpq8064_dtv()))
+ platform_add_devices(common_not_mpq_devices,
+ ARRAY_SIZE(common_not_mpq_devices));
enable_ddr3_regulator();
if (machine_is_apq8064_mtp()) {
apq8064_device_hsic_host.dev.platform_data = &msm_hsic_pdata;
diff --git a/arch/arm/mach-msm/board-8930.c b/arch/arm/mach-msm/board-8930.c
index 6fd0f1b..f52d312 100644
--- a/arch/arm/mach-msm/board-8930.c
+++ b/arch/arm/mach-msm/board-8930.c
@@ -41,6 +41,7 @@
#include <linux/i2c/isa1200.h>
#include <linux/gpio_keys.h>
#include <linux/memory.h>
+#include <linux/memblock.h>
#include <linux/slimbus/slimbus.h>
#include <linux/mfd/wcd9xxx/core.h>
@@ -76,6 +77,7 @@
#include <mach/ion.h>
#include <mach/mdm2.h>
#include <mach/msm_rtb.h>
+#include <linux/fmem.h>
#include "timer.h"
#include "devices.h"
@@ -122,17 +124,29 @@
#else
#define MSM_PMEM_SIZE 0x2800000 /* 40 Mbytes */
#endif
-
+#define MSM_LIQUID_PMEM_SIZE 0x4000000 /* 64 Mbytes */
#ifdef CONFIG_MSM_MULTIMEDIA_USE_ION
#define MSM_PMEM_KERNEL_EBI1_SIZE 0x65000
#define MSM_ION_SF_SIZE MSM_PMEM_SIZE
-#define MSM_ION_MM_FW_SIZE 0x200000 /* (2MB) */
#define MSM_ION_MM_SIZE MSM_PMEM_ADSP_SIZE
#define MSM_ION_QSECOM_SIZE 0x300000 /* (3MB) */
+#define MSM_ION_HEAP_NUM 8
+
+
+#define MSM_ION_MM_FW_SIZE 0x200000 /* (2MB) */
#define MSM_ION_MFC_SIZE SZ_8K
#define MSM_ION_AUDIO_SIZE MSM_PMEM_AUDIO_SIZE
-#define MSM_ION_HEAP_NUM 8
+
+#define MSM_LIQUID_ION_MM_SIZE (MSM_ION_MM_SIZE + 0x600000)
+#define MSM_LIQUID_ION_SF_SIZE MSM_LIQUID_PMEM_SIZE
+#define MSM_HDMI_PRIM_ION_SF_SIZE MSM_HDMI_PRIM_PMEM_SIZE
+
+#define MSM8930_FIXED_AREA_START 0xa0000000
+#define MAX_FIXED_AREA_SIZE 0x10000000
+#define MSM_MM_FW_SIZE 0x200000
+#define MSM8930_FW_START (MSM8930_FIXED_AREA_START - MSM_MM_FW_SIZE)
+
#else
#define MSM_PMEM_KERNEL_EBI1_SIZE 0x110C000
#define MSM_ION_HEAP_NUM 1
@@ -218,6 +232,9 @@
#endif /* CONFIG_MSM_MULTIMEDIA_USE_ION */
#endif /* CONFIG_ANDROID_PMEM */
+struct fmem_platform_data msm8930_fmem_pdata = {
+};
+
#define DSP_RAM_BASE_8960 0x8da00000
#define DSP_RAM_SIZE_8960 0x1800000
static int dspcrashd_pdata_8960 = 0xDEADDEAD;
@@ -294,24 +311,36 @@
return MEMTYPE_EBI1;
}
+#define FMEM_ENABLED 1
#ifdef CONFIG_ION_MSM
#ifdef CONFIG_MSM_MULTIMEDIA_USE_ION
static struct ion_cp_heap_pdata cp_mm_msm8930_ion_pdata = {
.permission_type = IPT_TYPE_MM_CARVEOUT,
.align = PAGE_SIZE,
+ .reusable = FMEM_ENABLED,
+ .mem_is_fmem = FMEM_ENABLED,
+ .fixed_position = FIXED_MIDDLE,
};
static struct ion_cp_heap_pdata cp_mfc_msm8930_ion_pdata = {
.permission_type = IPT_TYPE_MFC_SHAREDMEM,
.align = PAGE_SIZE,
+ .reusable = 0,
+ .mem_is_fmem = FMEM_ENABLED,
+ .fixed_position = FIXED_HIGH,
};
+
static struct ion_co_heap_pdata co_msm8930_ion_pdata = {
.adjacent_mem_id = INVALID_HEAP_ID,
.align = PAGE_SIZE,
+ .mem_is_fmem = 0,
};
+
static struct ion_co_heap_pdata fw_co_msm8930_ion_pdata = {
.adjacent_mem_id = ION_CP_MM_HEAP_ID,
.align = SZ_128K,
+ .mem_is_fmem = FMEM_ENABLED,
+ .fixed_position = FIXED_LOW,
};
#endif
@@ -399,15 +428,180 @@
};
#endif
+struct platform_device msm8930_fmem_device = {
+ .name = "fmem",
+ .id = 1,
+ .dev = { .platform_data = &msm8930_fmem_pdata },
+};
+
+static void __init reserve_mem_for_ion(enum ion_memory_types mem_type,
+ unsigned long size)
+{
+ msm8930_reserve_table[mem_type].size += size;
+}
+
+static void __init msm8930_reserve_fixed_area(unsigned long fixed_area_size)
+{
+#if defined(CONFIG_ION_MSM) && defined(CONFIG_MSM_MULTIMEDIA_USE_ION)
+ int ret;
+
+ if (fixed_area_size > MAX_FIXED_AREA_SIZE)
+ panic("fixed area size is larger than %dM\n",
+ MAX_FIXED_AREA_SIZE >> 20);
+
+ reserve_info->fixed_area_size = fixed_area_size;
+ reserve_info->fixed_area_start = MSM8930_FW_START;
+
+ ret = memblock_remove(reserve_info->fixed_area_start,
+ reserve_info->fixed_area_size);
+ BUG_ON(ret);
+#endif
+}
+
+/**
+ * Reserve memory for ION and calculate amount of reusable memory for fmem.
+ * We only reserve memory for heaps that are not reusable. However, we only
+ * support one reusable heap at the moment so we ignore the reusable flag for
+ * other than the first heap with reusable flag set. Also handle special case
+ * for video heaps (MM,FW, and MFC). Video requires heaps MM and MFC to be
+ * at a higher address than FW in addition to not more than 256MB away from the
+ * base address of the firmware. This means that if MM is reusable the other
+ * two heaps must be allocated in the same region as FW. This is handled by the
+ * mem_is_fmem flag in the platform data. In addition the MM heap must be
+ * adjacent to the FW heap for content protection purposes.
+ */
static void __init reserve_ion_memory(void)
{
#if defined(CONFIG_ION_MSM) && defined(CONFIG_MSM_MULTIMEDIA_USE_ION)
- msm8930_reserve_table[MEMTYPE_EBI1].size += MSM_ION_SF_SIZE;
- msm8930_reserve_table[MEMTYPE_EBI1].size += MSM_ION_MM_SIZE;
- msm8930_reserve_table[MEMTYPE_EBI1].size += MSM_ION_MM_FW_SIZE;
- msm8930_reserve_table[MEMTYPE_EBI1].size += MSM_ION_MFC_SIZE;
- msm8930_reserve_table[MEMTYPE_EBI1].size += MSM_ION_QSECOM_SIZE;
- msm8930_reserve_table[MEMTYPE_EBI1].size += MSM_ION_AUDIO_SIZE;
+ unsigned int i;
+ unsigned int reusable_count = 0;
+ unsigned int fixed_size = 0;
+ unsigned int fixed_low_size, fixed_middle_size, fixed_high_size;
+ unsigned long fixed_low_start, fixed_middle_start, fixed_high_start;
+
+ msm8930_fmem_pdata.size = 0;
+ msm8930_fmem_pdata.reserved_size_low = 0;
+ msm8930_fmem_pdata.reserved_size_high = 0;
+ fixed_low_size = 0;
+ fixed_middle_size = 0;
+ fixed_high_size = 0;
+
+ /* We only support 1 reusable heap. Check if more than one heap
+ * is specified as reusable and set as non-reusable if found.
+ */
+ for (i = 0; i < msm8930_ion_pdata.nr; ++i) {
+ const struct ion_platform_heap *heap =
+ &(msm8930_ion_pdata.heaps[i]);
+
+ if (heap->type == ION_HEAP_TYPE_CP && heap->extra_data) {
+ struct ion_cp_heap_pdata *data = heap->extra_data;
+
+ reusable_count += (data->reusable) ? 1 : 0;
+
+ if (data->reusable && reusable_count > 1) {
+ pr_err("%s: Too many heaps specified as "
+ "reusable. Heap %s was not configured "
+ "as reusable.\n", __func__, heap->name);
+ data->reusable = 0;
+ }
+ }
+ }
+
+ for (i = 0; i < msm8930_ion_pdata.nr; ++i) {
+ const struct ion_platform_heap *heap =
+ &(msm8930_ion_pdata.heaps[i]);
+
+ if (heap->extra_data) {
+ int fixed_position = NOT_FIXED;
+ int mem_is_fmem = 0;
+
+ switch (heap->type) {
+ case ION_HEAP_TYPE_CP:
+ mem_is_fmem = ((struct ion_cp_heap_pdata *)
+ heap->extra_data)->mem_is_fmem;
+ fixed_position = ((struct ion_cp_heap_pdata *)
+ heap->extra_data)->fixed_position;
+ break;
+ case ION_HEAP_TYPE_CARVEOUT:
+ mem_is_fmem = ((struct ion_co_heap_pdata *)
+ heap->extra_data)->mem_is_fmem;
+ fixed_position = ((struct ion_co_heap_pdata *)
+ heap->extra_data)->fixed_position;
+ break;
+ default:
+ break;
+ }
+
+ if (fixed_position != NOT_FIXED)
+ fixed_size += heap->size;
+ else
+ reserve_mem_for_ion(MEMTYPE_EBI1, heap->size);
+
+ if (fixed_position == FIXED_LOW)
+ fixed_low_size += heap->size;
+ else if (fixed_position == FIXED_MIDDLE)
+ fixed_middle_size += heap->size;
+ else if (fixed_position == FIXED_HIGH)
+ fixed_high_size += heap->size;
+
+ if (mem_is_fmem)
+ msm8930_fmem_pdata.size += heap->size;
+ }
+ }
+
+ if (!fixed_size)
+ return;
+
+ if (msm8930_fmem_pdata.size) {
+ msm8930_fmem_pdata.reserved_size_low = fixed_low_size;
+ msm8930_fmem_pdata.reserved_size_high = fixed_high_size;
+ }
+
+ /* Since the fixed area may be carved out of lowmem,
+ * make sure the length is a multiple of 1M.
+ */
+ fixed_size = (fixed_size + MSM_MM_FW_SIZE + SECTION_SIZE - 1)
+ & SECTION_MASK;
+ msm8930_reserve_fixed_area(fixed_size);
+
+ fixed_low_start = MSM8930_FIXED_AREA_START;
+ fixed_middle_start = fixed_low_start + fixed_low_size;
+ fixed_high_start = fixed_middle_start + fixed_middle_size;
+
+ for (i = 0; i < msm8930_ion_pdata.nr; ++i) {
+ struct ion_platform_heap *heap = &(msm8930_ion_pdata.heaps[i]);
+
+ if (heap->extra_data) {
+ int fixed_position = NOT_FIXED;
+
+ switch (heap->type) {
+ case ION_HEAP_TYPE_CP:
+ fixed_position = ((struct ion_cp_heap_pdata *)
+ heap->extra_data)->fixed_position;
+ break;
+ case ION_HEAP_TYPE_CARVEOUT:
+ fixed_position = ((struct ion_co_heap_pdata *)
+ heap->extra_data)->fixed_position;
+ break;
+ default:
+ break;
+ }
+
+ switch (fixed_position) {
+ case FIXED_LOW:
+ heap->base = fixed_low_start;
+ break;
+ case FIXED_MIDDLE:
+ heap->base = fixed_middle_start;
+ break;
+ case FIXED_HIGH:
+ heap->base = fixed_high_start;
+ break;
+ default:
+ break;
+ }
+ }
+ }
#endif
}
@@ -428,6 +622,7 @@
static struct reserve_info msm8930_reserve_info __initdata = {
.memtype_reserve_table = msm8930_reserve_table,
.calculate_reserve_sizes = msm8930_calculate_reserve_sizes,
+ .reserve_fixed_area = msm8930_reserve_fixed_area,
.paddr_to_memtype = msm8930_paddr_to_memtype,
};
@@ -448,12 +643,15 @@
/* Check if 32 bit overflow occured */
if (high < mb->start)
- high = ~0UL;
+ high -= PAGE_SIZE;
+
+ if (high < MAX_FIXED_AREA_SIZE + MSM8930_FIXED_AREA_START)
+ panic("fixed area extends beyond end of memory\n");
low &= ~(bank_size - 1);
if (high - low <= bank_size)
- return;
+ goto no_dmm;
msm8930_reserve_info.bank_size = bank_size;
#ifdef CONFIG_ENABLE_DMM
@@ -464,10 +662,11 @@
msm8930_reserve_info.low_unstable_address,
msm8930_reserve_info.max_unstable_size,
msm8930_reserve_info.bank_size);
-#else
- msm8930_reserve_info.low_unstable_address = 0;
- msm8930_reserve_info.max_unstable_size = 0;
+ return;
#endif
+no_dmm:
+ msm8930_reserve_info.low_unstable_address = high;
+ msm8930_reserve_info.max_unstable_size = 0;
}
static void __init place_movable_zone(void)
@@ -490,6 +689,18 @@
static void __init msm8930_reserve(void)
{
msm_reserve();
+ if (msm8930_fmem_pdata.size) {
+#if defined(CONFIG_ION_MSM) && defined(CONFIG_MSM_MULTIMEDIA_USE_ION)
+ if (reserve_info->fixed_area_size) {
+ msm8930_fmem_pdata.phys =
+ reserve_info->fixed_area_start + MSM_MM_FW_SIZE;
+ pr_info("mm fw at %lx (fixed) size %x\n",
+ reserve_info->fixed_area_start, MSM_MM_FW_SIZE);
+ pr_info("fmem start %lx (fixed) size %lx\n",
+ msm8930_fmem_pdata.phys, msm8930_fmem_pdata.size);
+ }
+#endif
+ }
}
static int msm8930_change_memory_power(u64 start, u64 size,
@@ -1740,6 +1951,7 @@
&msm8930_android_pmem_audio_device,
#endif /*CONFIG_MSM_MULTIMEDIA_USE_ION*/
#endif /*CONFIG_ANDROID_PMEM*/
+ &msm8930_fmem_device,
&msm_device_bam_dmux,
&msm_fm_platform_init,
diff --git a/arch/arm/mach-msm/board-8960-gpiomux.c b/arch/arm/mach-msm/board-8960-gpiomux.c
index 8b5c693..978eb09 100644
--- a/arch/arm/mach-msm/board-8960-gpiomux.c
+++ b/arch/arm/mach-msm/board-8960-gpiomux.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -597,6 +597,84 @@
};
#endif
+#ifdef CONFIG_MMC_MSM_SDC4_SUPPORT
+static struct gpiomux_setting sdcc4_clk_actv_cfg = {
+ .func = GPIOMUX_FUNC_2,
+ .drv = GPIOMUX_DRV_8MA,
+ .pull = GPIOMUX_PULL_NONE,
+};
+
+static struct gpiomux_setting sdcc4_cmd_data_0_3_actv_cfg = {
+ .func = GPIOMUX_FUNC_2,
+ .drv = GPIOMUX_DRV_8MA,
+ .pull = GPIOMUX_PULL_UP,
+};
+
+static struct gpiomux_setting sdcc4_suspend_cfg = {
+ .func = GPIOMUX_FUNC_GPIO,
+ .drv = GPIOMUX_DRV_2MA,
+ .pull = GPIOMUX_PULL_DOWN,
+};
+
+static struct gpiomux_setting sdcc4_data_1_suspend_cfg = {
+ .func = GPIOMUX_FUNC_GPIO,
+ .drv = GPIOMUX_DRV_8MA,
+ .pull = GPIOMUX_PULL_UP,
+};
+
+static struct msm_gpiomux_config msm8960_sdcc4_configs[] __initdata = {
+ {
+ /* SDC4_DATA_3 */
+ .gpio = 83,
+ .settings = {
+ [GPIOMUX_ACTIVE] = &sdcc4_cmd_data_0_3_actv_cfg,
+ [GPIOMUX_SUSPENDED] = &sdcc4_suspend_cfg,
+ },
+ },
+ {
+ /* SDC4_DATA_2 */
+ .gpio = 84,
+ .settings = {
+ [GPIOMUX_ACTIVE] = &sdcc4_cmd_data_0_3_actv_cfg,
+ [GPIOMUX_SUSPENDED] = &sdcc4_suspend_cfg,
+ },
+ },
+ {
+ /* SDC4_DATA_1 */
+ .gpio = 85,
+ .settings = {
+ [GPIOMUX_ACTIVE] = &sdcc4_cmd_data_0_3_actv_cfg,
+ [GPIOMUX_SUSPENDED] = &sdcc4_data_1_suspend_cfg,
+ },
+ },
+ {
+ /* SDC4_DATA_0 */
+ .gpio = 86,
+ .settings = {
+ [GPIOMUX_ACTIVE] = &sdcc4_cmd_data_0_3_actv_cfg,
+ [GPIOMUX_SUSPENDED] = &sdcc4_suspend_cfg,
+ },
+ },
+ {
+ /* SDC4_CMD */
+ .gpio = 87,
+ .settings = {
+ [GPIOMUX_ACTIVE] = &sdcc4_cmd_data_0_3_actv_cfg,
+ [GPIOMUX_SUSPENDED] = &sdcc4_suspend_cfg,
+ },
+ },
+ {
+ /* SDC4_CLK */
+ .gpio = 88,
+ .settings = {
+ [GPIOMUX_ACTIVE] = &sdcc4_clk_actv_cfg,
+ [GPIOMUX_SUSPENDED] = &sdcc4_suspend_cfg,
+ },
+ },
+};
+#endif
+
+
static struct msm_gpiomux_config hap_lvl_shft_config[] __initdata = {
{
.gpio = 47,
@@ -727,6 +805,83 @@
};
#endif
+#ifdef CONFIG_MMC_MSM_SDC2_SUPPORT
+static struct gpiomux_setting sdcc2_clk_actv_cfg = {
+ .func = GPIOMUX_FUNC_2,
+ .drv = GPIOMUX_DRV_8MA,
+ .pull = GPIOMUX_PULL_NONE,
+};
+
+static struct gpiomux_setting sdcc2_cmd_data_0_3_actv_cfg = {
+ .func = GPIOMUX_FUNC_2,
+ .drv = GPIOMUX_DRV_8MA,
+ .pull = GPIOMUX_PULL_UP,
+};
+
+static struct gpiomux_setting sdcc2_suspend_cfg = {
+ .func = GPIOMUX_FUNC_GPIO,
+ .drv = GPIOMUX_DRV_2MA,
+ .pull = GPIOMUX_PULL_DOWN,
+};
+
+static struct gpiomux_setting sdcc2_data_1_suspend_cfg = {
+ .func = GPIOMUX_FUNC_GPIO,
+ .drv = GPIOMUX_DRV_8MA,
+ .pull = GPIOMUX_PULL_UP,
+};
+
+static struct msm_gpiomux_config msm8960_sdcc2_configs[] __initdata = {
+ {
+ /* DATA_3 */
+ .gpio = 92,
+ .settings = {
+ [GPIOMUX_ACTIVE] = &sdcc2_cmd_data_0_3_actv_cfg,
+ [GPIOMUX_SUSPENDED] = &sdcc2_suspend_cfg,
+ },
+ },
+ {
+ /* DATA_2 */
+ .gpio = 91,
+ .settings = {
+ [GPIOMUX_ACTIVE] = &sdcc2_cmd_data_0_3_actv_cfg,
+ [GPIOMUX_SUSPENDED] = &sdcc2_suspend_cfg,
+ },
+ },
+ {
+ /* DATA_1 */
+ .gpio = 90,
+ .settings = {
+ [GPIOMUX_ACTIVE] = &sdcc2_cmd_data_0_3_actv_cfg,
+ [GPIOMUX_SUSPENDED] = &sdcc2_data_1_suspend_cfg,
+ },
+ },
+ {
+ /* DATA_0 */
+ .gpio = 89,
+ .settings = {
+ [GPIOMUX_ACTIVE] = &sdcc2_cmd_data_0_3_actv_cfg,
+ [GPIOMUX_SUSPENDED] = &sdcc2_suspend_cfg,
+ },
+ },
+ {
+ /* CMD */
+ .gpio = 97,
+ .settings = {
+ [GPIOMUX_ACTIVE] = &sdcc2_cmd_data_0_3_actv_cfg,
+ [GPIOMUX_SUSPENDED] = &sdcc2_suspend_cfg,
+ },
+ },
+ {
+ /* CLK */
+ .gpio = 98,
+ .settings = {
+ [GPIOMUX_ACTIVE] = &sdcc2_clk_actv_cfg,
+ [GPIOMUX_SUSPENDED] = &sdcc2_suspend_cfg,
+ },
+ },
+};
+#endif
+
int __init msm8960_init_gpiomux(void)
{
int rc = msm_gpiomux_init(NR_GPIO_IRQS);
@@ -758,6 +913,11 @@
msm_gpiomux_install(wcnss_5wire_interface,
ARRAY_SIZE(wcnss_5wire_interface));
+#ifdef CONFIG_MMC_MSM_SDC4_SUPPORT
+ msm_gpiomux_install(msm8960_sdcc4_configs,
+ ARRAY_SIZE(msm8960_sdcc4_configs));
+#endif
+
if (machine_is_msm8960_mtp() || machine_is_msm8960_fluid() ||
machine_is_msm8960_liquid() || machine_is_msm8960_cdp())
msm_gpiomux_install(hap_lvl_shft_config,
@@ -798,5 +958,10 @@
msm_gpiomux_install(msm8960_fusion_gsbi_configs,
ARRAY_SIZE(msm8960_fusion_gsbi_configs));
+#ifdef CONFIG_MMC_MSM_SDC2_SUPPORT
+ msm_gpiomux_install(msm8960_sdcc2_configs,
+ ARRAY_SIZE(msm8960_sdcc2_configs));
+#endif
+
return 0;
}
diff --git a/arch/arm/mach-msm/board-8960-regulator.c b/arch/arm/mach-msm/board-8960-regulator.c
index ed47ae2..3923ecf 100644
--- a/arch/arm/mach-msm/board-8960-regulator.c
+++ b/arch/arm/mach-msm/board-8960-regulator.c
@@ -163,6 +163,8 @@
VREG_CONSUMERS(S4) = {
REGULATOR_SUPPLY("8921_s4", NULL),
REGULATOR_SUPPLY("sdc_vccq", "msm_sdcc.1"),
+ REGULATOR_SUPPLY("sdc_vdd", "msm_sdcc.2"),
+ REGULATOR_SUPPLY("sdc_vddp", "msm_sdcc.4"),
REGULATOR_SUPPLY("riva_vddpx", "wcnss_wlan.0"),
REGULATOR_SUPPLY("hdmi_vcc", "hdmi_msm.0"),
REGULATOR_SUPPLY("VDDIO_CDC", "tabla-slim"),
@@ -193,7 +195,6 @@
};
VREG_CONSUMERS(LVS1) = {
REGULATOR_SUPPLY("8921_lvs1", NULL),
- REGULATOR_SUPPLY("sdc_vdd", "msm_sdcc.4"),
REGULATOR_SUPPLY("iris_vddio", "wcnss_wlan.0"),
};
VREG_CONSUMERS(LVS2) = {
diff --git a/arch/arm/mach-msm/board-8960-storage.c b/arch/arm/mach-msm/board-8960-storage.c
index f39a691..df1d846 100644
--- a/arch/arm/mach-msm/board-8960-storage.c
+++ b/arch/arm/mach-msm/board-8960-storage.c
@@ -46,6 +46,16 @@
.lpm_uA = 9000,
.hpm_uA = 200000, /* 200mA */
},
+ /* SDCC2 : SDIO slot connected */
+ [SDCC2] = {
+ .name = "sdc_vdd",
+ .high_vol_level = 1800000,
+ .low_vol_level = 1800000,
+ .always_on = 1,
+ .lpm_sup = 1,
+ .lpm_uA = 9000,
+ .hpm_uA = 200000, /* 200mA */
+ },
/* SDCC3 : External card slot connected */
[SDCC3] = {
.name = "sdc_vdd",
@@ -84,7 +94,17 @@
* during sleep.
*/
.lpm_uA = 2000,
- }
+ },
+ /* SDCC4 : SDIO slot connected */
+ [SDCC4] = {
+ .name = "sdc_vddp",
+ .high_vol_level = 1800000,
+ .low_vol_level = 1800000,
+ .always_on = 1,
+ .lpm_sup = 1,
+ .hpm_uA = 200000, /* 200mA */
+ .lpm_uA = 2000,
+ },
};
static struct msm_mmc_slot_reg_data mmc_slot_vreg_data[MAX_SDCC_CONTROLLER] = {
@@ -93,11 +113,19 @@
.vdd_data = &mmc_vdd_reg_data[SDCC1],
.vccq_data = &mmc_vccq_reg_data[SDCC1],
},
+ /* SDCC2 : SDIO card slot connected */
+ [SDCC2] = {
+ .vdd_data = &mmc_vdd_reg_data[SDCC2],
+ },
/* SDCC3 : External card slot connected */
[SDCC3] = {
.vdd_data = &mmc_vdd_reg_data[SDCC3],
.vddp_data = &mmc_vddp_reg_data[SDCC3],
- }
+ },
+ /* SDCC4 : SDIO card slot connected */
+ [SDCC4] = {
+ .vddp_data = &mmc_vddp_reg_data[SDCC4],
+ },
};
/* SDC1 pad data */
@@ -186,6 +214,35 @@
},
};
+struct msm_mmc_gpio sdc2_gpio[] = {
+ {92, "sdc2_dat_3"},
+ {91, "sdc2_dat_2"},
+ {90, "sdc2_dat_1"},
+ {89, "sdc2_dat_0"},
+ {97, "sdc2_cmd"},
+ {98, "sdc2_clk"}
+};
+
+struct msm_mmc_gpio sdc4_gpio[] = {
+ {83, "sdc4_dat_3"},
+ {84, "sdc4_dat_2"},
+ {85, "sdc4_dat_1"},
+ {86, "sdc4_dat_0"},
+ {87, "sdc4_cmd"},
+ {88, "sdc4_clk"}
+};
+
+struct msm_mmc_gpio_data mmc_gpio_data[MAX_SDCC_CONTROLLER] = {
+ [SDCC2] = {
+ .gpio = sdc2_gpio,
+ .size = ARRAY_SIZE(sdc2_gpio),
+ },
+ [SDCC4] = {
+ .gpio = sdc4_gpio,
+ .size = ARRAY_SIZE(sdc4_gpio),
+ },
+};
+
static struct msm_mmc_pad_data mmc_pad_data[MAX_SDCC_CONTROLLER] = {
[SDCC1] = {
.pull = &mmc_pad_pull_data[SDCC1],
@@ -201,9 +258,17 @@
[SDCC1] = {
.pad_data = &mmc_pad_data[SDCC1],
},
+ [SDCC2] = {
+ .is_gpio = 1,
+ .gpio_data = &mmc_gpio_data[SDCC2],
+ },
[SDCC3] = {
.pad_data = &mmc_pad_data[SDCC3],
},
+ [SDCC4] = {
+ .is_gpio = 1,
+ .gpio_data = &mmc_gpio_data[SDCC4],
+ },
};
#define MSM_MPM_PIN_SDC1_DAT1 17
@@ -237,6 +302,23 @@
};
#endif
+#ifdef CONFIG_MMC_MSM_SDC2_SUPPORT
+static unsigned int sdc2_sup_clk_rates[] = {
+ 400000, 24000000, 48000000
+};
+
+static struct mmc_platform_data msm8960_sdc2_data = {
+ .ocr_mask = MMC_VDD_165_195,
+ .mmc_bus_width = MMC_CAP_4_BIT_DATA,
+ .sup_clk_table = sdc2_sup_clk_rates,
+ .sup_clk_cnt = ARRAY_SIZE(sdc2_sup_clk_rates),
+ .pclk_src_dfab = 1,
+ .vreg_data = &mmc_slot_vreg_data[SDCC2],
+ .pin_data = &mmc_slot_pin_data[SDCC2],
+ .sdiowakeup_irq = MSM_GPIO_TO_INT(90),
+};
+#endif
+
#ifdef CONFIG_MMC_MSM_SDC3_SUPPORT
static struct mmc_platform_data msm8960_sdc3_data = {
.ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
@@ -263,14 +345,39 @@
};
#endif
+#ifdef CONFIG_MMC_MSM_SDC4_SUPPORT
+static unsigned int sdc4_sup_clk_rates[] = {
+ 400000, 24000000, 48000000
+};
+
+static struct mmc_platform_data msm8960_sdc4_data = {
+ .ocr_mask = MMC_VDD_165_195,
+ .mmc_bus_width = MMC_CAP_4_BIT_DATA,
+ .sup_clk_table = sdc4_sup_clk_rates,
+ .sup_clk_cnt = ARRAY_SIZE(sdc4_sup_clk_rates),
+ .pclk_src_dfab = 1,
+ .vreg_data = &mmc_slot_vreg_data[SDCC4],
+ .pin_data = &mmc_slot_pin_data[SDCC4],
+ .sdiowakeup_irq = MSM_GPIO_TO_INT(85),
+};
+#endif
+
void __init msm8960_init_mmc(void)
{
#ifdef CONFIG_MMC_MSM_SDC1_SUPPORT
/* SDC1 : eMMC card connected */
msm_add_sdcc(1, &msm8960_sdc1_data);
#endif
+#ifdef CONFIG_MMC_MSM_SDC2_SUPPORT
+ /* SDC2: SDIO slot for WLAN*/
+ msm_add_sdcc(2, &msm8960_sdc2_data);
+#endif
#ifdef CONFIG_MMC_MSM_SDC3_SUPPORT
/* SDC3: External card slot */
msm_add_sdcc(3, &msm8960_sdc3_data);
#endif
+#ifdef CONFIG_MMC_MSM_SDC4_SUPPORT
+ /* SDC4: SDIO slot for WLAN */
+ msm_add_sdcc(4, &msm8960_sdc4_data);
+#endif
}
diff --git a/arch/arm/mach-msm/board-msm7627a-io.c b/arch/arm/mach-msm/board-msm7627a-io.c
index 4df2232..49945d0 100644
--- a/arch/arm/mach-msm/board-msm7627a-io.c
+++ b/arch/arm/mach-msm/board-msm7627a-io.c
@@ -186,6 +186,56 @@
#define MXT_TS_IRQ_GPIO 48
#define MXT_TS_RESET_GPIO 26
+#define MAX_VKEY_LEN 100
+
+static ssize_t mxt_virtual_keys_register(struct kobject *kobj,
+ struct kobj_attribute *attr, char *buf)
+{
+ char *virtual_keys = __stringify(EV_KEY) ":" __stringify(KEY_MENU) \
+ ":60:840:120:80" ":" __stringify(EV_KEY) \
+ ":" __stringify(KEY_HOME) ":180:840:120:80" \
+ ":" __stringify(EV_KEY) ":" \
+ __stringify(KEY_BACK) ":300:840:120:80" \
+ ":" __stringify(EV_KEY) ":" \
+ __stringify(KEY_SEARCH) ":420:840:120:80" "\n";
+
+ return snprintf(buf, strnlen(virtual_keys, MAX_VKEY_LEN) + 1 , "%s",
+ virtual_keys);
+}
+
+static struct kobj_attribute mxt_virtual_keys_attr = {
+ .attr = {
+ .name = "virtualkeys.atmel_mxt_ts",
+ .mode = S_IRUGO,
+ },
+ .show = &mxt_virtual_keys_register,
+};
+
+static struct attribute *mxt_virtual_key_properties_attrs[] = {
+ &mxt_virtual_keys_attr.attr,
+ NULL,
+};
+
+static struct attribute_group mxt_virtual_key_properties_attr_group = {
+ .attrs = mxt_virtual_key_properties_attrs,
+};
+
+struct kobject *mxt_virtual_key_properties_kobj;
+
+static int mxt_vkey_setup(void)
+{
+ int retval;
+
+ mxt_virtual_key_properties_kobj =
+ kobject_create_and_add("board_properties", NULL);
+ if (mxt_virtual_key_properties_kobj)
+ retval = sysfs_create_group(mxt_virtual_key_properties_kobj,
+ &mxt_virtual_key_properties_attr_group);
+ if (!mxt_virtual_key_properties_kobj || retval)
+ pr_err("failed to create mxt board_properties\n");
+
+ return retval;
+}
static const u8 mxt_config_data[] = {
/* T6 Object */
@@ -232,6 +282,51 @@
80, 100, 15, 3,
};
+static const u8 mxt_config_data_evt[] = {
+ /* T6 Object */
+ 0, 0, 0, 0, 0, 0,
+ /* T38 Object */
+ 20, 0, 0, 0, 0, 0, 0, 0,
+ /* T7 Object */
+ 24, 12, 10,
+ /* T8 Object */
+ 30, 0, 20, 20, 0, 0, 9, 45, 10, 192,
+ /* T9 Object */
+ 3, 0, 0, 18, 11, 0, 16, 60, 3, 1,
+ 0, 1, 1, 0, 10, 10, 10, 10, 107, 3,
+ 223, 1, 0, 0, 0, 0, 0, 0, 0, 0,
+ 20, 15, 0, 0, 2,
+ /* T15 Object */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0,
+ /* T18 Object */
+ 0, 0,
+ /* T19 Object */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0,
+ /* T23 Object */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0,
+ /* T25 Object */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ /* T40 Object */
+ 17, 0, 0, 30, 30,
+ /* T42 Object */
+ 3, 20, 45, 40, 128, 0, 0, 0,
+ /* T46 Object */
+ 0, 2, 16, 16, 0, 0, 0, 0, 0,
+ /* T47 Object */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* T48 Object */
+ 1, 128, 96, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 6, 6, 0, 0, 63, 4, 64,
+ 10, 0, 32, 5, 0, 38, 0, 8, 0, 0,
+ 0, 0, 0, 0, 16, 65, 3, 1, 1, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0,
+};
+
static struct mxt_config_info mxt_config_array[] = {
{
.config = mxt_config_data,
@@ -715,7 +810,17 @@
i2c_register_board_info(MSM_GSBI1_QUP_I2C_BUS_ID,
synaptic_i2c_clearpad3k,
ARRAY_SIZE(synaptic_i2c_clearpad3k));
- } else if (machine_is_msm7627a_evb() || machine_is_msm8625_evb()) {
+ } else if (machine_is_msm7627a_evb() || machine_is_msm8625_evb() ||
+ machine_is_msm8625_evt()) {
+ /* Use configuration data for EVT */
+ if (machine_is_msm8625_evt()) {
+ mxt_config_array[0].config = mxt_config_data_evt;
+ mxt_config_array[0].config_length =
+ ARRAY_SIZE(mxt_config_data_evt);
+ mxt_platform_data.panel_maxy = 875;
+ mxt_vkey_setup();
+ }
+
rc = gpio_tlmm_config(GPIO_CFG(MXT_TS_IRQ_GPIO, 0,
GPIO_CFG_INPUT, GPIO_CFG_PULL_UP,
GPIO_CFG_8MA), GPIO_CFG_ENABLE);
diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c
index 13866e7..e5a31f2a 100644
--- a/arch/arm/mach-msm/board-msm8x60.c
+++ b/arch/arm/mach-msm/board-msm8x60.c
@@ -7517,7 +7517,7 @@
"msm_ebi2", "mem_clk");
return;
}
- clk_enable(mem_clk);
+ clk_prepare_enable(mem_clk);
clk_put(mem_clk);
ebi2_cfg_ptr = ioremap_nocache(0x1a100000, sizeof(uint32_t));
diff --git a/arch/arm/mach-msm/devices-8960.c b/arch/arm/mach-msm/devices-8960.c
index ef5881f..fd15c98 100644
--- a/arch/arm/mach-msm/devices-8960.c
+++ b/arch/arm/mach-msm/devices-8960.c
@@ -682,7 +682,6 @@
#define MSM_SDC2_BASE 0x12140000
#define MSM_SDC2_DML_BASE (MSM_SDC2_BASE + 0x800)
#define MSM_SDC2_BAM_BASE (MSM_SDC2_BASE + 0x2000)
-#define MSM_SDC2_BASE 0x12140000
#define MSM_SDC3_BASE 0x12180000
#define MSM_SDC3_DML_BASE (MSM_SDC3_BASE + 0x800)
#define MSM_SDC3_BAM_BASE (MSM_SDC3_BASE + 0x2000)
diff --git a/arch/arm/mach-msm/dma.c b/arch/arm/mach-msm/dma.c
index 69c91f1..cee6b17 100644
--- a/arch/arm/mach-msm/dma.c
+++ b/arch/arm/mach-msm/dma.c
@@ -59,18 +59,20 @@
int channel_active;
int sd;
size_t sd_size;
+ struct list_head staged_commands[MSM_DMOV_CHANNEL_COUNT];
struct list_head ready_commands[MSM_DMOV_CHANNEL_COUNT];
struct list_head active_commands[MSM_DMOV_CHANNEL_COUNT];
- spinlock_t lock;
+ struct mutex lock;
+ spinlock_t list_lock;
unsigned int irq;
struct clk *clk;
struct clk *pclk;
struct clk *ebiclk;
unsigned int clk_ctl;
- struct timer_list timer;
+ struct delayed_work work;
};
-static void msm_dmov_clock_timer(unsigned long);
+static void msm_dmov_clock_work(struct work_struct *);
static int msm_dmov_clk_toggle(int, int);
#ifdef CONFIG_ARCH_MSM8X60
@@ -163,15 +165,19 @@
{
.crci_conf = adm0_crci_conf,
.chan_conf = adm0_chan_conf,
- .lock = __SPIN_LOCK_UNLOCKED(dmov_lock),
+ .lock = __MUTEX_INITIALIZER(dmov_conf[0].lock),
+ .list_lock = __SPIN_LOCK_UNLOCKED(dmov_list_lock),
.clk_ctl = CLK_DIS,
- .timer = TIMER_INITIALIZER(msm_dmov_clock_timer, 0, 0),
+ .work = __DELAYED_WORK_INITIALIZER(dmov_conf[0].work,
+ msm_dmov_clock_work),
}, {
.crci_conf = adm1_crci_conf,
.chan_conf = adm1_chan_conf,
- .lock = __SPIN_LOCK_UNLOCKED(dmov_lock),
+ .lock = __MUTEX_INITIALIZER(dmov_conf[1].lock),
+ .list_lock = __SPIN_LOCK_UNLOCKED(dmov_list_lock),
.clk_ctl = CLK_DIS,
- .timer = TIMER_INITIALIZER(msm_dmov_clock_timer, 0, 1),
+ .work = __DELAYED_WORK_INITIALIZER(dmov_conf[1].work,
+ msm_dmov_clock_work),
}
};
#else
@@ -179,9 +185,11 @@
{
.crci_conf = NULL,
.chan_conf = NULL,
- .lock = __SPIN_LOCK_UNLOCKED(dmov_lock),
+ .lock = __MUTEX_INITIALIZER(dmov_conf[0].lock),
+ .list_lock = __SPIN_LOCK_UNLOCKED(dmov_list_lock),
.clk_ctl = CLK_DIS,
- .timer = TIMER_INITIALIZER(msm_dmov_clock_timer, 0, 0),
+ .work = __DELAYED_WORK_INITIALIZER(dmov_conf[0].work,
+ msm_dmov_clock_work),
}
};
#endif
@@ -257,69 +265,119 @@
return ret;
}
-static void msm_dmov_clock_timer(unsigned long adm)
+static void msm_dmov_clock_work(struct work_struct *work)
{
- unsigned long irq_flags;
- spin_lock_irqsave(&dmov_conf[adm].lock, irq_flags);
- if (dmov_conf[adm].clk_ctl == CLK_TO_BE_DIS) {
- BUG_ON(dmov_conf[adm].channel_active);
+ struct msm_dmov_conf *conf =
+ container_of(to_delayed_work(work), struct msm_dmov_conf, work);
+ int adm = DMOV_IRQ_TO_ADM(conf->irq);
+ mutex_lock(&conf->lock);
+ if (conf->clk_ctl == CLK_TO_BE_DIS) {
+ BUG_ON(conf->channel_active);
msm_dmov_clk_toggle(adm, 0);
- dmov_conf[adm].clk_ctl = CLK_DIS;
+ conf->clk_ctl = CLK_DIS;
}
- spin_unlock_irqrestore(&dmov_conf[adm].lock, irq_flags);
+ mutex_unlock(&conf->lock);
}
-void msm_dmov_stop_cmd(unsigned id, struct msm_dmov_cmd *cmd, int graceful)
-{
- int adm = DMOV_ID_TO_ADM(id);
- int ch = DMOV_ID_TO_CHAN(id);
- writel_relaxed((graceful << 31), DMOV_REG(DMOV_FLUSH0(ch), adm));
- wmb();
-}
-EXPORT_SYMBOL(msm_dmov_stop_cmd);
+enum {
+ NOFLUSH = 0,
+ GRACEFUL,
+ NONGRACEFUL,
+};
-void msm_dmov_enqueue_cmd_ext(unsigned id, struct msm_dmov_cmd *cmd)
+/* Caller must hold the list lock */
+static struct msm_dmov_cmd *start_ready_cmd(unsigned ch, int adm)
{
- unsigned long irq_flags;
- unsigned int status;
+ struct msm_dmov_cmd *cmd;
+
+ if (list_empty(&dmov_conf[adm].ready_commands[ch]))
+ return NULL;
+
+ cmd = list_entry(dmov_conf[adm].ready_commands[ch].next, typeof(*cmd),
+ list);
+ list_del(&cmd->list);
+ if (cmd->exec_func)
+ cmd->exec_func(cmd);
+ list_add_tail(&cmd->list, &dmov_conf[adm].active_commands[ch]);
+ if (!dmov_conf[adm].channel_active)
+ enable_irq(dmov_conf[adm].irq);
+ dmov_conf[adm].channel_active |= BIT(ch);
+ PRINT_IO("msm dmov enqueue command, %x, ch %d\n", cmd->cmdptr, ch);
+ writel_relaxed(cmd->cmdptr, DMOV_REG(DMOV_CMD_PTR(ch), adm));
+
+ return cmd;
+}
+
+static void msm_dmov_enqueue_cmd_ext_work(struct work_struct *work)
+{
+ struct msm_dmov_cmd *cmd =
+ container_of(work, struct msm_dmov_cmd, work);
+ unsigned id = cmd->id;
+ unsigned status;
+ unsigned long flags;
int adm = DMOV_ID_TO_ADM(id);
int ch = DMOV_ID_TO_CHAN(id);
- spin_lock_irqsave(&dmov_conf[adm].lock, irq_flags);
+ mutex_lock(&dmov_conf[adm].lock);
if (dmov_conf[adm].clk_ctl == CLK_DIS) {
status = msm_dmov_clk_toggle(adm, 1);
if (status != 0)
goto error;
} else if (dmov_conf[adm].clk_ctl == CLK_TO_BE_DIS)
- del_timer(&dmov_conf[adm].timer);
+ cancel_delayed_work_sync(&dmov_conf[adm].work);
dmov_conf[adm].clk_ctl = CLK_EN;
+ spin_lock_irqsave(&dmov_conf[adm].list_lock, flags);
+
+ cmd = list_entry(dmov_conf[adm].staged_commands[ch].next, typeof(*cmd),
+ list);
+ list_del(&cmd->list);
+ list_add_tail(&cmd->list, &dmov_conf[adm].ready_commands[ch]);
status = readl_relaxed(DMOV_REG(DMOV_STATUS(ch), adm));
if (status & DMOV_STATUS_CMD_PTR_RDY) {
PRINT_IO("msm_dmov_enqueue_cmd(%d), start command, status %x\n",
id, status);
- if (cmd->exec_func)
- cmd->exec_func(cmd);
- list_add_tail(&cmd->list, &dmov_conf[adm].active_commands[ch]);
- if (!dmov_conf[adm].channel_active)
- enable_irq(dmov_conf[adm].irq);
- dmov_conf[adm].channel_active |= 1U << ch;
- PRINT_IO("Writing %x exactly to register", cmd->cmdptr);
- writel_relaxed(cmd->cmdptr, DMOV_REG(DMOV_CMD_PTR(ch), adm));
- } else {
- if (!dmov_conf[adm].channel_active) {
- dmov_conf[adm].clk_ctl = CLK_TO_BE_DIS;
- mod_timer(&dmov_conf[adm].timer, jiffies + HZ);
+ cmd = start_ready_cmd(ch, adm);
+ /*
+ * We added something to the ready list, and still hold the
+ * list lock. Thus, no need to check for cmd == NULL
+ */
+ if (cmd->toflush) {
+ int flush = (cmd->toflush == GRACEFUL) ? 1 << 31 : 0;
+ writel_relaxed(flush, DMOV_REG(DMOV_FLUSH0(ch), adm));
}
- if (list_empty(&dmov_conf[adm].active_commands[ch]))
+ } else {
+ cmd->toflush = 0;
+ if (list_empty(&dmov_conf[adm].active_commands[ch]) &&
+ !list_empty(&dmov_conf[adm].ready_commands[ch]))
PRINT_ERROR("msm_dmov_enqueue_cmd_ext(%d), stalled, "
"status %x\n", id, status);
PRINT_IO("msm_dmov_enqueue_cmd(%d), enqueue command, status "
"%x\n", id, status);
- list_add_tail(&cmd->list, &dmov_conf[adm].ready_commands[ch]);
}
+ if (!dmov_conf[adm].channel_active) {
+ dmov_conf[adm].clk_ctl = CLK_TO_BE_DIS;
+ schedule_delayed_work(&dmov_conf[adm].work, HZ);
+ }
+ spin_unlock_irqrestore(&dmov_conf[adm].list_lock, flags);
error:
- spin_unlock_irqrestore(&dmov_conf[adm].lock, irq_flags);
+ mutex_unlock(&dmov_conf[adm].lock);
+}
+
+void msm_dmov_enqueue_cmd_ext(unsigned id, struct msm_dmov_cmd *cmd)
+{
+ int adm = DMOV_ID_TO_ADM(id);
+ int ch = DMOV_ID_TO_CHAN(id);
+ unsigned long flags;
+ cmd->id = id;
+ cmd->toflush = 0;
+ INIT_WORK(&cmd->work, msm_dmov_enqueue_cmd_ext_work);
+
+ spin_lock_irqsave(&dmov_conf[adm].list_lock, flags);
+ list_add_tail(&cmd->list, &dmov_conf[adm].staged_commands[ch]);
+ spin_unlock_irqrestore(&dmov_conf[adm].list_lock, flags);
+
+ schedule_work(&cmd->work);
}
EXPORT_SYMBOL(msm_dmov_enqueue_cmd_ext);
@@ -338,14 +396,18 @@
int ch = DMOV_ID_TO_CHAN(id);
int adm = DMOV_ID_TO_ADM(id);
int flush = graceful ? DMOV_FLUSH_TYPE : 0;
- spin_lock_irqsave(&dmov_conf[adm].lock, irq_flags);
+ struct msm_dmov_cmd *cmd;
+
+ spin_lock_irqsave(&dmov_conf[adm].list_lock, irq_flags);
/* XXX not checking if flush cmd sent already */
if (!list_empty(&dmov_conf[adm].active_commands[ch])) {
PRINT_IO("msm_dmov_flush(%d), send flush cmd\n", id);
writel_relaxed(flush, DMOV_REG(DMOV_FLUSH0(ch), adm));
}
+ list_for_each_entry(cmd, &dmov_conf[adm].staged_commands[ch], list)
+ cmd->toflush = graceful ? GRACEFUL : NONGRACEFUL;
/* spin_unlock_irqrestore has the necessary barrier */
- spin_unlock_irqrestore(&dmov_conf[adm].lock, irq_flags);
+ spin_unlock_irqrestore(&dmov_conf[adm].list_lock, irq_flags);
}
EXPORT_SYMBOL(msm_dmov_flush);
@@ -407,7 +469,7 @@
errdata->flush[5] = readl_relaxed(DMOV_REG(DMOV_FLUSH5(ch), adm));
}
-static irqreturn_t msm_datamover_irq_handler(int irq, void *dev_id)
+static irqreturn_t msm_dmov_isr(int irq, void *dev_id)
{
unsigned int int_status;
unsigned int mask;
@@ -420,11 +482,12 @@
struct msm_dmov_cmd *cmd;
int adm = DMOV_IRQ_TO_ADM(irq);
- spin_lock_irqsave(&dmov_conf[adm].lock, irq_flags);
+ mutex_lock(&dmov_conf[adm].lock);
/* read and clear isr */
int_status = readl_relaxed(DMOV_REG(DMOV_ISR, adm));
PRINT_FLOW("msm_datamover_irq_handler: DMOV_ISR %x\n", int_status);
+ spin_lock_irqsave(&dmov_conf[adm].list_lock, irq_flags);
while (int_status) {
mask = int_status & -int_status;
ch = fls(mask) - 1;
@@ -492,50 +555,38 @@
ch_status = readl_relaxed(DMOV_REG(DMOV_STATUS(ch),
adm));
PRINT_FLOW("msm_datamover_irq_handler id %d, status %x\n", id, ch_status);
- if ((ch_status & DMOV_STATUS_CMD_PTR_RDY) &&
- !list_empty(&dmov_conf[adm].ready_commands[ch])) {
- cmd = list_entry(dmov_conf[adm].
- ready_commands[ch].next, typeof(*cmd),
- list);
- list_del(&cmd->list);
- if (cmd->exec_func)
- cmd->exec_func(cmd);
- list_add_tail(&cmd->list,
- &dmov_conf[adm].active_commands[ch]);
- PRINT_FLOW("msm_datamover_irq_handler id %d, start command\n", id);
- writel_relaxed(cmd->cmdptr,
- DMOV_REG(DMOV_CMD_PTR(ch), adm));
- }
+ if (ch_status & DMOV_STATUS_CMD_PTR_RDY)
+ start_ready_cmd(ch, adm);
} while (ch_status & DMOV_STATUS_RSLT_VALID);
if (list_empty(&dmov_conf[adm].active_commands[ch]) &&
- list_empty(&dmov_conf[adm].ready_commands[ch]))
+ list_empty(&dmov_conf[adm].ready_commands[ch]))
dmov_conf[adm].channel_active &= ~(1U << ch);
PRINT_FLOW("msm_datamover_irq_handler id %d, status %x\n", id, ch_status);
}
+ spin_unlock_irqrestore(&dmov_conf[adm].list_lock, irq_flags);
if (!dmov_conf[adm].channel_active && valid) {
disable_irq_nosync(dmov_conf[adm].irq);
dmov_conf[adm].clk_ctl = CLK_TO_BE_DIS;
- mod_timer(&dmov_conf[adm].timer, jiffies + HZ);
+ schedule_delayed_work(&dmov_conf[adm].work, HZ);
}
- spin_unlock_irqrestore(&dmov_conf[adm].lock, irq_flags);
+ mutex_unlock(&dmov_conf[adm].lock);
return valid ? IRQ_HANDLED : IRQ_NONE;
}
static int msm_dmov_suspend_late(struct device *dev)
{
- unsigned long irq_flags;
struct platform_device *pdev = to_platform_device(dev);
int adm = (pdev->id >= 0) ? pdev->id : 0;
- spin_lock_irqsave(&dmov_conf[adm].lock, irq_flags);
+ mutex_lock(&dmov_conf[adm].lock);
if (dmov_conf[adm].clk_ctl == CLK_TO_BE_DIS) {
BUG_ON(dmov_conf[adm].channel_active);
- del_timer(&dmov_conf[adm].timer);
+ cancel_delayed_work_sync(&dmov_conf[adm].work);
msm_dmov_clk_toggle(adm, 0);
dmov_conf[adm].clk_ctl = CLK_DIS;
}
- spin_unlock_irqrestore(&dmov_conf[adm].lock, irq_flags);
+ mutex_unlock(&dmov_conf[adm].lock);
return 0;
}
@@ -650,8 +701,8 @@
if (!dmov_conf[adm].base)
return -ENOMEM;
- ret = request_irq(dmov_conf[adm].irq, msm_datamover_irq_handler,
- 0, "msmdatamover", NULL);
+ ret = request_threaded_irq(dmov_conf[adm].irq, NULL, msm_dmov_isr,
+ IRQF_ONESHOT, "msmdatamover", NULL);
if (ret) {
PRINT_ERROR("Requesting ADM%d irq %d failed\n", adm,
dmov_conf[adm].irq);
@@ -671,6 +722,7 @@
config_datamover(adm);
for (i = 0; i < MSM_DMOV_CHANNEL_COUNT; i++) {
+ INIT_LIST_HEAD(&dmov_conf[adm].staged_commands[i]);
INIT_LIST_HEAD(&dmov_conf[adm].ready_commands[i]);
INIT_LIST_HEAD(&dmov_conf[adm].active_commands[i]);
diff --git a/arch/arm/mach-msm/include/mach/dma.h b/arch/arm/mach-msm/include/mach/dma.h
index b3e536e..ba621e6 100644
--- a/arch/arm/mach-msm/include/mach/dma.h
+++ b/arch/arm/mach-msm/include/mach/dma.h
@@ -35,7 +35,10 @@
unsigned int result,
struct msm_dmov_errdata *err);
void (*exec_func)(struct msm_dmov_cmd *cmd);
+ struct work_struct work;
+ unsigned id; /* For internal use */
void *user; /* Pointer for caller's reference */
+ u8 toflush;
};
struct msm_dmov_pdata {
@@ -45,7 +48,6 @@
void msm_dmov_enqueue_cmd(unsigned id, struct msm_dmov_cmd *cmd);
void msm_dmov_enqueue_cmd_ext(unsigned id, struct msm_dmov_cmd *cmd);
-void msm_dmov_stop_cmd(unsigned id, struct msm_dmov_cmd *cmd, int graceful);
void msm_dmov_flush(unsigned int id, int graceful);
int msm_dmov_exec_cmd(unsigned id, unsigned int cmdptr);
diff --git a/arch/arm/mach-msm/peripheral-loader.c b/arch/arm/mach-msm/peripheral-loader.c
index fa9159e..0ecea85 100644
--- a/arch/arm/mach-msm/peripheral-loader.c
+++ b/arch/arm/mach-msm/peripheral-loader.c
@@ -350,13 +350,14 @@
}
mutex_lock(&pil->lock);
- if (!pil->count++) {
+ if (!pil->count) {
ret = load_image(pil);
if (ret) {
retval = ERR_PTR(ret);
goto err_load;
}
}
+ pil->count++;
pil_set_state(pil, PIL_ONLINE);
mutex_unlock(&pil->lock);
out:
diff --git a/drivers/gpu/msm/a2xx_reg.h b/drivers/gpu/msm/a2xx_reg.h
index 4c0bd19..41cb601 100644
--- a/drivers/gpu/msm/a2xx_reg.h
+++ b/drivers/gpu/msm/a2xx_reg.h
@@ -140,24 +140,9 @@
struct rb_edram_info_t f;
};
-#define RBBM_READ_ERROR_UNUSED0_SIZE 2
-#define RBBM_READ_ERROR_READ_ADDRESS_SIZE 15
-#define RBBM_READ_ERROR_UNUSED1_SIZE 13
-#define RBBM_READ_ERROR_READ_REQUESTER_SIZE 1
-#define RBBM_READ_ERROR_READ_ERROR_SIZE 1
-
-struct rbbm_read_error_t {
- unsigned int unused0:RBBM_READ_ERROR_UNUSED0_SIZE;
- unsigned int read_address:RBBM_READ_ERROR_READ_ADDRESS_SIZE;
- unsigned int unused1:RBBM_READ_ERROR_UNUSED1_SIZE;
- unsigned int read_requester:RBBM_READ_ERROR_READ_REQUESTER_SIZE;
- unsigned int read_error:RBBM_READ_ERROR_READ_ERROR_SIZE;
-};
-
-union rbbm_read_error_u {
- unsigned int val:32;
- struct rbbm_read_error_t f;
-};
+#define RBBM_READ_ERROR_ADDRESS_MASK 0x0001fffc
+#define RBBM_READ_ERROR_REQUESTER (1<<30)
+#define RBBM_READ_ERROR_ERROR (1<<31)
#define CP_RB_CNTL_RB_BUFSZ_SIZE 6
#define CP_RB_CNTL_UNUSED0_SIZE 2
diff --git a/drivers/gpu/msm/adreno.h b/drivers/gpu/msm/adreno.h
index 95378a1..a7ea20c 100644
--- a/drivers/gpu/msm/adreno.h
+++ b/drivers/gpu/msm/adreno.h
@@ -108,8 +108,10 @@
/* A2XX register sets defined in adreno_a2xx.c */
extern const unsigned int a200_registers[];
extern const unsigned int a220_registers[];
+extern const unsigned int a225_registers[];
extern const unsigned int a200_registers_count;
extern const unsigned int a220_registers_count;
+extern const unsigned int a225_registers_count;
/* A3XX register set defined in adreno_a3xx.c */
extern const unsigned int a3xx_registers[];
diff --git a/drivers/gpu/msm/adreno_a2xx.c b/drivers/gpu/msm/adreno_a2xx.c
index e10edea..eb936f8 100644
--- a/drivers/gpu/msm/adreno_a2xx.c
+++ b/drivers/gpu/msm/adreno_a2xx.c
@@ -55,7 +55,6 @@
0x4000, 0x4003, 0x4800, 0x4805, 0x4900, 0x4900, 0x4908, 0x4908,
};
-/* A220, A225 */
const unsigned int a220_registers[] = {
0x0000, 0x0002, 0x0004, 0x000B, 0x003B, 0x003D, 0x0040, 0x0044,
0x0046, 0x0047, 0x01C0, 0x01C1, 0x01C3, 0x01C8, 0x01D5, 0x01D9,
@@ -85,8 +84,40 @@
0x4900, 0x4900, 0x4908, 0x4908,
};
+const unsigned int a225_registers[] = {
+ 0x0000, 0x0002, 0x0004, 0x000B, 0x003B, 0x003D, 0x0040, 0x0044,
+ 0x0046, 0x0047, 0x013C, 0x013C, 0x0140, 0x014F, 0x01C0, 0x01C1,
+ 0x01C3, 0x01C8, 0x01D5, 0x01D9, 0x01DC, 0x01DD, 0x01EA, 0x01EA,
+ 0x01EE, 0x01F3, 0x01F6, 0x01F7, 0x01FC, 0x01FF, 0x0391, 0x0392,
+ 0x039B, 0x039E, 0x03B2, 0x03B5, 0x03B7, 0x03B7, 0x03F8, 0x03FB,
+ 0x0440, 0x0440, 0x0443, 0x0444, 0x044B, 0x044B, 0x044D, 0x044F,
+ 0x0452, 0x0452, 0x0454, 0x045B, 0x047F, 0x047F, 0x0578, 0x0587,
+ 0x05C9, 0x05C9, 0x05D0, 0x05D0, 0x0601, 0x0604, 0x0606, 0x0609,
+ 0x060B, 0x060E, 0x0613, 0x0614, 0x0A29, 0x0A2B, 0x0A2F, 0x0A31,
+ 0x0A40, 0x0A40, 0x0A42, 0x0A43, 0x0A45, 0x0A45, 0x0A4E, 0x0A4F,
+ 0x0C01, 0x0C1D, 0x0C30, 0x0C30, 0x0C38, 0x0C39, 0x0C3C, 0x0C3C,
+ 0x0C80, 0x0C81, 0x0C88, 0x0C93, 0x0D00, 0x0D03, 0x0D05, 0x0D06,
+ 0x0D08, 0x0D0B, 0x0D34, 0x0D35, 0x0DAE, 0x0DC1, 0x0DC8, 0x0DD4,
+ 0x0DD8, 0x0DD9, 0x0E00, 0x0E00, 0x0E02, 0x0E04, 0x0E17, 0x0E1E,
+ 0x0EC0, 0x0EC9, 0x0ECB, 0x0ECC, 0x0ED0, 0x0ED0, 0x0ED4, 0x0ED7,
+ 0x0EE0, 0x0EE2, 0x0F01, 0x0F02, 0x2000, 0x200F, 0x2080, 0x2082,
+ 0x2100, 0x2109, 0x210C, 0x2114, 0x2180, 0x2184, 0x21F5, 0x21F7,
+ 0x2200, 0x2202, 0x2204, 0x2206, 0x2208, 0x2210, 0x2220, 0x2222,
+ 0x2280, 0x2282, 0x2294, 0x2294, 0x2297, 0x2297, 0x2300, 0x230A,
+ 0x2312, 0x2312, 0x2315, 0x2316, 0x2318, 0x231D, 0x2324, 0x2326,
+ 0x2340, 0x2357, 0x2360, 0x2360, 0x2380, 0x2383, 0x2400, 0x240F,
+ 0x2480, 0x2482, 0x2500, 0x2509, 0x250C, 0x2514, 0x2580, 0x2584,
+ 0x25F5, 0x25F7, 0x2600, 0x2602, 0x2604, 0x2606, 0x2608, 0x2610,
+ 0x2620, 0x2622, 0x2680, 0x2682, 0x2694, 0x2694, 0x2697, 0x2697,
+ 0x2700, 0x270A, 0x2712, 0x2712, 0x2715, 0x2716, 0x2718, 0x271D,
+ 0x2724, 0x2726, 0x2740, 0x2757, 0x2760, 0x2760, 0x2780, 0x2783,
+ 0x4000, 0x4003, 0x4800, 0x4806, 0x4808, 0x4808, 0x4900, 0x4900,
+ 0x4908, 0x4908,
+};
+
const unsigned int a200_registers_count = ARRAY_SIZE(a200_registers) / 2;
const unsigned int a220_registers_count = ARRAY_SIZE(a220_registers) / 2;
+const unsigned int a225_registers_count = ARRAY_SIZE(a225_registers) / 2;
/*
*
@@ -1694,21 +1725,33 @@
{
unsigned int status = 0;
unsigned int rderr = 0;
+ unsigned int addr = 0;
+ const char *source;
adreno_regread(device, REG_RBBM_INT_STATUS, &status);
if (status & RBBM_INT_CNTL__RDERR_INT_MASK) {
- union rbbm_read_error_u rerr;
adreno_regread(device, REG_RBBM_READ_ERROR, &rderr);
- rerr.val = rderr;
- if (rerr.f.read_address == REG_CP_INT_STATUS &&
- rerr.f.read_error &&
- rerr.f.read_requester)
+ source = (rderr & RBBM_READ_ERROR_REQUESTER)
+ ? "host" : "cp";
+ /* convert to dword address */
+ addr = (rderr & RBBM_READ_ERROR_ADDRESS_MASK) >> 2;
+
+ /*
+ * Log CP_INT_STATUS interrupts from the CP at a
+ * lower level because they can happen frequently
+ * and are worked around in a2xx_irq_handler.
+ */
+ if (addr == REG_CP_INT_STATUS &&
+ rderr & RBBM_READ_ERROR_ERROR &&
+ rderr & RBBM_READ_ERROR_REQUESTER)
KGSL_DRV_WARN(device,
- "rbbm read error interrupt: %08x\n", rderr);
+ "rbbm read error interrupt: %s reg: %04X\n",
+ source, addr);
else
KGSL_DRV_CRIT(device,
- "rbbm read error interrupt: %08x\n", rderr);
+ "rbbm read error interrupt: %s reg: %04X\n",
+ source, addr);
}
status &= RBBM_INT_MASK;
diff --git a/drivers/gpu/msm/adreno_a2xx_snapshot.c b/drivers/gpu/msm/adreno_a2xx_snapshot.c
index 091db22..2368264 100644
--- a/drivers/gpu/msm/adreno_a2xx_snapshot.c
+++ b/drivers/gpu/msm/adreno_a2xx_snapshot.c
@@ -240,9 +240,12 @@
if (adreno_is_a20x(adreno_dev)) {
regs.regs = (unsigned int *) a200_registers;
regs.count = a200_registers_count;
- } else {
+ } else if (adreno_is_a220(adreno_dev)) {
regs.regs = (unsigned int *) a220_registers;
regs.count = a220_registers_count;
+ } else if (adreno_is_a225(adreno_dev)) {
+ regs.regs = (unsigned int *) a225_registers;
+ regs.count = a225_registers_count;
}
/* Master set of (non debug) registers */
diff --git a/drivers/gpu/msm/adreno_postmortem.c b/drivers/gpu/msm/adreno_postmortem.c
index 9d68c60..ec38f75 100644
--- a/drivers/gpu/msm/adreno_postmortem.c
+++ b/drivers/gpu/msm/adreno_postmortem.c
@@ -859,6 +859,9 @@
else if (adreno_is_a22x(adreno_dev))
adreno_dump_regs(device, a220_registers,
a220_registers_count);
+ else if (adreno_is_a225(adreno_dev))
+ adreno_dump_regs(device, a225_registers,
+ a225_registers_count);
else if (adreno_is_a3xx(adreno_dev))
adreno_dump_regs(device, a3xx_registers,
a3xx_registers_count);
diff --git a/drivers/media/video/Kconfig b/drivers/media/video/Kconfig
index 07a31a3..5aaef24 100644
--- a/drivers/media/video/Kconfig
+++ b/drivers/media/video/Kconfig
@@ -572,7 +572,7 @@
config MSM_VCAP
tristate "Qualcomm MSM VCAP"
depends on VIDEO_DEV && VIDEO_V4L2
- default n
+ default y
---help---
Enables VCAP driver. This device allows for video capture and
video processing using the v4l2 api
diff --git a/drivers/media/video/msm/sensors/ov5647_v4l2.c b/drivers/media/video/msm/sensors/ov5647_v4l2.c
index 83c83d1..d30d48b 100644
--- a/drivers/media/video/msm/sensors/ov5647_v4l2.c
+++ b/drivers/media/video/msm/sensors/ov5647_v4l2.c
@@ -32,11 +32,12 @@
};
static struct msm_camera_i2c_reg_conf ov5647_groupon_settings[] = {
- {0x0104, 0x01},
+ {0x3208, 0x0},
};
static struct msm_camera_i2c_reg_conf ov5647_groupoff_settings[] = {
- {0x0104, 0x0},
+ {0x3208, 0x10},
+ {0x3208, 0xa0},
};
static struct msm_camera_i2c_reg_conf ov5647_prev_settings[] = {
@@ -293,6 +294,8 @@
{0x518a, 0x04},
{0x518b, 0x00},
{0x5000, 0x06}, /*No lenc,WBC on*/
+ {0x4005, 0x18},
+ {0x4051, 0x8f},
};
@@ -407,7 +410,7 @@
uint16_t gain, uint32_t line)
{
- uint16_t max_line;
+ static uint16_t max_line = 1964;
uint8_t gain_lsb, gain_hsb;
u8 intg_time_hsb, intg_time_msb, intg_time_lsb;
@@ -417,8 +420,8 @@
CDBG(KERN_ERR "snapshot exposure seting 0x%x, 0x%x, %d"
, gain, line, line);
+ s_ctrl->func_tbl->sensor_group_hold_on(s_ctrl);
if (line > 1964) {
- s_ctrl->func_tbl->sensor_group_hold_on(s_ctrl);
msm_camera_i2c_write(s_ctrl->sensor_i2c_client,
s_ctrl->sensor_output_reg_addr->frame_length_lines,
(uint8_t)((line+4) >> 8),
@@ -428,21 +431,17 @@
s_ctrl->sensor_output_reg_addr->frame_length_lines + 1,
(uint8_t)((line+4) & 0x00FF),
MSM_CAMERA_I2C_BYTE_DATA);
- s_ctrl->func_tbl->sensor_group_hold_off(s_ctrl);
-
max_line = line + 4;
- } else if (line > 1968) {
- s_ctrl->func_tbl->sensor_group_hold_on(s_ctrl);
+ } else if (max_line > 1968) {
msm_camera_i2c_write(s_ctrl->sensor_i2c_client,
s_ctrl->sensor_output_reg_addr->frame_length_lines,
- (uint8_t)((line+4) >> 8),
+ (uint8_t)(1968 >> 8),
MSM_CAMERA_I2C_BYTE_DATA);
msm_camera_i2c_write(s_ctrl->sensor_i2c_client,
s_ctrl->sensor_output_reg_addr->frame_length_lines + 1,
- (uint8_t)((line+4) & 0x00FF),
+ (uint8_t)(1968 & 0x00FF),
MSM_CAMERA_I2C_BYTE_DATA);
- s_ctrl->func_tbl->sensor_group_hold_off(s_ctrl);
max_line = 1968;
}
@@ -454,8 +453,6 @@
intg_time_lsb = (u8) (line & 0x00FF);
/* FIXME for BLC trigger */
- s_ctrl->func_tbl->sensor_group_hold_on(s_ctrl);
-
/* Coarse Integration Time */
msm_camera_i2c_write(s_ctrl->sensor_i2c_client,
s_ctrl->sensor_exp_gain_info->coarse_int_time_addr,
@@ -481,7 +478,7 @@
msm_camera_i2c_write(s_ctrl->sensor_i2c_client,
s_ctrl->sensor_exp_gain_info->global_gain_addr + 1,
- gain_lsb-1,
+ gain_lsb^0x1,
MSM_CAMERA_I2C_BYTE_DATA);
/* Coarse Integration Time */
@@ -523,7 +520,7 @@
uint16_t gain, uint32_t line)
{
- uint16_t max_line;
+ static uint16_t max_line = 984;
u8 intg_time_hsb, intg_time_msb, intg_time_lsb;
uint8_t gain_lsb, gain_hsb;
@@ -533,9 +530,10 @@
gain_lsb = (uint8_t) (gain);
gain_hsb = (uint8_t)((gain & 0x300)>>8);
+ s_ctrl->func_tbl->sensor_group_hold_on(s_ctrl);
+
/* adjust frame rate */
if (line > 980 && line <= 984) {
-
msm_camera_i2c_write(s_ctrl->sensor_i2c_client,
s_ctrl->sensor_output_reg_addr->frame_length_lines,
(uint8_t)((line+4) >> 8),
@@ -546,7 +544,7 @@
(uint8_t)((line+4) & 0x00FF),
MSM_CAMERA_I2C_BYTE_DATA);
max_line = line + 4;
- } else if (line > 984) {
+ } else if (max_line > 984) {
msm_camera_i2c_write(s_ctrl->sensor_i2c_client,
s_ctrl->sensor_output_reg_addr->frame_length_lines,
@@ -566,7 +564,6 @@
intg_time_msb = (u8) ((line & 0xFF00) >> 8);
intg_time_lsb = (u8) (line & 0x00FF);
- s_ctrl->func_tbl->sensor_group_hold_on(s_ctrl);
/* Coarse Integration Time */
msm_camera_i2c_write(s_ctrl->sensor_i2c_client,
diff --git a/drivers/mmc/core/sdio_irq.c b/drivers/mmc/core/sdio_irq.c
index 28505636..d489233 100644
--- a/drivers/mmc/core/sdio_irq.c
+++ b/drivers/mmc/core/sdio_irq.c
@@ -31,6 +31,17 @@
{
int i, ret, count;
unsigned char pending;
+ struct sdio_func *func;
+
+ /*
+ * Optimization, if there is only 1 function interrupt registered
+ * call irq handler directly
+ */
+ func = card->sdio_single_irq;
+ if (func) {
+ func->irq_handler(func);
+ return 1;
+ }
ret = mmc_io_rw_direct(card, 0, 0, SDIO_CCCR_INTx, 0, &pending);
if (ret) {
@@ -42,7 +53,7 @@
count = 0;
for (i = 1; i <= 7; i++) {
if (pending & (1 << i)) {
- struct sdio_func *func = card->sdio_func[i - 1];
+ func = card->sdio_func[i - 1];
if (!func) {
printk(KERN_WARNING "%s: pending IRQ for "
"non-existent function\n",
@@ -192,6 +203,24 @@
return 0;
}
+/* If there is only 1 function registered set sdio_single_irq */
+static void sdio_single_irq_set(struct mmc_card *card)
+{
+ struct sdio_func *func;
+ int i;
+
+ card->sdio_single_irq = NULL;
+ if ((card->host->caps & MMC_CAP_SDIO_IRQ) &&
+ card->host->sdio_irqs == 1)
+ for (i = 0; i < card->sdio_funcs; i++) {
+ func = card->sdio_func[i];
+ if (func && func->irq_handler) {
+ card->sdio_single_irq = func;
+ break;
+ }
+ }
+}
+
/**
* sdio_claim_irq - claim the IRQ for a SDIO function
* @func: SDIO function
@@ -233,6 +262,7 @@
ret = sdio_card_irq_get(func->card);
if (ret)
func->irq_handler = NULL;
+ sdio_single_irq_set(func->card);
return ret;
}
@@ -257,6 +287,7 @@
if (func->irq_handler) {
func->irq_handler = NULL;
sdio_card_irq_put(func->card);
+ sdio_single_irq_set(func->card);
}
ret = mmc_io_rw_direct(func->card, 0, 0, SDIO_CCCR_IENx, 0, ®);
diff --git a/drivers/mmc/host/msm_sdcc.c b/drivers/mmc/host/msm_sdcc.c
index 73a31716..0d11dca 100644
--- a/drivers/mmc/host/msm_sdcc.c
+++ b/drivers/mmc/host/msm_sdcc.c
@@ -1612,8 +1612,7 @@
if (!cmd->data || cmd->error) {
if (host->curr.data && host->dma.sg &&
host->is_dma_mode)
- msm_dmov_stop_cmd(host->dma.channel,
- &host->dma.hdr, 0);
+ msm_dmov_flush(host->dma.channel, 0);
else if (host->curr.data && host->sps.sg &&
host->is_sps_mode){
/* Stop current SPS transfer */
@@ -1766,8 +1765,7 @@
msmsdcc_data_err(host, data, status);
host->curr.data_xfered = 0;
if (host->dma.sg && host->is_dma_mode)
- msm_dmov_stop_cmd(host->dma.channel,
- &host->dma.hdr, 0);
+ msm_dmov_flush(host->dma.channel, 0);
else if (host->sps.sg && host->is_sps_mode) {
/* Stop current SPS transfer */
msmsdcc_sps_exit_curr_xfer(host);
@@ -4340,8 +4338,7 @@
mrq->data->error = -ETIMEDOUT;
host->curr.data_xfered = 0;
if (host->dma.sg && host->is_dma_mode) {
- msm_dmov_stop_cmd(host->dma.channel,
- &host->dma.hdr, 0);
+ msm_dmov_flush(host->dma.channel, 0);
} else if (host->sps.sg && host->is_sps_mode) {
/* Stop current SPS transfer */
msmsdcc_sps_exit_curr_xfer(host);
diff --git a/drivers/tty/serial/msm_serial_hs.c b/drivers/tty/serial/msm_serial_hs.c
index f559160..d310381 100644
--- a/drivers/tty/serial/msm_serial_hs.c
+++ b/drivers/tty/serial/msm_serial_hs.c
@@ -769,8 +769,7 @@
*/
mb();
/* do discard flush */
- msm_dmov_stop_cmd(msm_uport->dma_rx_channel,
- &msm_uport->rx.xfer, 0);
+ msm_dmov_flush(msm_uport->dma_rx_channel, 0);
}
msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg);
@@ -831,8 +830,7 @@
if (msm_uport->rx.flush == FLUSH_NONE) {
wake_lock(&msm_uport->rx.wake_lock);
/* do discard flush */
- msm_dmov_stop_cmd(msm_uport->dma_rx_channel,
- &msm_uport->rx.xfer, 0);
+ msm_dmov_flush(msm_uport->dma_rx_channel, 0);
}
if (msm_uport->rx.flush != FLUSH_SHUTDOWN)
msm_uport->rx.flush = FLUSH_STOP;
diff --git a/include/linux/mmc/card.h b/include/linux/mmc/card.h
index 8a0c4d5..aa808dc 100644
--- a/include/linux/mmc/card.h
+++ b/include/linux/mmc/card.h
@@ -228,6 +228,7 @@
struct sdio_cccr cccr; /* common card info */
struct sdio_cis cis; /* common tuple info */
struct sdio_func *sdio_func[SDIO_MAX_FUNCS]; /* SDIO functions (devices) */
+ struct sdio_func *sdio_single_irq; /* SDIO function when only one IRQ active */
unsigned num_info; /* number of info strings */
const char **info; /* info strings */
struct sdio_func_tuple *tuples; /* unknown common tuples */