| commit | a93706853ab4555328cffc04eb85ac25c6e462d7 | [log] [tgz] |
|---|---|---|
| author | Padmanabhan Komanduru <pkomandu@codeaurora.org> | Thu Nov 28 17:54:10 2013 +0530 |
| committer | Padmanabhan Komanduru <pkomandu@codeaurora.org> | Wed Jan 08 15:58:58 2014 +0530 |
| tree | c57202e29689d79b11038e5c17d748d3c8a7f903 | |
| parent | 309bfae5e7bdc4ae503542fe728ea9ab99792714 [diff] |
msm: clock-mdss: Update the PLL lock sequence for 8x26 During suspend/resume stress tests, the DSI PLL is not getting locked after MDDF1CE sequence. Update the PLL lock sequence for 8x26 with the recommended and fine tuned settings. The new sequence is now MMDDF1CE. Also, update the PLL_LKDET_CFG2 setting for 8974. Change-Id: Ieef831ea48e6d2b95621f87dee5dc655f448bbe4 Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>