Merge "msm: clock-local: Move GFX3D core reset from reg_init() to post_init()" into msm-3.0
diff --git a/arch/arm/mach-msm/clock-8960.c b/arch/arm/mach-msm/clock-8960.c
index 93d0d2d..af8f0af 100644
--- a/arch/arm/mach-msm/clock-8960.c
+++ b/arch/arm/mach-msm/clock-8960.c
@@ -5899,18 +5899,6 @@
writel_relaxed(0, SW_RESET_CORE_REG);
writel_relaxed(0, SW_RESET_CORE2_REG);
- /* Reset 3D core once more, with its clock enabled. This can
- * eventually be done as part of the GDFS footswitch driver. */
- clk_set_rate(&gfx3d_clk.c, 27000000);
- clk_prepare_enable(&gfx3d_clk.c);
- writel_relaxed(BIT(12), SW_RESET_CORE_REG);
- mb();
- udelay(5);
- writel_relaxed(0, SW_RESET_CORE_REG);
- /* Make sure reset is de-asserted before clock is disabled. */
- mb();
- clk_disable_unprepare(&gfx3d_clk.c);
-
/* Enable TSSC and PDM PXO sources. */
writel_relaxed(BIT(11), TSSC_CLK_CTL_REG);
writel_relaxed(BIT(15), PDM_CLK_NS_REG);
@@ -6054,6 +6042,14 @@
/* Keep PXO on whenever APPS cpu is active */
clk_prepare_enable(&pxo_a_clk.c);
+ /* Reset 3D core while clocked to ensure it resets completely. */
+ clk_set_rate(&gfx3d_clk.c, 27000000);
+ clk_prepare_enable(&gfx3d_clk.c);
+ clk_reset(&gfx3d_clk.c, CLK_RESET_ASSERT);
+ udelay(5);
+ clk_reset(&gfx3d_clk.c, CLK_RESET_DEASSERT);
+ clk_disable_unprepare(&gfx3d_clk.c);
+
/* Initialize rates for clocks that only support one. */
clk_set_rate(&pdm_clk.c, 27000000);
clk_set_rate(&prng_clk.c, 64000000);
diff --git a/arch/arm/mach-msm/clock-8x60.c b/arch/arm/mach-msm/clock-8x60.c
index ad8c936..c724414 100644
--- a/arch/arm/mach-msm/clock-8x60.c
+++ b/arch/arm/mach-msm/clock-8x60.c
@@ -3813,18 +3813,6 @@
/* Deassert all MM core resets. */
writel_relaxed(0, SW_RESET_CORE_REG);
- /* Reset 3D core once more, with its clock enabled. This can
- * eventually be done as part of the GDFS footswitch driver. */
- clk_set_rate(&gfx3d_clk.c, 27000000);
- clk_prepare_enable(&gfx3d_clk.c);
- writel_relaxed(BIT(12), SW_RESET_CORE_REG);
- mb();
- udelay(5);
- writel_relaxed(0, SW_RESET_CORE_REG);
- /* Make sure reset is de-asserted before clock is disabled. */
- mb();
- clk_disable_unprepare(&gfx3d_clk.c);
-
/* Enable TSSC and PDM PXO sources. */
writel_relaxed(BIT(11), TSSC_CLK_CTL_REG);
writel_relaxed(BIT(15), PDM_CLK_NS_REG);
@@ -3838,6 +3826,14 @@
/* Keep PXO on whenever APPS cpu is active */
clk_prepare_enable(&pxo_a_clk.c);
+ /* Reset 3D core while clocked to ensure it resets completely. */
+ clk_set_rate(&gfx3d_clk.c, 27000000);
+ clk_prepare_enable(&gfx3d_clk.c);
+ clk_reset(&gfx3d_clk.c, CLK_RESET_ASSERT);
+ udelay(5);
+ clk_reset(&gfx3d_clk.c, CLK_RESET_DEASSERT);
+ clk_disable_unprepare(&gfx3d_clk.c);
+
/* Initialize rates for clocks that only support one. */
clk_set_rate(&pdm_clk.c, 27000000);
clk_set_rate(&prng_clk.c, 64000000);