msm: 9615: Enable RPM and MPM support for MSM9615
Change-Id: I9bf9f07fd8778f302eba94a0f8d4ac329d19002e
Signed-off-by: Praveen Chidambaram <pchidamb@codeaurora.org>
Conflicts:
arch/arm/mach-msm/board-9615.c
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index 8f7c692..7341853 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -161,6 +161,7 @@
select CPU_V7
select MSM_V2_TLMM
select MSM_GPIOMUX
+ select MSM_RPM
endmenu
choice
diff --git a/arch/arm/mach-msm/board-9615.c b/arch/arm/mach-msm/board-9615.c
index e53334c..ed93c3a 100644
--- a/arch/arm/mach-msm/board-9615.c
+++ b/arch/arm/mach-msm/board-9615.c
@@ -36,6 +36,7 @@
&msm_device_sps,
&msm9615_device_tsens,
&msm_device_nand,
+ &msm_rpm_device,
};
static struct pm8xxx_irq_platform_data pm8xxx_irq_pdata __devinitdata = {
diff --git a/arch/arm/mach-msm/devices-9615.c b/arch/arm/mach-msm/devices-9615.c
index e25b1f0..9521d0e 100644
--- a/arch/arm/mach-msm/devices-9615.c
+++ b/arch/arm/mach-msm/devices-9615.c
@@ -22,11 +22,16 @@
#include <mach/msm_iomap.h>
#include <mach/irqs.h>
#include <mach/socinfo.h>
+#include <mach/rpm.h>
#include <asm/hardware/cache-l2x0.h>
#include <mach/msm_sps.h>
#include <mach/dma.h>
#include "devices.h"
#include "acpuclock.h"
+#include "mpm.h"
+#include "spm.h"
+#include "pm.h"
+#include "rpm_resources.h"
/* Address of GSBI blocks */
#define MSM_GSBI1_PHYS 0x16000000
@@ -389,10 +394,175 @@
static int __init l2x0_cache_init(void){ return 0; }
#endif
+struct msm_rpm_map_data rpm_map_data[] __initdata = {
+ MSM_RPM_MAP(TRIGGER_TIMED_TO, TRIGGER_TIMED, 1),
+ MSM_RPM_MAP(TRIGGER_TIMED_SCLK_COUNT, TRIGGER_TIMED, 1),
+
+ MSM_RPM_MAP(RPM_CTL, RPM_CTL, 1),
+
+ MSM_RPM_MAP(CXO_CLK, CXO_CLK, 1),
+ MSM_RPM_MAP(SYSTEM_FABRIC_CLK, SYSTEM_FABRIC_CLK, 1),
+ MSM_RPM_MAP(DAYTONA_FABRIC_CLK, DAYTONA_FABRIC_CLK, 1),
+ MSM_RPM_MAP(SFPB_CLK, SFPB_CLK, 1),
+ MSM_RPM_MAP(CFPB_CLK, CFPB_CLK, 1),
+ MSM_RPM_MAP(EBI1_CLK, EBI1_CLK, 1),
+
+ MSM_RPM_MAP(SYS_FABRIC_CFG_HALT_0, SYS_FABRIC_CFG_HALT, 2),
+ MSM_RPM_MAP(SYS_FABRIC_CFG_CLKMOD_0, SYS_FABRIC_CFG_CLKMOD, 3),
+ MSM_RPM_MAP(SYS_FABRIC_CFG_IOCTL, SYS_FABRIC_CFG_IOCTL, 1),
+ MSM_RPM_MAP(SYSTEM_FABRIC_ARB_0, SYSTEM_FABRIC_ARB, 27),
+
+ MSM_RPM_MAP(PM8018_S1_0, PM8018_S1, 2),
+ MSM_RPM_MAP(PM8018_S2_0, PM8018_S2, 2),
+ MSM_RPM_MAP(PM8018_S3_0, PM8018_S3, 2),
+ MSM_RPM_MAP(PM8018_S4_0, PM8018_S4, 2),
+ MSM_RPM_MAP(PM8018_S5_0, PM8018_S5, 2),
+ MSM_RPM_MAP(PM8018_L1_0, PM8018_L1, 2),
+ MSM_RPM_MAP(PM8018_L2_0, PM8018_L2, 2),
+ MSM_RPM_MAP(PM8018_L3_0, PM8018_L3, 2),
+ MSM_RPM_MAP(PM8018_L4_0, PM8018_L4, 2),
+ MSM_RPM_MAP(PM8018_L5_0, PM8018_L5, 2),
+ MSM_RPM_MAP(PM8018_L6_0, PM8018_L6, 2),
+ MSM_RPM_MAP(PM8018_L7_0, PM8018_L7, 2),
+ MSM_RPM_MAP(PM8018_L8_0, PM8018_L8, 2),
+ MSM_RPM_MAP(PM8018_L9_0, PM8018_L9, 2),
+ MSM_RPM_MAP(PM8018_L10_0, PM8018_L10, 2),
+ MSM_RPM_MAP(PM8018_L11_0, PM8018_L11, 2),
+ MSM_RPM_MAP(PM8018_L12_0, PM8018_L12, 2),
+ MSM_RPM_MAP(PM8018_L13_0, PM8018_L13, 2),
+ MSM_RPM_MAP(PM8018_L14_0, PM8018_L14, 2),
+ MSM_RPM_MAP(PM8018_LVS1, PM8018_LVS1, 1),
+ MSM_RPM_MAP(NCP_0, NCP, 2),
+ MSM_RPM_MAP(CXO_BUFFERS, CXO_BUFFERS, 1),
+ MSM_RPM_MAP(USB_OTG_SWITCH, USB_OTG_SWITCH, 1),
+ MSM_RPM_MAP(HDMI_SWITCH, HDMI_SWITCH, 1),
+};
+unsigned int rpm_map_data_size = ARRAY_SIZE(rpm_map_data);
+
+static struct msm_rpm_platform_data msm_rpm_data = {
+ .reg_base_addrs = {
+ [MSM_RPM_PAGE_STATUS] = MSM_RPM_BASE,
+ [MSM_RPM_PAGE_CTRL] = MSM_RPM_BASE + 0x400,
+ [MSM_RPM_PAGE_REQ] = MSM_RPM_BASE + 0x600,
+ [MSM_RPM_PAGE_ACK] = MSM_RPM_BASE + 0xa00,
+ },
+
+ .irq_ack = RPM_APCC_CPU0_GP_HIGH_IRQ,
+ .irq_err = RPM_APCC_CPU0_GP_LOW_IRQ,
+ .irq_vmpm = RPM_APCC_CPU0_GP_MEDIUM_IRQ,
+ .msm_apps_ipc_rpm_reg = MSM_APCS_GCC_BASE + 0x008,
+ .msm_apps_ipc_rpm_val = 4,
+};
+
+struct platform_device msm_rpm_device = {
+ .name = "msm_rpm",
+ .id = -1,
+};
+
+static uint16_t msm_mpm_irqs_m2a[MSM_MPM_NR_MPM_IRQS] = {
+ [1] = MSM_GPIO_TO_INT(46),
+ [2] = MSM_GPIO_TO_INT(150),
+ [4] = MSM_GPIO_TO_INT(103),
+ [5] = MSM_GPIO_TO_INT(104),
+ [6] = MSM_GPIO_TO_INT(105),
+ [7] = MSM_GPIO_TO_INT(106),
+ [8] = MSM_GPIO_TO_INT(107),
+ [9] = MSM_GPIO_TO_INT(7),
+ [10] = MSM_GPIO_TO_INT(11),
+ [11] = MSM_GPIO_TO_INT(15),
+ [12] = MSM_GPIO_TO_INT(19),
+ [13] = MSM_GPIO_TO_INT(23),
+ [14] = MSM_GPIO_TO_INT(27),
+ [15] = MSM_GPIO_TO_INT(31),
+ [16] = MSM_GPIO_TO_INT(35),
+ [19] = MSM_GPIO_TO_INT(90),
+ [20] = MSM_GPIO_TO_INT(92),
+ [23] = MSM_GPIO_TO_INT(85),
+ [24] = MSM_GPIO_TO_INT(83),
+ [25] = USB1_HS_IRQ,
+ /*[27] = HDMI_IRQ,*/
+ [29] = MSM_GPIO_TO_INT(10),
+ [30] = MSM_GPIO_TO_INT(102),
+ [31] = MSM_GPIO_TO_INT(81),
+ [32] = MSM_GPIO_TO_INT(78),
+ [33] = MSM_GPIO_TO_INT(94),
+ [34] = MSM_GPIO_TO_INT(72),
+ [35] = MSM_GPIO_TO_INT(39),
+ [36] = MSM_GPIO_TO_INT(43),
+ [37] = MSM_GPIO_TO_INT(61),
+ [38] = MSM_GPIO_TO_INT(50),
+ [39] = MSM_GPIO_TO_INT(42),
+ [41] = MSM_GPIO_TO_INT(62),
+ [42] = MSM_GPIO_TO_INT(76),
+ [43] = MSM_GPIO_TO_INT(75),
+ [44] = MSM_GPIO_TO_INT(70),
+ [45] = MSM_GPIO_TO_INT(69),
+ [46] = MSM_GPIO_TO_INT(67),
+ [47] = MSM_GPIO_TO_INT(65),
+ [48] = MSM_GPIO_TO_INT(58),
+ [49] = MSM_GPIO_TO_INT(54),
+ [50] = MSM_GPIO_TO_INT(52),
+ [51] = MSM_GPIO_TO_INT(49),
+ [52] = MSM_GPIO_TO_INT(40),
+ [53] = MSM_GPIO_TO_INT(37),
+ [54] = MSM_GPIO_TO_INT(24),
+ [55] = MSM_GPIO_TO_INT(14),
+};
+
+static uint16_t msm_mpm_bypassed_apps_irqs[] = {
+ TLMM_MSM_SUMMARY_IRQ,
+ RPM_APCC_CPU0_GP_HIGH_IRQ,
+ RPM_APCC_CPU0_GP_MEDIUM_IRQ,
+ RPM_APCC_CPU0_GP_LOW_IRQ,
+ RPM_APCC_CPU0_WAKE_UP_IRQ,
+ LPASS_SCSS_GP_LOW_IRQ,
+ LPASS_SCSS_GP_MEDIUM_IRQ,
+ LPASS_SCSS_GP_HIGH_IRQ,
+ SPS_MTI_31,
+};
+
+struct msm_mpm_device_data msm_mpm_dev_data = {
+ .irqs_m2a = msm_mpm_irqs_m2a,
+ .irqs_m2a_size = ARRAY_SIZE(msm_mpm_irqs_m2a),
+ .bypassed_apps_irqs = msm_mpm_bypassed_apps_irqs,
+ .bypassed_apps_irqs_size = ARRAY_SIZE(msm_mpm_bypassed_apps_irqs),
+ .mpm_request_reg_base = MSM_RPM_BASE + 0x9d8,
+ .mpm_status_reg_base = MSM_RPM_BASE + 0xdf8,
+ .mpm_apps_ipc_reg = MSM_APCS_GCC_BASE + 0x008,
+ .mpm_apps_ipc_val = BIT(1),
+ .mpm_ipc_irq = RPM_APCC_CPU0_GP_MEDIUM_IRQ,
+
+};
+
+static struct msm_rpmrs_level msm_rpmrs_levels[] __initdata = {
+ {
+ MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT,
+ MSM_RPMRS_LIMITS(ON, ACTIVE, MAX, ACTIVE),
+ true,
+ 1, 8000, 100000, 1,
+ },
+
+ {
+ MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE,
+ MSM_RPMRS_LIMITS(ON, ACTIVE, MAX, ACTIVE),
+ true,
+ 1500, 5000, 60100000, 3000,
+ },
+ {
+ MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
+ MSM_RPMRS_LIMITS(ON, ACTIVE, MAX, ACTIVE),
+ false,
+ 2800, 5000, 60350000, 3500,
+ },
+};
+
void __init msm9615_device_init(void)
{
msm_clock_init(&msm9615_clock_init_data);
acpuclk_init(&acpuclk_9615_soc_data);
+ BUG_ON(msm_rpm_init(&msm_rpm_data));
+ BUG_ON(msm_rpmrs_levels_init(msm_rpmrs_levels,
+ ARRAY_SIZE(msm_rpmrs_levels)));
}
#define MSM_SHARED_RAM_PHYS 0x40000000
diff --git a/arch/arm/mach-msm/include/mach/rpm-9615.h b/arch/arm/mach-msm/include/mach/rpm-9615.h
new file mode 100644
index 0000000..f6a0e16
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/rpm-9615.h
@@ -0,0 +1,276 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ARCH_ARM_MACH_MSM_RPM_9615_H
+#define __ARCH_ARM_MACH_MSM_RPM_9615_H
+
+#define RPM_MAJOR_VER 3
+#define RPM_MINOR_VER 0
+#define RPM_BUILD_VER 0
+
+/* RPM control message RAM enums */
+enum {
+ MSM_RPM_CTRL_VERSION_MAJOR,
+ MSM_RPM_CTRL_VERSION_MINOR,
+ MSM_RPM_CTRL_VERSION_BUILD,
+
+ MSM_RPM_CTRL_REQ_CTX_0,
+ MSM_RPM_CTRL_REQ_CTX_7 = MSM_RPM_CTRL_REQ_CTX_0 + 7,
+ MSM_RPM_CTRL_REQ_SEL_0,
+ MSM_RPM_CTRL_REQ_SEL_3 = MSM_RPM_CTRL_REQ_SEL_0 + 3,
+ MSM_RPM_CTRL_ACK_CTX_0,
+ MSM_RPM_CTRL_ACK_CTX_7 = MSM_RPM_CTRL_ACK_CTX_0 + 7,
+ MSM_RPM_CTRL_ACK_SEL_0,
+ MSM_RPM_CTRL_ACK_SEL_7 = MSM_RPM_CTRL_ACK_SEL_0 + 7,
+};
+
+
+/* RPM resource select enums defined for RPM core
+ NOT IN SEQUENTIAL ORDER */
+enum {
+ MSM_RPM_SEL_NOTIFICATION = 0,
+ MSM_RPM_SEL_INVALIDATE = 1,
+ MSM_RPM_SEL_TRIGGER_TIMED = 2,
+ MSM_RPM_SEL_RPM_CTL = 3,
+
+ MSM_RPM_SEL_CXO_CLK = 5,
+ MSM_RPM_SEL_SYSTEM_FABRIC_CLK = 9,
+ MSM_RPM_SEL_DAYTONA_FABRIC_CLK = 11,
+ MSM_RPM_SEL_SFPB_CLK = 12,
+ MSM_RPM_SEL_CFPB_CLK = 13,
+ MSM_RPM_SEL_EBI1_CLK = 16,
+
+ MSM_RPM_SEL_SYS_FABRIC_CFG_HALT = 22,
+ MSM_RPM_SEL_SYS_FABRIC_CFG_CLKMOD = 23,
+ MSM_RPM_SEL_SYS_FABRIC_CFG_IOCTL = 24,
+ MSM_RPM_SEL_SYSTEM_FABRIC_ARB = 25,
+
+ MSM_RPM_SEL_PM8018_S1 = 30,
+ MSM_RPM_SEL_PM8018_S2 = 31,
+ MSM_RPM_SEL_PM8018_S3 = 32,
+ MSM_RPM_SEL_PM8018_S4 = 33,
+ MSM_RPM_SEL_PM8018_S5 = 34,
+ MSM_RPM_SEL_PM8018_L1 = 35,
+ MSM_RPM_SEL_PM8018_L2 = 36,
+ MSM_RPM_SEL_PM8018_L3 = 37,
+ MSM_RPM_SEL_PM8018_L4 = 38,
+ MSM_RPM_SEL_PM8018_L5 = 39,
+ MSM_RPM_SEL_PM8018_L6 = 40,
+ MSM_RPM_SEL_PM8018_L7 = 41,
+ MSM_RPM_SEL_PM8018_L8 = 42,
+ MSM_RPM_SEL_PM8018_L9 = 43,
+ MSM_RPM_SEL_PM8018_L10 = 44,
+ MSM_RPM_SEL_PM8018_L11 = 45,
+ MSM_RPM_SEL_PM8018_L12 = 46,
+ MSM_RPM_SEL_PM8018_L13 = 47,
+ MSM_RPM_SEL_PM8018_L14 = 48,
+ MSM_RPM_SEL_PM8018_LVS1 = 49,
+
+ MSM_RPM_SEL_NCP = 80,
+ MSM_RPM_SEL_CXO_BUFFERS = 81,
+ MSM_RPM_SEL_USB_OTG_SWITCH = 82,
+ MSM_RPM_SEL_HDMI_SWITCH = 83,
+
+ MSM_RPM_SEL_LAST = MSM_RPM_SEL_HDMI_SWITCH,
+};
+
+/* RPM resource (4 byte) word ID enum */
+enum {
+ MSM_RPM_ID_NOTIFICATION_CONFIGURED_0 = 0,
+ MSM_RPM_ID_NOTIFICATION_CONFIGURED_3 =
+ MSM_RPM_ID_NOTIFICATION_CONFIGURED_0 + 3,
+
+ MSM_RPM_ID_NOTIFICATION_REGISTERED_0 = 4,
+ MSM_RPM_ID_NOTIFICATION_REGISTERED_3 =
+ MSM_RPM_ID_NOTIFICATION_REGISTERED_0 + 3,
+
+ MSM_RPM_ID_INVALIDATE_0 = 8,
+ MSM_RPM_ID_INVALIDATE_7 =
+ MSM_RPM_ID_INVALIDATE_0 + 7,
+
+ MSM_RPM_ID_TRIGGER_TIMED_TO = 16,
+ MSM_RPM_ID_TRIGGER_TIMED_SCLK_COUNT = 17,
+
+ MSM_RPM_ID_RPM_CTL = 18,
+
+ /* TRIGGER_CLEAR/SET deprecated in these 24 RESERVED bytes */
+ MSM_RPM_ID_RESERVED_0 = 19,
+ MSM_RPM_ID_RESERVED_5 =
+ MSM_RPM_ID_RESERVED_0 + 5,
+
+ MSM_RPM_ID_CXO_CLK = 25,
+ MSM_RPM_ID_SYSTEM_FABRIC_CLK = 26,
+ MSM_RPM_ID_DAYTONA_FABRIC_CLK = 27,
+ MSM_RPM_ID_SFPB_CLK = 28,
+ MSM_RPM_ID_CFPB_CLK = 29,
+ MSM_RPM_ID_EBI1_CLK = 30,
+
+ MSM_RPM_ID_SYS_FABRIC_CFG_HALT_0 = 31,
+ MSM_RPM_ID_SYS_FABRIC_CFG_HALT_1 = 32,
+ MSM_RPM_ID_SYS_FABRIC_CFG_CLKMOD_0 = 33,
+ MSM_RPM_ID_SYS_FABRIC_CFG_CLKMOD_1 = 34,
+ MSM_RPM_ID_SYS_FABRIC_CFG_CLKMOD_2 = 35,
+ MSM_RPM_ID_SYS_FABRIC_CFG_IOCTL = 36,
+ MSM_RPM_ID_SYSTEM_FABRIC_ARB_0 = 37,
+ MSM_RPM_ID_SYSTEM_FABRIC_ARB_26 =
+ MSM_RPM_ID_SYSTEM_FABRIC_ARB_0 + 26,
+
+ MSM_RPM_ID_PM8018_S1_0 = 64,
+ MSM_RPM_ID_PM8018_S1_1 = 65,
+ MSM_RPM_ID_PM8018_S2_0 = 66,
+ MSM_RPM_ID_PM8018_S2_1 = 67,
+ MSM_RPM_ID_PM8018_S3_0 = 68,
+ MSM_RPM_ID_PM8018_S3_1 = 69,
+ MSM_RPM_ID_PM8018_S4_0 = 70,
+ MSM_RPM_ID_PM8018_S4_1 = 71,
+ MSM_RPM_ID_PM8018_S5_0 = 72,
+ MSM_RPM_ID_PM8018_S5_1 = 73,
+ MSM_RPM_ID_PM8018_L1_0 = 74,
+ MSM_RPM_ID_PM8018_L1_1 = 75,
+ MSM_RPM_ID_PM8018_L2_0 = 76,
+ MSM_RPM_ID_PM8018_L2_1 = 77,
+ MSM_RPM_ID_PM8018_L3_0 = 78,
+ MSM_RPM_ID_PM8018_L3_1 = 79,
+ MSM_RPM_ID_PM8018_L4_0 = 80,
+ MSM_RPM_ID_PM8018_L4_1 = 81,
+ MSM_RPM_ID_PM8018_L5_0 = 82,
+ MSM_RPM_ID_PM8018_L5_1 = 83,
+ MSM_RPM_ID_PM8018_L6_0 = 84,
+ MSM_RPM_ID_PM8018_L6_1 = 85,
+ MSM_RPM_ID_PM8018_L7_0 = 86,
+ MSM_RPM_ID_PM8018_L7_1 = 87,
+ MSM_RPM_ID_PM8018_L8_0 = 88,
+ MSM_RPM_ID_PM8018_L8_1 = 89,
+ MSM_RPM_ID_PM8018_L9_0 = 90,
+ MSM_RPM_ID_PM8018_L9_1 = 91,
+ MSM_RPM_ID_PM8018_L10_0 = 92,
+ MSM_RPM_ID_PM8018_L10_1 = 93,
+ MSM_RPM_ID_PM8018_L11_0 = 94,
+ MSM_RPM_ID_PM8018_L11_1 = 95,
+ MSM_RPM_ID_PM8018_L12_0 = 96,
+ MSM_RPM_ID_PM8018_L12_1 = 97,
+ MSM_RPM_ID_PM8018_L13_0 = 98,
+ MSM_RPM_ID_PM8018_L13_1 = 99,
+ MSM_RPM_ID_PM8018_L14_0 = 100,
+ MSM_RPM_ID_PM8018_L14_1 = 101,
+ MSM_RPM_ID_PM8018_LVS1 = 102,
+
+ MSM_RPM_ID_NCP_0 = 103,
+ MSM_RPM_ID_NCP_1 = 104,
+ MSM_RPM_ID_CXO_BUFFERS = 105,
+ MSM_RPM_ID_USB_OTG_SWITCH = 106,
+ MSM_RPM_ID_HDMI_SWITCH = 107,
+
+ MSM_RPM_ID_LAST = MSM_RPM_ID_HDMI_SWITCH,
+};
+
+/* RPM resources RPM_ID aliases */
+enum {
+ MSM_RPMRS_ID_RPM_CTL = MSM_RPM_ID_RPM_CTL,
+ /* XO clock for this target is CXO */
+ MSM_RPMRS_ID_PXO_CLK = MSM_RPM_ID_CXO_CLK,
+ MSM_RPMRS_ID_VDD_DIG_0 = MSM_RPM_ID_PM8018_S1_0,
+ MSM_RPMRS_ID_VDD_DIG_1 = MSM_RPM_ID_PM8018_S1_1,
+ MSM_RPMRS_ID_VDD_MEM_0 = MSM_RPM_ID_PM8018_L9_0,
+ MSM_RPMRS_ID_VDD_MEM_1 = MSM_RPM_ID_PM8018_L9_1,
+
+ /* MSM9615 L2 cache power control not via RPM
+ * MSM_RPM_ID_LAST + 1 indicates invalid */
+ MSM_RPMRS_ID_APPS_L2_CACHE_CTL = MSM_RPM_ID_LAST + 1
+};
+
+/* VDD values are in microvolts */
+#define MSM_RPMRS_VDD_MASK 0x7fffff
+enum {
+ MSM_RPMRS_VDD_MEM_RET_LOW = 750500,
+ MSM_RPMRS_VDD_MEM_RET_HIGH = 1050000,
+ MSM_RPMRS_VDD_MEM_ACTIVE = 1050000,
+ MSM_RPMRS_VDD_MEM_MAX = 1250000,
+};
+
+enum {
+ MSM_RPMRS_VDD_DIG_RET_LOW = 537500,
+ MSM_RPMRS_VDD_DIG_RET_HIGH = 950000,
+ MSM_RPMRS_VDD_DIG_ACTIVE = 1050000,
+ MSM_RPMRS_VDD_DIG_MAX = 1250000,
+};
+
+/* RPM status ID enum */
+enum {
+ MSM_RPM_STATUS_ID_VERSION_MAJOR = 0,
+ MSM_RPM_STATUS_ID_VERSION_MINOR = 1,
+ MSM_RPM_STATUS_ID_VERSION_BUILD = 2,
+ MSM_RPM_STATUS_ID_SUPPORTED_RESOURCES_0 = 3,
+ MSM_RPM_STATUS_ID_SUPPORTED_RESOURCES_1 = 4,
+ MSM_RPM_STATUS_ID_SUPPORTED_RESOURCES_2 = 5,
+ MSM_RPM_STATUS_ID_RESERVED_SUPPORTED_RESOURCES_0 = 6,
+ MSM_RPM_STATUS_ID_SEQUENCE = 7,
+ MSM_RPM_STATUS_ID_RPM_CTL = 8,
+ MSM_RPM_STATUS_ID_CXO_CLK = 9,
+ MSM_RPM_STATUS_ID_SYSTEM_FABRIC_CLK = 10,
+ MSM_RPM_STATUS_ID_DAYTONA_FABRIC_CLK = 11,
+ MSM_RPM_STATUS_ID_SFPB_CLK = 12,
+ MSM_RPM_STATUS_ID_CFPB_CLK = 13,
+ MSM_RPM_STATUS_ID_EBI1_CLK = 14,
+ MSM_RPM_STATUS_ID_SYS_FABRIC_CFG_HALT = 15,
+ MSM_RPM_STATUS_ID_SYS_FABRIC_CFG_CLKMOD = 16,
+ MSM_RPM_STATUS_ID_SYS_FABRIC_CFG_IOCTL = 17,
+ MSM_RPM_STATUS_ID_SYSTEM_FABRIC_ARB = 18,
+ MSM_RPM_STATUS_ID_PM8018_S1_0 = 19,
+ MSM_RPM_STATUS_ID_PM8018_S1_1 = 20,
+ MSM_RPM_STATUS_ID_PM8018_S2_0 = 21,
+ MSM_RPM_STATUS_ID_PM8018_S2_1 = 22,
+ MSM_RPM_STATUS_ID_PM8018_S3_0 = 23,
+ MSM_RPM_STATUS_ID_PM8018_S3_1 = 24,
+ MSM_RPM_STATUS_ID_PM8018_S4_0 = 25,
+ MSM_RPM_STATUS_ID_PM8018_S4_1 = 26,
+ MSM_RPM_STATUS_ID_PM8018_S5_0 = 27,
+ MSM_RPM_STATUS_ID_PM8018_S5_1 = 28,
+ MSM_RPM_STATUS_ID_PM8018_L1_0 = 29,
+ MSM_RPM_STATUS_ID_PM8018_L1_1 = 30,
+ MSM_RPM_STATUS_ID_PM8018_L2_0 = 31,
+ MSM_RPM_STATUS_ID_PM8018_L2_1 = 32,
+ MSM_RPM_STATUS_ID_PM8018_L3_0 = 33,
+ MSM_RPM_STATUS_ID_PM8018_L3_1 = 34,
+ MSM_RPM_STATUS_ID_PM8018_L4_0 = 35,
+ MSM_RPM_STATUS_ID_PM8018_L4_1 = 36,
+ MSM_RPM_STATUS_ID_PM8018_L5_0 = 37,
+ MSM_RPM_STATUS_ID_PM8018_L5_1 = 38,
+ MSM_RPM_STATUS_ID_PM8018_L6_0 = 39,
+ MSM_RPM_STATUS_ID_PM8018_L6_1 = 40,
+ MSM_RPM_STATUS_ID_PM8018_L7_0 = 41,
+ MSM_RPM_STATUS_ID_PM8018_L7_1 = 42,
+ MSM_RPM_STATUS_ID_PM8018_L8_0 = 43,
+ MSM_RPM_STATUS_ID_PM8018_L8_1 = 44,
+ MSM_RPM_STATUS_ID_PM8018_L9_0 = 45,
+ MSM_RPM_STATUS_ID_PM8018_L9_1 = 46,
+ MSM_RPM_STATUS_ID_PM8018_L10_0 = 47,
+ MSM_RPM_STATUS_ID_PM8018_L10_1 = 48,
+ MSM_RPM_STATUS_ID_PM8018_L11_0 = 49,
+ MSM_RPM_STATUS_ID_PM8018_L11_1 = 50,
+ MSM_RPM_STATUS_ID_PM8018_L12_0 = 51,
+ MSM_RPM_STATUS_ID_PM8018_L12_1 = 52,
+ MSM_RPM_STATUS_ID_PM8018_L13_0 = 53,
+ MSM_RPM_STATUS_ID_PM8018_L13_1 = 54,
+ MSM_RPM_STATUS_ID_PM8018_L14_0 = 55,
+ MSM_RPM_STATUS_ID_PM8018_L14_1 = 56,
+ MSM_RPM_STATUS_ID_PM8018_LVS1 = 57,
+ MSM_RPM_STATUS_ID_NCP_0 = 58,
+ MSM_RPM_STATUS_ID_NCP_1 = 59,
+ MSM_RPM_STATUS_ID_CXO_BUFFERS = 60,
+ MSM_RPM_STATUS_ID_USB_OTG_SWITCH = 61,
+ MSM_RPM_STATUS_ID_HDMI_SWITCH = 62,
+
+ MSM_RPM_STATUS_ID_LAST = MSM_RPM_STATUS_ID_HDMI_SWITCH,
+};
+
+#endif /* __ARCH_ARM_MACH_MSM_RPM_9615_H */
diff --git a/arch/arm/mach-msm/include/mach/rpm.h b/arch/arm/mach-msm/include/mach/rpm.h
index a4928c4..dda9954 100644
--- a/arch/arm/mach-msm/include/mach/rpm.h
+++ b/arch/arm/mach-msm/include/mach/rpm.h
@@ -20,6 +20,8 @@
#if defined(CONFIG_ARCH_MSM8X60)
#include <mach/rpm-8660.h>
+#elif defined(CONFIG_ARCH_MSM9615)
+#include <mach/rpm-9615.h>
#elif defined(CONFIG_ARCH_MSM8960)
#include <mach/rpm-8960.h>
#endif