Merge "msm: iommu: Support the secure domains"
diff --git a/Documentation/devicetree/bindings/arm/msm/spm-v2.txt b/Documentation/devicetree/bindings/arm/msm/spm-v2.txt
index 1a19dbb..a2d8359 100644
--- a/Documentation/devicetree/bindings/arm/msm/spm-v2.txt
+++ b/Documentation/devicetree/bindings/arm/msm/spm-v2.txt
@@ -33,8 +33,10 @@
between AVS controller requests
- qcom,saw2-pmic-data0..7: Specify the pmic data value and the associated FTS
index to send the PMIC data to
-- qcom,saw2-vctl-port: The FTS port used for changing voltage
-- qcom,saw2-phase-port: The FTS port used for changing the number of phases
+- qcom,saw2-vctl-port: The PVC (PMIC Virtual Channel) port used for changing
+ voltage
+- qcom,saw2-phase-port: The PVC port used for changing the number of phases
+- qcom,saw2-pfm-port: The PVC port used for enabling PWM/PFM modes
- qcom,saw2-spm-cmd-wfi: The WFI command sequence
- qcom,saw2-spm-cmd-ret: The Retention command sequence
- qcom,saw2-spm-cmd-spc: The Standalone PC command sequence
diff --git a/Documentation/devicetree/bindings/thermal/tsens.txt b/Documentation/devicetree/bindings/thermal/tsens.txt
index c683f58..0682cd1 100644
--- a/Documentation/devicetree/bindings/thermal/tsens.txt
+++ b/Documentation/devicetree/bindings/thermal/tsens.txt
@@ -17,10 +17,12 @@
- reg : offset and length of the QFPROM registers used for storing
the calibration data for the individual sensors.
- reg-names : resource names used for the physical address of the TSENS
- registers and the QFPROM efuse calibration address.
- Should be "tsens_physical" for physical address of the TSENS
- and "tsens_eeprom_physical" for physical address where calibration
- data is stored.
+ registers, the QFPROM efuse primary calibration address region,
+ Should be "tsens_physical" for physical address of the TSENS,
+ "tsens_eeprom_physical" for physical address where primary
+ calibration data is stored. This includes the backup
+ calibration address region if TSENS calibration data is stored
+ in the region.
- interrupts : TSENS interrupt for cool/warm temperature threshold.
- qcom,sensors : Total number of available Temperature sensors for TSENS.
- qcom,slope : One point calibration characterized slope data for each
@@ -28,14 +30,20 @@
as ADC code/DegC and the value is multipled by a factor
of 1000.
+Optional properties:
+- qcom,calibration-less-mode : If present the pre-characterized data for offsets
+ are used else it defaults to use calibration data from QFPROM.
+
Example:
tsens@fc4a8000 {
compatible = "qcom,msm-tsens";
reg = <0xfc4a8000 0x2000>,
- <0xfc4b80d0 0x5>;
- reg-names = "tsens_physical", "tsens_eeprom_physical";
+ <0xfc4b8000 0x1000>;
+ reg-names = "tsens_physical",
+ "tsens_eeprom_physical";
interrupts = <0 184 0>;
+ qcom,calibration-less-mode;
qcom,sensors = <11>;
qcom,slope = <1134 1122 1142 1123 1176 1176 1176 1186 1176
1176>;
diff --git a/arch/arm/boot/dts/msm8974.dtsi b/arch/arm/boot/dts/msm8974.dtsi
index 9d985bf..615a387 100644
--- a/arch/arm/boot/dts/msm8974.dtsi
+++ b/arch/arm/boot/dts/msm8974.dtsi
@@ -971,9 +971,10 @@
tsens@fc4a8000 {
compatible = "qcom,msm-tsens";
reg = <0xfc4a8000 0x2000>,
- <0xfc4b80d0 0x5>;
+ <0xfc4b8000 0x1000>;
reg-names = "tsens_physical", "tsens_eeprom_physical";
interrupts = <0 184 0>;
+ qcom,calibration-less-mode;
qcom,sensors = <11>;
qcom,slope = <3200 3200 3200 3200 3200 3200 3200 3200 3200
3200 3200>;
diff --git a/arch/arm/boot/dts/msm8974_pm.dtsi b/arch/arm/boot/dts/msm8974_pm.dtsi
index b2f3fec..c6cbca3 100644
--- a/arch/arm/boot/dts/msm8974_pm.dtsi
+++ b/arch/arm/boot/dts/msm8974_pm.dtsi
@@ -124,6 +124,7 @@
qcom,vctl-timeout-us = <50>;
qcom,vctl-port = <0x0>;
qcom,phase-port = <0x1>;
+ qcom,pfm-port = <0x2>;
qcom,saw2-spm-cmd-ret = [00 20 03 22 00 0f];
qcom,saw2-spm-cmd-gdhs = [00 20 32 42 07 44 22 50 02 32 50 0f];
qcom,saw2-spm-cmd-pc = [00 10 32 b0 11 42 07 01 b0 12 44
diff --git a/arch/arm/boot/dts/msm9625-cdp.dts b/arch/arm/boot/dts/msm9625-cdp.dts
index 6234017..89c269e 100644
--- a/arch/arm/boot/dts/msm9625-cdp.dts
+++ b/arch/arm/boot/dts/msm9625-cdp.dts
@@ -17,7 +17,7 @@
/ {
model = "Qualcomm MSM 9625 CDP";
compatible = "qcom,msm9625-cdp", "qcom,msm9625";
- qcom,msm-id = <134 1 0>;
+ qcom,msm-id = <134 1 0>, <152 1 0>;
};
/* PM8019 GPIO and MPP configuration */
diff --git a/arch/arm/boot/dts/msm9625-mtp.dts b/arch/arm/boot/dts/msm9625-mtp.dts
index be57dda..a5673e5 100644
--- a/arch/arm/boot/dts/msm9625-mtp.dts
+++ b/arch/arm/boot/dts/msm9625-mtp.dts
@@ -17,7 +17,7 @@
/ {
model = "Qualcomm MSM 9625 MTP";
compatible = "qcom,msm9625-mtp", "qcom,msm9625";
- qcom,msm-id = <134 8 0>;
+ qcom,msm-id = <134 7 0>, <152 7 0>;
};
/* PM8019 GPIO and MPP configuration */
diff --git a/arch/arm/configs/msm7627a-perf_defconfig b/arch/arm/configs/msm7627a-perf_defconfig
index 9a0bfba..f7fb77b 100644
--- a/arch/arm/configs/msm7627a-perf_defconfig
+++ b/arch/arm/configs/msm7627a-perf_defconfig
@@ -58,6 +58,7 @@
CONFIG_MSM_RPC_PMIC=y
CONFIG_MSM_RPC_USB=y
CONFIG_MSM_RPC_PMAPP=y
+CONFIG_MSM_FIQ=y
CONFIG_ARM_THUMBEE=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
@@ -167,10 +168,10 @@
CONFIG_IP_NF_ARPTABLES=y
CONFIG_IP_NF_ARPFILTER=y
CONFIG_IP_NF_ARP_MANGLE=y
-CONFIG_IP6_NF_MANGLE=y
-CONFIG_IP6_NF_RAW=y
CONFIG_IP6_NF_IPTABLES=y
CONFIG_IP6_NF_FILTER=y
+CONFIG_IP6_NF_MANGLE=y
+CONFIG_IP6_NF_RAW=y
CONFIG_ATM=y
CONFIG_L2TP=y
CONFIG_L2TP_DEBUGFS=y
@@ -378,4 +379,3 @@
CONFIG_DYNAMIC_DEBUG=y
CONFIG_DEBUG_USER=y
CONFIG_CRYPTO_TWOFISH=y
-CONFIG_CRC_CCITT=y
diff --git a/arch/arm/configs/msm7627a_defconfig b/arch/arm/configs/msm7627a_defconfig
index 60a2d72..1145c0b 100644
--- a/arch/arm/configs/msm7627a_defconfig
+++ b/arch/arm/configs/msm7627a_defconfig
@@ -60,6 +60,7 @@
CONFIG_MSM_RPC_PMIC=y
CONFIG_MSM_RPC_USB=y
CONFIG_MSM_RPC_PMAPP=y
+CONFIG_MSM_FIQ=y
CONFIG_ARM_THUMBEE=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
@@ -169,10 +170,10 @@
CONFIG_IP_NF_ARPTABLES=y
CONFIG_IP_NF_ARPFILTER=y
CONFIG_IP_NF_ARP_MANGLE=y
-CONFIG_IP6_NF_MANGLE=y
-CONFIG_IP6_NF_RAW=y
CONFIG_IP6_NF_IPTABLES=y
CONFIG_IP6_NF_FILTER=y
+CONFIG_IP6_NF_MANGLE=y
+CONFIG_IP6_NF_RAW=y
CONFIG_ATM=y
CONFIG_L2TP=y
CONFIG_L2TP_DEBUGFS=y
diff --git a/arch/arm/configs/msm7630-perf_defconfig b/arch/arm/configs/msm7630-perf_defconfig
index 401654d..f2d25ac 100644
--- a/arch/arm/configs/msm7630-perf_defconfig
+++ b/arch/arm/configs/msm7630-perf_defconfig
@@ -280,8 +280,8 @@
CONFIG_FB_MSM_TRIPLE_BUFFER=y
CONFIG_FB_MSM_MDP40=y
CONFIG_FB_MSM_OVERLAY=y
-CONFIG_FB_MSM_OVERLAY0_WRITEBACK=y
CONFIG_FB_MSM_NO_MDP_PIPE_CTRL=y
+CONFIG_FB_MSM_OVERLAY0_WRITEBACK=y
CONFIG_FB_MSM_TRY_MDDI_CATCH_LCDC_PRISM=y
CONFIG_FB_MSM_HDMI_ADV7520_PANEL=y
CONFIG_BACKLIGHT_LCD_SUPPORT=y
diff --git a/arch/arm/configs/msm8660-perf_defconfig b/arch/arm/configs/msm8660-perf_defconfig
index 957dbcf..2ee3f3b 100644
--- a/arch/arm/configs/msm8660-perf_defconfig
+++ b/arch/arm/configs/msm8660-perf_defconfig
@@ -35,8 +35,6 @@
CONFIG_DEFAULT_DEADLINE=y
CONFIG_ARCH_MSM=y
CONFIG_ARCH_MSM8X60=y
-CONFIG_MACH_MSM8X60_RUMI3=y
-CONFIG_MACH_MSM8X60_SIM=y
CONFIG_MACH_MSM8X60_SURF=y
CONFIG_MACH_MSM8X60_FFA=y
CONFIG_MACH_MSM8X60_FLUID=y
@@ -64,13 +62,13 @@
CONFIG_MSM_RMT_STORAGE_CLIENT=y
CONFIG_MSM_SDIO_SMEM=y
# CONFIG_MSM_HW3D is not set
+CONFIG_MSM_SUBSYSTEM_RESTART=y
+CONFIG_MSM_SYSMON_COMM=y
CONFIG_MSM_PIL_MODEM=y
CONFIG_MSM_PIL_QDSP6V3=y
CONFIG_MSM_PIL_TZAPPS=y
CONFIG_MSM_PIL_DSPS=y
CONFIG_MSM_PIL_VIDC=y
-CONFIG_MSM_SUBSYSTEM_RESTART=y
-CONFIG_MSM_SYSMON_COMM=y
CONFIG_MSM_TZ_LOG=y
CONFIG_MSM_RPM_LOG=y
CONFIG_MSM_RPM_STATS_LOG=y
diff --git a/arch/arm/configs/msm8660_defconfig b/arch/arm/configs/msm8660_defconfig
index 4e5479a..25c5207 100644
--- a/arch/arm/configs/msm8660_defconfig
+++ b/arch/arm/configs/msm8660_defconfig
@@ -34,8 +34,6 @@
CONFIG_DEFAULT_DEADLINE=y
CONFIG_ARCH_MSM=y
CONFIG_ARCH_MSM8X60=y
-CONFIG_MACH_MSM8X60_RUMI3=y
-CONFIG_MACH_MSM8X60_SIM=y
CONFIG_MACH_MSM8X60_SURF=y
CONFIG_MACH_MSM8X60_FFA=y
CONFIG_MACH_MSM8X60_FLUID=y
@@ -63,20 +61,19 @@
CONFIG_MSM_RMT_STORAGE_CLIENT=y
CONFIG_MSM_SDIO_SMEM=y
# CONFIG_MSM_HW3D is not set
+CONFIG_MSM_SUBSYSTEM_RESTART=y
+CONFIG_MSM_SYSMON_COMM=y
CONFIG_MSM_PIL_MODEM=y
CONFIG_MSM_PIL_QDSP6V3=y
CONFIG_MSM_PIL_TZAPPS=y
CONFIG_MSM_PIL_DSPS=y
CONFIG_MSM_PIL_VIDC=y
-CONFIG_MSM_SUBSYSTEM_RESTART=y
-CONFIG_MSM_SYSMON_COMM=y
CONFIG_MSM_TZ_LOG=y
CONFIG_MSM_RPM_LOG=y
CONFIG_MSM_RPM_STATS_LOG=y
CONFIG_MSM_WATCHDOG=y
CONFIG_MSM_DLOAD_MODE=y
CONFIG_MSM_ETM=y
-CONFIG_MSM_SLEEP_STATS=y
CONFIG_MSM_GSBI9_UART=y
CONFIG_STRICT_MEMORY_RWX=y
CONFIG_NO_HZ=y
diff --git a/arch/arm/configs/msm8960-perf_defconfig b/arch/arm/configs/msm8960-perf_defconfig
index 6a6bfda..1558e11 100644
--- a/arch/arm/configs/msm8960-perf_defconfig
+++ b/arch/arm/configs/msm8960-perf_defconfig
@@ -39,8 +39,6 @@
CONFIG_ARCH_MSM8930=y
CONFIG_ARCH_APQ8064=y
CONFIG_MSM_KRAIT_TBB_ABORT_HANDLER=y
-CONFIG_MACH_MSM8960_SIM=y
-CONFIG_MACH_MSM8960_RUMI3=y
CONFIG_MACH_MSM8960_CDP=y
CONFIG_MACH_MSM8960_MTP=y
CONFIG_MACH_MSM8960_FLUID=y
@@ -50,8 +48,6 @@
CONFIG_MACH_MSM8930_FLUID=y
CONFIG_MACH_MSM8627_CDP=y
CONFIG_MACH_MSM8627_MTP=y
-CONFIG_MACH_APQ8064_SIM=y
-CONFIG_MACH_APQ8064_RUMI3=y
CONFIG_MACH_APQ8064_CDP=y
CONFIG_MACH_APQ8064_MTP=y
CONFIG_MACH_APQ8064_LIQUID=y
@@ -66,11 +62,14 @@
CONFIG_MSM_SMD_PKG4=y
CONFIG_MSM_PCIE=y
CONFIG_MSM_BAM_DMUX=y
+CONFIG_MSM_IPC_LOGGING=y
CONFIG_MSM_DSPS=y
CONFIG_MSM_IPC_ROUTER=y
CONFIG_MSM_IPC_ROUTER_SMD_XPRT=y
CONFIG_MSM_AVS_HW=y
# CONFIG_MSM_HW3D is not set
+CONFIG_MSM_SUBSYSTEM_RESTART=y
+CONFIG_MSM_SYSMON_COMM=y
CONFIG_MSM_PIL_LPASS_QDSP6V4=y
CONFIG_MSM_PIL_MODEM_QDSP6V4=y
CONFIG_MSM_PIL_RIVA=y
@@ -78,27 +77,20 @@
CONFIG_MSM_PIL_DSPS=y
CONFIG_MSM_PIL_VIDC=y
CONFIG_MSM_PIL_GSS=y
-CONFIG_MSM_SUBSYSTEM_RESTART=y
-CONFIG_MSM_SYSMON_COMM=y
-CONFIG_MSM_MODEM_8960=y
-CONFIG_MSM_LPASS_8960=y
-CONFIG_MSM_WCNSS_SSR_8960=y
-CONFIG_MSM_GSS_SSR_8064=y
CONFIG_MSM_TZ_LOG=y
CONFIG_MSM_RPM_LOG=y
-CONFIG_MSM_RPM_RBCPR_STATS_LOG=y
CONFIG_MSM_RPM_STATS_LOG=y
+CONFIG_MSM_RPM_RBCPR_STATS_LOG=y
+CONFIG_MSM_EVENT_TIMER=y
CONFIG_MSM_BUS_SCALING=y
CONFIG_MSM_BUS_RPM_MULTI_TIER_ENABLED=y
CONFIG_MSM_WATCHDOG=y
CONFIG_MSM_DLOAD_MODE=y
-CONFIG_MSM_SLEEP_STATS=y
CONFIG_MSM_EBI_ERP=y
CONFIG_MSM_CACHE_ERP=y
CONFIG_MSM_L1_ERR_PANIC=y
CONFIG_MSM_L1_ERR_LOG=y
CONFIG_MSM_L2_ERP_2BIT_PANIC=y
-CONFIG_MSM_EVENT_TIMER=y
CONFIG_MSM_DCVS=y
CONFIG_MSM_HSIC_SYSMON=y
CONFIG_STRICT_MEMORY_RWX=y
@@ -232,7 +224,6 @@
CONFIG_NET_EMATCH_META=y
CONFIG_NET_EMATCH_TEXT=y
CONFIG_NET_CLS_ACT=y
-CONFIG_MARIMBA_CORE=y
CONFIG_BT=y
CONFIG_BT_RFCOMM=y
CONFIG_BT_RFCOMM_TTY=y
@@ -243,8 +234,8 @@
CONFIG_BT_HCISMD=y
CONFIG_BT_HCIUART=y
CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_IBS=y
CONFIG_BT_HCIUART_ATH3K=y
+CONFIG_BT_HCIUART_IBS=y
CONFIG_MSM_BT_POWER=y
CONFIG_CFG80211=m
# CONFIG_CFG80211_WEXT is not set
@@ -285,6 +276,7 @@
CONFIG_USB_USBNET=y
CONFIG_MSM_RMNET_USB=y
CONFIG_WCNSS_CORE=y
+CONFIG_WCNSS_MEM_PRE_ALLOC=y
CONFIG_INPUT_EVDEV=y
CONFIG_INPUT_EVBUG=m
CONFIG_KEYBOARD_GPIO=y
@@ -297,11 +289,10 @@
CONFIG_TOUCHSCREEN_CYTTSP_I2C_QC=y
CONFIG_INPUT_MISC=y
CONFIG_INPUT_PMIC8XXX_PWRKEY=y
+CONFIG_INPUT_MPU3050=y
CONFIG_INPUT_UINPUT=y
CONFIG_STM_LIS3DH=y
-CONFIG_INPUT_MPU3050=y
# CONFIG_LEGACY_PTYS is not set
-CONFIG_MSM_IPC_LOGGING=y
CONFIG_N_SMUX=y
CONFIG_N_SMUX_LOOPBACK=y
CONFIG_SMUX_CTL=y
@@ -335,6 +326,7 @@
CONFIG_THERMAL_TSENS8960=y
CONFIG_THERMAL_PM8XXX=y
CONFIG_THERMAL_MONITOR=y
+CONFIG_MARIMBA_CORE=y
CONFIG_MFD_PM8921_CORE=y
CONFIG_MFD_PM8821_CORE=y
CONFIG_MFD_PM8038_CORE=y
@@ -348,7 +340,6 @@
CONFIG_MEDIA_CONTROLLER=y
CONFIG_VIDEO_DEV=y
CONFIG_VIDEO_V4L2_SUBDEV_API=y
-CONFIG_MSM_WFD=y
CONFIG_USER_RC_INPUT=y
CONFIG_IR_GPIO_CIR=y
# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
@@ -373,6 +364,7 @@
CONFIG_MSM_CSI20_HEADER=y
CONFIG_S5K3L1YX=y
CONFIG_IMX091=y
+CONFIG_MSM_WFD=y
CONFIG_RADIO_IRIS=y
CONFIG_RADIO_IRIS_TRANSPORT=m
CONFIG_ION=y
@@ -438,7 +430,6 @@
CONFIG_USB_GADGET_DEBUG_FILES=y
CONFIG_USB_CI13XXX_MSM=y
CONFIG_USB_G_ANDROID=y
-CONFIG_USB_ANDROID_RMNET_CTRL_SMD=y
CONFIG_MMC=y
CONFIG_MMC_PERF_PROFILING=y
CONFIG_MMC_UNSAFE_RESUME=y
@@ -474,6 +465,7 @@
CONFIG_MOBICORE_SUPPORT=m
CONFIG_MOBICORE_API=m
CONFIG_MSM_QDSS=y
+CONFIG_CONTROL_TRACE=m
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT3_FS=y
@@ -506,5 +498,3 @@
CONFIG_CRYPTO_DEV_QCE=m
CONFIG_CRYPTO_DEV_QCEDEV=m
CONFIG_CRC_CCITT=y
-CONFIG_WCNSS_MEM_PRE_ALLOC=y
-CONFIG_CONTROL_TRACE=m
diff --git a/arch/arm/configs/msm8960_defconfig b/arch/arm/configs/msm8960_defconfig
index cf2dd23..981cdce 100644
--- a/arch/arm/configs/msm8960_defconfig
+++ b/arch/arm/configs/msm8960_defconfig
@@ -38,8 +38,6 @@
CONFIG_ARCH_MSM8930=y
CONFIG_ARCH_APQ8064=y
CONFIG_MSM_KRAIT_TBB_ABORT_HANDLER=y
-CONFIG_MACH_MSM8960_SIM=y
-CONFIG_MACH_MSM8960_RUMI3=y
CONFIG_MACH_MSM8960_CDP=y
CONFIG_MACH_MSM8960_MTP=y
CONFIG_MACH_MSM8960_FLUID=y
@@ -49,8 +47,6 @@
CONFIG_MACH_MSM8930_FLUID=y
CONFIG_MACH_MSM8627_CDP=y
CONFIG_MACH_MSM8627_MTP=y
-CONFIG_MACH_APQ8064_SIM=y
-CONFIG_MACH_APQ8064_RUMI3=y
CONFIG_MACH_APQ8064_CDP=y
CONFIG_MACH_APQ8064_MTP=y
CONFIG_MACH_APQ8064_LIQUID=y
@@ -65,11 +61,14 @@
CONFIG_MSM_SMD_PKG4=y
CONFIG_MSM_PCIE=y
CONFIG_MSM_BAM_DMUX=y
+CONFIG_MSM_IPC_LOGGING=y
CONFIG_MSM_DSPS=y
CONFIG_MSM_IPC_ROUTER=y
CONFIG_MSM_IPC_ROUTER_SMD_XPRT=y
CONFIG_MSM_AVS_HW=y
# CONFIG_MSM_HW3D is not set
+CONFIG_MSM_SUBSYSTEM_RESTART=y
+CONFIG_MSM_SYSMON_COMM=y
CONFIG_MSM_PIL_LPASS_QDSP6V4=y
CONFIG_MSM_PIL_MODEM_QDSP6V4=y
CONFIG_MSM_PIL_RIVA=y
@@ -77,19 +76,13 @@
CONFIG_MSM_PIL_DSPS=y
CONFIG_MSM_PIL_VIDC=y
CONFIG_MSM_PIL_GSS=y
-CONFIG_MSM_SUBSYSTEM_RESTART=y
-CONFIG_MSM_SYSMON_COMM=y
-CONFIG_MSM_MODEM_8960=y
-CONFIG_MSM_LPASS_8960=y
-CONFIG_MSM_WCNSS_SSR_8960=y
-CONFIG_MSM_GSS_SSR_8064=y
CONFIG_MSM_TZ_LOG=y
CONFIG_MSM_RPM_LOG=y
CONFIG_MSM_RPM_STATS_LOG=y
CONFIG_MSM_RPM_RBCPR_STATS_LOG=y
+CONFIG_MSM_EVENT_TIMER=y
CONFIG_MSM_BUS_SCALING=y
CONFIG_MSM_BUS_RPM_MULTI_TIER_ENABLED=y
-CONFIG_MSM_EVENT_TIMER=y
CONFIG_MSM_WATCHDOG=y
CONFIG_MSM_DLOAD_MODE=y
CONFIG_MSM_RTB=y
@@ -236,7 +229,6 @@
CONFIG_NET_EMATCH_META=y
CONFIG_NET_EMATCH_TEXT=y
CONFIG_NET_CLS_ACT=y
-CONFIG_MARIMBA_CORE=y
CONFIG_BT=y
CONFIG_BT_RFCOMM=y
CONFIG_BT_RFCOMM_TTY=y
@@ -246,8 +238,8 @@
CONFIG_BT_HIDP=y
CONFIG_BT_HCISMD=y
CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_ATH3K=y
CONFIG_BT_HCIUART_H4=y
+CONFIG_BT_HCIUART_ATH3K=y
CONFIG_BT_HCIUART_IBS=y
CONFIG_MSM_BT_POWER=y
CONFIG_CFG80211=m
@@ -289,6 +281,7 @@
CONFIG_USB_USBNET=y
CONFIG_MSM_RMNET_USB=y
CONFIG_WCNSS_CORE=y
+CONFIG_WCNSS_MEM_PRE_ALLOC=y
CONFIG_INPUT_EVDEV=y
CONFIG_INPUT_EVBUG=m
CONFIG_KEYBOARD_GPIO=y
@@ -301,11 +294,10 @@
CONFIG_TOUCHSCREEN_CYTTSP_I2C_QC=y
CONFIG_INPUT_MISC=y
CONFIG_INPUT_PMIC8XXX_PWRKEY=y
+CONFIG_INPUT_MPU3050=y
CONFIG_INPUT_UINPUT=y
CONFIG_STM_LIS3DH=y
-CONFIG_INPUT_MPU3050=y
# CONFIG_LEGACY_PTYS is not set
-CONFIG_MSM_IPC_LOGGING=y
CONFIG_N_SMUX=y
CONFIG_N_SMUX_LOOPBACK=y
CONFIG_SMUX_CTL=y
@@ -339,6 +331,7 @@
CONFIG_THERMAL_TSENS8960=y
CONFIG_THERMAL_PM8XXX=y
CONFIG_THERMAL_MONITOR=y
+CONFIG_MARIMBA_CORE=y
CONFIG_MFD_PM8921_CORE=y
CONFIG_MFD_PM8821_CORE=y
CONFIG_MFD_PM8038_CORE=y
@@ -352,7 +345,6 @@
CONFIG_MEDIA_CONTROLLER=y
CONFIG_VIDEO_DEV=y
CONFIG_VIDEO_V4L2_SUBDEV_API=y
-CONFIG_MSM_WFD=y
CONFIG_USER_RC_INPUT=y
CONFIG_IR_GPIO_CIR=y
# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
@@ -376,6 +368,7 @@
CONFIG_MSM_CSI20_HEADER=y
CONFIG_S5K3L1YX=y
CONFIG_IMX091=y
+CONFIG_MSM_WFD=y
CONFIG_RADIO_IRIS=y
CONFIG_RADIO_IRIS_TRANSPORT=m
CONFIG_ION=y
@@ -440,7 +433,6 @@
CONFIG_USB_GADGET_DEBUG_FILES=y
CONFIG_USB_CI13XXX_MSM=y
CONFIG_USB_G_ANDROID=y
-CONFIG_USB_ANDROID_RMNET_CTRL_SMD=y
CONFIG_MMC=y
CONFIG_MMC_PERF_PROFILING=y
CONFIG_MMC_UNSAFE_RESUME=y
@@ -477,6 +469,7 @@
CONFIG_MOBICORE_API=m
CONFIG_MSM_QDSS=y
CONFIG_MSM_QDSS_ETM_DEFAULT_ENABLE=y
+CONFIG_CONTROL_TRACE=m
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT3_FS=y
@@ -514,7 +507,6 @@
CONFIG_FAULT_INJECTION_DEBUG_FS=y
CONFIG_FAULT_INJECTION_STACKTRACE_FILTER=y
CONFIG_DEBUG_PAGEALLOC=y
-CONFIG_ENABLE_DEFAULT_TRACERS=y
CONFIG_CPU_FREQ_SWITCH_PROFILER=y
CONFIG_DYNAMIC_DEBUG=y
CONFIG_DEBUG_USER=y
@@ -524,5 +516,3 @@
CONFIG_CRYPTO_DEV_QCE=m
CONFIG_CRYPTO_DEV_QCEDEV=m
CONFIG_CRC_CCITT=y
-CONFIG_WCNSS_MEM_PRE_ALLOC=y
-CONFIG_CONTROL_TRACE=m
diff --git a/arch/arm/configs/msm8974-perf_defconfig b/arch/arm/configs/msm8974-perf_defconfig
index 2f1833e..b2ee503 100644
--- a/arch/arm/configs/msm8974-perf_defconfig
+++ b/arch/arm/configs/msm8974-perf_defconfig
@@ -55,9 +55,6 @@
CONFIG_MSM_PIL_MBA=y
CONFIG_MSM_PIL_VENUS=y
CONFIG_MSM_PIL_PRONTO=y
-CONFIG_MSM_MODEM_SSR_8974=y
-CONFIG_MSM_ADSP_SSR_8974=y
-CONFIG_MSM_WCNSS_SSR_8974=y
CONFIG_MSM_TZ_LOG=y
CONFIG_MSM_DIRECT_SCLK_ACCESS=y
CONFIG_MSM_BUS_SCALING=y
@@ -73,6 +70,7 @@
CONFIG_MSM_L1_ERR_PANIC=y
CONFIG_MSM_L1_ERR_LOG=y
CONFIG_MSM_L2_ERP_2BIT_PANIC=y
+CONFIG_MSM_ENABLE_WDOG_DEBUG_CONTROL=y
CONFIG_STRICT_MEMORY_RWX=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
@@ -287,6 +285,7 @@
CONFIG_VIDEOBUF2_MSM_MEM=y
CONFIG_V4L_PLATFORM_DRIVERS=y
CONFIG_MSM_CAMERA_V4L2=y
+CONFIG_MT9M114=y
CONFIG_OV2720=y
CONFIG_MSM_CAMERA_SENSOR=y
CONFIG_MSM_ACTUATOR=y
@@ -298,7 +297,6 @@
CONFIG_MSM_CSI2_REGISTER=y
CONFIG_MSM_ISPIF=y
CONFIG_S5K3L1YX=y
-CONFIG_MT9M114=y
CONFIG_RADIO_IRIS=y
CONFIG_RADIO_IRIS_TRANSPORT=m
CONFIG_ION=y
@@ -402,4 +400,3 @@
CONFIG_CRYPTO_DEV_QCE=m
CONFIG_CRYPTO_DEV_QCEDEV=m
CONFIG_CRC_CCITT=y
-CONFIG_MSM_ENABLE_WDOG_DEBUG_CONTROL=y
diff --git a/arch/arm/configs/msm8974_defconfig b/arch/arm/configs/msm8974_defconfig
index f0d60c5..9d2b7f3 100644
--- a/arch/arm/configs/msm8974_defconfig
+++ b/arch/arm/configs/msm8974_defconfig
@@ -55,9 +55,6 @@
CONFIG_MSM_PIL_MBA=y
CONFIG_MSM_PIL_VENUS=y
CONFIG_MSM_PIL_PRONTO=y
-CONFIG_MSM_MODEM_SSR_8974=y
-CONFIG_MSM_ADSP_SSR_8974=y
-CONFIG_MSM_WCNSS_SSR_8974=y
CONFIG_MSM_TZ_LOG=y
CONFIG_MSM_DIRECT_SCLK_ACCESS=y
CONFIG_MSM_BUS_SCALING=y
@@ -76,6 +73,7 @@
CONFIG_MSM_L2_ERP_2BIT_PANIC=y
CONFIG_MSM_CACHE_DUMP=y
CONFIG_MSM_CACHE_DUMP_ON_PANIC=y
+CONFIG_MSM_ENABLE_WDOG_DEBUG_CONTROL=y
CONFIG_STRICT_MEMORY_RWX=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
@@ -275,16 +273,17 @@
CONFIG_GPIO_QPNP_PIN_DEBUG=y
CONFIG_POWER_SUPPLY=y
# CONFIG_BATTERY_MSM is not set
+CONFIG_QPNP_CHARGER=y
CONFIG_QPNP_BMS=y
CONFIG_SENSORS_QPNP_ADC_VOLTAGE=y
CONFIG_SENSORS_QPNP_ADC_CURRENT=y
-CONFIG_QPNP_CHARGER=y
CONFIG_THERMAL=y
CONFIG_THERMAL_TSENS8974=y
CONFIG_WCD9320_CODEC=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_STUB=y
CONFIG_REGULATOR_QPNP=y
+CONFIG_QPNP_PWM=y
CONFIG_MEDIA_SUPPORT=y
CONFIG_MEDIA_CONTROLLER=y
CONFIG_VIDEO_DEV=y
@@ -409,7 +408,6 @@
CONFIG_FAULT_INJECTION_DEBUG_FS=y
CONFIG_FAULT_INJECTION_STACKTRACE_FILTER=y
CONFIG_DEBUG_PAGEALLOC=y
-CONFIG_ENABLE_DEFAULT_TRACERS=y
CONFIG_CPU_FREQ_SWITCH_PROFILER=y
CONFIG_DYNAMIC_DEBUG=y
CONFIG_DEBUG_USER=y
@@ -422,4 +420,3 @@
CONFIG_CRYPTO_DEV_QCE=m
CONFIG_CRYPTO_DEV_QCEDEV=m
CONFIG_CRC_CCITT=y
-CONFIG_MSM_ENABLE_WDOG_DEBUG_CONTROL=y
diff --git a/arch/arm/configs/msm9615_defconfig b/arch/arm/configs/msm9615_defconfig
index 7c3d5b0..81b853d 100644
--- a/arch/arm/configs/msm9615_defconfig
+++ b/arch/arm/configs/msm9615_defconfig
@@ -47,11 +47,8 @@
CONFIG_MSM_IPC_ROUTER=y
CONFIG_MSM_IPC_ROUTER_SMD_XPRT=y
CONFIG_MSM_SUBSYSTEM_RESTART=y
-# CONFIG_MSM_SYSMON_COMM is not set
-CONFIG_MSM_MODEM_8960=y
CONFIG_MSM_PIL_LPASS_QDSP6V4=y
CONFIG_MSM_PIL_MODEM_QDSP6V4=y
-CONFIG_MSM_LPASS_8960=y
CONFIG_MSM_RPM_LOG=y
CONFIG_MSM_RPM_STATS_LOG=y
CONFIG_MSM_DIRECT_SCLK_ACCESS=y
diff --git a/arch/arm/configs/msm9625_defconfig b/arch/arm/configs/msm9625_defconfig
index 5054247..4e34ebd 100644
--- a/arch/arm/configs/msm9625_defconfig
+++ b/arch/arm/configs/msm9625_defconfig
@@ -118,6 +118,16 @@
CONFIG_USB_GADGET=y
CONFIG_USB_CI13XXX_MSM=y
CONFIG_USB_G_ANDROID=y
+CONFIG_MMC=y
+CONFIG_MMC_PERF_PROFILING=y
+CONFIG_MMC_UNSAFE_RESUME=y
+CONFIG_MMC_CLKGATE=y
+CONFIG_MMC_EMBEDDED_SDIO=y
+CONFIG_MMC_PARANOID_SD_INIT=y
+CONFIG_MMC_BLOCK_MINORS=32
+CONFIG_MMC_TEST=m
+CONFIG_MMC_MSM=y
+CONFIG_MMC_MSM_SPS_SUPPORT=y
CONFIG_RTC_CLASS=y
# CONFIG_RTC_DRV_MSM is not set
CONFIG_RTC_DRV_QPNP=y
@@ -159,13 +169,3 @@
# CONFIG_CRYPTO_HW is not set
CONFIG_CRC_CCITT=y
CONFIG_LIBCRC32C=y
-CONFIG_MMC=y
-CONFIG_MMC_PERF_PROFILING=y
-CONFIG_MMC_CLKGATE=y
-CONFIG_MMC_EMBEDDED_SDIO=y
-CONFIG_MMC_PARANOID_SD_INIT=y
-CONFIG_MMC_BLOCK_MINORS=32
-CONFIG_MMC_TEST=m
-CONFIG_MMC_MSM=y
-CONFIG_MMC_MSM_SPS_SUPPORT=y
-CONFIG_MMC_UNSAFE_RESUME=y
diff --git a/arch/arm/include/asm/fiq.h b/arch/arm/include/asm/fiq.h
index ec4b8b8..006f577 100644
--- a/arch/arm/include/asm/fiq.h
+++ b/arch/arm/include/asm/fiq.h
@@ -39,6 +39,7 @@
extern void set_fiq_handler(void *start, unsigned int length);
extern void enable_fiq(int fiq);
extern void disable_fiq(int fiq);
+extern void fiq_set_type(int fiq, unsigned int type);
#else
static inline int claim_fiq(struct fiq_handler *f)
{
@@ -48,6 +49,7 @@
static inline void set_fiq_handler(void *start, unsigned int length) { }
static inline void enable_fiq(int fiq) { }
static inline void disable_fiq(int fiq) { }
+static inline void fiq_set_type(int fiq, unsigned int type) { }
#endif
/* helpers defined in fiqasm.S: */
diff --git a/arch/arm/kernel/fiq.c b/arch/arm/kernel/fiq.c
index c32f845..ca852c5 100644
--- a/arch/arm/kernel/fiq.c
+++ b/arch/arm/kernel/fiq.c
@@ -39,6 +39,7 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/interrupt.h>
+#include <linux/irq.h>
#include <linux/seq_file.h>
#include <asm/cacheflush.h>
@@ -132,6 +133,11 @@
disable_irq(fiq + FIQ_START);
}
+void fiq_set_type(int fiq, unsigned int type)
+{
+ irq_set_irq_type(fiq + FIQ_START, type);
+}
+
EXPORT_SYMBOL(set_fiq_handler);
EXPORT_SYMBOL(__set_fiq_regs); /* defined in fiqasm.S */
EXPORT_SYMBOL(__get_fiq_regs); /* defined in fiqasm.S */
@@ -139,6 +145,7 @@
EXPORT_SYMBOL(release_fiq);
EXPORT_SYMBOL(enable_fiq);
EXPORT_SYMBOL(disable_fiq);
+EXPORT_SYMBOL(fiq_set_type);
void __init init_FIQ(void)
{
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index f8e01b6..fa983c4 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -2641,4 +2641,15 @@
used to control debug image.
This support is currently required for MSM8974 to disable debug image
on PS HOLD reset
+
+config MSM_FIQ
+ bool "Enable FIQ for debugging"
+ depends on ARCH_MSM8625
+ select FIQ
+ select GIC_SECURE
+ help
+ Enable any line to be used as an FIQ. This will help debugging
+ if apps is not responding and holding lock with irqs disabled.
+ Modem will then generate an raise a FIQ on this line before sending
+ SMSM reset.
endif
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index 34a81da..6b13eaf 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -398,3 +398,5 @@
ifdef CONFIG_MSM_CPR
obj-$(CONFIG_DEBUG_FS) += msm_cpr-debug.o
endif
+obj-$(CONFIG_MSM_FIQ) += msm7k_fiq.o
+obj-$(CONFIG_MSM_FIQ) += msm7k_fiq_handler.o
diff --git a/arch/arm/mach-msm/acpuclock-8064.c b/arch/arm/mach-msm/acpuclock-8064.c
index d1613d9..cda952f 100644
--- a/arch/arm/mach-msm/acpuclock-8064.c
+++ b/arch/arm/mach-msm/acpuclock-8064.c
@@ -132,8 +132,6 @@
[13] = { { 1080000, HFPLL, 1, 0x28 }, 1150000, 1150000, 5 },
[14] = { { 1134000, HFPLL, 1, 0x2A }, 1150000, 1150000, 5 },
[15] = { { 1188000, HFPLL, 1, 0x2C }, 1150000, 1150000, 5 },
- /* L2 Level 16 is for 8064ab only */
- [16] = { { 1242000, HFPLL, 1, 0x2E }, 1150000, 1150000, 5 },
{ }
};
@@ -215,27 +213,17 @@
{ 0, { 0 } }
};
-static struct acpu_level tbl_slow_1p7[] __initdata = {
+static struct acpu_level tbl_PVS0_1700MHz[] __initdata = {
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 950000 },
- { 0, { 432000, HFPLL, 2, 0x20 }, L2(6), 975000 },
{ 1, { 486000, HFPLL, 2, 0x24 }, L2(6), 975000 },
- { 0, { 540000, HFPLL, 2, 0x28 }, L2(6), 1000000 },
{ 1, { 594000, HFPLL, 1, 0x16 }, L2(6), 1000000 },
- { 0, { 648000, HFPLL, 1, 0x18 }, L2(6), 1025000 },
{ 1, { 702000, HFPLL, 1, 0x1A }, L2(6), 1025000 },
- { 0, { 756000, HFPLL, 1, 0x1C }, L2(6), 1075000 },
{ 1, { 810000, HFPLL, 1, 0x1E }, L2(6), 1075000 },
- { 0, { 864000, HFPLL, 1, 0x20 }, L2(6), 1100000 },
{ 1, { 918000, HFPLL, 1, 0x22 }, L2(6), 1100000 },
- { 0, { 972000, HFPLL, 1, 0x24 }, L2(6), 1125000 },
{ 1, { 1026000, HFPLL, 1, 0x26 }, L2(6), 1125000 },
- { 0, { 1080000, HFPLL, 1, 0x28 }, L2(15), 1175000 },
{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1175000 },
- { 0, { 1188000, HFPLL, 1, 0x2C }, L2(15), 1200000 },
{ 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 1200000 },
- { 0, { 1296000, HFPLL, 1, 0x30 }, L2(15), 1225000 },
{ 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1225000 },
- { 0, { 1404000, HFPLL, 1, 0x34 }, L2(15), 1237500 },
{ 1, { 1458000, HFPLL, 1, 0x36 }, L2(15), 1237500 },
{ 1, { 1512000, HFPLL, 1, 0x38 }, L2(15), 1250000 },
{ 1, { 1566000, HFPLL, 1, 0x3A }, L2(15), 1250000 },
@@ -244,38 +232,136 @@
{ 0, { 0 } }
};
-static struct acpu_level tbl_slow_2p0[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 950000 },
- { 0, { 432000, HFPLL, 2, 0x20 }, L2(6), 975000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(6), 975000 },
- { 0, { 540000, HFPLL, 2, 0x28 }, L2(6), 1000000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(6), 1000000 },
- { 0, { 648000, HFPLL, 1, 0x18 }, L2(6), 1025000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(6), 1025000 },
- { 0, { 756000, HFPLL, 1, 0x1C }, L2(6), 1075000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(6), 1075000 },
- { 0, { 864000, HFPLL, 1, 0x20 }, L2(6), 1100000 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(6), 1100000 },
- { 0, { 972000, HFPLL, 1, 0x24 }, L2(6), 1125000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(6), 1125000 },
- { 0, { 1080000, HFPLL, 1, 0x28 }, L2(15), 1175000 },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1175000 },
- { 0, { 1188000, HFPLL, 1, 0x2C }, L2(15), 1200000 },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 1200000 },
- { 0, { 1296000, HFPLL, 1, 0x30 }, L2(15), 1225000 },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1225000 },
- { 0, { 1404000, HFPLL, 1, 0x34 }, L2(15), 1237500 },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(15), 1237500 },
- { 1, { 1512000, HFPLL, 1, 0x38 }, L2(15), 1250000 },
- { 1, { 1566000, HFPLL, 1, 0x3A }, L2(15), 1250000 },
- { 1, { 1620000, HFPLL, 1, 0x3C }, L2(15), 1250000 },
- { 1, { 1674000, HFPLL, 1, 0x3E }, L2(15), 1250000 },
- { 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1250000 },
- { 1, { 1782000, HFPLL, 1, 0x42 }, L2(15), 1250000 },
- { 1, { 1836000, HFPLL, 1, 0x44 }, L2(15), 1250000 },
+static struct acpu_level tbl_PVS0_2000MHz[] __initdata = {
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 900000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(6), 900000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(6), 900000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(6), 900000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(6), 912500 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(6), 962500 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(6), 987500 },
+ { 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1012500 },
+ { 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 1025000 },
+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1075000 },
+ { 1, { 1458000, HFPLL, 1, 0x36 }, L2(15), 1112500 },
+ { 1, { 1566000, HFPLL, 1, 0x3A }, L2(15), 1150000 },
+ { 1, { 1674000, HFPLL, 1, 0x3E }, L2(15), 1200000 },
+ { 1, { 1782000, HFPLL, 1, 0x42 }, L2(15), 1262500 },
+ { 1, { 1890000, HFPLL, 1, 0x46 }, L2(15), 1300000 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level tbl_PVS1_2000MHz[] __initdata = {
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 900000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(6), 900000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(6), 900000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(6), 900000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(6), 900000 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(6), 962500 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(6), 987500 },
+ { 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1000000 },
+ { 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 1012500 },
+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1062500 },
+ { 1, { 1458000, HFPLL, 1, 0x36 }, L2(15), 1087500 },
+ { 1, { 1566000, HFPLL, 1, 0x3A }, L2(15), 1125000 },
+ { 1, { 1674000, HFPLL, 1, 0x3E }, L2(15), 1187500 },
+ { 1, { 1782000, HFPLL, 1, 0x42 }, L2(15), 1237500 },
+ { 1, { 1890000, HFPLL, 1, 0x46 }, L2(15), 1275000 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level tbl_PVS2_2000MHz[] __initdata = {
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 900000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(6), 900000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(6), 900000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(6), 900000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(6), 900000 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(6), 950000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(6), 975000 },
+ { 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 987500 },
+ { 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 1000000 },
+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1050000 },
+ { 1, { 1458000, HFPLL, 1, 0x36 }, L2(15), 1075000 },
+ { 1, { 1566000, HFPLL, 1, 0x3A }, L2(15), 1112500 },
+ { 1, { 1674000, HFPLL, 1, 0x3E }, L2(15), 1162500 },
+ { 1, { 1782000, HFPLL, 1, 0x42 }, L2(15), 1212500 },
{ 1, { 1890000, HFPLL, 1, 0x46 }, L2(15), 1250000 },
- { 1, { 1944000, HFPLL, 1, 0x48 }, L2(15), 1250000 },
- { 1, { 1998000, HFPLL, 1, 0x4A }, L2(15), 1250000 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level tbl_PVS3_2000MHz[] __initdata = {
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 900000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(6), 900000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(6), 900000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(6), 900000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(6), 900000 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(6), 925000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(6), 950000 },
+ { 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 962500 },
+ { 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 975000 },
+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1012500 },
+ { 1, { 1458000, HFPLL, 1, 0x36 }, L2(15), 1037500 },
+ { 1, { 1566000, HFPLL, 1, 0x3A }, L2(15), 1075000 },
+ { 1, { 1674000, HFPLL, 1, 0x3E }, L2(15), 1112500 },
+ { 1, { 1782000, HFPLL, 1, 0x42 }, L2(15), 1162500 },
+ { 1, { 1890000, HFPLL, 1, 0x46 }, L2(15), 1200000 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level tbl_PVS4_2000MHz[] __initdata = {
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 900000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(6), 900000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(6), 900000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(6), 900000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(6), 900000 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(6), 900000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(6), 925000 },
+ { 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 937500 },
+ { 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 950000 },
+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 975000 },
+ { 1, { 1458000, HFPLL, 1, 0x36 }, L2(15), 1000000 },
+ { 1, { 1566000, HFPLL, 1, 0x3A }, L2(15), 1037500 },
+ { 1, { 1674000, HFPLL, 1, 0x3E }, L2(15), 1062500 },
+ { 1, { 1782000, HFPLL, 1, 0x42 }, L2(15), 1112500 },
+ { 1, { 1890000, HFPLL, 1, 0x46 }, L2(15), 1150000 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level tbl_PVS5_2000MHz[] __initdata = {
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 900000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(6), 900000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(6), 900000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(6), 900000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(6), 900000 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(6), 900000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(6), 925000 },
+ { 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 937500 },
+ { 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 950000 },
+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 962500 },
+ { 1, { 1458000, HFPLL, 1, 0x36 }, L2(15), 987500 },
+ { 1, { 1566000, HFPLL, 1, 0x3A }, L2(15), 1012500 },
+ { 1, { 1674000, HFPLL, 1, 0x3E }, L2(15), 1037500 },
+ { 1, { 1782000, HFPLL, 1, 0x42 }, L2(15), 1087500 },
+ { 1, { 1890000, HFPLL, 1, 0x46 }, L2(15), 1125000 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level tbl_PVS6_2000MHz[] __initdata = {
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 900000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(6), 900000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(6), 900000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(6), 900000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(6), 900000 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(6), 900000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(6), 925000 },
+ { 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 937500 },
+ { 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 950000 },
+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 962500 },
+ { 1, { 1458000, HFPLL, 1, 0x36 }, L2(15), 975000 },
+ { 1, { 1566000, HFPLL, 1, 0x3A }, L2(15), 1000000 },
+ { 1, { 1674000, HFPLL, 1, 0x3E }, L2(15), 1025000 },
+ { 1, { 1782000, HFPLL, 1, 0x42 }, L2(15), 1062500 },
+ { 1, { 1890000, HFPLL, 1, 0x46 }, L2(15), 1100000 },
{ 0, { 0 } }
};
@@ -285,21 +371,21 @@
[0][PVS_FAST] = {tbl_fast, sizeof(tbl_fast), 25000 },
[0][PVS_FASTER] = {tbl_fast, sizeof(tbl_fast), 25000 },
- [1][0] = { tbl_slow_1p7, sizeof(tbl_slow_1p7), 0 },
- [1][1] = { tbl_slow_1p7, sizeof(tbl_slow_1p7), 0 },
- [1][2] = { tbl_slow_1p7, sizeof(tbl_slow_1p7), 0 },
- [1][3] = { tbl_slow_1p7, sizeof(tbl_slow_1p7), 0 },
- [1][4] = { tbl_slow_1p7, sizeof(tbl_slow_1p7), 0 },
- [1][5] = { tbl_slow_1p7, sizeof(tbl_slow_1p7), 0 },
- [1][6] = { tbl_slow_1p7, sizeof(tbl_slow_1p7), 0 },
+ [1][0] = { tbl_PVS0_1700MHz, sizeof(tbl_PVS0_1700MHz), 0 },
+ [1][1] = { tbl_PVS0_1700MHz, sizeof(tbl_PVS0_1700MHz), 0 },
+ [1][2] = { tbl_PVS0_1700MHz, sizeof(tbl_PVS0_1700MHz), 0 },
+ [1][3] = { tbl_PVS0_1700MHz, sizeof(tbl_PVS0_1700MHz), 0 },
+ [1][4] = { tbl_PVS0_1700MHz, sizeof(tbl_PVS0_1700MHz), 0 },
+ [1][5] = { tbl_PVS0_1700MHz, sizeof(tbl_PVS0_1700MHz), 0 },
+ [1][6] = { tbl_PVS0_1700MHz, sizeof(tbl_PVS0_1700MHz), 0 },
- [2][0] = { tbl_slow_2p0, sizeof(tbl_slow_2p0), 0 },
- [2][1] = { tbl_slow_2p0, sizeof(tbl_slow_2p0), 0 },
- [2][2] = { tbl_slow_2p0, sizeof(tbl_slow_2p0), 0 },
- [2][3] = { tbl_slow_2p0, sizeof(tbl_slow_2p0), 0 },
- [2][4] = { tbl_slow_2p0, sizeof(tbl_slow_2p0), 0 },
- [2][5] = { tbl_slow_2p0, sizeof(tbl_slow_2p0), 0 },
- [2][6] = { tbl_slow_2p0, sizeof(tbl_slow_2p0), 0 },
+ [2][0] = { tbl_PVS0_2000MHz, sizeof(tbl_PVS0_2000MHz), 0 },
+ [2][1] = { tbl_PVS1_2000MHz, sizeof(tbl_PVS1_2000MHz), 0 },
+ [2][2] = { tbl_PVS2_2000MHz, sizeof(tbl_PVS2_2000MHz), 0 },
+ [2][3] = { tbl_PVS3_2000MHz, sizeof(tbl_PVS3_2000MHz), 0 },
+ [2][4] = { tbl_PVS4_2000MHz, sizeof(tbl_PVS4_2000MHz), 0 },
+ [2][5] = { tbl_PVS5_2000MHz, sizeof(tbl_PVS5_2000MHz), 0 },
+ [2][6] = { tbl_PVS6_2000MHz, sizeof(tbl_PVS6_2000MHz), 0 },
};
static struct acpuclk_krait_params acpuclk_8064_params __initdata = {
diff --git a/arch/arm/mach-msm/board-8064.c b/arch/arm/mach-msm/board-8064.c
index b3add3b..f192bc8 100644
--- a/arch/arm/mach-msm/board-8064.c
+++ b/arch/arm/mach-msm/board-8064.c
@@ -2436,6 +2436,7 @@
static struct gpio_ir_recv_platform_data gpio_ir_recv_pdata = {
.gpio_nr = 88,
.active_low = 1,
+ .can_wakeup = true,
};
static struct platform_device gpio_ir_recv_pdev = {
@@ -3453,6 +3454,8 @@
apq8064_common_init();
if (machine_is_mpq8064_cdp() || machine_is_mpq8064_hrd() ||
machine_is_mpq8064_dtv()) {
+ gpio_ir_recv_pdata.swfi_latency =
+ msm_rpmrs_levels[0].latency_us;
enable_avc_i2c_bus();
msm_rotator_set_split_iommu_domain();
platform_add_devices(mpq_devices, ARRAY_SIZE(mpq_devices));
diff --git a/arch/arm/mach-msm/board-8930-gpiomux.c b/arch/arm/mach-msm/board-8930-gpiomux.c
index fcb5abd..cf44e08 100644
--- a/arch/arm/mach-msm/board-8930-gpiomux.c
+++ b/arch/arm/mach-msm/board-8930-gpiomux.c
@@ -69,7 +69,7 @@
static struct gpiomux_setting cdc_mclk = {
.func = GPIOMUX_FUNC_1,
- .drv = GPIOMUX_DRV_8MA,
+ .drv = GPIOMUX_DRV_2MA,
.pull = GPIOMUX_PULL_NONE,
};
diff --git a/arch/arm/mach-msm/board-9625.c b/arch/arm/mach-msm/board-9625.c
index 9b2bf25..43f863b 100644
--- a/arch/arm/mach-msm/board-9625.c
+++ b/arch/arm/mach-msm/board-9625.c
@@ -117,6 +117,10 @@
"spi_qsd.1", NULL),
OF_DEV_AUXDATA("qcom,spmi-pmic-arb", 0xFC4C0000, \
"spmi-pmic-arb.0", NULL),
+ OF_DEV_AUXDATA("qcom,msm-sdcc", 0xF98A4000, \
+ "msm_sdcc.2", NULL),
+ OF_DEV_AUXDATA("qcom,msm-sdcc", 0xF9864000, \
+ "msm_sdcc.3", NULL),
{}
};
diff --git a/arch/arm/mach-msm/clock-8974.c b/arch/arm/mach-msm/clock-8974.c
index b21e60e..246ceaf 100644
--- a/arch/arm/mach-msm/clock-8974.c
+++ b/arch/arm/mach-msm/clock-8974.c
@@ -4677,6 +4677,10 @@
{&gcc_ce1_clk.c, GCC_BASE, 0x0138},
{&gcc_lpass_q6_axi_clk.c, GCC_BASE, 0x0160},
{&gcc_mss_q6_bimc_axi_clk.c, GCC_BASE, 0x0031},
+ {&cnoc_clk.c, GCC_BASE, 0x0008},
+ {&pnoc_clk.c, GCC_BASE, 0x0010},
+ {&snoc_clk.c, GCC_BASE, 0x0000},
+ {&bimc_clk.c, GCC_BASE, 0x0155},
{&mmss_mmssnoc_axi_clk.c, MMSS_BASE, 0x0004},
{&ocmemnoc_clk.c, MMSS_BASE, 0x0007},
{&ocmemcx_ocmemnoc_clk.c, MMSS_BASE, 0x0009},
diff --git a/arch/arm/mach-msm/clock-9625.c b/arch/arm/mach-msm/clock-9625.c
index 69a52e9..275c4a8 100644
--- a/arch/arm/mach-msm/clock-9625.c
+++ b/arch/arm/mach-msm/clock-9625.c
@@ -2011,12 +2011,12 @@
CLK_LOOKUP("core_clk", gcc_pdm2_clk.c, ""),
CLK_LOOKUP("iface_clk", gcc_pdm_ahb_clk.c, ""),
- CLK_LOOKUP("iface_clk", gcc_sdcc2_ahb_clk.c, "f98a4000.qcom,sdcc"),
- CLK_LOOKUP("core_clk", gcc_sdcc2_apps_clk.c, "f98a4000.qcom,sdcc"),
- CLK_LOOKUP("bus_clk", pnoc_sdcc2_clk.c, "f98a4000.qcom,sdcc"),
- CLK_LOOKUP("iface_clk", gcc_sdcc3_ahb_clk.c, "f9864000.qcom,sdcc"),
- CLK_LOOKUP("core_clk", gcc_sdcc3_apps_clk.c, "f9864000.qcom,sdcc"),
- CLK_LOOKUP("bus_clk", pnoc_sdcc3_clk.c, "f9864000.qcom,sdcc"),
+ CLK_LOOKUP("iface_clk", gcc_sdcc2_ahb_clk.c, "msm_sdcc.2"),
+ CLK_LOOKUP("core_clk", gcc_sdcc2_apps_clk.c, "msm_sdcc.2"),
+ CLK_LOOKUP("bus_clk", pnoc_sdcc2_clk.c, "msm_sdcc.2"),
+ CLK_LOOKUP("iface_clk", gcc_sdcc3_ahb_clk.c, "msm_sdcc.3"),
+ CLK_LOOKUP("core_clk", gcc_sdcc3_apps_clk.c, "msm_sdcc.3"),
+ CLK_LOOKUP("bus_clk", pnoc_sdcc3_clk.c, "msm_sdcc.3"),
CLK_LOOKUP("iface_clk", gcc_usb_hs_ahb_clk.c, "f9a55000.usb"),
CLK_LOOKUP("core_clk", gcc_usb_hs_system_clk.c, "f9a55000.usb"),
diff --git a/arch/arm/mach-msm/clock-local.c b/arch/arm/mach-msm/clock-local.c
index ca031ad..d2260cb 100644
--- a/arch/arm/mach-msm/clock-local.c
+++ b/arch/arm/mach-msm/clock-local.c
@@ -352,7 +352,7 @@
u32 reg_val;
reg_val = b->ctl_reg ? readl_relaxed(b->ctl_reg) : 0;
- if (b->en_mask) {
+ if (b->ctl_reg && b->en_mask) {
reg_val &= ~(b->en_mask);
writel_relaxed(reg_val, b->ctl_reg);
}
diff --git a/arch/arm/mach-msm/include/mach/irqs-8625.h b/arch/arm/mach-msm/include/mach/irqs-8625.h
index 2ec0e21..2a61118 100644
--- a/arch/arm/mach-msm/include/mach/irqs-8625.h
+++ b/arch/arm/mach-msm/include/mach/irqs-8625.h
@@ -16,6 +16,10 @@
#define GIC_PPI_START 16
#define GIC_SPI_START 32
+#ifdef CONFIG_MSM_FIQ
+#define FIQ_START 0
+#endif
+
/* As per QGIC2 PPI 16 aka 0 is reserved */
#define MSM8625_INT_A5_PMU_IRQ (GIC_PPI_START + 1)
#define MSM8625_INT_DEBUG_TIMER_EXP (GIC_PPI_START + 2)
diff --git a/arch/arm/mach-msm/mpm-8625.c b/arch/arm/mach-msm/mpm-8625.c
index fe7ffff..c70ff5c 100644
--- a/arch/arm/mach-msm/mpm-8625.c
+++ b/arch/arm/mach-msm/mpm-8625.c
@@ -92,6 +92,7 @@
[MSM8625_INT_GPIO_GROUP2] = SMSM_FAKE_IRQ,
[MSM8625_INT_A9_M2A_0] = SMSM_FAKE_IRQ,
[MSM8625_INT_A9_M2A_1] = SMSM_FAKE_IRQ,
+ [MSM8625_INT_A9_M2A_2] = SMSM_FAKE_IRQ,
[MSM8625_INT_A9_M2A_5] = SMSM_FAKE_IRQ,
[MSM8625_INT_GP_TIMER_EXP] = SMSM_FAKE_IRQ,
[MSM8625_INT_DEBUG_TIMER_EXP] = SMSM_FAKE_IRQ,
diff --git a/arch/arm/mach-msm/msm7k_fiq.c b/arch/arm/mach-msm/msm7k_fiq.c
new file mode 100644
index 0000000..887218c
--- /dev/null
+++ b/arch/arm/mach-msm/msm7k_fiq.c
@@ -0,0 +1,82 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/slab.h>
+#include <linux/irq.h>
+#include <asm/fiq.h>
+#include <asm/hardware/gic.h>
+#include <asm/cacheflush.h>
+#include <mach/irqs-8625.h>
+
+#include "msm_watchdog.h"
+
+#define MODULE_NAME "MSM7K_FIQ"
+
+struct msm_watchdog_dump msm_dump_cpu_ctx;
+static int fiq_counter;
+void *msm7k_fiq_stack;
+
+/* Called from the FIQ asm handler */
+void msm7k_fiq_handler(void)
+{
+ struct irq_data *d;
+ struct irq_chip *c;
+
+ pr_info("Fiq is received %s\n", __func__);
+ fiq_counter++;
+ d = irq_get_irq_data(MSM8625_INT_A9_M2A_2);
+ c = irq_data_get_irq_chip(d);
+ c->irq_mask(d);
+ local_irq_disable();
+
+ /* Clear the IRQ from the ENABLE_SET */
+ gic_clear_irq_pending(MSM8625_INT_A9_M2A_2);
+ local_irq_enable();
+ flush_cache_all();
+ outer_flush_all();
+ return;
+}
+
+struct fiq_handler msm7k_fh = {
+ .name = MODULE_NAME,
+};
+
+static int __init msm_setup_fiq_handler(void)
+{
+ int ret = 0;
+
+ claim_fiq(&msm7k_fh);
+ set_fiq_handler(&msm7k_fiq_start, msm7k_fiq_length);
+ msm7k_fiq_stack = (void *)__get_free_pages(GFP_KERNEL,
+ THREAD_SIZE_ORDER);
+ if (msm7k_fiq_stack == NULL) {
+ pr_err("FIQ STACK SETUP IS NOT SUCCESSFUL\n");
+ return -ENOMEM;
+ }
+
+ fiq_set_type(MSM8625_INT_A9_M2A_2, IRQF_TRIGGER_RISING);
+ gic_set_irq_secure(MSM8625_INT_A9_M2A_2);
+ enable_irq(MSM8625_INT_A9_M2A_2);
+ pr_info("%s : msm7k fiq setup--done\n", __func__);
+ return ret;
+}
+
+static int __init init7k_fiq(void)
+{
+ if (msm_setup_fiq_handler())
+ pr_err("MSM7K FIQ INIT FAILED\n");
+
+ return 0;
+}
+late_initcall(init7k_fiq);
diff --git a/arch/arm/mach-msm/msm7k_fiq_handler.S b/arch/arm/mach-msm/msm7k_fiq_handler.S
new file mode 100644
index 0000000..e2da9cf
--- /dev/null
+++ b/arch/arm/mach-msm/msm7k_fiq_handler.S
@@ -0,0 +1,94 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+#define VERSION_ID 0x1
+#define MAGIC 0xDEAD0000 | VERSION_ID
+ .text
+ .align 3
+
+ENTRY(msm7k_fiq_start)
+ sub r14, r14, #4 @return address
+ ldr r8, Lmsm_fiq_stack
+ ldr sp, [r8] @get stack
+ stmfa sp!, {r0-r7, lr}
+ stmfa sp!, {r8-r9}
+ ldr r8, Ldump_cpu_ctx
+ @ store magic to indicate a valid dump
+ ldr r9, Lmagic
+ str r9, [r8], #4
+ @ get the current cpsr
+ mrs r9, cpsr
+ str r9, [r8],#4
+ stmia r8!, {r0-r7} @ get the USR r0-r7
+ mov r4, r8
+ mov r5, #PSR_I_BIT | PSR_F_BIT | SYSTEM_MODE
+ msr cpsr_c, r5 @ select SYSTEM mode
+ stmia r4!, {r8-r14}
+ mov r5, #PSR_I_BIT | PSR_F_BIT | IRQ_MODE
+ msr cpsr_c, r5 @ select IRQ mode
+ mrs r5, spsr
+ str r5, [r4], #4
+ stmia r4!, {r13-r14}
+ mov r5, #PSR_I_BIT | PSR_F_BIT | SVC_MODE
+ msr cpsr_c, r5 @ select SVC mode
+ mrs r5, spsr
+ str r5, [r4], #4
+ stmia r4!, {r13-r14}
+ mov r0, r13
+ mov r1, r14
+ mov r5, #PSR_I_BIT | PSR_F_BIT | FIQ_MODE
+ msr cpsr_c, r5 @ select FIQ mode
+ stmfa sp!, {r0-r1}
+ mov r5, #PSR_I_BIT | PSR_F_BIT | ABT_MODE
+ msr cpsr_c, r5 @ select ABT mode
+ mrs r5, spsr
+ str r5, [r4], #4
+ stmia r4!, {r13-r14}
+ mov r5, #PSR_I_BIT | PSR_F_BIT | UND_MODE
+ msr cpsr_c, r5 @ select UND mode
+ mrs r5, spsr
+ str r5, [r4], #4
+ stmia r4!, {r13-r14}
+ mov r5, #PSR_I_BIT | PSR_F_BIT | FIQ_MODE
+ msr cpsr_c, r5 @ select FIQ mode
+ mrs r5, spsr
+ str r5, [r4], #4
+ stmia r4!, {r8-r14}
+ dsb
+ mov r5, #PSR_I_BIT | PSR_F_BIT | SVC_MODE
+ msr cpsr_c, r5 @ select SVC mode
+ ldr r2, Lmsm_fiq_handler
+ blx r2
+ mov r5, #PSR_I_BIT | PSR_F_BIT | FIQ_MODE
+ msr cpsr_c, r5 @ select FIQ mode
+ ldmfa sp!, {r0, r1}
+ mov r5, #PSR_I_BIT | PSR_F_BIT | SVC_MODE
+ msr cpsr_c, r5 @ select SVC mode
+ mov r13, r0
+ mov r14, r1
+ mov r5, #PSR_I_BIT | PSR_F_BIT | FIQ_MODE
+ msr cpsr_c, r5 @ select SVC mode
+ ldmfa sp!, {r8-r9}
+ ldmfa sp!, {r0-r7, pc}^
+Ldump_cpu_ctx:
+ .word msm_dump_cpu_ctx
+Lmsm_fiq_stack:
+ .word msm7k_fiq_stack
+Lmagic:
+ .word MAGIC
+Lmsm_fiq_handler:
+ .word msm7k_fiq_handler
+ENTRY(msm7k_fiq_length)
+ .word . - msm7k_fiq_start
diff --git a/arch/arm/mach-msm/msm_watchdog.h b/arch/arm/mach-msm/msm_watchdog.h
index 5fb82ee..7bf97d9 100644
--- a/arch/arm/mach-msm/msm_watchdog.h
+++ b/arch/arm/mach-msm/msm_watchdog.h
@@ -72,6 +72,7 @@
void msm_wdog_fiq_setup(void *stack);
extern unsigned int msm_wdog_fiq_length, msm_wdog_fiq_start;
+extern unsigned int msm7k_fiq_start, msm7k_fiq_length;
#ifdef CONFIG_MSM_WATCHDOG
void pet_watchdog(void);
diff --git a/arch/arm/mach-msm/spm-v2.c b/arch/arm/mach-msm/spm-v2.c
index f0d3d06..17997d2 100644
--- a/arch/arm/mach-msm/spm-v2.c
+++ b/arch/arm/mach-msm/spm-v2.c
@@ -84,10 +84,6 @@
[MSM_SPM_REG_SAW2_VERSION] = 0xFD0,
};
-/******************************************************************************
- * Internal helper functions
- *****************************************************************************/
-
static inline uint32_t msm_spm_drv_get_num_spm_entry(
struct msm_spm_driver_data *dev)
{
@@ -150,6 +146,12 @@
{
unsigned int pmic_data = 0;
+ /**
+ * VCTL_PORT has to be 0, for PMIC_STS register to be updated.
+ * Ensure that vctl_port is always set to 0.
+ */
+ WARN_ON(dev->vctl_port);
+
pmic_data |= vlevel;
pmic_data |= (dev->vctl_port & 0x7) << 16;
@@ -213,10 +215,6 @@
return ret;
}
-/******************************************************************************
- * Public functions
- *****************************************************************************/
-
inline int msm_spm_drv_set_spm_enable(
struct msm_spm_driver_data *dev, bool enable)
{
@@ -381,69 +379,92 @@
goto set_vdd_bail;
}
- /* Set AVS min/max */
- msm_spm_drv_set_avs_vlevel(dev, vlevel);
-
if (msm_spm_debug_mask & MSM_SPM_DEBUG_VCTL)
- pr_info("%s: done, remaining timeout %uus\n",
+ pr_info("%s: done, remaining timeout %u us\n",
__func__, timeout_us);
+ /* Set AVS min/max */
+ msm_spm_drv_set_avs_vlevel(dev, vlevel);
msm_spm_drv_enable_avs(dev);
+
return 0;
set_vdd_bail:
msm_spm_drv_enable_avs(dev);
- pr_err("%s: failed %#x, remaining timeout %uus, vlevel %#x\n",
+ pr_err("%s: failed %#x, remaining timeout %u us, vlevel %#x\n",
__func__, vlevel, timeout_us, new_level);
return -EIO;
}
-int msm_spm_drv_set_phase(struct msm_spm_driver_data *dev,
- unsigned int phase_cnt)
+static int msm_spm_drv_get_pmic_port(struct msm_spm_driver_data *dev,
+ enum msm_spm_pmic_port port)
+{
+ int index = -1;
+
+ switch (port) {
+ case MSM_SPM_PMIC_VCTL_PORT:
+ index = dev->vctl_port;
+ break;
+ case MSM_SPM_PMIC_PHASE_PORT:
+ index = dev->phase_port;
+ break;
+ case MSM_SPM_PMIC_PFM_PORT:
+ index = dev->pfm_port;
+ break;
+ default:
+ break;
+ }
+
+ return index;
+}
+
+int msm_spm_drv_set_pmic_data(struct msm_spm_driver_data *dev,
+ enum msm_spm_pmic_port port, unsigned int data)
{
unsigned int pmic_data = 0;
unsigned int timeout_us = 0;
+ int index = 0;
if (dev->major != SAW2_MAJOR_2)
return -ENODEV;
- pmic_data |= phase_cnt & 0xFF;
- pmic_data |= (dev->phase_port & 0x7) << 16;
+ if (!msm_spm_pmic_arb_present(dev))
+ return -ENOSYS;
+
+ index = msm_spm_drv_get_pmic_port(dev, port);
+ if (index < 0)
+ return -ENODEV;
+
+ pmic_data |= data & 0xFF;
+ pmic_data |= (index & 0x7) << 16;
dev->reg_shadow[MSM_SPM_REG_SAW2_VCTL] &= ~0x700FF;
dev->reg_shadow[MSM_SPM_REG_SAW2_VCTL] |= pmic_data;
msm_spm_drv_flush_shadow(dev, MSM_SPM_REG_SAW2_VCTL);
mb();
- /* Wait for PMIC state to return to idle or until timeout */
timeout_us = dev->vctl_timeout_us;
- while (msm_spm_drv_get_sts_pmic_state(dev) != MSM_SPM_PMIC_STATE_IDLE) {
- if (!timeout_us)
- goto set_phase_bail;
+ /**
+ * Confirm the pmic data set was what hardware sent by
+ * checking the PMIC FSM state.
+ * We cannot use the sts_pmic_data and check it against
+ * the value like we do fot set_vdd, since the PMIC_STS
+ * is only updated for SAW_VCTL sent with port index 0.
+ */
+ do {
+ if (msm_spm_drv_get_sts_pmic_state(dev) ==
+ MSM_SPM_PMIC_STATE_IDLE)
+ break;
+ udelay(1);
+ } while (--timeout_us);
- if (timeout_us > 10) {
- udelay(10);
- timeout_us -= 10;
- } else {
- udelay(timeout_us);
- timeout_us = 0;
- }
+ if (!timeout_us) {
+ pr_err("%s: failed, remaining timeout %u us, data %d\n",
+ __func__, timeout_us, data);
+ return -EIO;
}
- if (msm_spm_drv_get_sts_curr_pmic_data(dev) != phase_cnt)
- goto set_phase_bail;
-
- if (msm_spm_debug_mask & MSM_SPM_DEBUG_VCTL)
- pr_info("%s: done, remaining timeout %uus\n",
- __func__, timeout_us);
-
return 0;
-
-set_phase_bail:
- pr_err("%s: failed, remaining timeout %uus, phase count %d\n",
- __func__, timeout_us, msm_spm_drv_get_sts_curr_pmic_data(dev));
- return -EIO;
-
}
void msm_spm_drv_reinit(struct msm_spm_driver_data *dev)
@@ -472,6 +493,7 @@
dev->vctl_port = data->vctl_port;
dev->phase_port = data->phase_port;
+ dev->pfm_port = data->pfm_port;
dev->reg_base_addr = data->reg_base_addr;
memcpy(dev->reg_shadow, data->reg_init_values,
sizeof(data->reg_init_values));
diff --git a/arch/arm/mach-msm/spm.h b/arch/arm/mach-msm/spm.h
index 09ee26a..4cdfcf8 100644
--- a/arch/arm/mach-msm/spm.h
+++ b/arch/arm/mach-msm/spm.h
@@ -112,6 +112,7 @@
uint32_t ver_reg;
uint32_t vctl_port;
uint32_t phase_port;
+ uint32_t pfm_port;
uint8_t awake_vlevel;
uint32_t vctl_timeout_us;
@@ -196,6 +197,12 @@
*/
int msm_spm_apcs_set_phase(unsigned int phase_cnt);
+/** msm_spm_enable_fts_lpm() : Enable FTS to switch to low power
+ * when the cores are in low power modes
+ * @mode: The mode configuration for FTS
+ */
+int msm_spm_enable_fts_lpm(uint32_t mode);
+
/* Internal low power management specific functions */
/**
@@ -234,6 +241,11 @@
{
return -ENOSYS;
}
+
+static inline int msm_spm_enable_fts_lpm(uint32_t mode)
+{
+ return -ENOSYS;
+}
#endif /* defined(CONFIG_MSM_L2_SPM) */
#else /* defined(CONFIG_MSM_SPM_V1) || defined(CONFIG_MSM_SPM_V2) */
static inline int msm_spm_set_low_power_mode(unsigned int mode, bool notify_rpm)
diff --git a/arch/arm/mach-msm/spm_devices.c b/arch/arm/mach-msm/spm_devices.c
index 12a6f08..152e2e9 100644
--- a/arch/arm/mach-msm/spm_devices.c
+++ b/arch/arm/mach-msm/spm_devices.c
@@ -260,10 +260,18 @@
int msm_spm_apcs_set_phase(unsigned int phase_cnt)
{
- return msm_spm_drv_set_phase(&msm_spm_l2_device.reg_data, phase_cnt);
+ return msm_spm_drv_set_pmic_data(&msm_spm_l2_device.reg_data,
+ MSM_SPM_PMIC_PHASE_PORT, phase_cnt);
}
EXPORT_SYMBOL(msm_spm_apcs_set_phase);
+int msm_spm_enable_fts_lpm(uint32_t mode)
+{
+ return msm_spm_drv_set_pmic_data(&msm_spm_l2_device.reg_data,
+ MSM_SPM_PMIC_PFM_PORT, mode);
+}
+EXPORT_SYMBOL(msm_spm_enable_fts_lpm);
+
/* Board file init function */
int __init msm_spm_l2_init(struct msm_spm_platform_data *data)
{
@@ -361,25 +369,6 @@
if (!ret)
spm_data.vctl_timeout_us = val;
- /* optional */
- key = "qcom,vctl-port";
- ret = of_property_read_u32(node, key, &val);
- if (!ret)
- spm_data.vctl_port = val;
-
- /* optional */
- key = "qcom,phase-port";
- ret = of_property_read_u32(node, key, &val);
- if (!ret)
- spm_data.phase_port = val;
-
- for (i = 0; i < ARRAY_SIZE(spm_of_data); i++) {
- ret = of_property_read_u32(node, spm_of_data[i].key, &val);
- if (ret)
- continue;
- spm_data.reg_init_values[spm_of_data[i].id] = val;
- }
-
/*
* Device with id 0..NR_CPUS are SPM for apps cores
* Device with id 0xFFFF is for L2 SPM.
@@ -395,6 +384,35 @@
dev = &msm_spm_l2_device;
}
+ spm_data.vctl_port = -1;
+ spm_data.phase_port = -1;
+ spm_data.pfm_port = -1;
+
+ /* optional */
+ if (dev == &msm_spm_l2_device) {
+ key = "qcom,vctl-port";
+ ret = of_property_read_u32(node, key, &val);
+ if (!ret)
+ spm_data.vctl_port = val;
+
+ key = "qcom,phase-port";
+ ret = of_property_read_u32(node, key, &val);
+ if (!ret)
+ spm_data.phase_port = val;
+
+ key = "qcom,pfm-port";
+ ret = of_property_read_u32(node, key, &val);
+ if (!ret)
+ spm_data.pfm_port = val;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(spm_of_data); i++) {
+ ret = of_property_read_u32(node, spm_of_data[i].key, &val);
+ if (ret)
+ continue;
+ spm_data.reg_init_values[spm_of_data[i].id] = val;
+ }
+
for (i = 0; i < num_modes; i++) {
key = mode_of_data[i].key;
modes[mode_count].cmd =
diff --git a/arch/arm/mach-msm/spm_driver.h b/arch/arm/mach-msm/spm_driver.h
index 4cdfd33..1beaffb 100644
--- a/arch/arm/mach-msm/spm_driver.h
+++ b/arch/arm/mach-msm/spm_driver.h
@@ -14,12 +14,19 @@
#include "spm.h"
+enum msm_spm_pmic_port {
+ MSM_SPM_PMIC_VCTL_PORT,
+ MSM_SPM_PMIC_PHASE_PORT,
+ MSM_SPM_PMIC_PFM_PORT,
+};
+
struct msm_spm_driver_data {
uint32_t major;
uint32_t minor;
uint32_t ver_reg;
uint32_t vctl_port;
uint32_t phase_port;
+ uint32_t pfm_port;
void __iomem *reg_base_addr;
uint32_t vctl_timeout_us;
uint32_t avs_timeout_us;
@@ -42,6 +49,6 @@
void msm_spm_drv_flush_seq_entry(struct msm_spm_driver_data *dev);
int msm_spm_drv_set_spm_enable(struct msm_spm_driver_data *dev,
bool enable);
-int msm_spm_drv_set_phase(struct msm_spm_driver_data *dev,
- unsigned int phase_cnt);
+int msm_spm_drv_set_pmic_data(struct msm_spm_driver_data *dev,
+ enum msm_spm_pmic_port port, unsigned int data);
#endif
diff --git a/drivers/gpu/msm/kgsl_iommu.c b/drivers/gpu/msm/kgsl_iommu.c
index 87e8746..97d88ff 100644
--- a/drivers/gpu/msm/kgsl_iommu.c
+++ b/drivers/gpu/msm/kgsl_iommu.c
@@ -923,19 +923,22 @@
unsigned int iommu_virt_addr;
struct kgsl_iommu_pt *iommu_pt = mmu_specific_pt;
int size = kgsl_sg_size(memdesc->sg, memdesc->sglen);
+ unsigned int iommu_flags = IOMMU_READ;
BUG_ON(NULL == iommu_pt);
+ if (protflags & GSL_PT_PAGE_WV)
+ iommu_flags |= IOMMU_WRITE;
iommu_virt_addr = memdesc->gpuaddr;
ret = iommu_map_range(iommu_pt->domain, iommu_virt_addr, memdesc->sg,
- size, (IOMMU_READ | IOMMU_WRITE));
+ size, iommu_flags);
if (ret) {
KGSL_CORE_ERR("iommu_map_range(%p, %x, %p, %d, %d) "
"failed with err: %d\n", iommu_pt->domain,
iommu_virt_addr, memdesc->sg, size,
- (IOMMU_READ | IOMMU_WRITE), ret);
+ iommu_flags, ret);
return ret;
}
diff --git a/drivers/media/rc/gpio-ir-recv.c b/drivers/media/rc/gpio-ir-recv.c
index d7dc67d..8a99968 100644
--- a/drivers/media/rc/gpio-ir-recv.c
+++ b/drivers/media/rc/gpio-ir-recv.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -18,17 +18,35 @@
#include <linux/slab.h>
#include <linux/platform_device.h>
#include <linux/irq.h>
+#include <linux/pm_qos.h>
+#include <linux/timer.h>
#include <media/rc-core.h>
#include <media/gpio-ir-recv.h>
#define GPIO_IR_DRIVER_NAME "gpio-rc-recv"
#define GPIO_IR_DEVICE_NAME "gpio_ir_recv"
+static int gpio_ir_timeout = 200;
+module_param_named(gpio_ir_timeout, gpio_ir_timeout, int, 0664);
+
+static int __init gpio_ir_timeout_setup(char *p)
+{
+ gpio_ir_timeout = memparse(p, NULL);
+ return 0;
+}
+
+early_param("gpio_ir_timeout", gpio_ir_timeout_setup);
+
struct gpio_rc_dev {
struct rc_dev *rcdev;
+ struct pm_qos_request pm_qos_req;
+ struct timer_list gpio_ir_timer;
unsigned int gpio_nr;
bool active_low;
int can_sleep;
+ bool can_wakeup;
+ bool pm_qos_vote;
+ int gpio_irq_latency;
};
static irqreturn_t gpio_ir_recv_irq(int irq, void *dev_id)
@@ -38,6 +56,12 @@
int rc = 0;
enum raw_event_type type = IR_SPACE;
+ if (!gpio_dev->pm_qos_vote && gpio_dev->can_wakeup) {
+ gpio_dev->pm_qos_vote = 1;
+ pm_qos_update_request(&gpio_dev->pm_qos_req,
+ gpio_dev->gpio_irq_latency);
+ }
+
if (gpio_dev->can_sleep)
gval = gpio_get_value_cansleep(gpio_dev->gpio_nr);
else
@@ -58,10 +82,22 @@
ir_raw_event_handle(gpio_dev->rcdev);
+ if (gpio_dev->can_wakeup)
+ mod_timer(&gpio_dev->gpio_ir_timer,
+ jiffies + msecs_to_jiffies(gpio_ir_timeout));
err_get_value:
return IRQ_HANDLED;
}
+static void gpio_ir_timer(unsigned long data)
+{
+ struct gpio_rc_dev *gpio_dev = (struct gpio_rc_dev *)data;
+
+ pm_qos_update_request(&gpio_dev->pm_qos_req, PM_QOS_DEFAULT_VALUE);
+ pm_qos_request_active(&gpio_dev->pm_qos_req);
+ gpio_dev->pm_qos_vote = 0;
+}
+
static int __devinit gpio_ir_recv_probe(struct platform_device *pdev)
{
struct gpio_rc_dev *gpio_dev;
@@ -96,6 +132,9 @@
gpio_dev->rcdev = rcdev;
gpio_dev->gpio_nr = pdata->gpio_nr;
gpio_dev->active_low = pdata->active_low;
+ gpio_dev->can_wakeup = pdata->can_wakeup;
+ gpio_dev->gpio_irq_latency = pdata->swfi_latency + 1;
+ gpio_dev->pm_qos_vote = 0;
rc = gpio_request(pdata->gpio_nr, "gpio-ir-recv");
if (rc < 0)
@@ -122,7 +161,14 @@
if (rc < 0)
goto err_request_irq;
- device_init_wakeup(&pdev->dev, pdata->can_wakeup);
+ if (gpio_dev->can_wakeup) {
+ pm_qos_add_request(&gpio_dev->pm_qos_req,
+ PM_QOS_CPU_DMA_LATENCY,
+ PM_QOS_DEFAULT_VALUE);
+ device_init_wakeup(&pdev->dev, pdata->can_wakeup);
+ setup_timer(&gpio_dev->gpio_ir_timer, gpio_ir_timer,
+ (unsigned long)gpio_dev);
+ }
return 0;
@@ -144,6 +190,10 @@
{
struct gpio_rc_dev *gpio_dev = platform_get_drvdata(pdev);
+ if (gpio_dev->can_wakeup) {
+ del_timer_sync(&gpio_dev->gpio_ir_timer);
+ pm_qos_remove_request(&gpio_dev->pm_qos_req);
+ }
free_irq(gpio_to_irq(gpio_dev->gpio_nr), gpio_dev);
platform_set_drvdata(pdev, NULL);
rc_unregister_device(gpio_dev->rcdev);
diff --git a/drivers/media/video/msm/jpeg_10/msm_jpeg_core.c b/drivers/media/video/msm/jpeg_10/msm_jpeg_core.c
index b67245c..a2fc813 100644
--- a/drivers/media/video/msm/jpeg_10/msm_jpeg_core.c
+++ b/drivers/media/video/msm/jpeg_10/msm_jpeg_core.c
@@ -159,7 +159,7 @@
void *msm_jpeg_core_err_irq(int jpeg_irq_status,
struct msm_jpeg_device *pgmn_dev)
{
- JPEG_PR_ERR("%s:%d]\n", __func__, jpeg_irq_status);
+ JPEG_PR_ERR("%s: Error %x\n", __func__, jpeg_irq_status);
return NULL;
}
@@ -211,6 +211,7 @@
if (msm_jpeg_hw_irq_is_frame_done(jpeg_irq_status)) {
/* send fe ping pong irq */
+ JPEG_DBG_HIGH("%s:%d] Session done\n", __func__, __LINE__);
data = msm_jpeg_core_fe_pingpong_irq(jpeg_irq_status,
pgmn_dev);
if (msm_jpeg_irq_handler)
diff --git a/drivers/media/video/msm/jpeg_10/msm_jpeg_hw.c b/drivers/media/video/msm/jpeg_10/msm_jpeg_hw.c
index e311e4c..c38771b 100644
--- a/drivers/media/video/msm/jpeg_10/msm_jpeg_hw.c
+++ b/drivers/media/video/msm/jpeg_10/msm_jpeg_hw.c
@@ -132,6 +132,10 @@
JPEG_PLN1_RD_OFFSET_BMSK, {0} },
{MSM_JPEG_HW_CMD_TYPE_WRITE, 1, JPEG_PLN1_RD_PNTR_ADDR,
JPEG_PLN1_RD_PNTR_BMSK, {0} },
+ {MSM_JPEG_HW_CMD_TYPE_WRITE, 1, JPEG_PLN2_RD_OFFSET_ADDR,
+ JPEG_PLN1_RD_OFFSET_BMSK, {0} },
+ {MSM_JPEG_HW_CMD_TYPE_WRITE, 1, JPEG_PLN2_RD_PNTR_ADDR,
+ JPEG_PLN2_RD_PNTR_BMSK, {0} },
};
void msm_jpeg_hw_fe_buffer_update(struct msm_jpeg_hw_buf *p_input,
@@ -156,7 +160,11 @@
hw_cmd_p->data = p_input->cbcr_buffer_addr;
msm_jpeg_hw_write(hw_cmd_p++, base);
wmb();
-
+ msm_jpeg_hw_write(hw_cmd_p++, base);
+ wmb();
+ hw_cmd_p->data = p_input->pln2_addr;
+ msm_jpeg_hw_write(hw_cmd_p++, base);
+ wmb();
}
return;
}
@@ -215,6 +223,7 @@
JPEG_PR_ERR("%s Output pln1 buffer address is %x\n", __func__,
p_input->cbcr_buffer_addr);
msm_jpeg_hw_write(hw_cmd_p++, base);
+ hw_cmd_p->data = p_input->pln2_addr;
JPEG_PR_ERR("%s Output pln2 buffer address is %x\n", __func__,
p_input->pln2_addr);
msm_jpeg_hw_write(hw_cmd_p++, base);
diff --git a/drivers/media/video/msm/jpeg_10/msm_jpeg_hw.h b/drivers/media/video/msm/jpeg_10/msm_jpeg_hw.h
index e90b941..084e36b 100644
--- a/drivers/media/video/msm/jpeg_10/msm_jpeg_hw.h
+++ b/drivers/media/video/msm/jpeg_10/msm_jpeg_hw.h
@@ -29,7 +29,7 @@
uint32_t num_of_mcu_rows;
struct ion_handle *handle;
uint32_t pln2_addr;
- uint32_t pln2_offset;
+ uint32_t pln2_len;
};
struct msm_jpeg_hw_pingpong {
diff --git a/drivers/media/video/msm/jpeg_10/msm_jpeg_hw_reg.h b/drivers/media/video/msm/jpeg_10/msm_jpeg_hw_reg.h
index 928d59e..ff99aa3 100644
--- a/drivers/media/video/msm/jpeg_10/msm_jpeg_hw_reg.h
+++ b/drivers/media/video/msm/jpeg_10/msm_jpeg_hw_reg.h
@@ -72,6 +72,12 @@
#define JPEG_PLN1_RD_OFFSET_ADDR 0x00000048
#define JPEG_PLN1_RD_OFFSET_BMSK 0x1FFFFFFF
+#define JPEG_PLN2_RD_PNTR_ADDR (JPEG_REG_BASE + 0x00000050)
+#define JPEG_PLN2_RD_PNTR_BMSK 0xFFFFFFFF
+
+#define JPEG_PLN2_RD_OFFSET_ADDR 0x00000054
+#define JPEG_PLN2_RD_OFFSET_BMSK 0x1FFFFFFF
+
#define JPEG_CMD_ADDR (JPEG_REG_BASE + 0x00000010)
#define JPEG_CMD_BMSK 0x00000FFF
#define JPEG_CMD_CLEAR_WRITE_PLN_QUEUES 0x700
diff --git a/drivers/media/video/msm/jpeg_10/msm_jpeg_sync.c b/drivers/media/video/msm/jpeg_10/msm_jpeg_sync.c
index a0aaf03..a7a9d70 100644
--- a/drivers/media/video/msm/jpeg_10/msm_jpeg_sync.c
+++ b/drivers/media/video/msm/jpeg_10/msm_jpeg_sync.c
@@ -368,8 +368,8 @@
buf_cmd.fd);
buf_p->y_buffer_addr = msm_jpeg_platform_v2p(pgmn_dev, buf_cmd.fd,
- buf_cmd.y_len, &buf_p->file, &buf_p->handle,
- pgmn_dev->domain_num);
+ buf_cmd.y_len + buf_cmd.cbcr_len + buf_cmd.pln2_len,
+ &buf_p->file, &buf_p->handle, pgmn_dev->domain_num);
if (!buf_p->y_buffer_addr) {
JPEG_PR_ERR("%s:%d] v2p wrong\n", __func__, __LINE__);
kfree(buf_p);
@@ -382,11 +382,23 @@
else
buf_p->cbcr_buffer_addr = 0x0;
- JPEG_DBG("%s:%d] After v2p pln0_addr =0x%x,pln0_len %d pl1_len %d",
+ if (buf_cmd.pln2_len)
+ buf_p->pln2_addr = buf_p->cbcr_buffer_addr +
+ buf_cmd.cbcr_len;
+ else
+ buf_p->pln2_addr = 0x0;
+
+ JPEG_DBG("%s:%d]After v2p pln0_addr %x pln0_len %d",
__func__, __LINE__, buf_p->y_buffer_addr,
- buf_cmd.y_len, buf_cmd.cbcr_len);
+ buf_cmd.y_len);
+
+ JPEG_DBG("pl1_len %d, pln1_addr %x, pln2_adrr %x,pln2_len %d",
+ buf_cmd.cbcr_len, buf_p->cbcr_buffer_addr,
+ buf_p->pln2_addr, buf_cmd.pln2_len);
+
buf_p->y_len = buf_cmd.y_len;
buf_p->cbcr_len = buf_cmd.cbcr_len;
+ buf_p->pln2_len = buf_cmd.pln2_len;
buf_p->vbuf = buf_cmd;
msm_jpeg_q_in(&pgmn_dev->output_buf_q, buf_p);
@@ -489,23 +501,31 @@
(int) buf_cmd.vaddr, buf_cmd.y_len);
buf_p->y_buffer_addr = msm_jpeg_platform_v2p(pgmn_dev, buf_cmd.fd,
- buf_cmd.y_len + buf_cmd.cbcr_len, &buf_p->file,
- &buf_p->handle, pgmn_dev->domain_num) + buf_cmd.offset
- + buf_cmd.y_off;
+ buf_cmd.y_len + buf_cmd.cbcr_len + buf_cmd.pln2_len,
+ &buf_p->file, &buf_p->handle, pgmn_dev->domain_num) +
+ buf_cmd.offset + buf_cmd.y_off;
buf_p->y_len = buf_cmd.y_len;
buf_p->cbcr_len = buf_cmd.cbcr_len;
+ buf_p->pln2_len = buf_cmd.pln2_len;
buf_p->num_of_mcu_rows = buf_cmd.num_of_mcu_rows;
- buf_p->y_len = buf_cmd.y_len;
- buf_p->cbcr_len = buf_cmd.cbcr_len;
+
if (buf_cmd.cbcr_len)
- buf_p->cbcr_buffer_addr = buf_p->y_buffer_addr + buf_cmd.y_len
- + buf_cmd.cbcr_off;
+ buf_p->cbcr_buffer_addr = buf_p->y_buffer_addr +
+ buf_cmd.y_len + buf_cmd.cbcr_off;
else
buf_p->cbcr_buffer_addr = 0x0;
- JPEG_DBG("%s: y_addr=%x, y_len=%x, cbcr_addr=%x, cbcr_len=%x, fd =%d\n",
+ if (buf_cmd.pln2_len)
+ buf_p->pln2_addr = buf_p->cbcr_buffer_addr +
+ buf_cmd.cbcr_len + buf_cmd.pln2_off;
+ else
+ buf_p->pln2_addr = 0x0;
+
+ JPEG_DBG("%s: y_addr=%x, y_len=%x, cbcr_addr=%x, cbcr_len=%d",
__func__, buf_p->y_buffer_addr, buf_p->y_len,
- buf_p->cbcr_buffer_addr, buf_p->cbcr_len, buf_cmd.fd);
+ buf_p->cbcr_buffer_addr, buf_p->cbcr_len);
+ JPEG_DBG("pln2_addr = %x, pln2_len = %d, fd =%d\n",
+ buf_p->pln2_addr, buf_p->pln2_len, buf_cmd.fd);
if (!buf_p->y_buffer_addr) {
JPEG_PR_ERR("%s:%d] v2p wrong\n", __func__, __LINE__);
@@ -733,9 +753,11 @@
for (i = 0; i < 2; i++)
kfree(buf_out_free[i]);
- msm_jpeg_io_dump(pgmn_dev->base, JPEG_REG_SIZE);
+ JPEG_DBG_HIGH("%s:%d] START\n", __func__, __LINE__);
+ wmb();
rc = msm_jpeg_ioctl_hw_cmds(pgmn_dev, arg);
- JPEG_DBG("%s:%d]\n", __func__, __LINE__);
+ wmb();
+ JPEG_DBG("%s:%d]", __func__, __LINE__);
return rc;
}
diff --git a/drivers/media/video/msm_vidc/msm_vidc_debug.c b/drivers/media/video/msm_vidc/msm_vidc_debug.c
index 7368136..914c422 100644
--- a/drivers/media/video/msm_vidc/msm_vidc_debug.c
+++ b/drivers/media/video/msm_vidc/msm_vidc_debug.c
@@ -15,6 +15,7 @@
#define MAX_DBG_BUF_SIZE 4096
int msm_vidc_debug;
+int msm_fw_debug;
struct debug_buffer {
char ptr[MAX_DBG_BUF_SIZE];
@@ -89,6 +90,7 @@
goto failed_create_dir;
}
msm_vidc_debug = 0;
+ msm_fw_debug = 0;
snprintf(debugfs_name, MAX_DEBUGFS_NAME, "core%d", core->id);
dir = debugfs_create_dir(debugfs_name, parent);
if (!dir) {
@@ -105,6 +107,12 @@
goto failed_create_dir;
}
msm_vidc_debug = 0x3;
+ if (!debugfs_create_u32("fw_level", S_IRUGO | S_IWUSR,
+ parent, &msm_fw_debug)) {
+ dprintk(VIDC_ERR, "debugfs_create_file: fail\n");
+ goto failed_create_dir;
+ }
+ msm_fw_debug = 0x18;
failed_create_dir:
return dir;
}
diff --git a/drivers/media/video/msm_vidc/msm_vidc_debug.h b/drivers/media/video/msm_vidc/msm_vidc_debug.h
index b641953..1a51173 100644
--- a/drivers/media/video/msm_vidc/msm_vidc_debug.h
+++ b/drivers/media/video/msm_vidc/msm_vidc_debug.h
@@ -42,6 +42,8 @@
};
extern int msm_vidc_debug;
+extern int msm_fw_debug;
+
#define dprintk(__level, __fmt, arg...) \
do { \
if (msm_vidc_debug & __level) \
diff --git a/drivers/media/video/msm_vidc/vidc_hal.c b/drivers/media/video/msm_vidc/vidc_hal.c
index aa30644..16e70b2 100644
--- a/drivers/media/video/msm_vidc/vidc_hal.c
+++ b/drivers/media/video/msm_vidc/vidc_hal.c
@@ -644,6 +644,24 @@
VIDC_VENUS0_WRAPPER_VBIF_REQ_PRIORITY, 0x5555556, 0);
}
+static int vidc_hal_sys_set_debug(struct hal_device *device, int debug)
+{
+ struct hfi_debug_config *hfi;
+ u8 packet[VIDC_IFACEQ_VAR_SMALL_PKT_SIZE];
+ struct hfi_cmd_sys_set_property_packet *pkt =
+ (struct hfi_cmd_sys_set_property_packet *) &packet;
+ pkt->size = sizeof(struct hfi_cmd_sys_set_property_packet) +
+ sizeof(struct hfi_debug_config) + sizeof(u32);
+ pkt->packet_type = HFI_CMD_SYS_SET_PROPERTY;
+ pkt->num_properties = 1;
+ pkt->rg_property_data[0] = HFI_PROPERTY_SYS_DEBUG_CONFIG;
+ hfi = (struct hfi_debug_config *) &pkt->rg_property_data[1];
+ hfi->debug_config = debug;
+ if (vidc_hal_iface_cmdq_write(device, pkt))
+ return -ENOTEMPTY;
+ return 0;
+}
+
int vidc_hal_core_init(void *device, int domain)
{
struct hfi_cmd_sys_init_packet pkt;
@@ -1444,17 +1462,6 @@
}
case HAL_CONFIG_VPE_DEINTERLACE:
break;
- case HAL_SYS_DEBUG_CONFIG:
- {
- struct hfi_debug_config *hfi;
- pkt->rg_property_data[0] = HFI_PROPERTY_SYS_DEBUG_CONFIG;
- hfi = (struct hfi_debug_config *) &pkt->rg_property_data[1];
- hfi->debug_config = ((struct hal_debug_config *)
- pdata)->debug_config;
- pkt->size = sizeof(struct hfi_cmd_sys_set_property_packet) +
- sizeof(struct hfi_debug_config);
- break;
- }
/* FOLLOWING PROPERTIES ARE NOT IMPLEMENTED IN CORE YET */
case HAL_CONFIG_BUFFER_REQUIREMENTS:
case HAL_CONFIG_PRIORITY:
@@ -1645,6 +1652,8 @@
pkt.session_codec = codec_type;
if (vidc_hal_iface_cmdq_write(dev, &pkt))
return NULL;
+ if (vidc_hal_sys_set_debug(dev, msm_fw_debug))
+ dprintk(VIDC_ERR, "Setting fw_debug msg ON failed");
return (void *) new_session;
}
diff --git a/drivers/media/video/msm_vidc/vidc_hal_interrupt_handler.c b/drivers/media/video/msm_vidc/vidc_hal_interrupt_handler.c
index a0dd93c..933c3ea 100644
--- a/drivers/media/video/msm_vidc/vidc_hal_interrupt_handler.c
+++ b/drivers/media/video/msm_vidc/vidc_hal_interrupt_handler.c
@@ -849,7 +849,12 @@
if (device) {
while (!vidc_hal_iface_msgq_read(device, packet)) {
hal_process_msg_packet(device,
- (struct vidc_hal_msg_pkt_hdr *) packet);
+ (struct vidc_hal_msg_pkt_hdr *) packet);
+ }
+ while (!vidc_hal_iface_dbgq_read(device, packet)) {
+ struct hfi_msg_sys_debug_packet *pkt =
+ (struct hfi_msg_sys_debug_packet *) packet;
+ dprintk(VIDC_FW, "FW-SAYS: %s", pkt->rg_msg_data);
}
} else {
dprintk(VIDC_ERR, "SPURIOUS_INTERRUPT");
diff --git a/drivers/platform/msm/qpnp-pwm.c b/drivers/platform/msm/qpnp-pwm.c
index a938a45..1729b49 100644
--- a/drivers/platform/msm/qpnp-pwm.c
+++ b/drivers/platform/msm/qpnp-pwm.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
@@ -168,6 +168,18 @@
QPNP_LPG_REVISION_1 = 0x1,
};
+/* LPG LUT MODE STATE */
+enum qpnp_lut_state {
+ QPNP_LUT_ENABLE = 0x0,
+ QPNP_LUT_DISABLE = 0x1,
+};
+
+/* PWM MODE STATE */
+enum qpnp_pwm_state {
+ QPNP_PWM_ENABLE = 0x0,
+ QPNP_PWM_DISABLE = 0x1,
+};
+
/* SPMI LPG registers */
enum qpnp_lpg_registers_list {
QPNP_LPG_PATTERN_CONFIG,
@@ -261,7 +273,7 @@
struct qpnp_lpg_chip {
struct spmi_device *spmi_dev;
struct pwm_device pwm_dev;
- struct mutex lpg_mutex;
+ spinlock_t lpg_lock;
struct qpnp_lpg_config lpg_config;
u8 qpnp_lpg_registers[QPNP_TOTAL_LPG_SPMI_REGISTERS];
enum qpnp_lpg_revision revision;
@@ -294,21 +306,22 @@
QPNP_EN_GLITCH_REMOVAL_MASK;
}
-static inline void qpnp_set_control(u8 *val, bool pwm_hi, bool pwm_lo,
- bool pwm_out, bool pwm_src, bool ramp_gen)
+static int qpnp_set_control(bool pwm_hi, bool pwm_lo, bool pwm_out,
+ bool pwm_src, bool ramp_gen)
{
- *val = (ramp_gen << QPNP_PWM_EN_RAMP_GEN_SHIFT) &
- QPNP_PWM_EN_RAMP_GEN_MASK;
- *val |= (pwm_src << QPNP_PWM_SRC_SELECT_SHIFT) &
- QPNP_PWM_SRC_SELECT_MASK;
- *val |= (pwm_out << QPNP_EN_PWM_OUTPUT_SHIFT) &
- QPNP_EN_PWM_OUTPUT_MASK;
- *val |= (pwm_lo << QPNP_EN_PWM_LO_SHIFT) & QPNP_EN_PWM_LO_MASK;
- *val |= (pwm_hi << QPNP_EN_PWM_HIGH_SHIFT) & QPNP_EN_PWM_HIGH_MASK;
+ return (ramp_gen << QPNP_PWM_EN_RAMP_GEN_SHIFT)
+ | (pwm_src << QPNP_PWM_SRC_SELECT_SHIFT)
+ | (pwm_out << QPNP_EN_PWM_OUTPUT_SHIFT)
+ | (pwm_lo << QPNP_EN_PWM_LO_SHIFT)
+ | (pwm_hi << QPNP_EN_PWM_HIGH_SHIFT);
}
-#define QPNP_ENABLE_LUT_CONTROL(p_val) qpnp_set_control(p_val, 1, 1, 1, 0, 1)
-#define QPNP_ENABLE_PWM_CONTROL(p_val) qpnp_set_control(p_val, 1, 1, 0, 1, 0)
+#define QPNP_ENABLE_LUT_CONTROL qpnp_set_control(0, 0, 0, 0, 1)
+#define QPNP_ENABLE_PWM_CONTROL qpnp_set_control(0, 0, 0, 1, 0)
+#define QPNP_ENABLE_PWM_MODE qpnp_set_control(1, 1, 1, 1, 0)
+#define QPNP_ENABLE_LPG_MODE qpnp_set_control(1, 1, 1, 0, 1)
+#define QPNP_DISABLE_PWM_MODE qpnp_set_control(0, 0, 0, 1, 0)
+#define QPNP_DISABLE_LPG_MODE qpnp_set_control(0, 0, 0, 0, 1)
#define QPNP_IS_PWM_CONFIG_SELECTED(val) (val & QPNP_PWM_SRC_SELECT_MASK)
@@ -339,13 +352,13 @@
*u8p |= val & mask;
}
-static int qpnp_lpg_save_and_write(u8 value, u8 mask, u8 *reg, u16 base_addr,
- u16 offset, u16 size, struct qpnp_lpg_chip *chip)
+static int qpnp_lpg_save_and_write(u8 value, u8 mask, u8 *reg, u16 addr,
+ u16 size, struct qpnp_lpg_chip *chip)
{
qpnp_lpg_save(reg, mask, value);
return spmi_ext_register_writel(chip->spmi_dev->ctrl,
- chip->spmi_dev->sid, SPMI_LPG_REG_ADDR(base_addr, offset), reg, size);
+ chip->spmi_dev->sid, addr, reg, size);
}
/*
@@ -466,7 +479,7 @@
return -EINVAL;
}
- for (i = 0; i <= lut->list_len; i++) {
+ for (i = 0; i < lut->list_len; i++) {
if (raw_value)
pwm_value = duty_pct[i];
else
@@ -541,7 +554,8 @@
rc = qpnp_lpg_save_and_write(value, mask,
&pwm->chip->qpnp_lpg_registers[QPNP_PWM_VALUE_LSB],
- lpg_config->base_addr, QPNP_PWM_VALUE_LSB, 1, chip);
+ SPMI_LPG_REG_ADDR(lpg_config->base_addr,
+ QPNP_PWM_VALUE_LSB), 1, chip);
if (rc)
return rc;
@@ -552,7 +566,8 @@
return qpnp_lpg_save_and_write(value, mask,
&pwm->chip->qpnp_lpg_registers[QPNP_PWM_VALUE_MSB],
- lpg_config->base_addr, QPNP_PWM_VALUE_MSB, 1, chip);
+ SPMI_LPG_REG_ADDR(lpg_config->base_addr,
+ QPNP_PWM_VALUE_MSB), 1, chip);
}
static int qpnp_lpg_configure_pattern(struct pwm_device *pwm)
@@ -570,7 +585,8 @@
return qpnp_lpg_save_and_write(value, mask,
&pwm->chip->qpnp_lpg_registers[QPNP_LPG_PATTERN_CONFIG],
- lpg_config->base_addr, QPNP_LPG_PATTERN_CONFIG, 1, chip);
+ SPMI_LPG_REG_ADDR(lpg_config->base_addr,
+ QPNP_LPG_PATTERN_CONFIG), 1, chip);
}
static int qpnp_lpg_configure_pwm(struct pwm_device *pwm)
@@ -601,7 +617,8 @@
return qpnp_lpg_save_and_write(value, mask,
&pwm->chip->qpnp_lpg_registers[QPNP_LPG_PWM_TYPE_CONFIG],
- lpg_config->base_addr, QPNP_LPG_PWM_TYPE_CONFIG, 1, chip);
+ SPMI_LPG_REG_ADDR(lpg_config->base_addr,
+ QPNP_LPG_PWM_TYPE_CONFIG), 1, chip);
}
static int qpnp_configure_pwm_control(struct pwm_device *pwm)
@@ -610,7 +627,7 @@
struct qpnp_lpg_chip *chip = pwm->chip;
u8 value, mask;
- QPNP_ENABLE_PWM_CONTROL(&value);
+ value = QPNP_ENABLE_PWM_CONTROL;
mask = QPNP_EN_PWM_HIGH_MASK | QPNP_EN_PWM_LO_MASK |
QPNP_EN_PWM_OUTPUT_MASK | QPNP_PWM_SRC_SELECT_MASK |
@@ -618,7 +635,8 @@
return qpnp_lpg_save_and_write(value, mask,
&pwm->chip->qpnp_lpg_registers[QPNP_ENABLE_CONTROL],
- lpg_config->base_addr, QPNP_ENABLE_CONTROL, 1, chip);
+ SPMI_LPG_REG_ADDR(lpg_config->base_addr,
+ QPNP_ENABLE_CONTROL), 1, chip);
}
@@ -628,7 +646,7 @@
struct qpnp_lpg_chip *chip = pwm->chip;
u8 value, mask;
- QPNP_ENABLE_LUT_CONTROL(&value);
+ value = QPNP_ENABLE_LUT_CONTROL;
mask = QPNP_EN_PWM_HIGH_MASK | QPNP_EN_PWM_LO_MASK |
QPNP_EN_PWM_OUTPUT_MASK | QPNP_PWM_SRC_SELECT_MASK |
@@ -636,7 +654,8 @@
return qpnp_lpg_save_and_write(value, mask,
&pwm->chip->qpnp_lpg_registers[QPNP_ENABLE_CONTROL],
- lpg_config->base_addr, QPNP_ENABLE_CONTROL, 1, chip);
+ SPMI_LPG_REG_ADDR(lpg_config->base_addr,
+ QPNP_ENABLE_CONTROL), 1, chip);
}
@@ -654,7 +673,8 @@
rc = qpnp_lpg_save_and_write(val, mask,
&pwm->chip->qpnp_lpg_registers[QPNP_RAMP_STEP_DURATION_LSB],
- lpg_config->base_addr, QPNP_RAMP_STEP_DURATION_LSB, 1, chip);
+ SPMI_LPG_REG_ADDR(lpg_config->base_addr,
+ QPNP_RAMP_STEP_DURATION_LSB), 1, chip);
if (rc)
return rc;
@@ -665,7 +685,8 @@
return qpnp_lpg_save_and_write(val, mask,
&pwm->chip->qpnp_lpg_registers[QPNP_RAMP_STEP_DURATION_MSB],
- lpg_config->base_addr, QPNP_RAMP_STEP_DURATION_MSB, 1, chip);
+ SPMI_LPG_REG_ADDR(lpg_config->base_addr,
+ QPNP_RAMP_STEP_DURATION_MSB), 1, chip);
}
static int qpnp_lpg_configure_pause(struct pwm_device *pwm)
@@ -682,7 +703,8 @@
rc = qpnp_lpg_save_and_write(value, mask,
&pwm->chip->qpnp_lpg_registers[QPNP_PAUSE_HI_MULTIPLIER_LSB],
- lpg_config->base_addr, QPNP_PAUSE_HI_MULTIPLIER_LSB, 1, chip);
+ SPMI_LPG_REG_ADDR(lpg_config->base_addr,
+ QPNP_PAUSE_HI_MULTIPLIER_LSB), 1, chip);
if (rc)
return rc;
@@ -694,14 +716,16 @@
rc = qpnp_lpg_save_and_write(value, mask,
&pwm->chip->qpnp_lpg_registers[QPNP_PAUSE_HI_MULTIPLIER_MSB],
- lpg_config->base_addr, QPNP_PAUSE_HI_MULTIPLIER_MSB, 1, chip);
+ SPMI_LPG_REG_ADDR(lpg_config->base_addr,
+ QPNP_PAUSE_HI_MULTIPLIER_MSB), 1, chip);
} else {
value = 0;
mask = QPNP_PAUSE_HI_MULTIPLIER_LSB_MASK;
rc = qpnp_lpg_save_and_write(value, mask,
&pwm->chip->qpnp_lpg_registers[QPNP_PAUSE_HI_MULTIPLIER_LSB],
- lpg_config->base_addr, QPNP_PAUSE_HI_MULTIPLIER_LSB, 1, chip);
+ SPMI_LPG_REG_ADDR(lpg_config->base_addr,
+ QPNP_PAUSE_HI_MULTIPLIER_LSB), 1, chip);
if (rc)
return rc;
@@ -709,7 +733,8 @@
rc = qpnp_lpg_save_and_write(value, mask,
&pwm->chip->qpnp_lpg_registers[QPNP_PAUSE_HI_MULTIPLIER_MSB],
- lpg_config->base_addr, QPNP_PAUSE_HI_MULTIPLIER_MSB, 1, chip);
+ SPMI_LPG_REG_ADDR(lpg_config->base_addr,
+ QPNP_PAUSE_HI_MULTIPLIER_MSB), 1, chip);
if (rc)
return rc;
@@ -721,7 +746,8 @@
rc = qpnp_lpg_save_and_write(value, mask,
&pwm->chip->qpnp_lpg_registers[QPNP_PAUSE_LO_MULTIPLIER_LSB],
- lpg_config->base_addr, QPNP_PAUSE_LO_MULTIPLIER_LSB, 1, chip);
+ SPMI_LPG_REG_ADDR(lpg_config->base_addr,
+ QPNP_PAUSE_LO_MULTIPLIER_LSB), 1, chip);
if (rc)
return rc;
@@ -733,14 +759,16 @@
rc = qpnp_lpg_save_and_write(value, mask,
&pwm->chip->qpnp_lpg_registers[QPNP_PAUSE_LO_MULTIPLIER_MSB],
- lpg_config->base_addr, QPNP_PAUSE_LO_MULTIPLIER_MSB, 1, chip);
+ SPMI_LPG_REG_ADDR(lpg_config->base_addr,
+ QPNP_PAUSE_LO_MULTIPLIER_MSB), 1, chip);
} else {
value = 0;
mask = QPNP_PAUSE_LO_MULTIPLIER_LSB_MASK;
rc = qpnp_lpg_save_and_write(value, mask,
&pwm->chip->qpnp_lpg_registers[QPNP_PAUSE_LO_MULTIPLIER_LSB],
- lpg_config->base_addr, QPNP_PAUSE_LO_MULTIPLIER_LSB, 1, chip);
+ SPMI_LPG_REG_ADDR(lpg_config->base_addr,
+ QPNP_PAUSE_LO_MULTIPLIER_LSB), 1, chip);
if (rc)
return rc;
@@ -748,7 +776,8 @@
rc = qpnp_lpg_save_and_write(value, mask,
&pwm->chip->qpnp_lpg_registers[QPNP_PAUSE_LO_MULTIPLIER_MSB],
- lpg_config->base_addr, QPNP_PAUSE_LO_MULTIPLIER_MSB, 1, chip);
+ SPMI_LPG_REG_ADDR(lpg_config->base_addr,
+ QPNP_PAUSE_LO_MULTIPLIER_MSB), 1, chip);
return rc;
}
@@ -768,7 +797,8 @@
rc = qpnp_lpg_save_and_write(value, mask,
&pwm->chip->qpnp_lpg_registers[QPNP_HI_INDEX],
- lpg_config->base_addr, QPNP_HI_INDEX, 1, chip);
+ SPMI_LPG_REG_ADDR(lpg_config->base_addr,
+ QPNP_HI_INDEX), 1, chip);
if (rc)
return rc;
@@ -777,7 +807,8 @@
rc = qpnp_lpg_save_and_write(value, mask,
&pwm->chip->qpnp_lpg_registers[QPNP_LO_INDEX],
- lpg_config->base_addr, QPNP_LO_INDEX, 1, chip);
+ SPMI_LPG_REG_ADDR(lpg_config->base_addr,
+ QPNP_LO_INDEX), 1, chip);
return rc;
}
@@ -819,90 +850,85 @@
return rc;
}
-static int qpnp_lpg_enable_lut(struct pwm_device *pwm)
+static int qpnp_lpg_configure_lut_state(struct pwm_device *pwm,
+ enum qpnp_lut_state state)
{
struct qpnp_lpg_config *lpg_config = &pwm->chip->lpg_config;
struct qpnp_lpg_chip *chip = pwm->chip;
- u8 value, mask, *reg;
+ u8 value1, value2, mask1, mask2;
+ u8 *reg1, *reg2;
u16 addr;
+ int rc;
- value = pwm->chip->qpnp_lpg_registers[QPNP_RAMP_CONTROL];
- reg = &pwm->chip->qpnp_lpg_registers[QPNP_RAMP_CONTROL];
+ value1 = pwm->chip->qpnp_lpg_registers[QPNP_RAMP_CONTROL];
+ reg1 = &pwm->chip->qpnp_lpg_registers[QPNP_RAMP_CONTROL];
+ reg2 = &pwm->chip->qpnp_lpg_registers[QPNP_ENABLE_CONTROL];
+ mask2 = QPNP_EN_PWM_HIGH_MASK | QPNP_EN_PWM_LO_MASK |
+ QPNP_EN_PWM_OUTPUT_MASK | QPNP_PWM_SRC_SELECT_MASK |
+ QPNP_PWM_EN_RAMP_GEN_MASK;
switch (chip->revision) {
case QPNP_LPG_REVISION_0:
- QPNP_ENABLE_LUT_V0(value);
- mask = QPNP_RAMP_START_MASK;
+ if (state == QPNP_LUT_ENABLE) {
+ QPNP_ENABLE_LUT_V0(value1);
+ value2 = QPNP_ENABLE_LPG_MODE;
+ } else {
+ QPNP_DISABLE_LUT_V0(value1);
+ value2 = QPNP_DISABLE_LPG_MODE;
+ }
+ mask1 = QPNP_RAMP_START_MASK;
addr = SPMI_LPG_REG_ADDR(lpg_config->base_addr,
QPNP_RAMP_CONTROL);
break;
case QPNP_LPG_REVISION_1:
- QPNP_ENABLE_LUT_V1(value, pwm->pwm_config.channel_id);
- mask = BIT(pwm->pwm_config.channel_id);
- addr = lpg_config->lut_base_addr +
- SPMI_LPG_REV1_RAMP_CONTROL_OFFSET;
- default:
- pr_err("Invalid LPG revision\n");
- return -EINVAL;
- }
-
- qpnp_lpg_save(reg, mask, value);
-
- return spmi_ext_register_writel(chip->spmi_dev->ctrl,
- chip->spmi_dev->sid, addr, reg, 1);
-}
-
-static int qpnp_lpg_disable_lut(struct pwm_device *pwm)
-{
- struct qpnp_lpg_config *lpg_config = &pwm->chip->lpg_config;
- struct qpnp_lpg_chip *chip = pwm->chip;
- u8 value, mask, *reg;
- u16 addr;
-
- value = pwm->chip->qpnp_lpg_registers[QPNP_RAMP_CONTROL];
- reg = &pwm->chip->qpnp_lpg_registers[QPNP_RAMP_CONTROL];
-
- switch (chip->revision) {
- case QPNP_LPG_REVISION_0:
- QPNP_DISABLE_LUT_V0(value);
- mask = QPNP_RAMP_START_MASK;
- addr = SPMI_LPG_REG_ADDR(lpg_config->base_addr,
- QPNP_RAMP_CONTROL);
- break;
- case QPNP_LPG_REVISION_1:
- QPNP_DISABLE_LUT_V1(value, pwm->pwm_config.channel_id);
- mask = BIT(pwm->pwm_config.channel_id);
+ if (state == QPNP_LUT_ENABLE) {
+ QPNP_ENABLE_LUT_V1(value1, pwm->pwm_config.channel_id);
+ value2 = QPNP_ENABLE_LPG_MODE;
+ } else {
+ QPNP_DISABLE_LUT_V1(value1, pwm->pwm_config.channel_id);
+ value2 = QPNP_DISABLE_LPG_MODE;
+ }
+ mask1 = BIT(pwm->pwm_config.channel_id);
addr = lpg_config->lut_base_addr +
SPMI_LPG_REV1_RAMP_CONTROL_OFFSET;
break;
default:
pr_err("Invalid LPG revision\n");
return -EINVAL;
- break;
}
- qpnp_lpg_save(reg, mask, value);
+ rc = qpnp_lpg_save_and_write(value1, mask1, reg1,
+ addr, 1, chip);
+ if (rc)
+ return rc;
+ addr = SPMI_LPG_REG_ADDR(lpg_config->base_addr,
+ QPNP_ENABLE_CONTROL);
+ return qpnp_lpg_save_and_write(value2, mask2, reg2,
+ addr, 1, chip);
- return spmi_ext_register_writel(chip->spmi_dev->ctrl,
- chip->spmi_dev->sid, addr, reg, 1);
}
-static int qpnp_lpg_enable_pwm(struct pwm_device *pwm)
+static int qpnp_lpg_configure_pwm_state(struct pwm_device *pwm,
+ enum qpnp_pwm_state state)
{
struct qpnp_lpg_config *lpg_config = &pwm->chip->lpg_config;
struct qpnp_lpg_chip *chip = pwm->chip;
u8 value, mask;
int rc;
- value = pwm->chip->qpnp_lpg_registers[QPNP_ENABLE_CONTROL];
+ if (state == QPNP_PWM_ENABLE)
+ value = QPNP_ENABLE_PWM_MODE;
+ else
+ value = QPNP_DISABLE_PWM_MODE;
- QPNP_ENABLE_PWM(value);
-
- mask = QPNP_EN_PWM_OUTPUT_MASK;
+ mask = QPNP_EN_PWM_HIGH_MASK | QPNP_EN_PWM_LO_MASK |
+ QPNP_EN_PWM_OUTPUT_MASK | QPNP_PWM_SRC_SELECT_MASK |
+ QPNP_PWM_EN_RAMP_GEN_MASK;
rc = qpnp_lpg_save_and_write(value, mask,
&pwm->chip->qpnp_lpg_registers[QPNP_ENABLE_CONTROL],
- lpg_config->base_addr, QPNP_ENABLE_CONTROL, 1, chip);
+ SPMI_LPG_REG_ADDR(lpg_config->base_addr,
+ QPNP_ENABLE_CONTROL), 1, chip);
if (rc)
goto out;
@@ -910,29 +936,13 @@
* Due to LPG hardware bug, in the PWM mode, having enabled PWM,
* We have to write PWM values one more time.
*/
- return qpnp_lpg_save_pwm_value(pwm);
+ if (state == QPNP_PWM_ENABLE)
+ return qpnp_lpg_save_pwm_value(pwm);
out:
return rc;
}
-static int qpnp_lpg_disable_pwm(struct pwm_device *pwm)
-{
- struct qpnp_lpg_config *lpg_config = &pwm->chip->lpg_config;
- struct qpnp_lpg_chip *chip = pwm->chip;
- u8 value, mask;
-
- value = pwm->chip->qpnp_lpg_registers[QPNP_ENABLE_CONTROL];
-
- QPNP_DISABLE_PWM(value);
-
- mask = QPNP_EN_PWM_OUTPUT_MASK;
-
- return qpnp_lpg_save_and_write(value, mask,
- &pwm->chip->qpnp_lpg_registers[QPNP_ENABLE_CONTROL],
- lpg_config->base_addr, QPNP_ENABLE_CONTROL, 1, chip);
-}
-
static int _pwm_config(struct pwm_device *pwm, int duty_us, int period_us)
{
struct qpnp_pwm_config *pwm_config;
@@ -1056,18 +1066,23 @@
{
int rc;
struct qpnp_lpg_chip *chip;
+ unsigned long flags;
chip = pwm->chip;
- mutex_lock(&pwm->chip->lpg_mutex);
+ spin_lock_irqsave(&pwm->chip->lpg_lock, flags);
if (QPNP_IS_PWM_CONFIG_SELECTED(
chip->qpnp_lpg_registers[QPNP_ENABLE_CONTROL]))
- rc = qpnp_lpg_enable_pwm(pwm);
+ rc = qpnp_lpg_configure_pwm_state(pwm, QPNP_PWM_ENABLE);
else
- rc = qpnp_lpg_enable_lut(pwm);
+ rc = qpnp_lpg_configure_lut_state(pwm, QPNP_LUT_ENABLE);
- mutex_unlock(&pwm->chip->lpg_mutex);
+ spin_unlock_irqrestore(&pwm->chip->lpg_lock, flags);
+
+ if (rc)
+ pr_err("Failed to enable PWM channel: %d\n",
+ pwm->pwm_config.channel_id);
return rc;
}
@@ -1082,6 +1097,7 @@
{
struct qpnp_lpg_chip *chip;
struct pwm_device *pwm;
+ unsigned long flags;
chip = radix_tree_lookup(&lpg_dev_tree, pwm_id);
@@ -1091,7 +1107,7 @@
return ERR_PTR(-EINVAL);
}
- mutex_lock(&chip->lpg_mutex);
+ spin_lock_irqsave(&chip->lpg_lock, flags);
pwm = &chip->pwm_dev;
@@ -1105,7 +1121,7 @@
pwm->pwm_config.lable = lable;
}
- mutex_unlock(&chip->lpg_mutex);
+ spin_unlock_irqrestore(&chip->lpg_lock, flags);
return pwm;
}
@@ -1118,24 +1134,25 @@
void pwm_free(struct pwm_device *pwm)
{
struct qpnp_pwm_config *pwm_config;
+ unsigned long flags;
if (pwm == NULL || IS_ERR(pwm) || pwm->chip == NULL) {
pr_err("Invalid pwm handle or no pwm_chip\n");
return;
}
- mutex_lock(&pwm->chip->lpg_mutex);
+ spin_lock_irqsave(&pwm->chip->lpg_lock, flags);
pwm_config = &pwm->pwm_config;
if (pwm_config->in_use) {
- qpnp_lpg_disable_pwm(pwm);
- qpnp_lpg_disable_lut(pwm);
+ qpnp_lpg_configure_pwm_state(pwm, QPNP_PWM_DISABLE);
+ qpnp_lpg_configure_lut_state(pwm, QPNP_LUT_DISABLE);
pwm_config->in_use = 0;
pwm_config->lable = NULL;
}
- mutex_unlock(&pwm->chip->lpg_mutex);
+ spin_unlock_irqrestore(&pwm->chip->lpg_lock, flags);
}
EXPORT_SYMBOL_GPL(pwm_free);
@@ -1148,6 +1165,7 @@
int pwm_config(struct pwm_device *pwm, int duty_us, int period_us)
{
int rc;
+ unsigned long flags;
if (pwm == NULL || IS_ERR(pwm) ||
duty_us > period_us ||
@@ -1160,9 +1178,12 @@
if (!pwm->pwm_config.in_use)
return -EINVAL;
- mutex_lock(&pwm->chip->lpg_mutex);
+ spin_lock_irqsave(&pwm->chip->lpg_lock, flags);
rc = _pwm_config(pwm, duty_us, period_us);
- mutex_unlock(&pwm->chip->lpg_mutex);
+ spin_unlock_irqrestore(&pwm->chip->lpg_lock, flags);
+
+ if (rc)
+ pr_err("Failed to configure PWM mode\n");
return rc;
}
@@ -1200,13 +1221,15 @@
{
struct qpnp_pwm_config *pwm_config;
struct qpnp_lpg_chip *chip;
+ unsigned long flags;
+ int rc = 0;
if (pwm == NULL || IS_ERR(pwm) || pwm->chip == NULL) {
pr_err("Invalid pwm handle or no pwm_chip\n");
return;
}
- mutex_lock(&pwm->chip->lpg_mutex);
+ spin_lock_irqsave(&pwm->chip->lpg_lock, flags);
chip = pwm->chip;
pwm_config = &pwm->pwm_config;
@@ -1214,12 +1237,18 @@
if (pwm_config->in_use) {
if (QPNP_IS_PWM_CONFIG_SELECTED(
chip->qpnp_lpg_registers[QPNP_ENABLE_CONTROL]))
- qpnp_lpg_disable_pwm(pwm);
+ rc = qpnp_lpg_configure_pwm_state(pwm,
+ QPNP_PWM_DISABLE);
else
- qpnp_lpg_disable_lut(pwm);
+ rc = qpnp_lpg_configure_lut_state(pwm,
+ QPNP_LUT_DISABLE);
}
- mutex_unlock(&pwm->chip->lpg_mutex);
+ spin_unlock_irqrestore(&pwm->chip->lpg_lock, flags);
+
+ if (rc)
+ pr_err("Failed to disable PWM channel: %d\n",
+ pwm_config->channel_id);
}
EXPORT_SYMBOL_GPL(pwm_disable);
@@ -1231,6 +1260,7 @@
int pwm_change_mode(struct pwm_device *pwm, enum pm_pwm_mode mode)
{
int rc;
+ unsigned long flags;
if (pwm == NULL || IS_ERR(pwm) || pwm->chip == NULL) {
pr_err("Invalid pwm handle or no pwm_chip\n");
@@ -1242,15 +1272,17 @@
return -EINVAL;
}
- mutex_lock(&pwm->chip->lpg_mutex);
+ spin_lock_irqsave(&pwm->chip->lpg_lock, flags);
if (mode)
rc = qpnp_configure_lpg_control(pwm);
else
rc = qpnp_configure_pwm_control(pwm);
- mutex_unlock(&pwm->chip->lpg_mutex);
+ spin_unlock_irqrestore(&pwm->chip->lpg_lock, flags);
+ if (rc)
+ pr_err("Failed to change the mode\n");
return rc;
}
EXPORT_SYMBOL_GPL(pwm_change_mode);
@@ -1267,6 +1299,7 @@
struct qpnp_pwm_config *pwm_config;
struct qpnp_lpg_config *lpg_config;
struct qpnp_lpg_chip *chip;
+ unsigned long flags;
int rc = 0;
if (pwm == NULL || IS_ERR(pwm) || period == NULL)
@@ -1274,7 +1307,7 @@
if (pwm->chip == NULL)
return -ENODEV;
- mutex_lock(&pwm->chip->lpg_mutex);
+ spin_lock_irqsave(&pwm->chip->lpg_lock, flags);
chip = pwm->chip;
pwm_config = &pwm->pwm_config;
@@ -1313,7 +1346,7 @@
}
out_unlock:
- mutex_unlock(&pwm->chip->lpg_mutex);
+ spin_unlock_irqrestore(&pwm->chip->lpg_lock, flags);
return rc;
}
EXPORT_SYMBOL(pwm_config_period);
@@ -1327,21 +1360,27 @@
{
struct qpnp_lpg_config *lpg_config;
struct qpnp_pwm_config *pwm_config;
+ unsigned long flags;
int rc = 0;
- if (pwm == NULL || IS_ERR(pwm))
+ if (pwm == NULL || IS_ERR(pwm)) {
+ pr_err("Invalid parameter passed\n");
return -EINVAL;
+ }
- if (pwm->chip == NULL)
+ if (pwm->chip == NULL) {
+ pr_err("Invalid device handle\n");
return -ENODEV;
+ }
lpg_config = &pwm->chip->lpg_config;
pwm_config = &pwm->pwm_config;
- mutex_lock(&pwm->chip->lpg_mutex);
+ spin_lock_irqsave(&pwm->chip->lpg_lock, flags);
if (!pwm_config->in_use || !pwm_config->pwm_period) {
rc = -EINVAL;
+ pr_err("PWM channel isn't in use or period value missing\n");
goto out_unlock;
}
@@ -1357,7 +1396,7 @@
pwm_config->channel_id, rc);
out_unlock:
- mutex_unlock(&pwm->chip->lpg_mutex);
+ spin_unlock_irqrestore(&pwm->chip->lpg_lock, flags);
return rc;
}
EXPORT_SYMBOL_GPL(pwm_config_pwm_value);
@@ -1372,6 +1411,7 @@
int pwm_lut_config(struct pwm_device *pwm, int period_us,
int duty_pct[], struct lut_params lut_params)
{
+ unsigned long flags;
int rc = 0;
if (pwm == NULL || IS_ERR(pwm) || !lut_params.idx_len) {
@@ -1405,11 +1445,14 @@
return -EINVAL;
}
- mutex_lock(&pwm->chip->lpg_mutex);
+ spin_lock_irqsave(&pwm->chip->lpg_lock, flags);
rc = _pwm_lut_config(pwm, period_us, duty_pct, lut_params);
- mutex_unlock(&pwm->chip->lpg_mutex);
+ spin_unlock_irqrestore(&pwm->chip->lpg_lock, flags);
+
+ if (rc)
+ pr_err("Failed to configure LUT\n");
return rc;
}
@@ -1640,7 +1683,7 @@
return -ENOMEM;
}
- mutex_init(&chip->lpg_mutex);
+ spin_lock_init(&chip->lpg_lock);
chip->spmi_dev = spmi;
chip->pwm_dev.chip = chip;
@@ -1680,7 +1723,6 @@
kfree(chip->lpg_config.lut_config.duty_pct_list);
failed_config:
dev_set_drvdata(&spmi->dev, NULL);
- mutex_destroy(&chip->lpg_mutex);
kfree(chip);
return rc;
}
@@ -1697,7 +1739,6 @@
if (chip) {
lpg_config = &chip->lpg_config;
kfree(lpg_config->lut_config.duty_pct_list);
- mutex_destroy(&chip->lpg_mutex);
kfree(chip);
}
diff --git a/drivers/thermal/msm8974-tsens.c b/drivers/thermal/msm8974-tsens.c
index 77cc1f9..f3387d9 100644
--- a/drivers/thermal/msm8974-tsens.c
+++ b/drivers/thermal/msm8974-tsens.c
@@ -56,6 +56,13 @@
#define TSENS_S0_MAIN_CONFIG(n) ((n) + 0x38)
#define TSENS_SN_REMOTE_CONFIG(n) ((n) + 0x3c)
+#define TSENS_EEPROM(n) ((n) + 0xd0)
+#define TSENS_EEPROM_REDUNDANCY_SEL(n) ((n) + 0x1cc)
+#define TSENS_EEPROM_BACKUP_REGION(n) ((n) + 0x440)
+
+#define TSENS_MAIN_CALIB_ADDR_RANGE 6
+#define TSENS_BACKUP_CALIB_ADDR_RANGE 4
+
/* TSENS calibration Mask data */
#define TSENS_BASE1_MASK 0xff
#define TSENS0_POINT1_MASK 0x3f00
@@ -67,8 +74,11 @@
#define TSENS6_POINT1_MASK 0x3f000
#define TSENS7_POINT1_MASK 0xfc0000
#define TSENS8_POINT1_MASK 0x3f000000
+#define TSENS8_POINT1_MASK_BACKUP 0x3f
#define TSENS9_POINT1_MASK 0x3f
+#define TSENS9_POINT1_MASK_BACKUP 0xfc0
#define TSENS10_POINT1_MASK 0xfc00
+#define TSENS10_POINT1_MASK_BACKUP 0x3f000
#define TSENS_CAL_SEL_0_1 0xc0000000
#define TSENS_CAL_SEL_2 0x40000000
#define TSENS_CAL_SEL_SHIFT 30
@@ -85,31 +95,55 @@
#define TSENS6_POINT1_SHIFT 12
#define TSENS7_POINT1_SHIFT 18
#define TSENS8_POINT1_SHIFT 24
+#define TSENS9_POINT1_BACKUP_SHIFT 6
#define TSENS10_POINT1_SHIFT 6
+#define TSENS10_POINT1_BACKUP_SHIFT 12
#define TSENS_POINT2_BASE_SHIFT 12
+#define TSENS_POINT2_BASE_BACKUP_SHIFT 18
#define TSENS0_POINT2_SHIFT 20
+#define TSENS0_POINT2_BACKUP_SHIFT 26
#define TSENS1_POINT2_SHIFT 26
+#define TSENS2_POINT2_BACKUP_SHIFT 6
#define TSENS3_POINT2_SHIFT 6
+#define TSENS3_POINT2_BACKUP_SHIFT 12
#define TSENS4_POINT2_SHIFT 12
+#define TSENS4_POINT2_BACKUP_SHIFT 18
#define TSENS5_POINT2_SHIFT 18
+#define TSENS5_POINT2_BACKUP_SHIFT 24
#define TSENS6_POINT2_SHIFT 24
+#define TSENS7_POINT2_BACKUP_SHIFT 6
#define TSENS8_POINT2_SHIFT 6
+#define TSENS8_POINT2_BACKUP_SHIFT 12
#define TSENS9_POINT2_SHIFT 12
+#define TSENS9_POINT2_BACKUP_SHIFT 18
#define TSENS10_POINT2_SHIFT 18
+#define TSENS10_POINT2_BACKUP_SHIFT 24
#define TSENS_BASE2_MASK 0xff000
+#define TSENS_BASE2_BACKUP_MASK 0xfc0000
#define TSENS0_POINT2_MASK 0x3f00000
+#define TSENS0_POINT2_BACKUP_MASK 0xfc000000
#define TSENS1_POINT2_MASK 0xfc000000
+#define TSENS1_POINT2_BACKUP_MASK 0x3f
#define TSENS2_POINT2_MASK 0x3f
+#define TSENS2_POINT2_BACKUP_MASK 0xfc0
#define TSENS3_POINT2_MASK 0xfc00
+#define TSENS3_POINT2_BACKUP_MASK 0x3f000
#define TSENS4_POINT2_MASK 0x3f000
+#define TSENS4_POINT2_BACKUP_MASK 0xfc0000
#define TSENS5_POINT2_MASK 0xfc0000
+#define TSENS5_POINT2_BACKUP_MASK 0x3f000000
#define TSENS6_POINT2_MASK 0x3f000000
+#define TSENS6_POINT2_BACKUP_MASK 0x3f
#define TSENS7_POINT2_MASK 0x3f
+#define TSENS7_POINT2_BACKUP_MASK 0xfc00
#define TSENS8_POINT2_MASK 0xfc00
+#define TSENS8_POINT2_BACKUP_MASK 0x3f000
#define TSENS9_POINT2_MASK 0x3f000
+#define TSENS9_POINT2_BACKUP_MASK 0xfc0000
#define TSENS10_POINT2_MASK 0xfc0000
+#define TSENS10_POINT2_BACKUP_MASK 0x3f000000
#define TSENS_BIT_APPEND 0x3
#define TSENS_CAL_DEGC_POINT1 30
@@ -128,6 +162,10 @@
#define TSENS_SN_MIN_MAX_STATUS_CTRL_DATA 0x3ffc00
#define TSENS_SN_REMOTE_CFG_DATA 0x11c3
+#define TSENS_QFPROM_BACKUP_SEL 0x3
+#define TSENS_QFPROM_BACKUP_REDUN_SEL 0xe0000000
+#define TSENS_QFPROM_BACKUP_REDUN_SHIFT 29
+
/* Trips: warm and cool */
enum tsens_trip_type {
TSENS_TRIP_WARM = 0,
@@ -149,6 +187,7 @@
struct tsens_tm_device {
struct platform_device *pdev;
bool prev_reading_avail;
+ bool calibration_less_mode;
int tsens_factor;
uint32_t tsens_num_sensor;
int tsens_irq;
@@ -515,78 +554,185 @@
int tsens6_point2 = 0, tsens7_point2 = 0, tsens8_point2 = 0;
int tsens9_point2 = 0, tsens10_point2 = 0;
int tsens_base2_data = 0, tsens_calibration_mode = 0, temp = 0;
- uint32_t calib_data[5];
+ uint32_t calib_data[6], calib_redun_sel, calib_data_backup[4];
- for (i = 0; i < 5; i++)
- calib_data[i] = readl_relaxed(tmdev->tsens_calib_addr
+ if (tmdev->calibration_less_mode)
+ goto calibration_less_mode;
+
+ calib_redun_sel = readl_relaxed(
+ TSENS_EEPROM_REDUNDANCY_SEL(tmdev->tsens_calib_addr));
+ calib_redun_sel = calib_redun_sel & TSENS_QFPROM_BACKUP_REDUN_SEL;
+ calib_redun_sel >>= TSENS_QFPROM_BACKUP_REDUN_SHIFT;
+
+ for (i = 0; i < TSENS_MAIN_CALIB_ADDR_RANGE; i++)
+ calib_data[i] = readl_relaxed(
+ (TSENS_EEPROM(tmdev->tsens_calib_addr))
+ (i * TSENS_SN_ADDR_OFFSET));
- tsens_calibration_mode = (calib_data[1] & TSENS_CAL_SEL_0_1)
- >> TSENS_CAL_SEL_SHIFT;
- temp = (calib_data[3] & TSENS_CAL_SEL_2)
- >> TSENS_CAL_SEL_SHIFT_2;
- tsens_calibration_mode |= temp;
+ if (calib_redun_sel == TSENS_QFPROM_BACKUP_SEL) {
+ tsens_calibration_mode = (calib_data[4] & TSENS_CAL_SEL_0_1)
+ >> TSENS_CAL_SEL_SHIFT;
+ temp = (calib_data[5] & TSENS_CAL_SEL_2)
+ >> TSENS_CAL_SEL_SHIFT_2;
+ tsens_calibration_mode |= temp;
- if (tsens_calibration_mode == 0) {
- pr_debug("TSENS is calibrationless mode\n");
+ for (i = 0; i < TSENS_BACKUP_CALIB_ADDR_RANGE; i++)
+ calib_data_backup[i] = readl_relaxed(
+ (TSENS_EEPROM_BACKUP_REGION(
+ tmdev->tsens_calib_addr))
+ + (i * TSENS_SN_ADDR_OFFSET));
+
+ if ((tsens_calibration_mode == TSENS_ONE_POINT_CALIB)
+ || (tsens_calibration_mode ==
+ TSENS_TWO_POINT_CALIB) ||
+ (tsens_calibration_mode ==
+ TSENS_ONE_POINT_CALIB_OPTION_2)) {
+ pr_debug("backup one point calibrationless mode\n");
+ tsens_base1_data = (calib_data_backup[0] &
+ TSENS_BASE1_MASK);
+ tsens0_point1 = (calib_data_backup[0] &
+ TSENS0_POINT1_MASK) >>
+ TSENS0_POINT1_SHIFT;
+ tsens1_point1 = (calib_data_backup[0] &
+ TSENS1_POINT1_MASK) >> TSENS1_POINT1_SHIFT;
+ tsens2_point1 = (calib_data_backup[0] &
+ TSENS2_POINT1_MASK) >> TSENS2_POINT1_SHIFT;
+ tsens3_point1 = (calib_data_backup[0] &
+ TSENS3_POINT1_MASK) >> TSENS3_POINT1_SHIFT;
+ tsens4_point1 = (calib_data_backup[1] &
+ TSENS4_POINT1_MASK);
+ tsens5_point1 = (calib_data_backup[1] &
+ TSENS5_POINT1_MASK) >> TSENS5_POINT1_SHIFT;
+ tsens6_point1 = (calib_data_backup[1] &
+ TSENS6_POINT1_MASK) >> TSENS6_POINT1_SHIFT;
+ tsens7_point1 = (calib_data_backup[1] &
+ TSENS7_POINT1_MASK) >> TSENS7_POINT1_SHIFT;
+ tsens8_point1 = (calib_data_backup[2] &
+ TSENS8_POINT1_MASK_BACKUP) >>
+ TSENS8_POINT1_SHIFT;
+ tsens9_point1 = (calib_data_backup[2] &
+ TSENS9_POINT1_MASK_BACKUP) >>
+ TSENS9_POINT1_BACKUP_SHIFT;
+ tsens10_point1 = (calib_data_backup[2] &
+ TSENS10_POINT1_MASK_BACKUP) >>
+ TSENS10_POINT1_BACKUP_SHIFT;
+ } else if (tsens_calibration_mode == TSENS_TWO_POINT_CALIB) {
+ pr_debug("backup two point calibrationless mode\n");
+ tsens_base2_data = (calib_data_backup[2] &
+ TSENS_BASE2_BACKUP_MASK) >>
+ TSENS_POINT2_BASE_BACKUP_SHIFT;
+ tsens0_point2 = (calib_data_backup[2] &
+ TSENS0_POINT2_BACKUP_MASK) >>
+ TSENS0_POINT2_BACKUP_SHIFT;
+ tsens1_point2 = (calib_data_backup[3] &
+ TSENS1_POINT2_BACKUP_MASK);
+ tsens2_point2 = (calib_data_backup[3] &
+ TSENS2_POINT2_BACKUP_MASK) >>
+ TSENS2_POINT2_BACKUP_SHIFT;
+ tsens3_point2 = (calib_data_backup[3] &
+ TSENS3_POINT2_BACKUP_MASK) >>
+ TSENS3_POINT2_BACKUP_SHIFT;
+ tsens4_point2 = (calib_data_backup[3] &
+ TSENS4_POINT2_BACKUP_MASK) >>
+ TSENS4_POINT2_BACKUP_SHIFT;
+ tsens5_point2 = (calib_data[4] & TSENS5_POINT2_BACKUP_MASK) >>
+ TSENS5_POINT2_BACKUP_SHIFT;
+ tsens6_point2 = (calib_data[5] & TSENS6_POINT2_BACKUP_MASK);
+ tsens7_point2 = (calib_data[5] & TSENS7_POINT2_BACKUP_MASK) >>
+ TSENS7_POINT2_BACKUP_SHIFT;
+ tsens8_point2 = (calib_data[5] & TSENS8_POINT2_BACKUP_MASK) >>
+ TSENS8_POINT2_BACKUP_SHIFT;
+ tsens9_point2 = (calib_data[5] & TSENS9_POINT2_BACKUP_MASK) >>
+ TSENS9_POINT2_BACKUP_SHIFT;
+ tsens10_point2 = (calib_data[5] & TSENS10_POINT2_BACKUP_MASK)
+ >> TSENS10_POINT2_BACKUP_SHIFT;
+ } else {
+ pr_debug("TSENS:backup is calibrationless mode\n");
for (i = 0; i < tmdev->tsens_num_sensor; i++) {
tmdev->sensor[i].calib_data_point2 = 780;
tmdev->sensor[i].calib_data_point1 = 492;
}
+ tsens_calibration_mode = 0;
goto compute_intercept_slope;
- } else if ((tsens_calibration_mode == TSENS_ONE_POINT_CALIB) ||
- (tsens_calibration_mode == TSENS_TWO_POINT_CALIB)) {
- tsens_base1_data = (calib_data[0] & TSENS_BASE1_MASK);
- tsens0_point1 = (calib_data[0] & TSENS0_POINT1_MASK) >>
- TSENS0_POINT1_SHIFT;
- tsens1_point1 = (calib_data[0] & TSENS1_POINT1_MASK) >>
- TSENS1_POINT1_SHIFT;
- tsens2_point1 = (calib_data[0] & TSENS2_POINT1_MASK) >>
- TSENS2_POINT1_SHIFT;
- tsens3_point1 = (calib_data[0] & TSENS3_POINT1_MASK) >>
- TSENS3_POINT1_SHIFT;
- tsens4_point1 = (calib_data[1] & TSENS4_POINT1_MASK);
- tsens5_point1 = (calib_data[1] & TSENS5_POINT1_MASK) >>
- TSENS5_POINT1_SHIFT;
- tsens6_point1 = (calib_data[1] & TSENS6_POINT1_MASK) >>
- TSENS6_POINT1_SHIFT;
- tsens7_point1 = (calib_data[1] & TSENS7_POINT1_MASK) >>
- TSENS7_POINT1_SHIFT;
- tsens8_point1 = (calib_data[1] & TSENS8_POINT1_MASK) >>
- TSENS8_POINT1_SHIFT;
- tsens9_point1 = (calib_data[2] & TSENS9_POINT1_MASK);
- tsens10_point1 = (calib_data[2] & TSENS10_POINT1_MASK) >>
- TSENS10_POINT1_SHIFT;
- } else if (tsens_calibration_mode == TSENS_TWO_POINT_CALIB) {
- tsens_base2_data = (calib_data[2] & TSENS_BASE2_MASK) >>
- TSENS_POINT2_BASE_SHIFT;
- tsens0_point2 = (calib_data[2] & TSENS0_POINT2_MASK) >>
- TSENS0_POINT2_SHIFT;
- tsens1_point2 = (calib_data[2] & TSENS1_POINT2_MASK) >>
- TSENS1_POINT2_SHIFT;
- tsens2_point2 = (calib_data[3] & TSENS2_POINT2_MASK);
- tsens3_point2 = (calib_data[3] & TSENS3_POINT2_MASK) >>
- TSENS3_POINT2_SHIFT;
- tsens4_point2 = (calib_data[3] & TSENS4_POINT2_MASK) >>
- TSENS4_POINT2_SHIFT;
- tsens5_point2 = (calib_data[3] & TSENS5_POINT2_MASK) >>
- TSENS5_POINT2_SHIFT;
- tsens6_point2 = (calib_data[3] & TSENS6_POINT2_MASK) >>
- TSENS6_POINT2_SHIFT;
- tsens7_point2 = (calib_data[4] & TSENS7_POINT2_MASK);
- tsens8_point2 = (calib_data[4] & TSENS8_POINT2_MASK) >>
- TSENS8_POINT2_SHIFT;
- tsens9_point2 = (calib_data[4] & TSENS9_POINT2_MASK) >>
- TSENS9_POINT2_SHIFT;
- tsens10_point2 = (calib_data[4] & TSENS10_POINT2_MASK) >>
- TSENS10_POINT2_SHIFT;
+ }
} else {
- pr_debug("Calibration mode is unknown: %d\n",
- tsens_calibration_mode);
- return -ENODEV;
+ tsens_calibration_mode = (calib_data[1] & TSENS_CAL_SEL_0_1)
+ >> TSENS_CAL_SEL_SHIFT;
+ temp = (calib_data[3] & TSENS_CAL_SEL_2)
+ >> TSENS_CAL_SEL_SHIFT_2;
+ tsens_calibration_mode |= temp;
+ if ((tsens_calibration_mode == TSENS_ONE_POINT_CALIB) ||
+ (tsens_calibration_mode ==
+ TSENS_ONE_POINT_CALIB_OPTION_2) ||
+ (tsens_calibration_mode == TSENS_TWO_POINT_CALIB)) {
+ pr_debug("TSENS is one point calibrationless mode\n");
+ tsens_base1_data = (calib_data[0] & TSENS_BASE1_MASK);
+ tsens0_point1 = (calib_data[0] & TSENS0_POINT1_MASK) >>
+ TSENS0_POINT1_SHIFT;
+ tsens1_point1 = (calib_data[0] & TSENS1_POINT1_MASK) >>
+ TSENS1_POINT1_SHIFT;
+ tsens2_point1 = (calib_data[0] & TSENS2_POINT1_MASK) >>
+ TSENS2_POINT1_SHIFT;
+ tsens3_point1 = (calib_data[0] & TSENS3_POINT1_MASK) >>
+ TSENS3_POINT1_SHIFT;
+ tsens4_point1 = (calib_data[1] & TSENS4_POINT1_MASK);
+ tsens5_point1 = (calib_data[1] & TSENS5_POINT1_MASK) >>
+ TSENS5_POINT1_SHIFT;
+ tsens6_point1 = (calib_data[1] & TSENS6_POINT1_MASK) >>
+ TSENS6_POINT1_SHIFT;
+ tsens7_point1 = (calib_data[1] & TSENS7_POINT1_MASK) >>
+ TSENS7_POINT1_SHIFT;
+ tsens8_point1 = (calib_data[1] & TSENS8_POINT1_MASK) >>
+ TSENS8_POINT1_SHIFT;
+ tsens9_point1 = (calib_data[2] & TSENS9_POINT1_MASK);
+ tsens10_point1 = (calib_data[2] & TSENS10_POINT1_MASK)
+ >> TSENS10_POINT1_SHIFT;
+ } else if (tsens_calibration_mode == TSENS_TWO_POINT_CALIB) {
+ pr_debug("TSENS is two point calibrationless mode\n");
+ tsens_base2_data = (calib_data[2] & TSENS_BASE2_MASK) >>
+ TSENS_POINT2_BASE_SHIFT;
+ tsens0_point2 = (calib_data[2] & TSENS0_POINT2_MASK) >>
+ TSENS0_POINT2_SHIFT;
+ tsens1_point2 = (calib_data[2] & TSENS1_POINT2_MASK) >>
+ TSENS1_POINT2_SHIFT;
+ tsens2_point2 = (calib_data[3] & TSENS2_POINT2_MASK);
+ tsens3_point2 = (calib_data[3] & TSENS3_POINT2_MASK) >>
+ TSENS3_POINT2_SHIFT;
+ tsens4_point2 = (calib_data[3] & TSENS4_POINT2_MASK) >>
+ TSENS4_POINT2_SHIFT;
+ tsens5_point2 = (calib_data[3] & TSENS5_POINT2_MASK) >>
+ TSENS5_POINT2_SHIFT;
+ tsens6_point2 = (calib_data[3] & TSENS6_POINT2_MASK) >>
+ TSENS6_POINT2_SHIFT;
+ tsens7_point2 = (calib_data[4] & TSENS7_POINT2_MASK);
+ tsens8_point2 = (calib_data[4] & TSENS8_POINT2_MASK) >>
+ TSENS8_POINT2_SHIFT;
+ tsens9_point2 = (calib_data[4] & TSENS9_POINT2_MASK) >>
+ TSENS9_POINT2_SHIFT;
+ tsens10_point2 = (calib_data[4] & TSENS10_POINT2_MASK)
+ >> TSENS10_POINT2_SHIFT;
+ } else {
+calibration_less_mode:
+ pr_debug("TSENS is calibrationless mode\n");
+ for (i = 0; i < tmdev->tsens_num_sensor; i++)
+ tmdev->sensor[i].calib_data_point2 = 780;
+ tmdev->sensor[0].calib_data_point1 = 502;
+ tmdev->sensor[1].calib_data_point1 = 509;
+ tmdev->sensor[2].calib_data_point1 = 503;
+ tmdev->sensor[3].calib_data_point1 = 509;
+ tmdev->sensor[4].calib_data_point1 = 505;
+ tmdev->sensor[5].calib_data_point1 = 509;
+ tmdev->sensor[6].calib_data_point1 = 507;
+ tmdev->sensor[7].calib_data_point1 = 510;
+ tmdev->sensor[8].calib_data_point1 = 508;
+ tmdev->sensor[9].calib_data_point1 = 509;
+ tmdev->sensor[10].calib_data_point1 = 508;
+ goto compute_intercept_slope;
+ }
}
if (tsens_calibration_mode == TSENS_ONE_POINT_CALIB) {
+ pr_debug("old one point calibration calculation\n");
tmdev->sensor[0].calib_data_point1 =
(((tsens_base1_data) << 2) | TSENS_BIT_APPEND) + tsens0_point1;
tmdev->sensor[1].calib_data_point1 =
@@ -613,6 +759,8 @@
if ((tsens_calibration_mode == TSENS_ONE_POINT_CALIB_OPTION_2) ||
(tsens_calibration_mode == TSENS_TWO_POINT_CALIB)) {
+ pr_debug("one and two point calibration calculation\n");
+
tmdev->sensor[0].calib_data_point1 =
((((tsens_base1_data) + tsens0_point1) << 2) |
TSENS_BIT_APPEND);
@@ -649,6 +797,7 @@
}
if (tsens_calibration_mode == TSENS_TWO_POINT_CALIB) {
+ pr_debug("two point calibration calculation\n");
tmdev->sensor[0].calib_data_point2 =
(((tsens_base2_data + tsens0_point2) << 2) | TSENS_BIT_APPEND);
tmdev->sensor[1].calib_data_point2 =
@@ -708,7 +857,7 @@
}
tsens_slope_data = devm_kzalloc(&pdev->dev,
- tsens_num_sensors, GFP_KERNEL);
+ tsens_num_sensors * sizeof(u32), GFP_KERNEL);
if (!tsens_slope_data) {
dev_err(&pdev->dev, "can not allocate slope data\n");
return -ENOMEM;
@@ -735,18 +884,23 @@
tmdev->sensor[i].slope_mul_tsens_factor = tsens_slope_data[i];
tmdev->tsens_factor = TSENS_SLOPE_FACTOR;
tmdev->tsens_num_sensor = tsens_num_sensors;
+ tmdev->calibration_less_mode = of_property_read_bool(of_node,
+ "qcom,calibration-less-mode");
tmdev->tsens_irq = platform_get_irq(pdev, 0);
if (tmdev->tsens_irq < 0) {
pr_err("Invalid get irq\n");
- return tmdev->tsens_irq;
+ rc = tmdev->tsens_irq;
+ goto fail_tmdev;
}
+ /* TSENS register region */
tmdev->res_tsens_mem = platform_get_resource_byname(pdev,
IORESOURCE_MEM, "tsens_physical");
if (!tmdev->res_tsens_mem) {
pr_err("Could not get tsens physical address resource\n");
- return -EINVAL;
+ rc = -EINVAL;
+ goto fail_tmdev;
}
tmdev->tsens_len = tmdev->res_tsens_mem->end -
@@ -756,7 +910,8 @@
tmdev->tsens_len, tmdev->res_tsens_mem->name);
if (!res_mem) {
pr_err("Request tsens physical memory region failed\n");
- return -EINVAL;
+ rc = -EINVAL;
+ goto fail_tmdev;
}
tmdev->tsens_addr = ioremap(res_mem->start, tmdev->tsens_len);
@@ -766,6 +921,7 @@
goto fail_unmap_tsens_region;
}
+ /* TSENS calibration region */
tmdev->res_calib_mem = platform_get_resource_byname(pdev,
IORESOURCE_MEM, "tsens_eeprom_physical");
if (!tmdev->res_calib_mem) {
@@ -806,6 +962,8 @@
if (tmdev->res_tsens_mem)
release_mem_region(tmdev->res_tsens_mem->start,
tmdev->tsens_len);
+fail_tmdev:
+ tmdev = NULL;
return rc;
}
@@ -818,9 +976,13 @@
return -EBUSY;
}
- if (pdev->dev.of_node)
+ if (pdev->dev.of_node) {
rc = get_device_tree_data(pdev);
- else
+ if (rc) {
+ pr_err("Error reading TSENS DT\n");
+ return rc;
+ }
+ } else
return -ENODEV;
tmdev->pdev = pdev;
@@ -899,14 +1061,12 @@
iounmap(tmdev->tsens_calib_addr);
if (tmdev->res_calib_mem)
release_mem_region(tmdev->res_calib_mem->start,
- tmdev->calib_len);
+ tmdev->calib_len);
if (tmdev->tsens_addr)
iounmap(tmdev->tsens_addr);
if (tmdev->res_tsens_mem)
release_mem_region(tmdev->res_tsens_mem->start,
- tmdev->tsens_len);
- kfree(tmdev);
-
+ tmdev->tsens_len);
return rc;
}
@@ -921,12 +1081,12 @@
iounmap(tmdev->tsens_calib_addr);
if (tmdev->res_calib_mem)
release_mem_region(tmdev->res_calib_mem->start,
- tmdev->calib_len);
+ tmdev->calib_len);
if (tmdev->tsens_addr)
iounmap(tmdev->tsens_addr);
if (tmdev->res_tsens_mem)
release_mem_region(tmdev->res_tsens_mem->start,
- tmdev->tsens_len);
+ tmdev->tsens_len);
free_irq(tmdev->tsens_irq, tmdev);
platform_set_drvdata(pdev, NULL);
diff --git a/drivers/video/msm/mdp4_overlay_dsi_cmd.c b/drivers/video/msm/mdp4_overlay_dsi_cmd.c
index ecdd567..5daa3ad 100644
--- a/drivers/video/msm/mdp4_overlay_dsi_cmd.c
+++ b/drivers/video/msm/mdp4_overlay_dsi_cmd.c
@@ -516,9 +516,9 @@
vctrl = &vsync_ctrl_db[cndx];
pr_debug("%s: ISR, cpu=%d\n", __func__, smp_processor_id());
vctrl->rdptr_intr_tot++;
- vctrl->vsync_time = ktime_get();
spin_lock(&vctrl->spin_lock);
+ vctrl->vsync_time = ktime_get();
complete_all(&vctrl->vsync_comp);
vctrl->wait_vsync_cnt = 0;
@@ -647,6 +647,7 @@
struct vsycn_ctrl *vctrl;
ssize_t ret = 0;
unsigned long flags;
+ u64 vsync_tick;
cndx = 0;
vctrl = &vsync_ctrl_db[0];
@@ -661,10 +662,15 @@
vctrl->wait_vsync_cnt++;
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
- wait_for_completion(&vctrl->vsync_comp);
+ ret = wait_for_completion_interruptible(&vctrl->vsync_comp);
+ if (ret)
+ return ret;
- ret = snprintf(buf, PAGE_SIZE, "VSYNC=%llu",
- ktime_to_ns(vctrl->vsync_time));
+ spin_lock_irqsave(&vctrl->spin_lock, flags);
+ vsync_tick = ktime_to_ns(vctrl->vsync_time);
+ spin_unlock_irqrestore(&vctrl->spin_lock, flags);
+
+ ret = snprintf(buf, PAGE_SIZE, "VSYNC=%llu", vsync_tick);
buf[strlen(buf) + 1] = '\0';
return ret;
}
diff --git a/drivers/video/msm/mdp4_overlay_dsi_video.c b/drivers/video/msm/mdp4_overlay_dsi_video.c
index 6aa101f..8bffb51 100644
--- a/drivers/video/msm/mdp4_overlay_dsi_video.c
+++ b/drivers/video/msm/mdp4_overlay_dsi_video.c
@@ -382,6 +382,7 @@
struct vsycn_ctrl *vctrl;
ssize_t ret = 0;
unsigned long flags;
+ u64 vsync_tick;
cndx = 0;
vctrl = &vsync_ctrl_db[0];
@@ -395,10 +396,15 @@
INIT_COMPLETION(vctrl->vsync_comp);
vctrl->wait_vsync_cnt++;
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
- wait_for_completion(&vctrl->vsync_comp);
+ ret = wait_for_completion_interruptible(&vctrl->vsync_comp);
+ if (ret)
+ return ret;
- ret = snprintf(buf, PAGE_SIZE, "VSYNC=%llu",
- ktime_to_ns(vctrl->vsync_time));
+ spin_lock_irqsave(&vctrl->spin_lock, flags);
+ vsync_tick = ktime_to_ns(vctrl->vsync_time);
+ spin_unlock_irqrestore(&vctrl->spin_lock, flags);
+
+ ret = snprintf(buf, PAGE_SIZE, "VSYNC=%llu", vsync_tick);
buf[strlen(buf) + 1] = '\0';
return ret;
}
@@ -918,9 +924,10 @@
cndx = 0;
vctrl = &vsync_ctrl_db[cndx];
pr_debug("%s: cpu=%d\n", __func__, smp_processor_id());
- vctrl->vsync_time = ktime_get();
spin_lock(&vctrl->spin_lock);
+ vctrl->vsync_time = ktime_get();
+
if (vctrl->wait_vsync_cnt) {
complete_all(&vctrl->vsync_comp);
vctrl->wait_vsync_cnt = 0;
diff --git a/drivers/video/msm/mdp4_overlay_dtv.c b/drivers/video/msm/mdp4_overlay_dtv.c
index 21e5d1d..c049d14 100644
--- a/drivers/video/msm/mdp4_overlay_dtv.c
+++ b/drivers/video/msm/mdp4_overlay_dtv.c
@@ -322,6 +322,7 @@
struct vsycn_ctrl *vctrl;
ssize_t ret = 0;
unsigned long flags;
+ u64 vsync_tick;
cndx = 0;
vctrl = &vsync_ctrl_db[0];
@@ -336,10 +337,15 @@
INIT_COMPLETION(vctrl->vsync_comp);
vctrl->wait_vsync_cnt++;
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
- wait_for_completion(&vctrl->vsync_comp);
+ ret = wait_for_completion_interruptible(&vctrl->vsync_comp);
+ if (ret)
+ return ret;
- ret = snprintf(buf, PAGE_SIZE, "VSYNC=%llu",
- ktime_to_ns(vctrl->vsync_time));
+ spin_lock_irqsave(&vctrl->spin_lock, flags);
+ vsync_tick = ktime_to_ns(vctrl->vsync_time);
+ spin_unlock_irqrestore(&vctrl->spin_lock, flags);
+
+ ret = snprintf(buf, PAGE_SIZE, "VSYNC=%llu", vsync_tick);
buf[strlen(buf) + 1] = '\0';
return ret;
}
@@ -855,9 +861,10 @@
cndx = 0;
vctrl = &vsync_ctrl_db[cndx];
pr_debug("%s: cpu=%d\n", __func__, smp_processor_id());
- vctrl->vsync_time = ktime_get();
spin_lock(&vctrl->spin_lock);
+ vctrl->vsync_time = ktime_get();
+
if (vctrl->wait_vsync_cnt) {
complete_all(&vctrl->vsync_comp);
vctrl->wait_vsync_cnt = 0;
diff --git a/drivers/video/msm/mdp4_overlay_lcdc.c b/drivers/video/msm/mdp4_overlay_lcdc.c
index 1f5136f..9a3f022 100644
--- a/drivers/video/msm/mdp4_overlay_lcdc.c
+++ b/drivers/video/msm/mdp4_overlay_lcdc.c
@@ -366,6 +366,7 @@
struct vsycn_ctrl *vctrl;
ssize_t ret = 0;
unsigned long flags;
+ u64 vsync_tick;
cndx = 0;
vctrl = &vsync_ctrl_db[0];
@@ -379,10 +380,15 @@
INIT_COMPLETION(vctrl->vsync_comp);
vctrl->wait_vsync_cnt++;
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
- wait_for_completion(&vctrl->vsync_comp);
+ ret = wait_for_completion_interruptible(&vctrl->vsync_comp);
+ if (ret)
+ return ret;
- ret = snprintf(buf, PAGE_SIZE, "VSYNC=%llu",
- ktime_to_ns(vctrl->vsync_time));
+ spin_lock_irqsave(&vctrl->spin_lock, flags);
+ vsync_tick = ktime_to_ns(vctrl->vsync_time);
+ spin_unlock_irqrestore(&vctrl->spin_lock, flags);
+
+ ret = snprintf(buf, PAGE_SIZE, "VSYNC=%llu", vsync_tick);
buf[strlen(buf) + 1] = '\0';
return ret;
}
@@ -804,9 +810,10 @@
cndx = 0;
vctrl = &vsync_ctrl_db[cndx];
pr_debug("%s: cpu=%d\n", __func__, smp_processor_id());
- vctrl->vsync_time = ktime_get();
spin_lock(&vctrl->spin_lock);
+ vctrl->vsync_time = ktime_get();
+
if (vctrl->wait_vsync_cnt) {
complete_all(&vctrl->vsync_comp);
vctrl->wait_vsync_cnt = 0;
diff --git a/include/media/gpio-ir-recv.h b/include/media/gpio-ir-recv.h
index 3eab611..ffdf2f0 100644
--- a/include/media/gpio-ir-recv.h
+++ b/include/media/gpio-ir-recv.h
@@ -17,6 +17,7 @@
unsigned int gpio_nr;
bool active_low;
bool can_wakeup;
+ u32 swfi_latency;
};
#endif /* __GPIO_IR_RECV_H__ */
diff --git a/sound/soc/codecs/wcd9xxx-mbhc.c b/sound/soc/codecs/wcd9xxx-mbhc.c
index 16d415b..3d7c0d4 100644
--- a/sound/soc/codecs/wcd9xxx-mbhc.c
+++ b/sound/soc/codecs/wcd9xxx-mbhc.c
@@ -37,7 +37,8 @@
#include "wcd9xxx-resmgr.h"
#define WCD9XXX_JACK_MASK (SND_JACK_HEADSET | SND_JACK_OC_HPHL | \
- SND_JACK_OC_HPHR | SND_JACK_UNSUPPORTED)
+ SND_JACK_OC_HPHR | SND_JACK_LINEOUT | \
+ SND_JACK_UNSUPPORTED)
#define WCD9XXX_JACK_BUTTON_MASK (SND_JACK_BTN_0 | SND_JACK_BTN_1 | \
SND_JACK_BTN_2 | SND_JACK_BTN_3 | \
SND_JACK_BTN_4 | SND_JACK_BTN_5 | \
@@ -574,6 +575,8 @@
{
WCD9XXX_BCL_ASSERT_LOCKED(mbhc->resmgr);
+ pr_debug("%s: enter insertion %d hph_status %x\n",
+ __func__, insertion, mbhc->hph_status);
if (!insertion) {
/* Report removal */
mbhc->hph_status &= ~jack_type;
@@ -601,6 +604,16 @@
mbhc->current_plug = PLUG_TYPE_NONE;
mbhc->polling_active = false;
} else {
+ if (mbhc->mbhc_cfg->detect_extn_cable) {
+ /* Report removal of current jack type */
+ if (mbhc->hph_status != jack_type) {
+ pr_debug("%s: Reporting removal (%x)\n",
+ __func__, mbhc->hph_status);
+ wcd9xxx_jack_report(&mbhc->headset_jack,
+ 0, WCD9XXX_JACK_MASK);
+ mbhc->hph_status = 0;
+ }
+ }
/* Report insertion */
mbhc->hph_status |= jack_type;
@@ -611,6 +624,8 @@
} else if (jack_type == SND_JACK_HEADSET) {
mbhc->polling_active = BUTTON_POLLING_SUPPORTED;
mbhc->current_plug = PLUG_TYPE_HEADSET;
+ } else if (jack_type == SND_JACK_LINEOUT) {
+ mbhc->current_plug = PLUG_TYPE_HIGH_HPH;
}
pr_debug("%s: Reporting insertion %d(%x)\n", __func__,
jack_type, mbhc->hph_status);
@@ -620,6 +635,8 @@
}
/* Setup insert detect */
wcd9xxx_insert_detect_setup(mbhc, !insertion);
+
+ pr_debug("%s: leave hph_status %x\n", __func__, mbhc->hph_status);
}
/* should be called under interrupt context that hold suspend */
@@ -929,6 +946,7 @@
bool highdelta;
bool ahighv = false, highv;
+ pr_debug("%s: enter\n", __func__);
WCD9XXX_BCL_ASSERT_LOCKED(mbhc->resmgr);
/* make sure override is on */
@@ -1035,6 +1053,7 @@
}
pr_debug("%s: Detected plug type %d\n", __func__, plug_type[0]);
+ pr_debug("%s: leave\n", __func__);
return plug_type[0];
}
@@ -1068,6 +1087,9 @@
const struct wcd9xxx_mbhc_plug_detect_cfg *plug_det =
WCD9XXX_MBHC_CAL_PLUG_DET_PTR(mbhc->mbhc_cfg->calibration);
+ pr_debug("%s: enter insertion(%d) trigger(0x%x)\n",
+ __func__, insertion, trigger);
+
if (!mbhc->mbhc_cfg->calibration) {
pr_err("Error, no wcd9xxx calibration\n");
return -EINVAL;
@@ -1179,6 +1201,7 @@
wcd9xxx_enable_irq(mbhc->resmgr->core, WCD9XXX_IRQ_MBHC_INSERTION);
snd_soc_update_bits(codec, WCD9XXX_A_CDC_MBHC_INT_CTL, 0x1, 0x1);
+ pr_debug("%s: leave\n", __func__);
return 0;
}
@@ -1187,6 +1210,9 @@
static void wcd9xxx_find_plug_and_report(struct wcd9xxx_mbhc *mbhc,
enum wcd9xxx_mbhc_plug_type plug_type)
{
+ pr_debug("%s: enter current_plug(%d) new_plug(%d)\n",
+ __func__, mbhc->current_plug, plug_type);
+
WCD9XXX_BCL_ASSERT_LOCKED(mbhc->resmgr);
if (plug_type == PLUG_TYPE_HEADPHONE &&
@@ -1198,11 +1224,14 @@
wcd9xxx_report_plug(mbhc, 1, SND_JACK_HEADPHONE);
wcd9xxx_cleanup_hs_polling(mbhc);
} else if (plug_type == PLUG_TYPE_GND_MIC_SWAP) {
- if (mbhc->current_plug == PLUG_TYPE_HEADSET)
- wcd9xxx_report_plug(mbhc, 0, SND_JACK_HEADSET);
- else if (mbhc->current_plug == PLUG_TYPE_HEADPHONE)
- wcd9xxx_report_plug(mbhc, 0, SND_JACK_HEADPHONE);
-
+ if (!mbhc->mbhc_cfg->detect_extn_cable) {
+ if (mbhc->current_plug == PLUG_TYPE_HEADSET)
+ wcd9xxx_report_plug(mbhc, 0,
+ SND_JACK_HEADSET);
+ else if (mbhc->current_plug == PLUG_TYPE_HEADPHONE)
+ wcd9xxx_report_plug(mbhc, 0,
+ SND_JACK_HEADPHONE);
+ }
wcd9xxx_report_plug(mbhc, 1, SND_JACK_UNSUPPORTED);
wcd9xxx_cleanup_hs_polling(mbhc);
} else if (plug_type == PLUG_TYPE_HEADSET) {
@@ -1214,17 +1243,35 @@
msleep(100);
wcd9xxx_start_hs_polling(mbhc);
} else if (plug_type == PLUG_TYPE_HIGH_HPH) {
- if (mbhc->current_plug == PLUG_TYPE_NONE)
- wcd9xxx_report_plug(mbhc, 1, SND_JACK_HEADPHONE);
- wcd9xxx_cleanup_hs_polling(mbhc);
- pr_debug("setup mic trigger for further detection\n");
- mbhc->lpi_enabled = true;
- wcd9xxx_enable_hs_detect(mbhc, 1, MBHC_USE_MB_TRIGGER |
- MBHC_USE_HPHL_TRIGGER, false);
+ if (mbhc->mbhc_cfg->detect_extn_cable) {
+ /* High impedance device found. Report as LINEOUT*/
+ wcd9xxx_report_plug(mbhc, 1, SND_JACK_LINEOUT);
+ wcd9xxx_cleanup_hs_polling(mbhc);
+ pr_debug("%s: setup mic trigger for further detection\n",
+ __func__);
+ mbhc->lpi_enabled = true;
+ /*
+ * Do not enable HPHL trigger. If playback is active,
+ * it might lead to continuous false HPHL triggers
+ */
+ wcd9xxx_enable_hs_detect(mbhc, 1, MBHC_USE_MB_TRIGGER,
+ false);
+ } else {
+ if (mbhc->current_plug == PLUG_TYPE_NONE)
+ wcd9xxx_report_plug(mbhc, 1,
+ SND_JACK_HEADPHONE);
+ wcd9xxx_cleanup_hs_polling(mbhc);
+ pr_debug("setup mic trigger for further detection\n");
+ mbhc->lpi_enabled = true;
+ wcd9xxx_enable_hs_detect(mbhc, 1, MBHC_USE_MB_TRIGGER |
+ MBHC_USE_HPHL_TRIGGER,
+ false);
+ }
} else {
WARN(1, "Unexpected current plug_type %d, plug_type %d\n",
mbhc->current_plug, plug_type);
}
+ pr_debug("%s: leave\n", __func__);
}
/* called under codec_resource_lock acquisition */
@@ -1260,6 +1307,7 @@
__func__, plug_type);
wcd9xxx_find_plug_and_report(mbhc, plug_type);
}
+ pr_debug("%s: leave\n", __func__);
}
/* called under codec_resource_lock acquisition */
@@ -1269,6 +1317,7 @@
const struct wcd9xxx_mbhc_plug_detect_cfg *plug_det =
WCD9XXX_MBHC_CAL_PLUG_DET_PTR(mbhc->mbhc_cfg->calibration);
+ pr_debug("%s: enter\n", __func__);
WCD9XXX_BCL_ASSERT_LOCKED(mbhc->resmgr);
/*
@@ -1289,6 +1338,7 @@
__func__);
else
wcd9xxx_mbhc_decide_swch_plug(mbhc);
+ pr_debug("%s: leave\n", __func__);
}
/* called only from interrupt which is under codec_resource_lock acquisition */
@@ -1313,6 +1363,19 @@
pr_debug("%s: Invalid insertion stop plug detection\n",
__func__);
}
+ } else if (mbhc->mbhc_cfg->detect_extn_cable) {
+ pr_debug("%s: Removal\n", __func__);
+ if (!wcd9xxx_swch_level_remove(mbhc)) {
+ /*
+ * Switch indicates, something is still inserted.
+ * This could be extension cable i.e. headset is
+ * removed from extension cable.
+ */
+ /* cancel detect plug */
+ wcd9xxx_cancel_hs_detect_plug(mbhc,
+ &mbhc->correct_plug_swch);
+ wcd9xxx_mbhc_decide_swch_plug(mbhc);
+ }
} else {
pr_err("%s: Switch IRQ used, invalid MBHC Removal\n", __func__);
}
@@ -1398,9 +1461,100 @@
/* called only from interrupt which is under codec_resource_lock acquisition */
static void wcd9xxx_hs_remove_irq_swch(struct wcd9xxx_mbhc *mbhc)
{
+ pr_debug("%s: enter\n", __func__);
if (wcd9xxx_hs_remove_settle(mbhc))
wcd9xxx_start_hs_polling(mbhc);
- pr_debug("%s: remove settle done\n", __func__);
+ pr_debug("%s: leave\n", __func__);
+}
+
+/* called only from interrupt which is under codec_resource_lock acquisition */
+static void wcd9xxx_hs_remove_irq_noswch(struct wcd9xxx_mbhc *mbhc)
+{
+ short bias_value;
+ bool removed = true;
+ struct snd_soc_codec *codec = mbhc->codec;
+ const struct wcd9xxx_mbhc_general_cfg *generic =
+ WCD9XXX_MBHC_CAL_GENERAL_PTR(mbhc->mbhc_cfg->calibration);
+ int min_us = FAKE_REMOVAL_MIN_PERIOD_MS * 1000;
+
+ pr_debug("%s: enter\n", __func__);
+ if (mbhc->current_plug != PLUG_TYPE_HEADSET) {
+ pr_debug("%s(): Headset is not inserted, ignore removal\n",
+ __func__);
+ snd_soc_update_bits(codec, WCD9XXX_A_CDC_MBHC_CLK_CTL,
+ 0x08, 0x08);
+ return;
+ }
+
+ usleep_range(generic->t_shutdown_plug_rem,
+ generic->t_shutdown_plug_rem);
+
+ do {
+ bias_value = wcd9xxx_codec_sta_dce(mbhc, 1, true);
+ pr_debug("%s: DCE %d,%d, %d us left\n", __func__, bias_value,
+ wcd9xxx_codec_sta_dce_v(mbhc, 1, bias_value), min_us);
+ if (bias_value < wcd9xxx_get_current_v_ins(mbhc, false)) {
+ pr_debug("%s: checking false removal\n", __func__);
+ msleep(500);
+ removed = !wcd9xxx_hs_remove_settle(mbhc);
+ pr_debug("%s: headset %sactually removed\n", __func__,
+ removed ? "" : "not ");
+ break;
+ }
+ min_us -= mbhc->mbhc_data.t_dce;
+ } while (min_us > 0);
+
+ if (removed) {
+ if (mbhc->mbhc_cfg->detect_extn_cable) {
+ if (!wcd9xxx_swch_level_remove(mbhc)) {
+ /*
+ * extension cable is still plugged in
+ * report it as LINEOUT device
+ */
+ wcd9xxx_report_plug(mbhc, 1, SND_JACK_LINEOUT);
+ wcd9xxx_cleanup_hs_polling(mbhc);
+ wcd9xxx_enable_hs_detect(mbhc, 1,
+ MBHC_USE_MB_TRIGGER,
+ false);
+ }
+ } else {
+ /* Cancel possibly running hs_detect_work */
+ wcd9xxx_cancel_hs_detect_plug(mbhc,
+ &mbhc->correct_plug_noswch);
+ /*
+ * If this removal is not false, first check the micbias
+ * switch status and switch it to LDOH if it is already
+ * switched to VDDIO.
+ */
+ wcd9xxx_switch_micbias(mbhc, 0);
+
+ wcd9xxx_report_plug(mbhc, 0, SND_JACK_HEADSET);
+ wcd9xxx_cleanup_hs_polling(mbhc);
+ wcd9xxx_enable_hs_detect(mbhc, 1, MBHC_USE_MB_TRIGGER |
+ MBHC_USE_HPHL_TRIGGER,
+ true);
+ }
+ } else {
+ wcd9xxx_start_hs_polling(mbhc);
+ }
+ pr_debug("%s: leave\n", __func__);
+}
+
+/* called only from interrupt which is under codec_resource_lock acquisition */
+static void wcd9xxx_hs_insert_irq_extn(struct wcd9xxx_mbhc *mbhc,
+ bool is_mb_trigger)
+{
+ /* Cancel possibly running hs_detect_work */
+ wcd9xxx_cancel_hs_detect_plug(mbhc, &mbhc->correct_plug_swch);
+
+ if (is_mb_trigger) {
+ pr_debug("%s: Waiting for Headphone left trigger\n", __func__);
+ wcd9xxx_enable_hs_detect(mbhc, 1, MBHC_USE_HPHL_TRIGGER, false);
+ } else {
+ pr_debug("%s: HPHL trigger received, detecting plug type\n",
+ __func__);
+ wcd9xxx_mbhc_detect_plug_type(mbhc);
+ }
}
static irqreturn_t wcd9xxx_hs_remove_irq(int irq, void *data)
@@ -1415,7 +1569,11 @@
if (vddio)
__wcd9xxx_switch_micbias(mbhc, 0, false, true);
- wcd9xxx_hs_remove_irq_swch(mbhc);
+ if (mbhc->mbhc_cfg->detect_extn_cable &&
+ !wcd9xxx_swch_level_remove(mbhc))
+ wcd9xxx_hs_remove_irq_noswch(mbhc);
+ else
+ wcd9xxx_hs_remove_irq_swch(mbhc);
/*
* if driver turned off vddio switch and headset is not removed,
@@ -1449,7 +1607,11 @@
snd_soc_update_bits(codec, WCD9XXX_A_MBHC_HPH, 0x13, 0x00);
snd_soc_update_bits(codec, mbhc->mbhc_bias_regs.ctl_reg, 0x01, 0x00);
- wcd9xxx_hs_insert_irq_swch(mbhc, is_removal);
+ if (mbhc->mbhc_cfg->detect_extn_cable &&
+ mbhc->current_plug == PLUG_TYPE_HIGH_HPH)
+ wcd9xxx_hs_insert_irq_extn(mbhc, is_mb_trigger);
+ else
+ wcd9xxx_hs_insert_irq_swch(mbhc, is_removal);
WCD9XXX_BCL_UNLOCK(mbhc->resmgr);
return IRQ_HANDLED;
@@ -1642,7 +1804,7 @@
{
struct wcd9xxx_mbhc *mbhc;
struct snd_soc_codec *codec;
- enum wcd9xxx_mbhc_plug_type plug_type;
+ enum wcd9xxx_mbhc_plug_type plug_type = PLUG_TYPE_INVALID;
unsigned long timeout;
int retry = 0, pt_gnd_mic_swap_cnt = 0;
bool correction = false;
@@ -1686,18 +1848,26 @@
plug_type = wcd9xxx_codec_get_plug_type(mbhc, true);
WCD9XXX_BCL_UNLOCK(mbhc->resmgr);
+ pr_debug("%s: attempt(%d) current_plug(%d) new_plug(%d)\n",
+ __func__, retry, mbhc->current_plug, plug_type);
if (plug_type == PLUG_TYPE_INVALID) {
pr_debug("Invalid plug in attempt # %d\n", retry);
- if (retry == NUM_ATTEMPTS_TO_REPORT &&
+ if (!mbhc->mbhc_cfg->detect_extn_cable &&
+ retry == NUM_ATTEMPTS_TO_REPORT &&
mbhc->current_plug == PLUG_TYPE_NONE) {
wcd9xxx_report_plug(mbhc, 1,
SND_JACK_HEADPHONE);
}
} else if (plug_type == PLUG_TYPE_HEADPHONE) {
pr_debug("Good headphone detected, continue polling\n");
- if (mbhc->current_plug == PLUG_TYPE_NONE)
+ if (mbhc->mbhc_cfg->detect_extn_cable) {
+ if (mbhc->current_plug != plug_type)
+ wcd9xxx_report_plug(mbhc, 1,
+ SND_JACK_HEADPHONE);
+ } else if (mbhc->current_plug == PLUG_TYPE_NONE) {
wcd9xxx_report_plug(mbhc, 1,
SND_JACK_HEADPHONE);
+ }
} else {
if (plug_type == PLUG_TYPE_GND_MIC_SWAP) {
pt_gnd_mic_swap_cnt++;
@@ -1741,7 +1911,20 @@
wcd9xxx_turn_onoff_override(codec, false);
wcd9xxx_onoff_ext_mclk(mbhc, false);
- pr_debug("%s: leave\n", __func__);
+
+ if (mbhc->mbhc_cfg->detect_extn_cable) {
+ WCD9XXX_BCL_LOCK(mbhc->resmgr);
+ if (mbhc->current_plug == PLUG_TYPE_HEADPHONE ||
+ mbhc->current_plug == PLUG_TYPE_GND_MIC_SWAP ||
+ mbhc->current_plug == PLUG_TYPE_INVALID ||
+ plug_type == PLUG_TYPE_INVALID) {
+ /* Enable removal detection */
+ wcd9xxx_cleanup_hs_polling(mbhc);
+ wcd9xxx_enable_hs_detect(mbhc, 0, 0, false);
+ }
+ WCD9XXX_BCL_UNLOCK(mbhc->resmgr);
+ }
+ pr_debug("%s: leave current_plug(%d)\n", __func__, mbhc->current_plug);
/* unlock sleep */
wcd9xxx_unlock_sleep(mbhc->resmgr->core);
}
@@ -1799,6 +1982,9 @@
wcd9xxx_cleanup_hs_polling(mbhc);
wcd9xxx_report_plug(mbhc, 0, SND_JACK_HEADSET);
is_removed = true;
+ } else if (mbhc->current_plug == PLUG_TYPE_HIGH_HPH) {
+ wcd9xxx_report_plug(mbhc, 0, SND_JACK_LINEOUT);
+ is_removed = true;
}
if (is_removed) {
diff --git a/sound/soc/codecs/wcd9xxx-mbhc.h b/sound/soc/codecs/wcd9xxx-mbhc.h
index 0934b5e..fb1dfdc 100644
--- a/sound/soc/codecs/wcd9xxx-mbhc.h
+++ b/sound/soc/codecs/wcd9xxx-mbhc.h
@@ -185,6 +185,7 @@
unsigned int gpio_irq;
int gpio_level_insert;
bool insert_detect; /* codec has own MBHC_INSERT_DETECT */
+ bool detect_extn_cable;
/* swap_gnd_mic returns true if extern GND/MIC swap switch toggled */
bool (*swap_gnd_mic) (struct snd_soc_codec *);
};
diff --git a/sound/soc/msm/msm8974.c b/sound/soc/msm/msm8974.c
index e65d83f..e8ea058 100644
--- a/sound/soc/msm/msm8974.c
+++ b/sound/soc/msm/msm8974.c
@@ -69,6 +69,7 @@
.gpio = 0,
.gpio_irq = 0,
.gpio_level_insert = 1,
+ .detect_extn_cable = true,
.insert_detect = true,
.swap_gnd_mic = NULL,
};