arm/dt: msm8974: i2c: Set different clock rate for v1 and v2
Platforms with chipset 8974-v1 are using 19.2MHz clock for i2c
while platforms with chipset 8974-v2 are using 50MHz clock
for i2c. This patch sets the correct clock rate per platform.
CRs-Fixed: 452047
Change-Id: I74b95a489d2fcfc55c3896a44ebe53553f33414b
Signed-off-by: Gilad Avidov <gavidov@codeaurora.org>
diff --git a/arch/arm/boot/dts/msm8974-v1.dtsi b/arch/arm/boot/dts/msm8974-v1.dtsi
index eb69c51..5c0b18d 100644
--- a/arch/arm/boot/dts/msm8974-v1.dtsi
+++ b/arch/arm/boot/dts/msm8974-v1.dtsi
@@ -35,3 +35,12 @@
&tsens {
qcom,calibration-less-mode;
};
+
+/* I2C clock frequency overrides */
+&i2c_0 {
+ qcom,i2c-src-freq = <19200000>;
+};
+
+&i2c_2 {
+ qcom,i2c-src-freq = <19200000>;
+};
diff --git a/arch/arm/boot/dts/msm8974.dtsi b/arch/arm/boot/dts/msm8974.dtsi
index b63b50f..3a225bb 100644
--- a/arch/arm/boot/dts/msm8974.dtsi
+++ b/arch/arm/boot/dts/msm8974.dtsi
@@ -542,7 +542,7 @@
qcom,pmic-arb-channel = <0>;
};
- i2c@f9967000 { /* BLSP#11 */
+ i2c_0: i2c@f9967000 { /* BLSP#11 */
cell-index = <0>;
compatible = "qcom,i2c-qup";
reg = <0Xf9967000 0x1000>;
@@ -552,10 +552,10 @@
interrupts = <0 105 0>;
interrupt-names = "qup_err_intr";
qcom,i2c-bus-freq = <100000>;
- qcom,i2c-src-freq = <19200000>;
+ qcom,i2c-src-freq = <50000000>;
};
- i2c@f9924000 {
+ i2c_2: i2c@f9924000 {
cell-index = <2>;
compatible = "qcom,i2c-qup";
reg = <0xf9924000 0x1000>;
@@ -565,7 +565,7 @@
interrupts = <0 96 0>;
interrupt-names = "qup_err_intr";
qcom,i2c-bus-freq = <100000>;
- qcom,i2c-src-freq = <19200000>;
+ qcom,i2c-src-freq = <50000000>;
};
spi@f9923000 {