Revert "msm: acpuclock-8974: Revert back to previous CPU voltages and max freqs"
This reverts commit 335bc46dce43c63a5d49ce9c4931c5990170c298.
The revert of the acpuclock table to lower voltages did indeed
improve stability, but was not the underlying root cause of the
reported failures.
It turns out that a hardware bug prevented the PMIC regulator
MODE_CTL register from being reset in WARM_RESET. Consequently,
we often left the regulator running in PFM mode. This is bad,
since our software assumes the default value is PWM. Thus we
would often end up bringing up cores at higher current
requests than that tolerated in PFM mode, and crash the system.
Change-Id: Ie8b1ccef10577aceaa5201ec67dd220dcd87c210
Signed-off-by: Michael Bohan <mbohan@codeaurora.org>
diff --git a/arch/arm/mach-msm/acpuclock-8974.c b/arch/arm/mach-msm/acpuclock-8974.c
index 69b35e9..f929943 100644
--- a/arch/arm/mach-msm/acpuclock-8974.c
+++ b/arch/arm/mach-msm/acpuclock-8974.c
@@ -142,26 +142,26 @@
};
static struct acpu_level acpu_freq_tbl[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 950000, 100000 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(0), 950000, 3200000 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(0), 950000, 3200000 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(0), 950000, 3200000 },
- { 1, { 576000, HFPLL, 1, 30 }, L2(0), 950000, 3200000 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(16), 950000, 3200000 },
- { 0, { 729600, HFPLL, 1, 38 }, L2(16), 950000, 3200000 },
- { 1, { 806400, HFPLL, 1, 42 }, L2(16), 950000, 3200000 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(16), 950000, 3200000 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(16), 950000, 3200000 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(16), 950000, 3200000 },
- { 1, { 1113600, HFPLL, 1, 58 }, L2(16), 1050000, 3200000 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(16), 1050000, 3200000 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(16), 1050000, 3200000 },
- { 1, { 1344000, HFPLL, 1, 70 }, L2(16), 1050000, 3200000 },
- { 1, { 1420800, HFPLL, 1, 74 }, L2(16), 1050000, 3200000 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 1050000, 3200000 },
- { 0, { 1574400, HFPLL, 1, 82 }, L2(16), 1050000, 3200000 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(16), 1050000, 3200000 },
- { 0, { 1728000, HFPLL, 1, 90 }, L2(16), 1050000, 3200000 },
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 850000, 100000 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(0), 850000, 3200000 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(0), 850000, 3200000 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(0), 850000, 3200000 },
+ { 1, { 576000, HFPLL, 1, 30 }, L2(0), 850000, 3200000 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(16), 850000, 3200000 },
+ { 0, { 729600, HFPLL, 1, 38 }, L2(16), 850000, 3200000 },
+ { 1, { 806400, HFPLL, 1, 42 }, L2(16), 850000, 3200000 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(16), 870000, 3200000 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(16), 880000, 3200000 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(16), 900000, 3200000 },
+ { 1, { 1113600, HFPLL, 1, 58 }, L2(16), 915000, 3200000 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(16), 935000, 3200000 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(16), 950000, 3200000 },
+ { 1, { 1344000, HFPLL, 1, 70 }, L2(16), 970000, 3200000 },
+ { 1, { 1420800, HFPLL, 1, 74 }, L2(16), 985000, 3200000 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 1000000, 3200000 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(16), 1015000, 3200000 },
+ { 1, { 1651200, HFPLL, 1, 86 }, L2(16), 1030000, 3200000 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(16), 1050000, 3200000 },
{ 0, { 1804800, HFPLL, 1, 94 }, L2(16), 1050000, 3200000 },
{ 0, { 1881600, HFPLL, 1, 98 }, L2(16), 1050000, 3200000 },
{ 0, { 1958400, HFPLL, 1, 102 }, L2(16), 1050000, 3200000 },