| commit | b3c6b76ffb1a8c8d1f12e838a25c1a86f5316e2c | [log] [tgz] |
|---|---|---|
| author | Pavel Pisa <ppisa@pikron.com> | Wed Mar 07 23:56:16 2007 +0100 |
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | Mon Mar 12 16:49:35 2007 +0000 |
| tree | 7e68897d90f93ea62b890128408cfbf2d0b57c86 | |
| parent | 83b84c4e8c7cf00e26610f03ee59e9be010f527c [diff] |
[ARM] 4255/1: i.MX/MX1 Correct MPU PLL reference clock value. Only System PLL clock source is selectable by CSCR_SYSTEM_SEL bit. MPU PLL is driven by 512*CLK32 for each case. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>