tree fa32093d96a9b9469a0d2a39fdc169628db9981e
parent 2aa54b2009bb4f85cdc42d16dde18093dd832a31
author Hillf Danton <dhillf@gmail.com> 1321402889 +0000
committer Ralf Baechle <ralf@linux-mips.org> 1323295497 +0000

MIPS: Netlogic: Mark Netlogic chips as SMT capable

Netlogic XLR chip has multiple cores. Each core includes four integrated
hardware threads, and they share L1 data and instruction caches.

If the chip is marked to be SMT capable, scheduler then could do more, say,
idle load balancing.

Changes are now confined only to the code of XLR, and hardware is probed
to get core ID for correct setup.

[jayachandranc: simplified and adapted for new merged XLR/XLP code]

Signed-off-by: Hillf Danton <dhillf@gmail.com>
Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2972/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>