| commit | 30ab05acb22ebbf642a47eb3225ad0b6a8cac79f | [log] [tgz] |
|---|---|---|
| author | Aarushi Girdhar <agirdhar@codeaurora.org> | Thu Mar 19 19:01:15 2015 +0530 |
| committer | Gerrit - the friendly Code Review server <code-review@localhost> | Thu Mar 19 06:35:54 2015 -0700 |
| tree | 81f6f467f8da603c6a2661c4ba5a36d029899abe | |
| parent | dd5f388f42264038fbafe8caf4f68101d6673fa5 [diff] |
ARM: dts: msm: update the DSI PHY lane configuration settings With the present DSI lane configuration, there is slight delay observed on data transfer between different data lanes. Update the DSI PHY lane configuration with the recommended settings from the h/w team to fix this issue. Change-Id: Ic3bb40145334fa33035559303f8ec10f6bb04377 Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org> Signed-off-by: Aarushi Girdhar <agirdhar@codeaurora.org>