Merge "mfd: pmic8058: Remove reset_pwr_off, smpl control and WD reset control APIs" into msm-3.0
diff --git a/drivers/mfd/pmic8058.c b/drivers/mfd/pmic8058.c
index ae721e4..7c56dd6 100644
--- a/drivers/mfd/pmic8058.c
+++ b/drivers/mfd/pmic8058.c
@@ -42,15 +42,6 @@
#define REG_TEMP_ALRM_CTRL 0x1B
#define REG_TEMP_ALRM_PWM 0x9B
-/* PON CNTL 1 register */
-#define SSBI_REG_ADDR_PON_CNTL_1 0x01C
-
-#define PM8058_PON_PUP_MASK 0xF0
-
-#define PM8058_PON_WD_EN_MASK 0x08
-#define PM8058_PON_WD_EN_RESET 0x08
-#define PM8058_PON_WD_EN_PWR_OFF 0x00
-
/* PON CNTL 4 register */
#define SSBI_REG_ADDR_PON_CNTL_4 0x98
#define PM8058_PON_RESET_EN_MASK 0x01
@@ -59,60 +50,6 @@
#define SSBI_REG_ADDR_PON_CNTL_5 0x7B
#define PM8058_HARD_RESET_EN_MASK 0x08
-/* Regulator master enable addresses */
-#define SSBI_REG_ADDR_VREG_EN_MSM 0x018
-#define SSBI_REG_ADDR_VREG_EN_GRP_5_4 0x1C8
-
-/* Regulator control registers for shutdown/reset */
-#define SSBI_REG_ADDR_S0_CTRL 0x004
-#define SSBI_REG_ADDR_S1_CTRL 0x005
-#define SSBI_REG_ADDR_S3_CTRL 0x111
-#define SSBI_REG_ADDR_L21_CTRL 0x120
-#define SSBI_REG_ADDR_L22_CTRL 0x121
-
-#define REGULATOR_ENABLE_MASK 0x80
-#define REGULATOR_ENABLE 0x80
-#define REGULATOR_DISABLE 0x00
-#define REGULATOR_PULL_DOWN_MASK 0x40
-#define REGULATOR_PULL_DOWN_EN 0x40
-#define REGULATOR_PULL_DOWN_DIS 0x00
-
-/* Buck CTRL register */
-#define SMPS_LEGACY_VREF_SEL 0x20
-#define SMPS_LEGACY_VPROG_MASK 0x1F
-#define SMPS_ADVANCED_BAND_MASK 0xC0
-#define SMPS_ADVANCED_BAND_SHIFT 6
-#define SMPS_ADVANCED_VPROG_MASK 0x3F
-
-/* Buck TEST2 registers for shutdown/reset */
-#define SSBI_REG_ADDR_S0_TEST2 0x084
-#define SSBI_REG_ADDR_S1_TEST2 0x085
-#define SSBI_REG_ADDR_S3_TEST2 0x11A
-
-#define REGULATOR_BANK_WRITE 0x80
-#define REGULATOR_BANK_MASK 0x70
-#define REGULATOR_BANK_SHIFT 4
-#define REGULATOR_BANK_SEL(n) ((n) << REGULATOR_BANK_SHIFT)
-
-/* Buck TEST2 register bank 1 */
-#define SMPS_LEGACY_VLOW_SEL 0x01
-
-/* Buck TEST2 register bank 7 */
-#define SMPS_ADVANCED_MODE_MASK 0x02
-#define SMPS_ADVANCED_MODE 0x02
-#define SMPS_LEGACY_MODE 0x00
-
-/* SLEEP CNTL register */
-#define SSBI_REG_ADDR_SLEEP_CNTL 0x02B
-
-#define PM8058_SLEEP_SMPL_EN_MASK 0x04
-#define PM8058_SLEEP_SMPL_EN_RESET 0x04
-#define PM8058_SLEEP_SMPL_EN_PWR_OFF 0x00
-
-#define PM8058_SLEEP_SMPL_SEL_MASK 0x03
-#define PM8058_SLEEP_SMPL_SEL_MIN 0
-#define PM8058_SLEEP_SMPL_SEL_MAX 3
-
/* GP_TEST1 register */
#define SSBI_REG_ADDR_GP_TEST_1 0x07A
@@ -154,322 +91,6 @@
return msm_ssbi_write(dev->parent, addr, buf, len);
}
-static int pm8058_masked_write(u16 addr, u8 val, u8 mask)
-{
- int rc;
- u8 reg;
-
- if (pmic_chip == NULL)
- return -ENODEV;
-
- rc = ssbi_read(pmic_chip->dev, addr, ®, 1);
- if (rc) {
- pr_err("%s: ssbi_read(0x%03X) failed: rc=%d\n", __func__, addr,
- rc);
- goto done;
- }
-
- reg &= ~mask;
- reg |= val & mask;
-
- rc = ssbi_write(pmic_chip->dev, addr, ®, 1);
- if (rc)
- pr_err("%s: ssbi_write(0x%03X)=0x%02X failed: rc=%d\n",
- __func__, addr, reg, rc);
-done:
- return rc;
-}
-
-/**
- * pm8058_smpl_control - enables/disables SMPL detection
- * @enable: 0 = shutdown PMIC on power loss, 1 = reset PMIC on power loss
- *
- * This function enables or disables the Sudden Momentary Power Loss detection
- * module. If SMPL detection is enabled, then when a sufficiently long power
- * loss event occurs, the PMIC will automatically reset itself. If SMPL
- * detection is disabled, then the PMIC will shutdown when power loss occurs.
- *
- * RETURNS: an appropriate -ERRNO error value on error, or zero for success.
- */
-int pm8058_smpl_control(int enable)
-{
- return pm8058_masked_write(SSBI_REG_ADDR_SLEEP_CNTL,
- (enable ? PM8058_SLEEP_SMPL_EN_RESET
- : PM8058_SLEEP_SMPL_EN_PWR_OFF),
- PM8058_SLEEP_SMPL_EN_MASK);
-}
-EXPORT_SYMBOL(pm8058_smpl_control);
-
-/**
- * pm8058_smpl_set_delay - sets the SMPL detection time delay
- * @delay: enum value corresponding to delay time
- *
- * This function sets the time delay of the SMPL detection module. If power
- * is reapplied within this interval, then the PMIC reset automatically. The
- * SMPL detection module must be enabled for this delay time to take effect.
- *
- * RETURNS: an appropriate -ERRNO error value on error, or zero for success.
- */
-int pm8058_smpl_set_delay(enum pm8058_smpl_delay delay)
-{
- if (delay < PM8058_SLEEP_SMPL_SEL_MIN
- || delay > PM8058_SLEEP_SMPL_SEL_MAX) {
- pr_err("%s: invalid delay specified: %d\n", __func__, delay);
- return -EINVAL;
- }
-
- return pm8058_masked_write(SSBI_REG_ADDR_SLEEP_CNTL, delay,
- PM8058_SLEEP_SMPL_SEL_MASK);
-}
-EXPORT_SYMBOL(pm8058_smpl_set_delay);
-
-/**
- * pm8058_watchdog_reset_control - enables/disables watchdog reset detection
- * @enable: 0 = shutdown when PS_HOLD goes low, 1 = reset when PS_HOLD goes low
- *
- * This function enables or disables the PMIC watchdog reset detection feature.
- * If watchdog reset detection is enabled, then the PMIC will reset itself
- * when PS_HOLD goes low. If it is not enabled, then the PMIC will shutdown
- * when PS_HOLD goes low.
- *
- * RETURNS: an appropriate -ERRNO error value on error, or zero for success.
- */
-int pm8058_watchdog_reset_control(int enable)
-{
- return pm8058_masked_write(SSBI_REG_ADDR_PON_CNTL_1,
- (enable ? PM8058_PON_WD_EN_RESET
- : PM8058_PON_WD_EN_PWR_OFF),
- PM8058_PON_WD_EN_MASK);
-}
-EXPORT_SYMBOL(pm8058_watchdog_reset_control);
-
-/*
- * Set an SMPS regulator to be disabled in its CTRL register, but enabled
- * in the master enable register. Also set it's pull down enable bit.
- * Take care to make sure that the output voltage doesn't change if switching
- * from advanced mode to legacy mode.
- */
-static int disable_smps_locally_set_pull_down(u16 ctrl_addr, u16 test2_addr,
- u16 master_enable_addr, u8 master_enable_bit)
-{
- int rc = 0;
- u8 vref_sel, vlow_sel, band, vprog, bank, reg;
-
- if (pmic_chip == NULL)
- return -ENODEV;
-
- bank = REGULATOR_BANK_SEL(7);
- rc = ssbi_write(pmic_chip->dev, test2_addr, &bank, 1);
- if (rc) {
- pr_err("%s: FAIL ssbi_write(0x%03X): rc=%d\n", __func__,
- test2_addr, rc);
- goto done;
- }
-
- rc = ssbi_read(pmic_chip->dev, test2_addr, ®, 1);
- if (rc) {
- pr_err("%s: FAIL pm8058_read(0x%03X): rc=%d\n",
- __func__, test2_addr, rc);
- goto done;
- }
-
- /* Check if in advanced mode. */
- if ((reg & SMPS_ADVANCED_MODE_MASK) == SMPS_ADVANCED_MODE) {
- /* Determine current output voltage. */
- rc = ssbi_read(pmic_chip->dev, ctrl_addr, ®, 1);
- if (rc) {
- pr_err("%s: FAIL pm8058_read(0x%03X): rc=%d\n",
- __func__, ctrl_addr, rc);
- goto done;
- }
-
- band = (reg & SMPS_ADVANCED_BAND_MASK)
- >> SMPS_ADVANCED_BAND_SHIFT;
- switch (band) {
- case 3:
- vref_sel = 0;
- vlow_sel = 0;
- break;
- case 2:
- vref_sel = SMPS_LEGACY_VREF_SEL;
- vlow_sel = 0;
- break;
- case 1:
- vref_sel = SMPS_LEGACY_VREF_SEL;
- vlow_sel = SMPS_LEGACY_VLOW_SEL;
- break;
- default:
- pr_err("%s: regulator already disabled\n", __func__);
- return -EPERM;
- }
- vprog = (reg & SMPS_ADVANCED_VPROG_MASK);
- /* Round up if fine step is in use. */
- vprog = (vprog + 1) >> 1;
- if (vprog > SMPS_LEGACY_VPROG_MASK)
- vprog = SMPS_LEGACY_VPROG_MASK;
-
- /* Set VLOW_SEL bit. */
- bank = REGULATOR_BANK_SEL(1);
- rc = ssbi_write(pmic_chip->dev, test2_addr, &bank, 1);
- if (rc) {
- pr_err("%s: FAIL ssbi_write(0x%03X): rc=%d\n",
- __func__, test2_addr, rc);
- goto done;
- }
- rc = pm8058_masked_write(test2_addr,
- REGULATOR_BANK_WRITE | REGULATOR_BANK_SEL(1)
- | vlow_sel,
- REGULATOR_BANK_WRITE | REGULATOR_BANK_MASK
- | SMPS_LEGACY_VLOW_SEL);
- if (rc)
- goto done;
-
- /* Switch to legacy mode */
- bank = REGULATOR_BANK_SEL(7);
- rc = ssbi_write(pmic_chip->dev, test2_addr, &bank, 1);
- if (rc) {
- pr_err("%s: FAIL ssbi_write(0x%03X): rc=%d\n", __func__,
- test2_addr, rc);
- goto done;
- }
- rc = pm8058_masked_write(test2_addr,
- REGULATOR_BANK_WRITE | REGULATOR_BANK_SEL(7)
- | SMPS_LEGACY_MODE,
- REGULATOR_BANK_WRITE | REGULATOR_BANK_MASK
- | SMPS_ADVANCED_MODE_MASK);
- if (rc)
- goto done;
-
- /* Enable locally, enable pull down, keep voltage the same. */
- rc = pm8058_masked_write(ctrl_addr,
- REGULATOR_ENABLE | REGULATOR_PULL_DOWN_EN
- | vref_sel | vprog,
- REGULATOR_ENABLE_MASK | REGULATOR_PULL_DOWN_MASK
- | SMPS_LEGACY_VREF_SEL | SMPS_LEGACY_VPROG_MASK);
- if (rc)
- goto done;
- }
-
- /* Enable in master control register. */
- rc = pm8058_masked_write(master_enable_addr, master_enable_bit,
- master_enable_bit);
- if (rc)
- goto done;
-
- /* Disable locally and enable pull down. */
- rc = pm8058_masked_write(ctrl_addr,
- REGULATOR_DISABLE | REGULATOR_PULL_DOWN_EN,
- REGULATOR_ENABLE_MASK | REGULATOR_PULL_DOWN_MASK);
-
-done:
- return rc;
-}
-
-static int disable_ldo_locally_set_pull_down(u16 ctrl_addr,
- u16 master_enable_addr, u8 master_enable_bit)
-{
- int rc;
-
- /* Enable LDO in master control register. */
- rc = pm8058_masked_write(master_enable_addr, master_enable_bit,
- master_enable_bit);
- if (rc)
- goto done;
-
- /* Disable LDO in CTRL register and set pull down */
- rc = pm8058_masked_write(ctrl_addr,
- REGULATOR_DISABLE | REGULATOR_PULL_DOWN_EN,
- REGULATOR_ENABLE_MASK | REGULATOR_PULL_DOWN_MASK);
-
-done:
- return rc;
-}
-
-int pm8058_reset_pwr_off(int reset)
-{
- int rc;
- u8 pon, ctrl, smpl;
-
- if (pmic_chip == NULL)
- return -ENODEV;
-
- /* When shutting down, enable active pulldowns on important rails. */
- if (!reset) {
- /* Disable SMPS's 0,1,3 locally and set pulldown enable bits. */
- disable_smps_locally_set_pull_down(SSBI_REG_ADDR_S0_CTRL,
- SSBI_REG_ADDR_S0_TEST2, SSBI_REG_ADDR_VREG_EN_MSM, BIT(7));
- disable_smps_locally_set_pull_down(SSBI_REG_ADDR_S1_CTRL,
- SSBI_REG_ADDR_S1_TEST2, SSBI_REG_ADDR_VREG_EN_MSM, BIT(6));
- disable_smps_locally_set_pull_down(SSBI_REG_ADDR_S3_CTRL,
- SSBI_REG_ADDR_S3_TEST2, SSBI_REG_ADDR_VREG_EN_GRP_5_4,
- BIT(7) | BIT(4));
- /* Disable LDO 21 locally and set pulldown enable bit. */
- disable_ldo_locally_set_pull_down(SSBI_REG_ADDR_L21_CTRL,
- SSBI_REG_ADDR_VREG_EN_GRP_5_4, BIT(1));
- }
-
- /* Set regulator L22 to 1.225V in high power mode. */
- rc = ssbi_read(pmic_chip->dev, SSBI_REG_ADDR_L22_CTRL, &ctrl, 1);
- if (rc) {
- pr_err("%s: FAIL ssbi_read(0x%x): rc=%d\n", __func__,
- SSBI_REG_ADDR_L22_CTRL, rc);
- goto get_out3;
- }
- /* Leave pull-down state intact. */
- ctrl &= 0x40;
- ctrl |= 0x93;
- rc = ssbi_write(pmic_chip->dev, SSBI_REG_ADDR_L22_CTRL, &ctrl, 1);
- if (rc)
- pr_err("%s: FAIL ssbi_write(0x%x)=0x%x: rc=%d\n", __func__,
- SSBI_REG_ADDR_L22_CTRL, ctrl, rc);
-
-get_out3:
- if (!reset) {
- /* Only modify the SLEEP_CNTL reg if shutdown is desired. */
- rc = ssbi_read(pmic_chip->dev, SSBI_REG_ADDR_SLEEP_CNTL,
- &smpl, 1);
- if (rc) {
- pr_err("%s: FAIL ssbi_read(0x%x): rc=%d\n",
- __func__, SSBI_REG_ADDR_SLEEP_CNTL, rc);
- goto get_out2;
- }
-
- smpl &= ~PM8058_SLEEP_SMPL_EN_MASK;
- smpl |= PM8058_SLEEP_SMPL_EN_PWR_OFF;
-
- rc = ssbi_write(pmic_chip->dev, SSBI_REG_ADDR_SLEEP_CNTL,
- &smpl, 1);
- if (rc)
- pr_err("%s: FAIL ssbi_write(0x%x)=0x%x: rc=%d\n",
- __func__, SSBI_REG_ADDR_SLEEP_CNTL, smpl, rc);
- }
-
-get_out2:
- rc = ssbi_read(pmic_chip->dev, SSBI_REG_ADDR_PON_CNTL_1, &pon, 1);
- if (rc) {
- pr_err("%s: FAIL ssbi_read(0x%x): rc=%d\n",
- __func__, SSBI_REG_ADDR_PON_CNTL_1, rc);
- goto get_out;
- }
-
- pon &= ~PM8058_PON_WD_EN_MASK;
- pon |= reset ? PM8058_PON_WD_EN_RESET : PM8058_PON_WD_EN_PWR_OFF;
-
- /* Enable all pullups */
- pon |= PM8058_PON_PUP_MASK;
-
- rc = ssbi_write(pmic_chip->dev, SSBI_REG_ADDR_PON_CNTL_1, &pon, 1);
- if (rc) {
- pr_err("%s: FAIL ssbi_write(0x%x)=0x%x: rc=%d\n",
- __func__, SSBI_REG_ADDR_PON_CNTL_1, pon, rc);
- goto get_out;
- }
-
-get_out:
- return rc;
-}
-EXPORT_SYMBOL(pm8058_reset_pwr_off);
-
/**
* pm8058_stay_on - enables stay_on feature
*
diff --git a/include/linux/mfd/pmic8058.h b/include/linux/mfd/pmic8058.h
index cf753b5d..0699c46 100644
--- a/include/linux/mfd/pmic8058.h
+++ b/include/linux/mfd/pmic8058.h
@@ -144,54 +144,9 @@
struct pmic8058_charger_data *charger_pdata;
};
-#ifdef CONFIG_PMIC8058
-int pm8058_reset_pwr_off(int reset);
-#else
-static inline int pm8058_reset_pwr_off(int reset) { return 0; }
-#endif
-
-
int pm8058_hard_reset_config(enum pon_config config);
/**
- * pm8058_smpl_control - enables/disables SMPL detection
- * @enable: 0 = shutdown PMIC on power loss, 1 = reset PMIC on power loss
- *
- * This function enables or disables the Sudden Momentary Power Loss detection
- * module. If SMPL detection is enabled, then when a sufficiently long power
- * loss event occurs, the PMIC will automatically reset itself. If SMPL
- * detection is disabled, then the PMIC will shutdown when power loss occurs.
- *
- * RETURNS: an appropriate -ERRNO error value on error, or zero for success.
- */
-int pm8058_smpl_control(int enable);
-
-/**
- * pm8058_smpl_set_delay - sets the SMPL detection time delay
- * @delay: enum value corresponding to delay time
- *
- * This function sets the time delay of the SMPL detection module. If power
- * is reapplied within this interval, then the PMIC reset automatically. The
- * SMPL detection module must be enabled for this delay time to take effect.
- *
- * RETURNS: an appropriate -ERRNO error value on error, or zero for success.
- */
-int pm8058_smpl_set_delay(enum pm8058_smpl_delay delay);
-
-/**
- * pm8058_watchdog_reset_control - enables/disables watchdog reset detection
- * @enable: 0 = shutdown when PS_HOLD goes low, 1 = reset when PS_HOLD goes low
- *
- * This function enables or disables the PMIC watchdog reset detection feature.
- * If watchdog reset detection is enabled, then the PMIC will reset itself
- * when PS_HOLD goes low. If it is not enabled, then the PMIC will shutdown
- * when PS_HOLD goes low.
- *
- * RETURNS: an appropriate -ERRNO error value on error, or zero for success.
- */
-int pm8058_watchdog_reset_control(int enable);
-
-/**
* pm8058_stay_on - enables stay_on feature
*
* PMIC stay-on feature allows PMIC to ignore MSM PS_HOLD=low