[XTENSA] Flush the page-address in update-mmu instead of user-address
The TLB entry for the user address doesn't exist at the time we
want to flush the caches, so use the page address. Note that processor
configurations with cache-aliasing issues are treated separately.
Signed-off-by: Chris Zankel <chris@zankel.net>
diff --git a/arch/xtensa/mm/cache.c b/arch/xtensa/mm/cache.c
index 42bfb69..3ba990c 100644
--- a/arch/xtensa/mm/cache.c
+++ b/arch/xtensa/mm/cache.c
@@ -180,9 +180,9 @@
#else
if (!PageReserved(page) && !test_bit(PG_arch_1, &page->flags)
&& (vma->vm_flags & VM_EXEC) != 0) {
- unsigned long vaddr = addr & PAGE_MASK;
- __flush_dcache_page(vaddr);
- __invalidate_icache_page(vaddr);
+ unsigned long paddr = (unsigned long) page_address(page);
+ __flush_dcache_page(paddr);
+ __invalidate_icache_page(paddr);
set_bit(PG_arch_1, &page->flags);
}
#endif