| commit | b76f190d3b3c6ce9a07a483b5e85df449c7f5366 | [log] [tgz] |
|---|---|---|
| author | Matt Wagantall <mattw@codeaurora.org> | Thu Aug 09 14:51:28 2012 -0700 |
| committer | Matt Wagantall <mattw@codeaurora.org> | Fri Aug 10 00:17:14 2012 -0700 |
| tree | 33da689a8a6e14b51bbfeb3e2eb692ab325223a1 | |
| parent | 3e04184032acc1c946c8e3ff56ca513aa956c1ee [diff] |
msm: pil-q6v5: Disable Q6 core_clk and core_rclk gating Leaving clock gating enabled for these causes issues for JTAG debugging. Disable clock gating by default and leave enabling it again to the Q6 software. Change-Id: Id6c41b93b94e5fe05a80918aa1e0ce129e857ccc Signed-off-by: Matt Wagantall <mattw@codeaurora.org>