ARM: dts: msm: Add cpu clock device for 8610
Replace the device which controls the cpu frequency with a new
version. Add the cpubw device to manage DDR bandwidth.
Change-Id: Icc377f4ddab1cc0a9a80f344887adeec629e62b3
Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
diff --git a/arch/arm/boot/dts/msm8610-regulator.dtsi b/arch/arm/boot/dts/msm8610-regulator.dtsi
index 1340612..30c557d 100644
--- a/arch/arm/boot/dts/msm8610-regulator.dtsi
+++ b/arch/arm/boot/dts/msm8610-regulator.dtsi
@@ -36,7 +36,7 @@
interrupts = <0 15 0>;
regulator-name = "apc_corner";
regulator-min-microvolt = <1>;
- regulator-max-microvolt = <12>;
+ regulator-max-microvolt = <3>;
qcom,pvs-fuse-redun-sel = <53 25 3 2 1>;
qcom,pvs-fuse = <23 6 5 1>;
@@ -83,7 +83,6 @@
qcom,cpr-fuse-redun-bp-scheme = <25>;
qcom,cpr-fuse-redun-target-quot = <32 12 0>;
qcom,cpr-fuse-redun-ro-sel = <44 26 29>;
- qcom,cpr-corner-map = <1 1 2 2 3 3 3 3 3 3 3 3>;
qcom,cpr-enable;
};
diff --git a/arch/arm/boot/dts/msm8610-v1-pm.dtsi b/arch/arm/boot/dts/msm8610-v1-pm.dtsi
index ea37413..e075c71 100644
--- a/arch/arm/boot/dts/msm8610-v1-pm.dtsi
+++ b/arch/arm/boot/dts/msm8610-v1-pm.dtsi
@@ -302,6 +302,8 @@
qcom,pc-mode = "tz_l2_int";
qcom,use-sync-timer;
qcom,pc-resets-timer;
+ qcom,cpus-as-clocks;
+ qcom,synced-clocks;
};
qcom,cpu-sleep-status@f9088008{
diff --git a/arch/arm/boot/dts/msm8610-v2-pm.dtsi b/arch/arm/boot/dts/msm8610-v2-pm.dtsi
index 19fb185..447290d 100644
--- a/arch/arm/boot/dts/msm8610-v2-pm.dtsi
+++ b/arch/arm/boot/dts/msm8610-v2-pm.dtsi
@@ -304,6 +304,8 @@
qcom,pc-mode = "tz_l2_int";
qcom,use-sync-timer;
qcom,pc-resets-timer;
+ qcom,cpus-as-clocks;
+ qcom,synced-clocks;
};
qcom,cpu-sleep-status@f9088008{
diff --git a/arch/arm/boot/dts/msm8610.dtsi b/arch/arm/boot/dts/msm8610.dtsi
index 84adad4..6e10deb 100644
--- a/arch/arm/boot/dts/msm8610.dtsi
+++ b/arch/arm/boot/dts/msm8610.dtsi
@@ -463,11 +463,39 @@
qcom,ipi-ping;
};
- qcom,acpuclk@f9011050 {
- compatible = "qcom,acpuclk-a7";
+ qcom,clock-a7@f9011050 {
+ compatible = "qcom,clock-a7-8226";
reg = <0xf9011050 0x8>;
- reg-names = "rcg_base";
- a7_cpu-supply = <&apc_vreg_corner>;
+ reg-names = "rcg-base";
+ clock-names = "clk-4", "clk-5";
+ qcom,speed0-bin-v0 =
+ < 0 0>,
+ < 384000000 1>,
+ < 787200000 2>,
+ <1190400000 3>;
+
+ cpu-vdd-supply = <&apc_vreg_corner>;
+ };
+
+ qcom,cpubw {
+ compatible = "qcom,cpubw";
+ qcom,cpu-mem-ports = <1 512>;
+ qcom,bw-tbl =
+ < 762 /* 100 MHz */ >,
+ < 1525 /* 200 MHz */ >,
+ < 2540 /* 333 MHz */ >;
+ };
+
+ qcom,msm-cpufreq@0 {
+ reg = <0 4>;
+ compatible = "qcom,msm-cpufreq";
+ qcom,cpufreq-table =
+ < 300000 762 >,
+ < 384000 762 >,
+ < 600000 1525 >,
+ < 787200 1525 >,
+ < 998400 2540 >,
+ < 1190400 2540 >;
};
spmi_bus: qcom,spmi@fc4c0000 {