tree c4fa3bbc3a0f1bd6a146e8ec1918c2076f8d5730
parent 088dd1f81b3577c17c4c4381696bf2105ea0e43a
author David S. Miller <davem@davemloft.net> 1120508764 -0700
committer David S. Miller <davem@davemloft.net> 1120508764 -0700

[SPARC64]: Do proper DMA IRQ syncing on Tomatillo

This was the main impetus behind adding the PCI IRQ shim.

In order to properly order DMA writes wrt. interrupts, you have to
write to a PCI controller register, then poll for that bit clearing.
There is one bit for each interrupt source, and setting this register
bit tells Tomatillo to drain all pending DMA from that device.

Furthermore, Tomatillo's with revision less than 4 require us to do a
block store due to some memory transaction ordering issues it has on
JBUS.

Signed-off-by: David S. Miller <davem@davemloft.net>