USB: xhci: Add PORTSC register write delay quirk for DWC3 controller
In Synopsis DWC3 controller, PORTSC register access involves multiple clock
domains. When the software does a PORTSC write, handshakes are needed
across these clock domains. This results in long access times, especially
for USB 2.0 ports. In order to solve this issue, when the PORTSC write
operations happen on the system bus, the command is latched and system bus
is released immediately. However, the real PORTSC write access will take
some time internally to complete. If the software quickly does a read to
the PORTSC, some fields (port status change related fields like OCC, etc.)
may not have correct value due to the current way of handling these bits.
The workaround is to give some delay (5 mac2_clk -> UTMI clock = 60 MHz ->
(16.66 ns x 5 = 84ns) ~100ns after writing to the PORTSC register.
Add controller vendor id and revision fields to the XHCI platform data.
Update quirks field based on the vendor id and revision in the XHCI
platform driver.
CRs-fixed: 371299
Change-Id: Ibe4a88119c483afb522e9a96667f17dccbf74122
Signed-off-by: Pavankumar Kondeti <pkondeti@codeaurora.org>
diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c
index e03b0bb..8467dc0 100644
--- a/drivers/usb/host/xhci-plat.c
+++ b/drivers/usb/host/xhci-plat.c
@@ -18,16 +18,26 @@
#include "xhci.h"
+#define SYNOPSIS_DWC3_VENDOR 0x5533
+
static struct usb_phy *phy;
static void xhci_plat_quirks(struct device *dev, struct xhci_hcd *xhci)
{
+ struct xhci_plat_data *pdata = dev->platform_data;
+
/*
* As of now platform drivers don't provide MSI support so we ensure
* here that the generic code does not try to make a pci_dev from our
* dev struct in order to setup MSI
*/
xhci->quirks |= XHCI_BROKEN_MSI;
+
+ if (!pdata)
+ return;
+ else if (pdata->vendor == SYNOPSIS_DWC3_VENDOR &&
+ pdata->revision < 0x230A)
+ xhci->quirks |= XHCI_PORTSC_DELAY;
}
/* called during probe() after chip reset completes */