USB: xhci: Add PORTSC register write delay quirk for DWC3 controller
In Synopsis DWC3 controller, PORTSC register access involves multiple clock
domains. When the software does a PORTSC write, handshakes are needed
across these clock domains. This results in long access times, especially
for USB 2.0 ports. In order to solve this issue, when the PORTSC write
operations happen on the system bus, the command is latched and system bus
is released immediately. However, the real PORTSC write access will take
some time internally to complete. If the software quickly does a read to
the PORTSC, some fields (port status change related fields like OCC, etc.)
may not have correct value due to the current way of handling these bits.
The workaround is to give some delay (5 mac2_clk -> UTMI clock = 60 MHz ->
(16.66 ns x 5 = 84ns) ~100ns after writing to the PORTSC register.
Add controller vendor id and revision fields to the XHCI platform data.
Update quirks field based on the vendor id and revision in the XHCI
platform driver.
CRs-fixed: 371299
Change-Id: Ibe4a88119c483afb522e9a96667f17dccbf74122
Signed-off-by: Pavankumar Kondeti <pkondeti@codeaurora.org>
diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
index 3d69c4b..127b0e9 100644
--- a/drivers/usb/host/xhci.h
+++ b/drivers/usb/host/xhci.h
@@ -1479,6 +1479,21 @@
#define XHCI_RESET_ON_RESUME (1 << 7)
#define XHCI_SW_BW_CHECKING (1 << 8)
#define XHCI_AMD_0x96_HOST (1 << 9)
+/*
+ * In Synopsis DWC3 controller, PORTSC register access involves multiple clock
+ * domains. When the software does a PORTSC write, handshakes are needed
+ * across these clock domains. This results in long access times, especially
+ * for USB 2.0 ports. In order to solve this issue, when the PORTSC write
+ * operations happen on the system bus, the command is latched and system bus
+ * is released immediately. However, the real PORTSC write access will take
+ * some time internally to complete. If the software quickly does a read to the
+ * PORTSC, some fields (port status change related fields like OCC, etc.) may
+ * not have correct value due to the current way of handling these bits.
+ *
+ * The workaround is to give some delay (5 mac2_clk -> UTMI clock = 60 MHz ->
+ * (16.66 ns x 5 = 84ns) ~100ns after writing to the PORTSC register.
+ */
+#define XHCI_PORTSC_DELAY (1 << 10)
unsigned int num_active_eps;
unsigned int limit_active_eps;
/* There are two roothubs to keep track of bus suspend info for */
@@ -1667,6 +1682,11 @@
static inline void xhci_unregister_pci(void) {}
#endif
+struct xhci_plat_data {
+ unsigned vendor;
+ unsigned revision;
+};
+
#if defined(CONFIG_USB_XHCI_PLATFORM) \
|| defined(CONFIG_USB_XHCI_PLATFORM_MODULE)
int xhci_register_plat(void);