Merge "msm: pil-modem: Combine SSR and PIL drivers"
diff --git a/Documentation/devicetree/bindings/arm/msm/qcom-wdog-debug.txt b/Documentation/devicetree/bindings/arm/msm/qcom-wdog-debug.txt
new file mode 100644
index 0000000..e5fd1b2
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/msm/qcom-wdog-debug.txt
@@ -0,0 +1,16 @@
+* Qualcomm's Watchdog Debug Image Controller
+
+The Qualcomm's Watchdog debug image controller is used for enabling/disabling of
+watchdog debug image feature.
+
+Required properties:
+- compatible : should be "qcom,msm-wdog-debug"
+- reg : base page aligned physical base address of the controller and length of
+ memory mapped region.
+
+Example:
+
+ qcom,msm-wdog-debug@fc401000 {
+ compatible = "qcom,msm-wdogi-debug";
+ reg = <0xfc401000 0x1000>;
+ };
diff --git a/Documentation/devicetree/bindings/coresight/coresight.txt b/Documentation/devicetree/bindings/coresight/coresight.txt
index c584073..f860618 100644
--- a/Documentation/devicetree/bindings/coresight/coresight.txt
+++ b/Documentation/devicetree/bindings/coresight/coresight.txt
@@ -31,6 +31,7 @@
component
- coresight-child-ports : list of input port numbers of the children
- coresight-default-sink : represents the default compile time CoreSight sink
+- qcom,pc-save : program counter save implemented
Examples:
@@ -103,4 +104,5 @@
coresight-outports = <0>;
coresight-child-list = <&funnel_kpss>;
coresight-child-ports = <0>;
+ qcom,pc-save;
};
diff --git a/Documentation/devicetree/bindings/input/touchscreen/atmel-mxt-ts.txt b/Documentation/devicetree/bindings/input/touchscreen/atmel-mxt-ts.txt
index a6c83d0..88fca69 100644
--- a/Documentation/devicetree/bindings/input/touchscreen/atmel-mxt-ts.txt
+++ b/Documentation/devicetree/bindings/input/touchscreen/atmel-mxt-ts.txt
@@ -27,6 +27,8 @@
- vcc_i2c-supply : Power source required to pull up i2c bus
- atmel,dig-reg-support : specify to indicate digital regulator is
needed
+ - atmel,need-calibration : specify to indicate whether calibration is
+ needed during wakeup.
Example:
i2c@f9966000 {
diff --git a/Documentation/devicetree/bindings/sound/qcom-audio-dev.txt b/Documentation/devicetree/bindings/sound/qcom-audio-dev.txt
index 0eb186e..2864fd1 100644
--- a/Documentation/devicetree/bindings/sound/qcom-audio-dev.txt
+++ b/Documentation/devicetree/bindings/sound/qcom-audio-dev.txt
@@ -48,6 +48,12 @@
- compatible : "qcom,msm-dai-fe"
+* msm-pcm-afe
+
+Required properties:
+
+ - compatible : "qcom,msm-pcm-afe"
+
* msm-dai-q6
[First Level Nodes]
@@ -63,6 +69,8 @@
- compatible : "qcom,msm-dai-q6-dev"
- qcom,msm-dai-q6-dev-id : The slimbus multi channel port ID
Value is from 16384 to 16393
+ BT SCO port ID value from 12288 to 12289
+ RT Proxy port ID values from 224 to 225 and 240 to 241
* msm-auxpcm
@@ -166,6 +174,36 @@
compatible = "qcom,msm-dai-q6-dev";
qcom,msm-dai-q6-dev-id = <16385>;
};
+
+ qcom,msm-dai-q6-bt-sco-rx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <12288>;
+ };
+
+ qcom,msm-dai-q6-bt-sco-tx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <12289>;
+ };
+
+ qcom,msm-dai-q6-be-afe-pcm-rx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <224>;
+ };
+
+ qcom,msm-dai-q6-be-afe-pcm-tx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <225>;
+ };
+
+ qcom,msm-dai-q6-afe-proxy-rx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <241>;
+ };
+
+ qcom,msm-dai-q6-afe-proxy-tx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <240>;
+ };
};
qcom,msm-auxpcm {
diff --git a/arch/Kconfig b/arch/Kconfig
index 0d88760..0a3ffe4 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -169,13 +169,6 @@
bool
depends on PERF_EVENTS
-config HAVE_HW_BRKPT_RESERVED_RW_ACCESS
- bool
- depends on HAVE_HW_BREAKPOINT
- help
- Some of the hardware might not have r/w access beyond a certain number
- of breakpoint register access.
-
config HAVE_MIXED_BREAKPOINTS_REGS
bool
depends on HAVE_HW_BREAKPOINT
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index d7ebcfe..5d5f9de 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -29,7 +29,7 @@
select HAVE_PERF_EVENTS
select PERF_USE_VMALLOC
select HAVE_REGS_AND_STACK_ACCESS_API
- #select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
+ select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
select HAVE_C_RECORDMCOUNT
select HAVE_GENERIC_HARDIRQS
select GENERIC_IRQ_SHOW
diff --git a/arch/arm/boot/dts/mpq8092-iommu.dtsi b/arch/arm/boot/dts/mpq8092-iommu.dtsi
old mode 100755
new mode 100644
diff --git a/arch/arm/boot/dts/msm-pm8841.dtsi b/arch/arm/boot/dts/msm-pm8841.dtsi
index 967d5ec..ea83231 100644
--- a/arch/arm/boot/dts/msm-pm8841.dtsi
+++ b/arch/arm/boot/dts/msm-pm8841.dtsi
@@ -22,7 +22,7 @@
#address-cells = <1>;
#size-cells = <1>;
- pm8841_mpps {
+ pm8841_mpps: mpps {
spmi-dev-container;
compatible = "qcom,qpnp-pin";
gpio-controller;
@@ -34,25 +34,21 @@
mpp@a000 {
reg = <0xa000 0x100>;
qcom,pin-num = <1>;
- status = "disabled";
};
mpp@a100 {
reg = <0xa100 0x100>;
qcom,pin-num = <2>;
- status = "disabled";
};
mpp@a200 {
reg = <0xa200 0x100>;
qcom,pin-num = <3>;
- status = "disabled";
};
mpp@a300 {
reg = <0xa300 0x100>;
qcom,pin-num = <4>;
- status = "disabled";
};
};
};
diff --git a/arch/arm/boot/dts/msm-pm8941.dtsi b/arch/arm/boot/dts/msm-pm8941.dtsi
index 8560f9f..f1e18cf 100644
--- a/arch/arm/boot/dts/msm-pm8941.dtsi
+++ b/arch/arm/boot/dts/msm-pm8941.dtsi
@@ -203,7 +203,7 @@
};
};
- pm8941_gpios {
+ pm8941_gpios: gpios {
spmi-dev-container;
compatible = "qcom,qpnp-pin";
gpio-controller;
@@ -215,221 +215,185 @@
gpio@c000 {
reg = <0xc000 0x100>;
qcom,pin-num = <1>;
- status = "disabled";
};
gpio@c100 {
reg = <0xc100 0x100>;
qcom,pin-num = <2>;
- status = "disabled";
};
gpio@c200 {
reg = <0xc200 0x100>;
qcom,pin-num = <3>;
- status = "disabled";
};
gpio@c300 {
reg = <0xc300 0x100>;
qcom,pin-num = <4>;
- status = "disabled";
};
gpio@c400 {
reg = <0xc400 0x100>;
qcom,pin-num = <5>;
- status = "disabled";
};
gpio@c500 {
reg = <0xc500 0x100>;
qcom,pin-num = <6>;
- status = "disabled";
};
gpio@c600 {
reg = <0xc600 0x100>;
qcom,pin-num = <7>;
- status = "disabled";
};
gpio@c700 {
reg = <0xc700 0x100>;
qcom,pin-num = <8>;
- status = "disabled";
};
gpio@c800 {
reg = <0xc800 0x100>;
qcom,pin-num = <9>;
- status = "disabled";
};
gpio@c900 {
reg = <0xc900 0x100>;
qcom,pin-num = <10>;
- status = "disabled";
};
gpio@ca00 {
reg = <0xca00 0x100>;
qcom,pin-num = <11>;
- status = "disabled";
};
gpio@cb00 {
reg = <0xcb00 0x100>;
qcom,pin-num = <12>;
- status = "disabled";
};
gpio@cc00 {
reg = <0xcc00 0x100>;
qcom,pin-num = <13>;
- status = "disabled";
};
gpio@cd00 {
reg = <0xcd00 0x100>;
qcom,pin-num = <14>;
- status = "disabled";
};
gpio@ce00 {
reg = <0xce00 0x100>;
qcom,pin-num = <15>;
- status = "disabled";
};
gpio@cf00 {
reg = <0xcf00 0x100>;
qcom,pin-num = <16>;
- status = "disabled";
};
gpio@d000 {
reg = <0xd000 0x100>;
qcom,pin-num = <17>;
- status = "disabled";
};
gpio@d100 {
reg = <0xd100 0x100>;
qcom,pin-num = <18>;
- status = "disabled";
};
gpio@d200 {
reg = <0xd200 0x100>;
qcom,pin-num = <19>;
- status = "disabled";
};
gpio@d300 {
reg = <0xd300 0x100>;
qcom,pin-num = <20>;
- status = "disabled";
};
gpio@d400 {
reg = <0xd400 0x100>;
qcom,pin-num = <21>;
- status = "disabled";
};
gpio@d500 {
reg = <0xd500 0x100>;
qcom,pin-num = <22>;
- status = "disabled";
};
gpio@d600 {
reg = <0xd600 0x100>;
qcom,pin-num = <23>;
- status = "disabled";
};
gpio@d700 {
reg = <0xd700 0x100>;
qcom,pin-num = <24>;
- status = "disabled";
};
gpio@d800 {
reg = <0xd800 0x100>;
qcom,pin-num = <25>;
- status = "disabled";
};
gpio@d900 {
reg = <0xd900 0x100>;
qcom,pin-num = <26>;
- status = "disabled";
};
gpio@da00 {
reg = <0xda00 0x100>;
qcom,pin-num = <27>;
- status = "disabled";
};
gpio@db00 {
reg = <0xdb00 0x100>;
qcom,pin-num = <28>;
- status = "disabled";
};
gpio@dc00 {
reg = <0xdc00 0x100>;
qcom,pin-num = <29>;
- status = "disabled";
};
gpio@dd00 {
reg = <0xdd00 0x100>;
qcom,pin-num = <30>;
- status = "disabled";
};
gpio@de00 {
reg = <0xde00 0x100>;
qcom,pin-num = <31>;
- status = "disabled";
};
gpio@df00 {
reg = <0xdf00 0x100>;
qcom,pin-num = <32>;
- status = "disabled";
};
gpio@e000 {
reg = <0xe000 0x100>;
qcom,pin-num = <33>;
- status = "disabled";
};
gpio@e100 {
reg = <0xe100 0x100>;
qcom,pin-num = <34>;
- status = "disabled";
};
gpio@e200 {
reg = <0xe200 0x100>;
qcom,pin-num = <35>;
- status = "disabled";
};
gpio@e300 {
reg = <0xe300 0x100>;
qcom,pin-num = <36>;
- status = "disabled";
};
};
- pm8941_mpps {
+ pm8941_mpps: mpps {
spmi-dev-container;
compatible = "qcom,qpnp-pin";
gpio-controller;
@@ -441,49 +405,41 @@
mpp@a000 {
reg = <0xa000 0x100>;
qcom,pin-num = <1>;
- status = "disabled";
};
mpp@a100 {
reg = <0xa100 0x100>;
qcom,pin-num = <2>;
- status = "disabled";
};
mpp@a200 {
reg = <0xa200 0x100>;
qcom,pin-num = <3>;
- status = "disabled";
};
mpp@a300 {
reg = <0xa300 0x100>;
qcom,pin-num = <4>;
- status = "disabled";
};
mpp@a400 {
reg = <0xa400 0x100>;
qcom,pin-num = <5>;
- status = "disabled";
};
mpp@a500 {
reg = <0xa500 0x100>;
qcom,pin-num = <6>;
- status = "disabled";
};
mpp@a600 {
reg = <0xa600 0x100>;
qcom,pin-num = <7>;
- status = "disabled";
};
mpp@a700 {
reg = <0xa700 0x100>;
qcom,pin-num = <8>;
- status = "disabled";
};
};
diff --git a/arch/arm/boot/dts/msm8974-cdp.dts b/arch/arm/boot/dts/msm8974-cdp.dts
index 7aeb33c..aff0adc 100644
--- a/arch/arm/boot/dts/msm8974-cdp.dts
+++ b/arch/arm/boot/dts/msm8974-cdp.dts
@@ -168,3 +168,196 @@
cd-gpios = <&msmgpio 62 0x1>;
wp-gpios = <&pm8941_gpios 29 0x1>;
};
+
+&pm8941_gpios {
+ gpio@c000 { /* GPIO 1 */
+ };
+
+ gpio@c100 { /* GPIO 2 */
+ };
+
+ gpio@c200 { /* GPIO 3 */
+ qcom,mode = <0>;
+ qcom,pull = <0>;
+ qcom,vin-sel = <2>;
+ qcom,select = <0>;
+ };
+
+ gpio@c300 { /* GPIO 4 */
+ qcom,mode = <0>;
+ qcom,pull = <0>;
+ qcom,vin-sel = <2>;
+ qcom,select = <0>;
+ };
+
+ gpio@c400 { /* GPIO 5 */
+ qcom,mode = <0>;
+ qcom,pull = <0>;
+ qcom,vin-sel = <2>;
+ qcom,select = <0>;
+ };
+
+ gpio@c500 { /* GPIO 6 */
+ };
+
+ gpio@c600 { /* GPIO 7 */
+ };
+
+ gpio@c700 { /* GPIO 8 */
+ };
+
+ gpio@c800 { /* GPIO 9 */
+ };
+
+ gpio@c900 { /* GPIO 10 */
+ };
+
+ gpio@ca00 { /* GPIO 11 */
+ };
+
+ gpio@cb00 { /* GPIO 12 */
+ };
+
+ gpio@cc00 { /* GPIO 13 */
+ };
+
+ gpio@cd00 { /* GPIO 14 */
+ };
+
+ gpio@ce00 { /* GPIO 15 */
+ qcom,mode = <1>;
+ qcom,output-type = <0>;
+ qcom,pull = <5>;
+ qcom,vin-sel = <2>;
+ qcom,out-strength = <3>;
+ qcom,src-select = <2>;
+ qcom,master-en = <1>;
+ };
+
+ gpio@cf00 { /* GPIO 16 */
+ };
+
+ gpio@d000 { /* GPIO 17 */
+ };
+
+ gpio@d100 { /* GPIO 18 */
+ };
+
+ gpio@d200 { /* GPIO 19 */
+ qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */
+ qcom,output-type = <0>; /* QPNP_PIN_OUT_BUF_CMOS */
+ qcom,pull = <5>; /* QPNP_PIN_PULL_NO */
+ qcom,vin-sel = <2>; /* QPNP_PIN_VIN2 */
+ qcom,out-strength = <2>; /* QPNP_PIN_OUT_STRENGTH_MED */
+ qcom,src-select = <0>; /* QPNP_PIN_SEL_FUNC_CONSTANT */
+ qcom,master-en = <1>;
+ };
+
+ gpio@d300 { /* GPIO 20 */
+ };
+
+ gpio@d400 { /* GPIO 21 */
+ };
+
+ gpio@d500 { /* GPIO 22 */
+ };
+
+ gpio@d600 { /* GPIO 23 */
+ };
+
+ gpio@d700 { /* GPIO 24 */
+ };
+
+ gpio@d800 { /* GPIO 25 */
+ };
+
+ gpio@d900 { /* GPIO 26 */
+ };
+
+ gpio@da00 { /* GPIO 27 */
+ };
+
+ gpio@db00 { /* GPIO 28 */
+ };
+
+ gpio@dc00 { /* GPIO 29 */
+ qcom,pull = <0>; /* set to default pull */
+ qcom,master-en = <1>;
+ qcom,vin-sel = <2>; /* select 1.8 V source */
+ };
+
+ gpio@dd00 { /* GPIO 30 */
+ };
+
+ gpio@de00 { /* GPIO 31 */
+ };
+
+ gpio@df00 { /* GPIO 32 */
+ };
+
+ gpio@e000 { /* GPIO 33 */
+ };
+
+ gpio@e100 { /* GPIO 34 */
+ };
+
+ gpio@e200 { /* GPIO 35 */
+ };
+
+ gpio@e300 { /* GPIO 36 */
+ };
+};
+
+&pm8941_mpps {
+
+ mpp@a000 { /* MPP 1 */
+ };
+
+ mpp@a100 { /* MPP 2 */
+ };
+
+ mpp@a200 { /* MPP 3 */
+ };
+
+ mpp@a300 { /* MPP 4 */
+ };
+
+ mpp@a400 { /* MPP 5 */
+ /* SPI_ETH config */
+ qcom,mode = <1>; /* DIG_OUT */
+ qcom,output-type = <0>; /* CMOS */
+ qcom,vin-sel = <2>; /* PM8941_S3 1.8V > 1.6V */
+ qcom,src-select = <0>; /* CONSTANT */
+ qcom,master-en = <1>; /* ENABLE MPP */
+ };
+
+ mpp@a500 { /* MPP 6 */
+ /* SPI_ETH_RST config */
+ qcom,mode = <1>; /* DIG_OUT */
+ qcom,output-type = <0>; /* CMOS */
+ qcom,vin-sel = <2>; /* PM8941_S3 1.8V > 1.6V */
+ qcom,src-select = <0>; /* CONSTANT */
+ qcom,master-en = <1>; /* ENABLE MPP */
+ };
+
+ mpp@a600 { /* MPP 7 */
+ };
+
+ mpp@a700 { /* MPP 8 */
+ };
+};
+
+&pm8841_mpps {
+
+ mpp@a000 { /* MPP 1 */
+ };
+
+ mpp@a100 { /* MPP 2 */
+ };
+
+ mpp@a200 { /* MPP 3 */
+ };
+
+ mpp@a300 { /* MPP 4 */
+ };
+};
diff --git a/arch/arm/boot/dts/msm8974-coresight.dtsi b/arch/arm/boot/dts/msm8974-coresight.dtsi
index 0b09bc8..ee3df10 100644
--- a/arch/arm/boot/dts/msm8974-coresight.dtsi
+++ b/arch/arm/boot/dts/msm8974-coresight.dtsi
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -141,6 +141,7 @@
coresight-outports = <0>;
coresight-child-list = <&funnel_kpss>;
coresight-child-ports = <0>;
+ qcom,pc-save;
};
etm1: etm@fc33d000 {
@@ -153,6 +154,7 @@
coresight-outports = <0>;
coresight-child-list = <&funnel_kpss>;
coresight-child-ports = <1>;
+ qcom,pc-save;
};
etm2: etm@fc33e000 {
@@ -165,6 +167,7 @@
coresight-outports = <0>;
coresight-child-list = <&funnel_kpss>;
coresight-child-ports = <2>;
+ qcom,pc-save;
};
etm3: etm@fc33f000 {
@@ -177,6 +180,7 @@
coresight-outports = <0>;
coresight-child-list = <&funnel_kpss>;
coresight-child-ports = <3>;
+ qcom,pc-save;
};
csr: csr@fc302000 {
diff --git a/arch/arm/boot/dts/msm8974-gpio.dtsi b/arch/arm/boot/dts/msm8974-gpio.dtsi
deleted file mode 100644
index dac87a3..0000000
--- a/arch/arm/boot/dts/msm8974-gpio.dtsi
+++ /dev/null
@@ -1,273 +0,0 @@
-/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-&spmi_bus {
-
- qcom,pm8941@0 {
-
- pm8941_gpios: pm8941_gpios {
-
- gpio@c000 {
- status = "ok";
- };
-
- gpio@c100 {
- status = "ok";
- };
-
- gpio@c200 {
- qcom,mode = <0>;
- qcom,pull = <0>;
- qcom,vin-sel = <2>;
- qcom,select = <0>;
- status = "ok";
- };
-
- gpio@c300 {
- qcom,mode = <0>;
- qcom,pull = <0>;
- qcom,vin-sel = <2>;
- qcom,select = <0>;
- status = "ok";
- };
-
- gpio@c400 {
- qcom,mode = <0>;
- qcom,pull = <0>;
- qcom,vin-sel = <2>;
- qcom,select = <0>;
- status = "ok";
- };
-
- gpio@c500 {
- status = "ok";
- };
-
- gpio@c600 {
- status = "ok";
- };
-
- gpio@c700 {
- status = "ok";
- };
-
- gpio@c800 {
- status = "ok";
- };
-
- gpio@c900 {
- status = "ok";
- };
-
- gpio@ca00 {
- status = "ok";
- };
-
- gpio@cb00 {
- status = "ok";
- };
-
- gpio@cc00 {
- status = "ok";
- };
-
- gpio@cd00 {
- status = "ok";
- };
-
- gpio@ce00 {
- status = "ok";
- qcom,mode = <1>;
- qcom,output-type = <0>;
- qcom,pull = <5>;
- qcom,vin-sel = <2>;
- qcom,out-strength = <3>;
- qcom,src-select = <2>;
- qcom,master-en = <1>;
- };
-
- gpio@cf00 {
- status = "ok";
- };
-
- gpio@d000 {
- status = "ok";
- };
-
- gpio@d100 {
- status = "ok";
- };
-
- gpio@d200 {
- status = "ok";
- qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */
- qcom,output-type = <0>; /* QPNP_PIN_OUT_BUF_CMOS */
- qcom,pull = <5>; /* QPNP_PIN_PULL_NO */
- qcom,vin-sel = <2>; /* QPNP_PIN_VIN2 */
- qcom,out-strength = <2>; /* QPNP_PIN_OUT_STRENGTH_MED */
- qcom,src-select = <0>; /* QPNP_PIN_SEL_FUNC_CONSTANT */
- qcom,master-en = <1>;
- };
-
- gpio@d300 {
- status = "ok";
- };
-
- gpio@d400 {
- status = "ok";
- };
-
- gpio@d500 {
- status = "ok";
- };
-
- gpio@d600 {
- status = "ok";
- };
-
- gpio@d700 {
- status = "ok";
- };
-
- gpio@d800 {
- qcom,out-strength = <1>;
- status = "ok";
- };
-
- gpio@d900 {
- qcom,out-strength = <1>;
- status = "ok";
- };
-
- gpio@da00 {
- qcom,out-strength = <1>;
- status = "ok";
- };
-
- gpio@db00 {
- qcom,out-strength = <1>;
- status = "ok";
- };
-
- gpio@dc00 {
- qcom,pull = <0>; /* set to default pull */
- qcom,master-en = <1>;
- qcom,vin-sel = <2>; /* select 1.8 V source */
- status = "ok";
- };
-
- gpio@dd00 {
- qcom,out-strength = <1>;
- status = "ok";
- };
-
- gpio@de00 {
- qcom,out-strength = <1>;
- status = "ok";
- };
-
- gpio@df00 {
- qcom,out-strength = <1>;
- status = "ok";
- };
-
- gpio@e000 {
- qcom,out-strength = <1>;
- status = "ok";
- };
-
- gpio@e100 {
- qcom,out-strength = <1>;
- status = "ok";
- };
-
- gpio@e200 {
- qcom,out-strength = <1>;
- status = "ok";
- };
-
- gpio@e300 {
- qcom,out-strength = <1>;
- status = "ok";
- };
- };
-
- pm8941_mpps: pm8941_mpps {
-
- mpp@a000 {
- status = "ok";
- };
-
- mpp@a100 {
- status = "ok";
- };
-
- mpp@a200 {
- status = "ok";
- };
-
- mpp@a300 {
- status = "ok";
- };
-
- mpp@a400 {
- status = "ok";
- /* SPI_ETH config */
- qcom,mode = <1>; /* DIG_OUT */
- qcom,output-type = <0>; /* CMOS */
- qcom,vin-sel = <2>; /* PM8941_S3 1.8V > 1.6V */
- qcom,src-select = <0>; /* CONSTANT */
- qcom,master-en = <1>; /* ENABLE MPP */
- };
-
- mpp@a500 {
- status = "ok";
- /* SPI_ETH_RST config */
- qcom,mode = <1>; /* DIG_OUT */
- qcom,output-type = <0>; /* CMOS */
- qcom,vin-sel = <2>; /* PM8941_S3 1.8V > 1.6V */
- qcom,src-select = <0>; /* CONSTANT */
- qcom,master-en = <1>; /* ENABLE MPP */
- };
-
- mpp@a600 {
- status = "ok";
- };
-
- mpp@a700 {
- status = "ok";
- };
- };
- };
-
- qcom,pm8841@4 {
-
- pm8841_mpps: pm8841_mpps {
-
- mpp@a000 {
- status = "ok";
- };
-
- mpp@a100 {
- status = "ok";
- };
-
- mpp@a200 {
- status = "ok";
- };
-
- mpp@a300 {
- status = "ok";
- };
- };
- };
-};
diff --git a/arch/arm/boot/dts/msm8974-liquid.dts b/arch/arm/boot/dts/msm8974-liquid.dts
index 5de2d43..2abc1d5 100644
--- a/arch/arm/boot/dts/msm8974-liquid.dts
+++ b/arch/arm/boot/dts/msm8974-liquid.dts
@@ -24,4 +24,195 @@
};
};
+&pm8941_gpios {
+ gpio@c000 { /* GPIO 1 */
+ };
+ gpio@c100 { /* GPIO 2 */
+ };
+
+ gpio@c200 { /* GPIO 3 */
+ qcom,mode = <0>;
+ qcom,pull = <0>;
+ qcom,vin-sel = <2>;
+ qcom,select = <0>;
+ };
+
+ gpio@c300 { /* GPIO 4 */
+ qcom,mode = <0>;
+ qcom,pull = <0>;
+ qcom,vin-sel = <2>;
+ qcom,select = <0>;
+ };
+
+ gpio@c400 { /* GPIO 5 */
+ qcom,mode = <0>;
+ qcom,pull = <0>;
+ qcom,vin-sel = <2>;
+ qcom,select = <0>;
+ };
+
+ gpio@c500 { /* GPIO 6 */
+ };
+
+ gpio@c600 { /* GPIO 7 */
+ };
+
+ gpio@c700 { /* GPIO 8 */
+ };
+
+ gpio@c800 { /* GPIO 9 */
+ };
+
+ gpio@c900 { /* GPIO 10 */
+ };
+
+ gpio@ca00 { /* GPIO 11 */
+ };
+
+ gpio@cb00 { /* GPIO 12 */
+ };
+
+ gpio@cc00 { /* GPIO 13 */
+ };
+
+ gpio@cd00 { /* GPIO 14 */
+ };
+
+ gpio@ce00 { /* GPIO 15 */
+ qcom,mode = <1>;
+ qcom,output-type = <0>;
+ qcom,pull = <5>;
+ qcom,vin-sel = <2>;
+ qcom,out-strength = <3>;
+ qcom,src-select = <2>;
+ qcom,master-en = <1>;
+ };
+
+ gpio@cf00 { /* GPIO 16 */
+ };
+
+ gpio@d000 { /* GPIO 17 */
+ };
+
+ gpio@d100 { /* GPIO 18 */
+ };
+
+ gpio@d200 { /* GPIO 19 */
+ qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */
+ qcom,output-type = <0>; /* QPNP_PIN_OUT_BUF_CMOS */
+ qcom,pull = <5>; /* QPNP_PIN_PULL_NO */
+ qcom,vin-sel = <2>; /* QPNP_PIN_VIN2 */
+ qcom,out-strength = <2>; /* QPNP_PIN_OUT_STRENGTH_MED */
+ qcom,src-select = <0>; /* QPNP_PIN_SEL_FUNC_CONSTANT */
+ qcom,master-en = <1>;
+ };
+
+ gpio@d300 { /* GPIO 20 */
+ };
+
+ gpio@d400 { /* GPIO 21 */
+ };
+
+ gpio@d500 { /* GPIO 22 */
+ };
+
+ gpio@d600 { /* GPIO 23 */
+ };
+
+ gpio@d700 { /* GPIO 24 */
+ };
+
+ gpio@d800 { /* GPIO 25 */
+ };
+
+ gpio@d900 { /* GPIO 26 */
+ };
+
+ gpio@da00 { /* GPIO 27 */
+ };
+
+ gpio@db00 { /* GPIO 28 */
+ };
+
+ gpio@dc00 { /* GPIO 29 */
+ qcom,pull = <0>; /* set to default pull */
+ qcom,master-en = <1>;
+ qcom,vin-sel = <2>; /* select 1.8 V source */
+ };
+
+ gpio@dd00 { /* GPIO 30 */
+ };
+
+ gpio@de00 { /* GPIO 31 */
+ };
+
+ gpio@df00 { /* GPIO 32 */
+ };
+
+ gpio@e000 { /* GPIO 33 */
+ };
+
+ gpio@e100 { /* GPIO 34 */
+ };
+
+ gpio@e200 { /* GPIO 35 */
+ };
+
+ gpio@e300 { /* GPIO 36 */
+ };
+};
+
+&pm8941_mpps {
+
+ mpp@a000 { /* MPP 1 */
+ };
+
+ mpp@a100 { /* MPP 2 */
+ };
+
+ mpp@a200 { /* MPP 3 */
+ };
+
+ mpp@a300 { /* MPP 4 */
+ };
+
+ mpp@a400 { /* MPP 5 */
+ /* SPI_ETH config */
+ qcom,mode = <1>; /* DIG_OUT */
+ qcom,output-type = <0>; /* CMOS */
+ qcom,vin-sel = <2>; /* PM8941_S3 1.8V > 1.6V */
+ qcom,src-select = <0>; /* CONSTANT */
+ qcom,master-en = <1>; /* ENABLE MPP */
+ };
+
+ mpp@a500 { /* MPP 6 */
+ /* SPI_ETH_RST config */
+ qcom,mode = <1>; /* DIG_OUT */
+ qcom,output-type = <0>; /* CMOS */
+ qcom,vin-sel = <2>; /* PM8941_S3 1.8V > 1.6V */
+ qcom,src-select = <0>; /* CONSTANT */
+ qcom,master-en = <1>; /* ENABLE MPP */
+ };
+
+ mpp@a600 { /* MPP 7 */
+ };
+
+ mpp@a700 { /* MPP 8 */
+ };
+};
+
+&pm8841_mpps {
+
+ mpp@a000 { /* MPP 1 */
+ };
+
+ mpp@a100 { /* MPP 2 */
+ };
+
+ mpp@a200 { /* MPP 3 */
+ };
+
+ mpp@a300 { /* MPP 4 */
+ };
+};
diff --git a/arch/arm/boot/dts/msm8974-mdss.dtsi b/arch/arm/boot/dts/msm8974-mdss.dtsi
index 344aa7f..ee5836c 100644
--- a/arch/arm/boot/dts/msm8974-mdss.dtsi
+++ b/arch/arm/boot/dts/msm8974-mdss.dtsi
@@ -55,7 +55,7 @@
qcom,mdss_wb_panel {
compatible = "qcom,mdss_wb";
- qcom,mdss_pan_res = <640 480>;
+ qcom,mdss_pan_res = <1920 1080>;
qcom,mdss_pan_bpp = <24>;
};
};
diff --git a/arch/arm/boot/dts/msm8974-mtp.dts b/arch/arm/boot/dts/msm8974-mtp.dts
index ed89368..e183d04 100644
--- a/arch/arm/boot/dts/msm8974-mtp.dts
+++ b/arch/arm/boot/dts/msm8974-mtp.dts
@@ -167,3 +167,196 @@
interrupt-names = "core_irq", "bam_irq", "status_irq";
cd-gpios = <&msmgpio 62 0x1>;
};
+
+&pm8941_gpios {
+ gpio@c000 { /* GPIO 1 */
+ };
+
+ gpio@c100 { /* GPIO 2 */
+ };
+
+ gpio@c200 { /* GPIO 3 */
+ qcom,mode = <0>;
+ qcom,pull = <0>;
+ qcom,vin-sel = <2>;
+ qcom,select = <0>;
+ };
+
+ gpio@c300 { /* GPIO 4 */
+ qcom,mode = <0>;
+ qcom,pull = <0>;
+ qcom,vin-sel = <2>;
+ qcom,select = <0>;
+ };
+
+ gpio@c400 { /* GPIO 5 */
+ qcom,mode = <0>;
+ qcom,pull = <0>;
+ qcom,vin-sel = <2>;
+ qcom,select = <0>;
+ };
+
+ gpio@c500 { /* GPIO 6 */
+ };
+
+ gpio@c600 { /* GPIO 7 */
+ };
+
+ gpio@c700 { /* GPIO 8 */
+ };
+
+ gpio@c800 { /* GPIO 9 */
+ };
+
+ gpio@c900 { /* GPIO 10 */
+ };
+
+ gpio@ca00 { /* GPIO 11 */
+ };
+
+ gpio@cb00 { /* GPIO 12 */
+ };
+
+ gpio@cc00 { /* GPIO 13 */
+ };
+
+ gpio@cd00 { /* GPIO 14 */
+ };
+
+ gpio@ce00 { /* GPIO 15 */
+ qcom,mode = <1>;
+ qcom,output-type = <0>;
+ qcom,pull = <5>;
+ qcom,vin-sel = <2>;
+ qcom,out-strength = <3>;
+ qcom,src-select = <2>;
+ qcom,master-en = <1>;
+ };
+
+ gpio@cf00 { /* GPIO 16 */
+ };
+
+ gpio@d000 { /* GPIO 17 */
+ };
+
+ gpio@d100 { /* GPIO 18 */
+ };
+
+ gpio@d200 { /* GPIO 19 */
+ qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */
+ qcom,output-type = <0>; /* QPNP_PIN_OUT_BUF_CMOS */
+ qcom,pull = <5>; /* QPNP_PIN_PULL_NO */
+ qcom,vin-sel = <2>; /* QPNP_PIN_VIN2 */
+ qcom,out-strength = <2>; /* QPNP_PIN_OUT_STRENGTH_MED */
+ qcom,src-select = <0>; /* QPNP_PIN_SEL_FUNC_CONSTANT */
+ qcom,master-en = <1>;
+ };
+
+ gpio@d300 { /* GPIO 20 */
+ };
+
+ gpio@d400 { /* GPIO 21 */
+ };
+
+ gpio@d500 { /* GPIO 22 */
+ };
+
+ gpio@d600 { /* GPIO 23 */
+ };
+
+ gpio@d700 { /* GPIO 24 */
+ };
+
+ gpio@d800 { /* GPIO 25 */
+ };
+
+ gpio@d900 { /* GPIO 26 */
+ };
+
+ gpio@da00 { /* GPIO 27 */
+ };
+
+ gpio@db00 { /* GPIO 28 */
+ };
+
+ gpio@dc00 { /* GPIO 29 */
+ qcom,pull = <0>; /* set to default pull */
+ qcom,master-en = <1>;
+ qcom,vin-sel = <2>; /* select 1.8 V source */
+ };
+
+ gpio@dd00 { /* GPIO 30 */
+ };
+
+ gpio@de00 { /* GPIO 31 */
+ };
+
+ gpio@df00 { /* GPIO 32 */
+ };
+
+ gpio@e000 { /* GPIO 33 */
+ };
+
+ gpio@e100 { /* GPIO 34 */
+ };
+
+ gpio@e200 { /* GPIO 35 */
+ };
+
+ gpio@e300 { /* GPIO 36 */
+ };
+};
+
+&pm8941_mpps {
+
+ mpp@a000 { /* MPP 1 */
+ };
+
+ mpp@a100 { /* MPP 2 */
+ };
+
+ mpp@a200 { /* MPP 3 */
+ };
+
+ mpp@a300 { /* MPP 4 */
+ };
+
+ mpp@a400 { /* MPP 5 */
+ /* SPI_ETH config */
+ qcom,mode = <1>; /* DIG_OUT */
+ qcom,output-type = <0>; /* CMOS */
+ qcom,vin-sel = <2>; /* PM8941_S3 1.8V > 1.6V */
+ qcom,src-select = <0>; /* CONSTANT */
+ qcom,master-en = <1>; /* ENABLE MPP */
+ };
+
+ mpp@a500 { /* MPP 6 */
+ /* SPI_ETH_RST config */
+ qcom,mode = <1>; /* DIG_OUT */
+ qcom,output-type = <0>; /* CMOS */
+ qcom,vin-sel = <2>; /* PM8941_S3 1.8V > 1.6V */
+ qcom,src-select = <0>; /* CONSTANT */
+ qcom,master-en = <1>; /* ENABLE MPP */
+ };
+
+ mpp@a600 { /* MPP 7 */
+ };
+
+ mpp@a700 { /* MPP 8 */
+ };
+};
+
+&pm8841_mpps {
+
+ mpp@a000 { /* MPP 1 */
+ };
+
+ mpp@a100 { /* MPP 2 */
+ };
+
+ mpp@a200 { /* MPP 3 */
+ };
+
+ mpp@a300 { /* MPP 4 */
+ };
+};
diff --git a/arch/arm/boot/dts/msm8974.dtsi b/arch/arm/boot/dts/msm8974.dtsi
index c3c0d56..a00d37e 100644
--- a/arch/arm/boot/dts/msm8974.dtsi
+++ b/arch/arm/boot/dts/msm8974.dtsi
@@ -673,6 +673,10 @@
compatible = "qcom,msm-dai-fe";
};
+ qcom,msm-pcm-afe {
+ compatible = "qcom,msm-pcm-afe";
+ };
+
qcom,msm-dai-q6 {
compatible = "qcom,msm-dai-q6";
qcom,msm-dai-q6-sb-0-rx {
@@ -684,6 +688,36 @@
compatible = "qcom,msm-dai-q6-dev";
qcom,msm-dai-q6-dev-id = <16385>;
};
+
+ qcom,msm-dai-q6-bt-sco-rx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <12288>;
+ };
+
+ qcom,msm-dai-q6-bt-sco-tx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <12289>;
+ };
+
+ qcom,msm-dai-q6-be-afe-pcm-rx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <224>;
+ };
+
+ qcom,msm-dai-q6-be-afe-pcm-tx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <225>;
+ };
+
+ qcom,msm-dai-q6-afe-proxy-rx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <241>;
+ };
+
+ qcom,msm-dai-q6-afe-proxy-tx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <240>;
+ };
};
qcom,msm-auxpcm {
@@ -998,11 +1032,16 @@
reg = <0xfc834000 0x7000>;
interrupts = <0 29 1>;
};
+
+ qcom,msm-wdog-debug@fc401000 {
+ compatible = "qcom,msm-wdog-debug";
+ reg = <0xfc401000 0x1000>;
+ };
+
};
/include/ "msm-pm8x41-rpm-regulator.dtsi"
/include/ "msm-pm8841.dtsi"
/include/ "msm-pm8941.dtsi"
/include/ "msm8974-regulator.dtsi"
-/include/ "msm8974-gpio.dtsi"
/include/ "msm8974-clock.dtsi"
diff --git a/arch/arm/boot/dts/msm9625.dtsi b/arch/arm/boot/dts/msm9625.dtsi
index 767f385..7b0fc34 100644
--- a/arch/arm/boot/dts/msm9625.dtsi
+++ b/arch/arm/boot/dts/msm9625.dtsi
@@ -48,7 +48,7 @@
reg = <0xF9021000 0x1000>;
interrupts = <0 7 0>;
irq-is-not-percpu;
- clock-frequency = <5000000>;
+ clock-frequency = <19200000>;
};
qcom,sps@f9980000 {
diff --git a/arch/arm/configs/msm8974-perf_defconfig b/arch/arm/configs/msm8974-perf_defconfig
index b318c30..2f1833e 100644
--- a/arch/arm/configs/msm8974-perf_defconfig
+++ b/arch/arm/configs/msm8974-perf_defconfig
@@ -371,6 +371,7 @@
CONFIG_QPNP_CLKDIV=y
CONFIG_MSM_IOMMU=y
CONFIG_MSM_QDSS=y
+CONFIG_MSM_QDSS_ETM_PCSAVE_DEFAULT_ENABLE=y
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT3_FS=y
@@ -401,3 +402,4 @@
CONFIG_CRYPTO_DEV_QCE=m
CONFIG_CRYPTO_DEV_QCEDEV=m
CONFIG_CRC_CCITT=y
+CONFIG_MSM_ENABLE_WDOG_DEBUG_CONTROL=y
diff --git a/arch/arm/configs/msm8974_defconfig b/arch/arm/configs/msm8974_defconfig
index 914547f..d6e84f6 100644
--- a/arch/arm/configs/msm8974_defconfig
+++ b/arch/arm/configs/msm8974_defconfig
@@ -49,6 +49,7 @@
CONFIG_MSM_IPC_ROUTER_SMD_XPRT=y
# CONFIG_MSM_HW3D is not set
CONFIG_MSM_SUBSYSTEM_RESTART=y
+CONFIG_MSM_SYSMON_COMM=y
CONFIG_MSM_PIL_LPASS_QDSP6V5=y
CONFIG_MSM_PIL_MSS_QDSP6V5=y
CONFIG_MSM_PIL_MBA=y
@@ -72,7 +73,6 @@
CONFIG_MSM_L1_ERR_PANIC=y
CONFIG_MSM_L1_ERR_LOG=y
CONFIG_MSM_L2_ERP_PRINT_ACCESS_ERRORS=y
-CONFIG_MSM_L2_ERP_1BIT_PANIC=y
CONFIG_MSM_L2_ERP_2BIT_PANIC=y
CONFIG_MSM_CACHE_DUMP=y
CONFIG_MSM_CACHE_DUMP_ON_PANIC=y
@@ -376,6 +376,7 @@
CONFIG_QPNP_CLKDIV=y
CONFIG_MSM_IOMMU=y
CONFIG_MSM_QDSS=y
+CONFIG_MSM_QDSS_ETM_PCSAVE_DEFAULT_ENABLE=y
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT3_FS=y
@@ -421,3 +422,4 @@
CONFIG_CRYPTO_DEV_QCE=m
CONFIG_CRYPTO_DEV_QCEDEV=m
CONFIG_CRC_CCITT=y
+CONFIG_MSM_ENABLE_WDOG_DEBUG_CONTROL=y
diff --git a/arch/arm/configs/msm9625_defconfig b/arch/arm/configs/msm9625_defconfig
index d2e37e0..de93fa5 100644
--- a/arch/arm/configs/msm9625_defconfig
+++ b/arch/arm/configs/msm9625_defconfig
@@ -49,18 +49,18 @@
CONFIG_NEON=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
# CONFIG_SUSPEND is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_OF_PARTS=y
-CONFIG_MTD_BLOCK=y
-# CONFIG_MTD_MSM_NAND is not set
-CONFIG_MTD_MSM_QPIC_NAND=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IPV6=y
# CONFIG_WIRELESS is not set
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_OF_PARTS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_MTD_MSM_NAND is not set
+CONFIG_MTD_MSM_QPIC_NAND=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
# CONFIG_ANDROID_PMEM is not set
@@ -107,6 +107,7 @@
# CONFIG_RTC_DRV_MSM is not set
CONFIG_RTC_DRV_QPNP=y
CONFIG_SPS=y
+CONFIG_USB_BAM=y
CONFIG_SPS_SUPPORT_BAMDMA=y
CONFIG_SPS_SUPPORT_NDP_BAM=y
CONFIG_VFAT_FS=y
diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c
index ff2c0ad..1692129 100644
--- a/arch/arm/kernel/hw_breakpoint.c
+++ b/arch/arm/kernel/hw_breakpoint.c
@@ -216,6 +216,20 @@
return core_has_mismatch_brps() ? brps - 1 : brps;
}
+/* Determine if halting mode is enabled */
+static int halting_mode_enabled(void)
+{
+ u32 dscr;
+
+ ARM_DBG_READ(c1, 0, dscr);
+
+ if (WARN_ONCE(dscr & ARM_DSCR_HDBGEN,
+ "halting debug mode enabled. "
+ "Unable to access hardware resources.\n"))
+ return -EPERM;
+ return 0;
+}
+
/*
* In order to access the breakpoint/watchpoint control registers,
* we must be running in debug monitor mode. Unfortunately, we can
@@ -225,16 +239,14 @@
static int enable_monitor_mode(void)
{
u32 dscr;
- int ret = 0;
+ int ret;
ARM_DBG_READ(c1, 0, dscr);
/* Ensure that halting mode is disabled. */
- if (WARN_ONCE(dscr & ARM_DSCR_HDBGEN,
- "halting debug mode enabled. Unable to access hardware resources.\n")) {
- ret = -EPERM;
+ ret = halting_mode_enabled();
+ if (ret)
goto out;
- }
/* If monitor mode is already enabled, just return. */
if (dscr & ARM_DSCR_MDBGEN)
@@ -853,18 +865,6 @@
return ret;
}
-static void reset_brps_reserved_reg(int n)
-{
- int i;
-
- /* we must also reset any reserved registers. */
- for (i = 0; i < n; ++i) {
- write_wb_reg(ARM_BASE_BCR + i, 0UL);
- write_wb_reg(ARM_BASE_BVR + i, 0UL);
- }
-
-}
-
/*
* One-time initialisation.
*/
@@ -947,19 +947,21 @@
isb();
reset_regs:
- if (enable_monitor_mode())
+ if (halting_mode_enabled())
return;
-#ifdef CONFIG_HAVE_HW_BRKPT_RESERVED_RW_ACCESS
- reset_brps_reserved_reg(core_num_brps);
-#else
- reset_brps_reserved_reg(core_num_brps + core_num_reserved_brps);
-#endif
+ /* We must also reset any reserved registers. */
+ raw_num_brps = get_num_brp_resources();
+ for (i = 0; i < raw_num_brps; ++i) {
+ write_wb_reg(ARM_BASE_BCR + i, 0UL);
+ write_wb_reg(ARM_BASE_BVR + i, 0UL);
+ }
for (i = 0; i < core_num_wrps; ++i) {
write_wb_reg(ARM_BASE_WCR + i, 0UL);
write_wb_reg(ARM_BASE_WVR + i, 0UL);
}
+ enable_monitor_mode();
}
static int __cpuinit dbg_reset_notify(struct notifier_block *self,
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index 3f92a39..157f159 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -412,7 +412,6 @@
select HAVE_ARCH_HAS_CURRENT_TIMER
select MSM_JTAG if MSM_QDSS
bool
- select HAVE_HW_BRKPT_RESERVED_RW_ACCESS
config ARCH_MSM_CORTEXMP
select MSM_SMP
@@ -426,7 +425,6 @@
config ARCH_MSM_CORTEX_A5
bool
- select HAVE_HW_BRKPT_RESERVED_RW_ACCESS
config ARCH_MSM7X27A
bool
@@ -2645,4 +2643,12 @@
such as display backlight, vreg pin-ctrl, smps clock over the RPC
interface. This support is required for MSMs on which the APPS
does not have a direct access to the PMIC.
+
+config MSM_ENABLE_WDOG_DEBUG_CONTROL
+ bool "MSM Watchdog driver to disable debug Image"
+ help
+ This driver supports the configuration of the GCC_WDOG_DEBUG register
+ used to control debug image.
+ This support is currently required for MSM8974 to disable debug image
+ on PS HOLD reset
endif
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index 6504f4f..1b42d2d 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -275,7 +275,7 @@
obj-$(CONFIG_MACH_MSM8930_CDP) += board-8930-all.o board-8930-regulator-pm8038.o board-8930-regulator-pm8917.o
obj-$(CONFIG_MACH_MSM8930_MTP) += board-8930-all.o board-8930-regulator-pm8038.o board-8930-regulator-pm8917.o
obj-$(CONFIG_MACH_MSM8930_FLUID) += board-8930-all.o board-8930-regulator-pm8038.o board-8930-regulator-pm8917.o
-obj-$(CONFIG_PM8921_BMS) += bms-batterydata.o bms-batterydata-desay.o
+obj-$(CONFIG_PM8921_BMS) += bms-batterydata.o bms-batterydata-desay.o batterydata-lib.o
obj-$(CONFIG_MACH_APQ8064_CDP) += board-8064-all.o board-8064-regulator.o
obj-$(CONFIG_MACH_APQ8064_MTP) += board-8064-all.o board-8064-regulator.o
obj-$(CONFIG_MACH_APQ8064_LIQUID) += board-8064-all.o board-8064-regulator.o
@@ -384,6 +384,7 @@
obj-$(CONFIG_MSM_RPC_USB) += rpc_hsusb.o rpc_fsusb.o
obj-$(CONFIG_MSM_RPC_PMAPP) += rpc_pmapp.o
+obj-$(CONFIG_MSM_ENABLE_WDOG_DEBUG_CONTROL) += wdog_debug.o
ifdef CONFIG_MSM_CPR
obj-$(CONFIG_DEBUG_FS) += msm_cpr-debug.o
diff --git a/arch/arm/mach-msm/acpuclock-8064.c b/arch/arm/mach-msm/acpuclock-8064.c
index 06c2579..d0de62b 100644
--- a/arch/arm/mach-msm/acpuclock-8064.c
+++ b/arch/arm/mach-msm/acpuclock-8064.c
@@ -44,6 +44,7 @@
.hfpll_phys_base = 0x00903200,
.aux_clk_sel_phys = 0x02088014,
.aux_clk_sel = 3,
+ .sec_clk_sel = 2,
.l2cpmr_iaddr = 0x4501,
.vreg[VREG_CORE] = { "krait0", 1300000 },
.vreg[VREG_MEM] = { "krait0_mem", 1150000 },
@@ -54,6 +55,7 @@
.hfpll_phys_base = 0x00903240,
.aux_clk_sel_phys = 0x02098014,
.aux_clk_sel = 3,
+ .sec_clk_sel = 2,
.l2cpmr_iaddr = 0x5501,
.vreg[VREG_CORE] = { "krait1", 1300000 },
.vreg[VREG_MEM] = { "krait1_mem", 1150000 },
@@ -64,6 +66,7 @@
.hfpll_phys_base = 0x00903280,
.aux_clk_sel_phys = 0x020A8014,
.aux_clk_sel = 3,
+ .sec_clk_sel = 2,
.l2cpmr_iaddr = 0x6501,
.vreg[VREG_CORE] = { "krait2", 1300000 },
.vreg[VREG_MEM] = { "krait2_mem", 1150000 },
@@ -74,6 +77,7 @@
.hfpll_phys_base = 0x009032C0,
.aux_clk_sel_phys = 0x020B8014,
.aux_clk_sel = 3,
+ .sec_clk_sel = 2,
.l2cpmr_iaddr = 0x7501,
.vreg[VREG_CORE] = { "krait3", 1300000 },
.vreg[VREG_MEM] = { "krait3_mem", 1150000 },
@@ -84,6 +88,7 @@
.hfpll_phys_base = 0x00903300,
.aux_clk_sel_phys = 0x02011028,
.aux_clk_sel = 3,
+ .sec_clk_sel = 2,
.l2cpmr_iaddr = 0x0500,
.vreg[VREG_HFPLL_A] = { "l2_hfpll", 1800000 },
},
@@ -106,100 +111,100 @@
};
static struct l2_level l2_freq_tbl[] __initdata __initdata = {
- [0] = { { 384000, PLL_8, 0, 2, 0x00 }, 1050000, 1050000, 1 },
- [1] = { { 432000, HFPLL, 2, 0, 0x20 }, 1050000, 1050000, 2 },
- [2] = { { 486000, HFPLL, 2, 0, 0x24 }, 1050000, 1050000, 2 },
- [3] = { { 540000, HFPLL, 2, 0, 0x28 }, 1050000, 1050000, 2 },
- [4] = { { 594000, HFPLL, 1, 0, 0x16 }, 1050000, 1050000, 2 },
- [5] = { { 648000, HFPLL, 1, 0, 0x18 }, 1050000, 1050000, 4 },
- [6] = { { 702000, HFPLL, 1, 0, 0x1A }, 1050000, 1050000, 4 },
- [7] = { { 756000, HFPLL, 1, 0, 0x1C }, 1150000, 1150000, 4 },
- [8] = { { 810000, HFPLL, 1, 0, 0x1E }, 1150000, 1150000, 4 },
- [9] = { { 864000, HFPLL, 1, 0, 0x20 }, 1150000, 1150000, 4 },
- [10] = { { 918000, HFPLL, 1, 0, 0x22 }, 1150000, 1150000, 5 },
- [11] = { { 972000, HFPLL, 1, 0, 0x24 }, 1150000, 1150000, 5 },
- [12] = { { 1026000, HFPLL, 1, 0, 0x26 }, 1150000, 1150000, 5 },
- [13] = { { 1080000, HFPLL, 1, 0, 0x28 }, 1150000, 1150000, 5 },
- [14] = { { 1134000, HFPLL, 1, 0, 0x2A }, 1150000, 1150000, 5 },
- [15] = { { 1188000, HFPLL, 1, 0, 0x2C }, 1150000, 1150000, 5 },
+ [0] = { { 384000, PLL_8, 0, 0x00 }, 1050000, 1050000, 1 },
+ [1] = { { 432000, HFPLL, 2, 0x20 }, 1050000, 1050000, 2 },
+ [2] = { { 486000, HFPLL, 2, 0x24 }, 1050000, 1050000, 2 },
+ [3] = { { 540000, HFPLL, 2, 0x28 }, 1050000, 1050000, 2 },
+ [4] = { { 594000, HFPLL, 1, 0x16 }, 1050000, 1050000, 2 },
+ [5] = { { 648000, HFPLL, 1, 0x18 }, 1050000, 1050000, 4 },
+ [6] = { { 702000, HFPLL, 1, 0x1A }, 1050000, 1050000, 4 },
+ [7] = { { 756000, HFPLL, 1, 0x1C }, 1150000, 1150000, 4 },
+ [8] = { { 810000, HFPLL, 1, 0x1E }, 1150000, 1150000, 4 },
+ [9] = { { 864000, HFPLL, 1, 0x20 }, 1150000, 1150000, 4 },
+ [10] = { { 918000, HFPLL, 1, 0x22 }, 1150000, 1150000, 5 },
+ [11] = { { 972000, HFPLL, 1, 0x24 }, 1150000, 1150000, 5 },
+ [12] = { { 1026000, HFPLL, 1, 0x26 }, 1150000, 1150000, 5 },
+ [13] = { { 1080000, HFPLL, 1, 0x28 }, 1150000, 1150000, 5 },
+ [14] = { { 1134000, HFPLL, 1, 0x2A }, 1150000, 1150000, 5 },
+ [15] = { { 1188000, HFPLL, 1, 0x2C }, 1150000, 1150000, 5 },
{ }
};
static struct acpu_level acpu_freq_tbl_slow[] __initdata = {
- { 1, { 384000, PLL_8, 0, 2, 0x00 }, L2(0), 950000 },
- { 0, { 432000, HFPLL, 2, 0, 0x20 }, L2(6), 975000 },
- { 1, { 486000, HFPLL, 2, 0, 0x24 }, L2(6), 975000 },
- { 0, { 540000, HFPLL, 2, 0, 0x28 }, L2(6), 1000000 },
- { 1, { 594000, HFPLL, 1, 0, 0x16 }, L2(6), 1000000 },
- { 0, { 648000, HFPLL, 1, 0, 0x18 }, L2(6), 1025000 },
- { 1, { 702000, HFPLL, 1, 0, 0x1A }, L2(6), 1025000 },
- { 0, { 756000, HFPLL, 1, 0, 0x1C }, L2(6), 1075000 },
- { 1, { 810000, HFPLL, 1, 0, 0x1E }, L2(6), 1075000 },
- { 0, { 864000, HFPLL, 1, 0, 0x20 }, L2(6), 1100000 },
- { 1, { 918000, HFPLL, 1, 0, 0x22 }, L2(6), 1100000 },
- { 0, { 972000, HFPLL, 1, 0, 0x24 }, L2(6), 1125000 },
- { 1, { 1026000, HFPLL, 1, 0, 0x26 }, L2(6), 1125000 },
- { 0, { 1080000, HFPLL, 1, 0, 0x28 }, L2(15), 1175000 },
- { 1, { 1134000, HFPLL, 1, 0, 0x2A }, L2(15), 1175000 },
- { 0, { 1188000, HFPLL, 1, 0, 0x2C }, L2(15), 1200000 },
- { 1, { 1242000, HFPLL, 1, 0, 0x2E }, L2(15), 1200000 },
- { 0, { 1296000, HFPLL, 1, 0, 0x30 }, L2(15), 1225000 },
- { 1, { 1350000, HFPLL, 1, 0, 0x32 }, L2(15), 1225000 },
- { 0, { 1404000, HFPLL, 1, 0, 0x34 }, L2(15), 1237500 },
- { 1, { 1458000, HFPLL, 1, 0, 0x36 }, L2(15), 1237500 },
- { 1, { 1512000, HFPLL, 1, 0, 0x38 }, L2(15), 1250000 },
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 950000 },
+ { 0, { 432000, HFPLL, 2, 0x20 }, L2(6), 975000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(6), 975000 },
+ { 0, { 540000, HFPLL, 2, 0x28 }, L2(6), 1000000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(6), 1000000 },
+ { 0, { 648000, HFPLL, 1, 0x18 }, L2(6), 1025000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(6), 1025000 },
+ { 0, { 756000, HFPLL, 1, 0x1C }, L2(6), 1075000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(6), 1075000 },
+ { 0, { 864000, HFPLL, 1, 0x20 }, L2(6), 1100000 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(6), 1100000 },
+ { 0, { 972000, HFPLL, 1, 0x24 }, L2(6), 1125000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(6), 1125000 },
+ { 0, { 1080000, HFPLL, 1, 0x28 }, L2(15), 1175000 },
+ { 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1175000 },
+ { 0, { 1188000, HFPLL, 1, 0x2C }, L2(15), 1200000 },
+ { 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 1200000 },
+ { 0, { 1296000, HFPLL, 1, 0x30 }, L2(15), 1225000 },
+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1225000 },
+ { 0, { 1404000, HFPLL, 1, 0x34 }, L2(15), 1237500 },
+ { 1, { 1458000, HFPLL, 1, 0x36 }, L2(15), 1237500 },
+ { 1, { 1512000, HFPLL, 1, 0x38 }, L2(15), 1250000 },
{ 0, { 0 } }
};
static struct acpu_level acpu_freq_tbl_nom[] __initdata = {
- { 1, { 384000, PLL_8, 0, 2, 0x00 }, L2(0), 900000 },
- { 0, { 432000, HFPLL, 2, 0, 0x20 }, L2(6), 925000 },
- { 1, { 486000, HFPLL, 2, 0, 0x24 }, L2(6), 925000 },
- { 0, { 540000, HFPLL, 2, 0, 0x28 }, L2(6), 950000 },
- { 1, { 594000, HFPLL, 1, 0, 0x16 }, L2(6), 950000 },
- { 0, { 648000, HFPLL, 1, 0, 0x18 }, L2(6), 975000 },
- { 1, { 702000, HFPLL, 1, 0, 0x1A }, L2(6), 975000 },
- { 0, { 756000, HFPLL, 1, 0, 0x1C }, L2(6), 1025000 },
- { 1, { 810000, HFPLL, 1, 0, 0x1E }, L2(6), 1025000 },
- { 0, { 864000, HFPLL, 1, 0, 0x20 }, L2(6), 1050000 },
- { 1, { 918000, HFPLL, 1, 0, 0x22 }, L2(6), 1050000 },
- { 0, { 972000, HFPLL, 1, 0, 0x24 }, L2(6), 1075000 },
- { 1, { 1026000, HFPLL, 1, 0, 0x26 }, L2(6), 1075000 },
- { 0, { 1080000, HFPLL, 1, 0, 0x28 }, L2(15), 1125000 },
- { 1, { 1134000, HFPLL, 1, 0, 0x2A }, L2(15), 1125000 },
- { 0, { 1188000, HFPLL, 1, 0, 0x2C }, L2(15), 1150000 },
- { 1, { 1242000, HFPLL, 1, 0, 0x2E }, L2(15), 1150000 },
- { 0, { 1296000, HFPLL, 1, 0, 0x30 }, L2(15), 1175000 },
- { 1, { 1350000, HFPLL, 1, 0, 0x32 }, L2(15), 1175000 },
- { 0, { 1404000, HFPLL, 1, 0, 0x34 }, L2(15), 1187500 },
- { 1, { 1458000, HFPLL, 1, 0, 0x36 }, L2(15), 1187500 },
- { 1, { 1512000, HFPLL, 1, 0, 0x38 }, L2(15), 1200000 },
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 900000 },
+ { 0, { 432000, HFPLL, 2, 0x20 }, L2(6), 925000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(6), 925000 },
+ { 0, { 540000, HFPLL, 2, 0x28 }, L2(6), 950000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(6), 950000 },
+ { 0, { 648000, HFPLL, 1, 0x18 }, L2(6), 975000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(6), 975000 },
+ { 0, { 756000, HFPLL, 1, 0x1C }, L2(6), 1025000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(6), 1025000 },
+ { 0, { 864000, HFPLL, 1, 0x20 }, L2(6), 1050000 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(6), 1050000 },
+ { 0, { 972000, HFPLL, 1, 0x24 }, L2(6), 1075000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(6), 1075000 },
+ { 0, { 1080000, HFPLL, 1, 0x28 }, L2(15), 1125000 },
+ { 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1125000 },
+ { 0, { 1188000, HFPLL, 1, 0x2C }, L2(15), 1150000 },
+ { 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 1150000 },
+ { 0, { 1296000, HFPLL, 1, 0x30 }, L2(15), 1175000 },
+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1175000 },
+ { 0, { 1404000, HFPLL, 1, 0x34 }, L2(15), 1187500 },
+ { 1, { 1458000, HFPLL, 1, 0x36 }, L2(15), 1187500 },
+ { 1, { 1512000, HFPLL, 1, 0x38 }, L2(15), 1200000 },
{ 0, { 0 } }
};
static struct acpu_level acpu_freq_tbl_fast[] __initdata = {
- { 1, { 384000, PLL_8, 0, 2, 0x00 }, L2(0), 850000 },
- { 0, { 432000, HFPLL, 2, 0, 0x20 }, L2(6), 875000 },
- { 1, { 486000, HFPLL, 2, 0, 0x24 }, L2(6), 875000 },
- { 0, { 540000, HFPLL, 2, 0, 0x28 }, L2(6), 900000 },
- { 1, { 594000, HFPLL, 1, 0, 0x16 }, L2(6), 900000 },
- { 0, { 648000, HFPLL, 1, 0, 0x18 }, L2(6), 925000 },
- { 1, { 702000, HFPLL, 1, 0, 0x1A }, L2(6), 925000 },
- { 0, { 756000, HFPLL, 1, 0, 0x1C }, L2(6), 975000 },
- { 1, { 810000, HFPLL, 1, 0, 0x1E }, L2(6), 975000 },
- { 0, { 864000, HFPLL, 1, 0, 0x20 }, L2(6), 1000000 },
- { 1, { 918000, HFPLL, 1, 0, 0x22 }, L2(6), 1000000 },
- { 0, { 972000, HFPLL, 1, 0, 0x24 }, L2(6), 1025000 },
- { 1, { 1026000, HFPLL, 1, 0, 0x26 }, L2(6), 1025000 },
- { 0, { 1080000, HFPLL, 1, 0, 0x28 }, L2(15), 1075000 },
- { 1, { 1134000, HFPLL, 1, 0, 0x2A }, L2(15), 1075000 },
- { 0, { 1188000, HFPLL, 1, 0, 0x2C }, L2(15), 1100000 },
- { 1, { 1242000, HFPLL, 1, 0, 0x2E }, L2(15), 1100000 },
- { 0, { 1296000, HFPLL, 1, 0, 0x30 }, L2(15), 1125000 },
- { 1, { 1350000, HFPLL, 1, 0, 0x32 }, L2(15), 1125000 },
- { 0, { 1404000, HFPLL, 1, 0, 0x34 }, L2(15), 1137500 },
- { 1, { 1458000, HFPLL, 1, 0, 0x36 }, L2(15), 1137500 },
- { 1, { 1512000, HFPLL, 1, 0, 0x38 }, L2(15), 1150000 },
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 850000 },
+ { 0, { 432000, HFPLL, 2, 0x20 }, L2(6), 875000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(6), 875000 },
+ { 0, { 540000, HFPLL, 2, 0x28 }, L2(6), 900000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(6), 900000 },
+ { 0, { 648000, HFPLL, 1, 0x18 }, L2(6), 925000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(6), 925000 },
+ { 0, { 756000, HFPLL, 1, 0x1C }, L2(6), 975000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(6), 975000 },
+ { 0, { 864000, HFPLL, 1, 0x20 }, L2(6), 1000000 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(6), 1000000 },
+ { 0, { 972000, HFPLL, 1, 0x24 }, L2(6), 1025000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(6), 1025000 },
+ { 0, { 1080000, HFPLL, 1, 0x28 }, L2(15), 1075000 },
+ { 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1075000 },
+ { 0, { 1188000, HFPLL, 1, 0x2C }, L2(15), 1100000 },
+ { 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 1100000 },
+ { 0, { 1296000, HFPLL, 1, 0x30 }, L2(15), 1125000 },
+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1125000 },
+ { 0, { 1404000, HFPLL, 1, 0x34 }, L2(15), 1137500 },
+ { 1, { 1458000, HFPLL, 1, 0x36 }, L2(15), 1137500 },
+ { 1, { 1512000, HFPLL, 1, 0x38 }, L2(15), 1150000 },
{ 0, { 0 } }
};
diff --git a/arch/arm/mach-msm/acpuclock-8627.c b/arch/arm/mach-msm/acpuclock-8627.c
index 9e6662d..da49656 100644
--- a/arch/arm/mach-msm/acpuclock-8627.c
+++ b/arch/arm/mach-msm/acpuclock-8627.c
@@ -50,6 +50,7 @@
.hfpll_phys_base = 0x00903200,
.aux_clk_sel_phys = 0x02088014,
.aux_clk_sel = 3,
+ .sec_clk_sel = 2,
.l2cpmr_iaddr = 0x4501,
.vreg[VREG_CORE] = { "krait0", 1300000 },
.vreg[VREG_MEM] = { "krait0_mem", 1150000 },
@@ -60,6 +61,7 @@
.hfpll_phys_base = 0x00903300,
.aux_clk_sel_phys = 0x02098014,
.aux_clk_sel = 3,
+ .sec_clk_sel = 2,
.l2cpmr_iaddr = 0x5501,
.vreg[VREG_CORE] = { "krait1", 1300000 },
.vreg[VREG_MEM] = { "krait1_mem", 1150000 },
@@ -70,6 +72,7 @@
.hfpll_phys_base = 0x00903400,
.aux_clk_sel_phys = 0x02011028,
.aux_clk_sel = 3,
+ .sec_clk_sel = 2,
.l2cpmr_iaddr = 0x0500,
.vreg[VREG_HFPLL_A] = { "l2_hfpll", 1800000 },
},
@@ -92,35 +95,35 @@
/* TODO: Update vdd_dig, vdd_mem and bw when data is available. */
static struct l2_level l2_freq_tbl[] __initdata = {
- [0] = { { 384000, PLL_8, 0, 2, 0x00 }, LVL_NOM, 1050000, 1 },
- [1] = { { 432000, HFPLL, 2, 0, 0x20 }, LVL_NOM, 1050000, 1 },
- [2] = { { 486000, HFPLL, 2, 0, 0x24 }, LVL_NOM, 1050000, 1 },
- [3] = { { 540000, HFPLL, 2, 0, 0x28 }, LVL_NOM, 1050000, 2 },
- [4] = { { 594000, HFPLL, 1, 0, 0x16 }, LVL_NOM, 1050000, 2 },
- [5] = { { 648000, HFPLL, 1, 0, 0x18 }, LVL_NOM, 1050000, 2 },
- [6] = { { 702000, HFPLL, 1, 0, 0x1A }, LVL_NOM, 1050000, 3 },
- [7] = { { 756000, HFPLL, 1, 0, 0x1C }, LVL_HIGH, 1150000, 3 },
- [8] = { { 810000, HFPLL, 1, 0, 0x1E }, LVL_HIGH, 1150000, 3 },
- [9] = { { 864000, HFPLL, 1, 0, 0x20 }, LVL_HIGH, 1150000, 4 },
- [10] = { { 918000, HFPLL, 1, 0, 0x22 }, LVL_HIGH, 1150000, 4 },
- [11] = { { 972000, HFPLL, 1, 0, 0x24 }, LVL_HIGH, 1150000, 4 },
+ [0] = { { 384000, PLL_8, 0, 0x00 }, LVL_NOM, 1050000, 1 },
+ [1] = { { 432000, HFPLL, 2, 0x20 }, LVL_NOM, 1050000, 1 },
+ [2] = { { 486000, HFPLL, 2, 0x24 }, LVL_NOM, 1050000, 1 },
+ [3] = { { 540000, HFPLL, 2, 0x28 }, LVL_NOM, 1050000, 2 },
+ [4] = { { 594000, HFPLL, 1, 0x16 }, LVL_NOM, 1050000, 2 },
+ [5] = { { 648000, HFPLL, 1, 0x18 }, LVL_NOM, 1050000, 2 },
+ [6] = { { 702000, HFPLL, 1, 0x1A }, LVL_NOM, 1050000, 3 },
+ [7] = { { 756000, HFPLL, 1, 0x1C }, LVL_HIGH, 1150000, 3 },
+ [8] = { { 810000, HFPLL, 1, 0x1E }, LVL_HIGH, 1150000, 3 },
+ [9] = { { 864000, HFPLL, 1, 0x20 }, LVL_HIGH, 1150000, 4 },
+ [10] = { { 918000, HFPLL, 1, 0x22 }, LVL_HIGH, 1150000, 4 },
+ [11] = { { 972000, HFPLL, 1, 0x24 }, LVL_HIGH, 1150000, 4 },
{ }
};
/* TODO: Update core voltages when data is available. */
static struct acpu_level acpu_freq_tbl[] __initdata = {
- { 1, { 384000, PLL_8, 0, 2, 0x00 }, L2(0), 900000 },
- { 1, { 432000, HFPLL, 2, 0, 0x20 }, L2(4), 925000 },
- { 1, { 486000, HFPLL, 2, 0, 0x24 }, L2(4), 925000 },
- { 1, { 540000, HFPLL, 2, 0, 0x28 }, L2(4), 937500 },
- { 1, { 594000, HFPLL, 1, 0, 0x16 }, L2(4), 962500 },
- { 1, { 648000, HFPLL, 1, 0, 0x18 }, L2(8), 987500 },
- { 1, { 702000, HFPLL, 1, 0, 0x1A }, L2(8), 1000000 },
- { 1, { 756000, HFPLL, 1, 0, 0x1C }, L2(8), 1025000 },
- { 1, { 810000, HFPLL, 1, 0, 0x1E }, L2(8), 1062500 },
- { 1, { 864000, HFPLL, 1, 0, 0x20 }, L2(11), 1062500 },
- { 1, { 918000, HFPLL, 1, 0, 0x22 }, L2(11), 1087500 },
- { 1, { 972000, HFPLL, 1, 0, 0x24 }, L2(11), 1100000 },
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 900000 },
+ { 1, { 432000, HFPLL, 2, 0x20 }, L2(4), 925000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(4), 925000 },
+ { 1, { 540000, HFPLL, 2, 0x28 }, L2(4), 937500 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(4), 962500 },
+ { 1, { 648000, HFPLL, 1, 0x18 }, L2(8), 987500 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(8), 1000000 },
+ { 1, { 756000, HFPLL, 1, 0x1C }, L2(8), 1025000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(8), 1062500 },
+ { 1, { 864000, HFPLL, 1, 0x20 }, L2(11), 1062500 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(11), 1087500 },
+ { 1, { 972000, HFPLL, 1, 0x24 }, L2(11), 1100000 },
{ 0, { 0 } }
};
diff --git a/arch/arm/mach-msm/acpuclock-8930.c b/arch/arm/mach-msm/acpuclock-8930.c
index b8ca865..b4f2a1e 100644
--- a/arch/arm/mach-msm/acpuclock-8930.c
+++ b/arch/arm/mach-msm/acpuclock-8930.c
@@ -50,6 +50,7 @@
.hfpll_phys_base = 0x00903200,
.aux_clk_sel_phys = 0x02088014,
.aux_clk_sel = 3,
+ .sec_clk_sel = 2,
.l2cpmr_iaddr = 0x4501,
.vreg[VREG_CORE] = { "krait0", 1300000 },
.vreg[VREG_MEM] = { "krait0_mem", 1150000 },
@@ -61,6 +62,7 @@
.hfpll_phys_base = 0x00903300,
.aux_clk_sel_phys = 0x02098014,
.aux_clk_sel = 3,
+ .sec_clk_sel = 2,
.l2cpmr_iaddr = 0x5501,
.vreg[VREG_CORE] = { "krait1", 1300000 },
.vreg[VREG_MEM] = { "krait1_mem", 1150000 },
@@ -72,6 +74,7 @@
.hfpll_phys_base = 0x00903400,
.aux_clk_sel_phys = 0x02011028,
.aux_clk_sel = 3,
+ .sec_clk_sel = 2,
.l2cpmr_iaddr = 0x0500,
.vreg[VREG_HFPLL_A] = { "l2_s8", 2050000 },
.vreg[VREG_HFPLL_B] = { "l2_l23", 1800000 },
@@ -83,6 +86,7 @@
.hfpll_phys_base = 0x00903200,
.aux_clk_sel_phys = 0x02088014,
.aux_clk_sel = 3,
+ .sec_clk_sel = 2,
.l2cpmr_iaddr = 0x4501,
.vreg[VREG_CORE] = { "krait0", 1300000 },
.vreg[VREG_MEM] = { "krait0_mem", 1150000 },
@@ -93,6 +97,7 @@
.hfpll_phys_base = 0x00903300,
.aux_clk_sel_phys = 0x02098014,
.aux_clk_sel = 3,
+ .sec_clk_sel = 2,
.l2cpmr_iaddr = 0x5501,
.vreg[VREG_CORE] = { "krait1", 1300000 },
.vreg[VREG_MEM] = { "krait1_mem", 1150000 },
@@ -103,6 +108,7 @@
.hfpll_phys_base = 0x00903400,
.aux_clk_sel_phys = 0x02011028,
.aux_clk_sel = 3,
+ .sec_clk_sel = 2,
.l2cpmr_iaddr = 0x0500,
.vreg[VREG_HFPLL_A] = { "l2_hfpll", 1800000 },
},
@@ -128,82 +134,82 @@
/* TODO: Update vdd_dig, vdd_mem and bw when data is available. */
static struct l2_level l2_freq_tbl[] __initdata = {
- [0] = { { 384000, PLL_8, 0, 2, 0x00 }, LVL_NOM, 1050000, 1 },
- [1] = { { 432000, HFPLL, 2, 0, 0x20 }, LVL_NOM, 1050000, 2 },
- [2] = { { 486000, HFPLL, 2, 0, 0x24 }, LVL_NOM, 1050000, 2 },
- [3] = { { 540000, HFPLL, 2, 0, 0x28 }, LVL_NOM, 1050000, 2 },
- [4] = { { 594000, HFPLL, 1, 0, 0x16 }, LVL_NOM, 1050000, 2 },
- [5] = { { 648000, HFPLL, 1, 0, 0x18 }, LVL_NOM, 1050000, 4 },
- [6] = { { 702000, HFPLL, 1, 0, 0x1A }, LVL_NOM, 1050000, 4 },
- [7] = { { 756000, HFPLL, 1, 0, 0x1C }, LVL_HIGH, 1150000, 4 },
- [8] = { { 810000, HFPLL, 1, 0, 0x1E }, LVL_HIGH, 1150000, 4 },
- [9] = { { 864000, HFPLL, 1, 0, 0x20 }, LVL_HIGH, 1150000, 4 },
- [10] = { { 918000, HFPLL, 1, 0, 0x22 }, LVL_HIGH, 1150000, 7 },
- [11] = { { 972000, HFPLL, 1, 0, 0x24 }, LVL_HIGH, 1150000, 7 },
- [12] = { { 1026000, HFPLL, 1, 0, 0x26 }, LVL_HIGH, 1150000, 7 },
- [13] = { { 1080000, HFPLL, 1, 0, 0x28 }, LVL_HIGH, 1150000, 7 },
- [14] = { { 1134000, HFPLL, 1, 0, 0x2A }, LVL_HIGH, 1150000, 7 },
- [15] = { { 1188000, HFPLL, 1, 0, 0x2C }, LVL_HIGH, 1150000, 7 },
+ [0] = { { 384000, PLL_8, 0, 0x00 }, LVL_NOM, 1050000, 1 },
+ [1] = { { 432000, HFPLL, 2, 0x20 }, LVL_NOM, 1050000, 2 },
+ [2] = { { 486000, HFPLL, 2, 0x24 }, LVL_NOM, 1050000, 2 },
+ [3] = { { 540000, HFPLL, 2, 0x28 }, LVL_NOM, 1050000, 2 },
+ [4] = { { 594000, HFPLL, 1, 0x16 }, LVL_NOM, 1050000, 2 },
+ [5] = { { 648000, HFPLL, 1, 0x18 }, LVL_NOM, 1050000, 4 },
+ [6] = { { 702000, HFPLL, 1, 0x1A }, LVL_NOM, 1050000, 4 },
+ [7] = { { 756000, HFPLL, 1, 0x1C }, LVL_HIGH, 1150000, 4 },
+ [8] = { { 810000, HFPLL, 1, 0x1E }, LVL_HIGH, 1150000, 4 },
+ [9] = { { 864000, HFPLL, 1, 0x20 }, LVL_HIGH, 1150000, 4 },
+ [10] = { { 918000, HFPLL, 1, 0x22 }, LVL_HIGH, 1150000, 7 },
+ [11] = { { 972000, HFPLL, 1, 0x24 }, LVL_HIGH, 1150000, 7 },
+ [12] = { { 1026000, HFPLL, 1, 0x26 }, LVL_HIGH, 1150000, 7 },
+ [13] = { { 1080000, HFPLL, 1, 0x28 }, LVL_HIGH, 1150000, 7 },
+ [14] = { { 1134000, HFPLL, 1, 0x2A }, LVL_HIGH, 1150000, 7 },
+ [15] = { { 1188000, HFPLL, 1, 0x2C }, LVL_HIGH, 1150000, 7 },
{ }
};
static struct acpu_level acpu_freq_tbl_slow[] __initdata = {
- { 1, { 384000, PLL_8, 0, 2, 0x00 }, L2(0), 950000 },
- { 1, { 432000, HFPLL, 2, 0, 0x20 }, L2(5), 975000 },
- { 1, { 486000, HFPLL, 2, 0, 0x24 }, L2(5), 975000 },
- { 1, { 540000, HFPLL, 2, 0, 0x28 }, L2(5), 1000000 },
- { 1, { 594000, HFPLL, 1, 0, 0x16 }, L2(5), 1000000 },
- { 1, { 648000, HFPLL, 1, 0, 0x18 }, L2(5), 1025000 },
- { 1, { 702000, HFPLL, 1, 0, 0x1A }, L2(5), 1025000 },
- { 1, { 756000, HFPLL, 1, 0, 0x1C }, L2(10), 1075000 },
- { 1, { 810000, HFPLL, 1, 0, 0x1E }, L2(10), 1075000 },
- { 1, { 864000, HFPLL, 1, 0, 0x20 }, L2(10), 1100000 },
- { 1, { 918000, HFPLL, 1, 0, 0x22 }, L2(10), 1100000 },
- { 1, { 972000, HFPLL, 1, 0, 0x24 }, L2(10), 1125000 },
- { 1, { 1026000, HFPLL, 1, 0, 0x26 }, L2(10), 1125000 },
- { 1, { 1080000, HFPLL, 1, 0, 0x28 }, L2(15), 1175000 },
- { 1, { 1134000, HFPLL, 1, 0, 0x2A }, L2(15), 1175000 },
- { 1, { 1188000, HFPLL, 1, 0, 0x2C }, L2(15), 1200000 },
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 950000 },
+ { 1, { 432000, HFPLL, 2, 0x20 }, L2(5), 975000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 975000 },
+ { 1, { 540000, HFPLL, 2, 0x28 }, L2(5), 1000000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 1000000 },
+ { 1, { 648000, HFPLL, 1, 0x18 }, L2(5), 1025000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 1025000 },
+ { 1, { 756000, HFPLL, 1, 0x1C }, L2(10), 1075000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(10), 1075000 },
+ { 1, { 864000, HFPLL, 1, 0x20 }, L2(10), 1100000 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(10), 1100000 },
+ { 1, { 972000, HFPLL, 1, 0x24 }, L2(10), 1125000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(10), 1125000 },
+ { 1, { 1080000, HFPLL, 1, 0x28 }, L2(15), 1175000 },
+ { 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1175000 },
+ { 1, { 1188000, HFPLL, 1, 0x2C }, L2(15), 1200000 },
{ 0, { 0 } }
};
static struct acpu_level acpu_freq_tbl_nom[] __initdata = {
- { 1, { 384000, PLL_8, 0, 2, 0x00 }, L2(0), 925000 },
- { 1, { 432000, HFPLL, 2, 0, 0x20 }, L2(5), 950000 },
- { 1, { 486000, HFPLL, 2, 0, 0x24 }, L2(5), 950000 },
- { 1, { 540000, HFPLL, 2, 0, 0x28 }, L2(5), 975000 },
- { 1, { 594000, HFPLL, 1, 0, 0x16 }, L2(5), 975000 },
- { 1, { 648000, HFPLL, 1, 0, 0x18 }, L2(5), 1000000 },
- { 1, { 702000, HFPLL, 1, 0, 0x1A }, L2(5), 1000000 },
- { 1, { 756000, HFPLL, 1, 0, 0x1C }, L2(10), 1050000 },
- { 1, { 810000, HFPLL, 1, 0, 0x1E }, L2(10), 1050000 },
- { 1, { 864000, HFPLL, 1, 0, 0x20 }, L2(10), 1075000 },
- { 1, { 918000, HFPLL, 1, 0, 0x22 }, L2(10), 1075000 },
- { 1, { 972000, HFPLL, 1, 0, 0x24 }, L2(10), 1100000 },
- { 1, { 1026000, HFPLL, 1, 0, 0x26 }, L2(10), 1100000 },
- { 1, { 1080000, HFPLL, 1, 0, 0x28 }, L2(15), 1150000 },
- { 1, { 1134000, HFPLL, 1, 0, 0x2A }, L2(15), 1150000 },
- { 1, { 1188000, HFPLL, 1, 0, 0x2C }, L2(15), 1175000 },
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 925000 },
+ { 1, { 432000, HFPLL, 2, 0x20 }, L2(5), 950000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 950000 },
+ { 1, { 540000, HFPLL, 2, 0x28 }, L2(5), 975000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 975000 },
+ { 1, { 648000, HFPLL, 1, 0x18 }, L2(5), 1000000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 1000000 },
+ { 1, { 756000, HFPLL, 1, 0x1C }, L2(10), 1050000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(10), 1050000 },
+ { 1, { 864000, HFPLL, 1, 0x20 }, L2(10), 1075000 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(10), 1075000 },
+ { 1, { 972000, HFPLL, 1, 0x24 }, L2(10), 1100000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(10), 1100000 },
+ { 1, { 1080000, HFPLL, 1, 0x28 }, L2(15), 1150000 },
+ { 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1150000 },
+ { 1, { 1188000, HFPLL, 1, 0x2C }, L2(15), 1175000 },
{ 0, { 0 } }
};
static struct acpu_level acpu_freq_tbl_fast[] __initdata = {
- { 1, { 384000, PLL_8, 0, 2, 0x00 }, L2(0), 900000 },
- { 1, { 432000, HFPLL, 2, 0, 0x20 }, L2(5), 900000 },
- { 1, { 486000, HFPLL, 2, 0, 0x24 }, L2(5), 900000 },
- { 1, { 540000, HFPLL, 2, 0, 0x28 }, L2(5), 925000 },
- { 1, { 594000, HFPLL, 1, 0, 0x16 }, L2(5), 925000 },
- { 1, { 648000, HFPLL, 1, 0, 0x18 }, L2(5), 950000 },
- { 1, { 702000, HFPLL, 1, 0, 0x1A }, L2(5), 950000 },
- { 1, { 756000, HFPLL, 1, 0, 0x1C }, L2(10), 1000000 },
- { 1, { 810000, HFPLL, 1, 0, 0x1E }, L2(10), 1000000 },
- { 1, { 864000, HFPLL, 1, 0, 0x20 }, L2(10), 1025000 },
- { 1, { 918000, HFPLL, 1, 0, 0x22 }, L2(10), 1025000 },
- { 1, { 972000, HFPLL, 1, 0, 0x24 }, L2(10), 1050000 },
- { 1, { 1026000, HFPLL, 1, 0, 0x26 }, L2(10), 1050000 },
- { 1, { 1080000, HFPLL, 1, 0, 0x28 }, L2(15), 1100000 },
- { 1, { 1134000, HFPLL, 1, 0, 0x2A }, L2(15), 1100000 },
- { 1, { 1188000, HFPLL, 1, 0, 0x2C }, L2(15), 1125000 },
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 900000 },
+ { 1, { 432000, HFPLL, 2, 0x20 }, L2(5), 900000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 900000 },
+ { 1, { 540000, HFPLL, 2, 0x28 }, L2(5), 925000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 925000 },
+ { 1, { 648000, HFPLL, 1, 0x18 }, L2(5), 950000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 950000 },
+ { 1, { 756000, HFPLL, 1, 0x1C }, L2(10), 1000000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(10), 1000000 },
+ { 1, { 864000, HFPLL, 1, 0x20 }, L2(10), 1025000 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(10), 1025000 },
+ { 1, { 972000, HFPLL, 1, 0x24 }, L2(10), 1050000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(10), 1050000 },
+ { 1, { 1080000, HFPLL, 1, 0x28 }, L2(15), 1100000 },
+ { 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1100000 },
+ { 1, { 1188000, HFPLL, 1, 0x2C }, L2(15), 1125000 },
{ 0, { 0 } }
};
diff --git a/arch/arm/mach-msm/acpuclock-8930aa.c b/arch/arm/mach-msm/acpuclock-8930aa.c
index d589f1a..bcb00ea 100644
--- a/arch/arm/mach-msm/acpuclock-8930aa.c
+++ b/arch/arm/mach-msm/acpuclock-8930aa.c
@@ -50,6 +50,7 @@
.hfpll_phys_base = 0x00903200,
.aux_clk_sel_phys = 0x02088014,
.aux_clk_sel = 3,
+ .sec_clk_sel = 2,
.l2cpmr_iaddr = 0x4501,
.vreg[VREG_CORE] = { "krait0", 1300000 },
.vreg[VREG_MEM] = { "krait0_mem", 1150000 },
@@ -60,6 +61,7 @@
.hfpll_phys_base = 0x00903300,
.aux_clk_sel_phys = 0x02098014,
.aux_clk_sel = 3,
+ .sec_clk_sel = 2,
.l2cpmr_iaddr = 0x5501,
.vreg[VREG_CORE] = { "krait1", 1300000 },
.vreg[VREG_MEM] = { "krait1_mem", 1150000 },
@@ -70,6 +72,7 @@
.hfpll_phys_base = 0x00903400,
.aux_clk_sel_phys = 0x02011028,
.aux_clk_sel = 3,
+ .sec_clk_sel = 2,
.l2cpmr_iaddr = 0x0500,
.vreg[VREG_HFPLL_A] = { "l2_hfpll", 1800000 },
},
@@ -95,94 +98,94 @@
/* TODO: Update vdd_dig, vdd_mem and bw when data is available. */
static struct l2_level l2_freq_tbl[] __initdata = {
- [0] = { { 384000, PLL_8, 0, 2, 0x00 }, LVL_NOM, 1050000, 1 },
- [1] = { { 432000, HFPLL, 2, 0, 0x20 }, LVL_NOM, 1050000, 2 },
- [2] = { { 486000, HFPLL, 2, 0, 0x24 }, LVL_NOM, 1050000, 2 },
- [3] = { { 540000, HFPLL, 2, 0, 0x28 }, LVL_NOM, 1050000, 2 },
- [4] = { { 594000, HFPLL, 1, 0, 0x16 }, LVL_NOM, 1050000, 2 },
- [5] = { { 648000, HFPLL, 1, 0, 0x18 }, LVL_NOM, 1050000, 4 },
- [6] = { { 702000, HFPLL, 1, 0, 0x1A }, LVL_NOM, 1050000, 4 },
- [7] = { { 756000, HFPLL, 1, 0, 0x1C }, LVL_HIGH, 1150000, 4 },
- [8] = { { 810000, HFPLL, 1, 0, 0x1E }, LVL_HIGH, 1150000, 4 },
- [9] = { { 864000, HFPLL, 1, 0, 0x20 }, LVL_HIGH, 1150000, 4 },
- [10] = { { 918000, HFPLL, 1, 0, 0x22 }, LVL_HIGH, 1150000, 7 },
- [11] = { { 972000, HFPLL, 1, 0, 0x24 }, LVL_HIGH, 1150000, 7 },
- [12] = { { 1026000, HFPLL, 1, 0, 0x26 }, LVL_HIGH, 1150000, 7 },
- [13] = { { 1080000, HFPLL, 1, 0, 0x28 }, LVL_HIGH, 1150000, 7 },
- [14] = { { 1134000, HFPLL, 1, 0, 0x2A }, LVL_HIGH, 1150000, 7 },
- [15] = { { 1188000, HFPLL, 1, 0, 0x2C }, LVL_HIGH, 1150000, 7 },
+ [0] = { { 384000, PLL_8, 0, 0x00 }, LVL_NOM, 1050000, 1 },
+ [1] = { { 432000, HFPLL, 2, 0x20 }, LVL_NOM, 1050000, 2 },
+ [2] = { { 486000, HFPLL, 2, 0x24 }, LVL_NOM, 1050000, 2 },
+ [3] = { { 540000, HFPLL, 2, 0x28 }, LVL_NOM, 1050000, 2 },
+ [4] = { { 594000, HFPLL, 1, 0x16 }, LVL_NOM, 1050000, 2 },
+ [5] = { { 648000, HFPLL, 1, 0x18 }, LVL_NOM, 1050000, 4 },
+ [6] = { { 702000, HFPLL, 1, 0x1A }, LVL_NOM, 1050000, 4 },
+ [7] = { { 756000, HFPLL, 1, 0x1C }, LVL_HIGH, 1150000, 4 },
+ [8] = { { 810000, HFPLL, 1, 0x1E }, LVL_HIGH, 1150000, 4 },
+ [9] = { { 864000, HFPLL, 1, 0x20 }, LVL_HIGH, 1150000, 4 },
+ [10] = { { 918000, HFPLL, 1, 0x22 }, LVL_HIGH, 1150000, 7 },
+ [11] = { { 972000, HFPLL, 1, 0x24 }, LVL_HIGH, 1150000, 7 },
+ [12] = { { 1026000, HFPLL, 1, 0x26 }, LVL_HIGH, 1150000, 7 },
+ [13] = { { 1080000, HFPLL, 1, 0x28 }, LVL_HIGH, 1150000, 7 },
+ [14] = { { 1134000, HFPLL, 1, 0x2A }, LVL_HIGH, 1150000, 7 },
+ [15] = { { 1188000, HFPLL, 1, 0x2C }, LVL_HIGH, 1150000, 7 },
{ }
};
static struct acpu_level acpu_freq_tbl_slow[] __initdata = {
- { 1, { 384000, PLL_8, 0, 2, 0x00 }, L2(0), 950000 },
- { 1, { 432000, HFPLL, 2, 0, 0x20 }, L2(5), 975000 },
- { 1, { 486000, HFPLL, 2, 0, 0x24 }, L2(5), 975000 },
- { 1, { 540000, HFPLL, 2, 0, 0x28 }, L2(5), 1000000 },
- { 1, { 594000, HFPLL, 1, 0, 0x16 }, L2(5), 1000000 },
- { 1, { 648000, HFPLL, 1, 0, 0x18 }, L2(5), 1025000 },
- { 1, { 702000, HFPLL, 1, 0, 0x1A }, L2(5), 1025000 },
- { 1, { 756000, HFPLL, 1, 0, 0x1C }, L2(10), 1075000 },
- { 1, { 810000, HFPLL, 1, 0, 0x1E }, L2(10), 1075000 },
- { 1, { 864000, HFPLL, 1, 0, 0x20 }, L2(10), 1100000 },
- { 1, { 918000, HFPLL, 1, 0, 0x22 }, L2(10), 1100000 },
- { 1, { 972000, HFPLL, 1, 0, 0x24 }, L2(10), 1125000 },
- { 1, { 1026000, HFPLL, 1, 0, 0x26 }, L2(10), 1125000 },
- { 1, { 1080000, HFPLL, 1, 0, 0x28 }, L2(15), 1175000 },
- { 1, { 1134000, HFPLL, 1, 0, 0x2A }, L2(15), 1175000 },
- { 1, { 1188000, HFPLL, 1, 0, 0x2C }, L2(15), 1200000 },
- { 1, { 1242000, HFPLL, 1, 0, 0x2E }, L2(15), 1200000 },
- { 1, { 1296000, HFPLL, 1, 0, 0x30 }, L2(15), 1225000 },
- { 1, { 1350000, HFPLL, 1, 0, 0x32 }, L2(15), 1225000 },
- { 1, { 1404000, HFPLL, 1, 0, 0x34 }, L2(15), 1237500 },
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 950000 },
+ { 1, { 432000, HFPLL, 2, 0x20 }, L2(5), 975000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 975000 },
+ { 1, { 540000, HFPLL, 2, 0x28 }, L2(5), 1000000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 1000000 },
+ { 1, { 648000, HFPLL, 1, 0x18 }, L2(5), 1025000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 1025000 },
+ { 1, { 756000, HFPLL, 1, 0x1C }, L2(10), 1075000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(10), 1075000 },
+ { 1, { 864000, HFPLL, 1, 0x20 }, L2(10), 1100000 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(10), 1100000 },
+ { 1, { 972000, HFPLL, 1, 0x24 }, L2(10), 1125000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(10), 1125000 },
+ { 1, { 1080000, HFPLL, 1, 0x28 }, L2(15), 1175000 },
+ { 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1175000 },
+ { 1, { 1188000, HFPLL, 1, 0x2C }, L2(15), 1200000 },
+ { 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 1200000 },
+ { 1, { 1296000, HFPLL, 1, 0x30 }, L2(15), 1225000 },
+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1225000 },
+ { 1, { 1404000, HFPLL, 1, 0x34 }, L2(15), 1237500 },
{ 0, { 0 } }
};
static struct acpu_level acpu_freq_tbl_nom[] __initdata = {
- { 1, { 384000, PLL_8, 0, 2, 0x00 }, L2(0), 925000 },
- { 1, { 432000, HFPLL, 2, 0, 0x20 }, L2(5), 950000 },
- { 1, { 486000, HFPLL, 2, 0, 0x24 }, L2(5), 950000 },
- { 1, { 540000, HFPLL, 2, 0, 0x28 }, L2(5), 975000 },
- { 1, { 594000, HFPLL, 1, 0, 0x16 }, L2(5), 975000 },
- { 1, { 648000, HFPLL, 1, 0, 0x18 }, L2(5), 1000000 },
- { 1, { 702000, HFPLL, 1, 0, 0x1A }, L2(5), 1000000 },
- { 1, { 756000, HFPLL, 1, 0, 0x1C }, L2(10), 1050000 },
- { 1, { 810000, HFPLL, 1, 0, 0x1E }, L2(10), 1050000 },
- { 1, { 864000, HFPLL, 1, 0, 0x20 }, L2(10), 1075000 },
- { 1, { 918000, HFPLL, 1, 0, 0x22 }, L2(10), 1075000 },
- { 1, { 972000, HFPLL, 1, 0, 0x24 }, L2(10), 1100000 },
- { 1, { 1026000, HFPLL, 1, 0, 0x26 }, L2(10), 1100000 },
- { 1, { 1080000, HFPLL, 1, 0, 0x28 }, L2(15), 1150000 },
- { 1, { 1134000, HFPLL, 1, 0, 0x2A }, L2(15), 1150000 },
- { 1, { 1188000, HFPLL, 1, 0, 0x2C }, L2(15), 1175000 },
- { 1, { 1242000, HFPLL, 1, 0, 0x2E }, L2(15), 1175000 },
- { 1, { 1296000, HFPLL, 1, 0, 0x30 }, L2(15), 1200000 },
- { 1, { 1350000, HFPLL, 1, 0, 0x32 }, L2(15), 1200000 },
- { 1, { 1404000, HFPLL, 1, 0, 0x34 }, L2(15), 1212500 },
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 925000 },
+ { 1, { 432000, HFPLL, 2, 0x20 }, L2(5), 950000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 950000 },
+ { 1, { 540000, HFPLL, 2, 0x28 }, L2(5), 975000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 975000 },
+ { 1, { 648000, HFPLL, 1, 0x18 }, L2(5), 1000000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 1000000 },
+ { 1, { 756000, HFPLL, 1, 0x1C }, L2(10), 1050000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(10), 1050000 },
+ { 1, { 864000, HFPLL, 1, 0x20 }, L2(10), 1075000 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(10), 1075000 },
+ { 1, { 972000, HFPLL, 1, 0x24 }, L2(10), 1100000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(10), 1100000 },
+ { 1, { 1080000, HFPLL, 1, 0x28 }, L2(15), 1150000 },
+ { 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1150000 },
+ { 1, { 1188000, HFPLL, 1, 0x2C }, L2(15), 1175000 },
+ { 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 1175000 },
+ { 1, { 1296000, HFPLL, 1, 0x30 }, L2(15), 1200000 },
+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1200000 },
+ { 1, { 1404000, HFPLL, 1, 0x34 }, L2(15), 1212500 },
{ 0, { 0 } }
};
static struct acpu_level acpu_freq_tbl_fast[] __initdata = {
- { 1, { 384000, PLL_8, 0, 2, 0x00 }, L2(0), 900000 },
- { 1, { 432000, HFPLL, 2, 0, 0x20 }, L2(5), 900000 },
- { 1, { 486000, HFPLL, 2, 0, 0x24 }, L2(5), 900000 },
- { 1, { 540000, HFPLL, 2, 0, 0x28 }, L2(5), 925000 },
- { 1, { 594000, HFPLL, 1, 0, 0x16 }, L2(5), 925000 },
- { 1, { 648000, HFPLL, 1, 0, 0x18 }, L2(5), 950000 },
- { 1, { 702000, HFPLL, 1, 0, 0x1A }, L2(5), 950000 },
- { 1, { 756000, HFPLL, 1, 0, 0x1C }, L2(10), 1000000 },
- { 1, { 810000, HFPLL, 1, 0, 0x1E }, L2(10), 1000000 },
- { 1, { 864000, HFPLL, 1, 0, 0x20 }, L2(10), 1025000 },
- { 1, { 918000, HFPLL, 1, 0, 0x22 }, L2(10), 1025000 },
- { 1, { 972000, HFPLL, 1, 0, 0x24 }, L2(10), 1050000 },
- { 1, { 1026000, HFPLL, 1, 0, 0x26 }, L2(10), 1050000 },
- { 1, { 1080000, HFPLL, 1, 0, 0x28 }, L2(15), 1100000 },
- { 1, { 1134000, HFPLL, 1, 0, 0x2A }, L2(15), 1100000 },
- { 1, { 1188000, HFPLL, 1, 0, 0x2C }, L2(15), 1125000 },
- { 1, { 1242000, HFPLL, 1, 0, 0x2E }, L2(15), 1125000 },
- { 1, { 1296000, HFPLL, 1, 0, 0x30 }, L2(15), 1150000 },
- { 1, { 1350000, HFPLL, 1, 0, 0x32 }, L2(15), 1150000 },
- { 1, { 1404000, HFPLL, 1, 0, 0x34 }, L2(15), 1162500 },
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 900000 },
+ { 1, { 432000, HFPLL, 2, 0x20 }, L2(5), 900000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 900000 },
+ { 1, { 540000, HFPLL, 2, 0x28 }, L2(5), 925000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 925000 },
+ { 1, { 648000, HFPLL, 1, 0x18 }, L2(5), 950000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 950000 },
+ { 1, { 756000, HFPLL, 1, 0x1C }, L2(10), 1000000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(10), 1000000 },
+ { 1, { 864000, HFPLL, 1, 0x20 }, L2(10), 1025000 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(10), 1025000 },
+ { 1, { 972000, HFPLL, 1, 0x24 }, L2(10), 1050000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(10), 1050000 },
+ { 1, { 1080000, HFPLL, 1, 0x28 }, L2(15), 1100000 },
+ { 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1100000 },
+ { 1, { 1188000, HFPLL, 1, 0x2C }, L2(15), 1125000 },
+ { 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 1125000 },
+ { 1, { 1296000, HFPLL, 1, 0x30 }, L2(15), 1150000 },
+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1150000 },
+ { 1, { 1404000, HFPLL, 1, 0x34 }, L2(15), 1162500 },
{ 0, { 0 } }
};
diff --git a/arch/arm/mach-msm/acpuclock-8960.c b/arch/arm/mach-msm/acpuclock-8960.c
index e16c6b6..cf6a6c2 100644
--- a/arch/arm/mach-msm/acpuclock-8960.c
+++ b/arch/arm/mach-msm/acpuclock-8960.c
@@ -44,6 +44,7 @@
.hfpll_phys_base = 0x00903200,
.aux_clk_sel_phys = 0x02088014,
.aux_clk_sel = 3,
+ .sec_clk_sel = 2,
.l2cpmr_iaddr = 0x4501,
.vreg[VREG_CORE] = { "krait0", 1300000 },
.vreg[VREG_MEM] = { "krait0_mem", 1150000 },
@@ -55,6 +56,7 @@
.hfpll_phys_base = 0x00903300,
.aux_clk_sel_phys = 0x02098014,
.aux_clk_sel = 3,
+ .sec_clk_sel = 2,
.l2cpmr_iaddr = 0x5501,
.vreg[VREG_CORE] = { "krait1", 1300000 },
.vreg[VREG_MEM] = { "krait1_mem", 1150000 },
@@ -66,6 +68,7 @@
.hfpll_phys_base = 0x00903400,
.aux_clk_sel_phys = 0x02011028,
.aux_clk_sel = 3,
+ .sec_clk_sel = 2,
.l2cpmr_iaddr = 0x0500,
.vreg[VREG_HFPLL_A] = { "l2_s8", 2050000 },
.vreg[VREG_HFPLL_B] = { "l2_l23", 1800000 },
@@ -90,105 +93,105 @@
};
static struct l2_level l2_freq_tbl[] __initdata = {
- [0] = { { 384000, PLL_8, 0, 2, 0x00 }, 1050000, 1050000, 1 },
- [1] = { { 432000, HFPLL, 2, 0, 0x20 }, 1050000, 1050000, 2 },
- [2] = { { 486000, HFPLL, 2, 0, 0x24 }, 1050000, 1050000, 2 },
- [3] = { { 540000, HFPLL, 2, 0, 0x28 }, 1050000, 1050000, 2 },
- [4] = { { 594000, HFPLL, 1, 0, 0x16 }, 1050000, 1050000, 2 },
- [5] = { { 648000, HFPLL, 1, 0, 0x18 }, 1050000, 1050000, 4 },
- [6] = { { 702000, HFPLL, 1, 0, 0x1A }, 1050000, 1050000, 4 },
- [7] = { { 756000, HFPLL, 1, 0, 0x1C }, 1150000, 1150000, 4 },
- [8] = { { 810000, HFPLL, 1, 0, 0x1E }, 1150000, 1150000, 4 },
- [9] = { { 864000, HFPLL, 1, 0, 0x20 }, 1150000, 1150000, 4 },
- [10] = { { 918000, HFPLL, 1, 0, 0x22 }, 1150000, 1150000, 6 },
- [11] = { { 972000, HFPLL, 1, 0, 0x24 }, 1150000, 1150000, 6 },
- [12] = { { 1026000, HFPLL, 1, 0, 0x26 }, 1150000, 1150000, 6 },
- [13] = { { 1080000, HFPLL, 1, 0, 0x28 }, 1150000, 1150000, 6 },
- [14] = { { 1134000, HFPLL, 1, 0, 0x2A }, 1150000, 1150000, 6 },
- [15] = { { 1188000, HFPLL, 1, 0, 0x2C }, 1150000, 1150000, 6 },
- [16] = { { 1242000, HFPLL, 1, 0, 0x2E }, 1150000, 1150000, 6 },
- [17] = { { 1296000, HFPLL, 1, 0, 0x30 }, 1150000, 1150000, 6 },
- [18] = { { 1350000, HFPLL, 1, 0, 0x32 }, 1150000, 1150000, 6 },
+ [0] = { { 384000, PLL_8, 0, 0x00 }, 1050000, 1050000, 1 },
+ [1] = { { 432000, HFPLL, 2, 0x20 }, 1050000, 1050000, 2 },
+ [2] = { { 486000, HFPLL, 2, 0x24 }, 1050000, 1050000, 2 },
+ [3] = { { 540000, HFPLL, 2, 0x28 }, 1050000, 1050000, 2 },
+ [4] = { { 594000, HFPLL, 1, 0x16 }, 1050000, 1050000, 2 },
+ [5] = { { 648000, HFPLL, 1, 0x18 }, 1050000, 1050000, 4 },
+ [6] = { { 702000, HFPLL, 1, 0x1A }, 1050000, 1050000, 4 },
+ [7] = { { 756000, HFPLL, 1, 0x1C }, 1150000, 1150000, 4 },
+ [8] = { { 810000, HFPLL, 1, 0x1E }, 1150000, 1150000, 4 },
+ [9] = { { 864000, HFPLL, 1, 0x20 }, 1150000, 1150000, 4 },
+ [10] = { { 918000, HFPLL, 1, 0x22 }, 1150000, 1150000, 6 },
+ [11] = { { 972000, HFPLL, 1, 0x24 }, 1150000, 1150000, 6 },
+ [12] = { { 1026000, HFPLL, 1, 0x26 }, 1150000, 1150000, 6 },
+ [13] = { { 1080000, HFPLL, 1, 0x28 }, 1150000, 1150000, 6 },
+ [14] = { { 1134000, HFPLL, 1, 0x2A }, 1150000, 1150000, 6 },
+ [15] = { { 1188000, HFPLL, 1, 0x2C }, 1150000, 1150000, 6 },
+ [16] = { { 1242000, HFPLL, 1, 0x2E }, 1150000, 1150000, 6 },
+ [17] = { { 1296000, HFPLL, 1, 0x30 }, 1150000, 1150000, 6 },
+ [18] = { { 1350000, HFPLL, 1, 0x32 }, 1150000, 1150000, 6 },
{ }
};
#define AVS(x) .avsdscr_setting = (x)
static struct acpu_level acpu_freq_tbl_slow[] __initdata = {
- { 1, { 384000, PLL_8, 0, 2, 0x00 }, L2(0), 950000, AVS(0x40001F) },
- { 0, { 432000, HFPLL, 2, 0, 0x20 }, L2(6), 975000 },
- { 1, { 486000, HFPLL, 2, 0, 0x24 }, L2(6), 975000 },
- { 0, { 540000, HFPLL, 2, 0, 0x28 }, L2(6), 1000000 },
- { 1, { 594000, HFPLL, 1, 0, 0x16 }, L2(6), 1000000 },
- { 0, { 648000, HFPLL, 1, 0, 0x18 }, L2(6), 1025000 },
- { 1, { 702000, HFPLL, 1, 0, 0x1A }, L2(6), 1025000 },
- { 0, { 756000, HFPLL, 1, 0, 0x1C }, L2(6), 1075000 },
- { 1, { 810000, HFPLL, 1, 0, 0x1E }, L2(6), 1075000 },
- { 0, { 864000, HFPLL, 1, 0, 0x20 }, L2(6), 1100000 },
- { 1, { 918000, HFPLL, 1, 0, 0x22 }, L2(6), 1100000 },
- { 0, { 972000, HFPLL, 1, 0, 0x24 }, L2(6), 1125000 },
- { 1, { 1026000, HFPLL, 1, 0, 0x26 }, L2(6), 1125000 },
- { 0, { 1080000, HFPLL, 1, 0, 0x28 }, L2(18), 1175000, AVS(0x400015) },
- { 1, { 1134000, HFPLL, 1, 0, 0x2A }, L2(18), 1175000, AVS(0x400015) },
- { 0, { 1188000, HFPLL, 1, 0, 0x2C }, L2(18), 1200000, AVS(0x400015) },
- { 1, { 1242000, HFPLL, 1, 0, 0x2E }, L2(18), 1200000, AVS(0x400015) },
- { 0, { 1296000, HFPLL, 1, 0, 0x30 }, L2(18), 1225000, AVS(0x400015) },
- { 1, { 1350000, HFPLL, 1, 0, 0x32 }, L2(18), 1225000, AVS(0x400015) },
- { 0, { 1404000, HFPLL, 1, 0, 0x34 }, L2(18), 1237500, AVS(0x400015) },
- { 1, { 1458000, HFPLL, 1, 0, 0x36 }, L2(18), 1237500, AVS(0x100018) },
- { 1, { 1512000, HFPLL, 1, 0, 0x38 }, L2(18), 1250000, AVS(0x400012) },
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 950000, AVS(0x40001F) },
+ { 0, { 432000, HFPLL, 2, 0x20 }, L2(6), 975000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(6), 975000 },
+ { 0, { 540000, HFPLL, 2, 0x28 }, L2(6), 1000000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(6), 1000000 },
+ { 0, { 648000, HFPLL, 1, 0x18 }, L2(6), 1025000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(6), 1025000 },
+ { 0, { 756000, HFPLL, 1, 0x1C }, L2(6), 1075000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(6), 1075000 },
+ { 0, { 864000, HFPLL, 1, 0x20 }, L2(6), 1100000 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(6), 1100000 },
+ { 0, { 972000, HFPLL, 1, 0x24 }, L2(6), 1125000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(6), 1125000 },
+ { 0, { 1080000, HFPLL, 1, 0x28 }, L2(18), 1175000, AVS(0x400015) },
+ { 1, { 1134000, HFPLL, 1, 0x2A }, L2(18), 1175000, AVS(0x400015) },
+ { 0, { 1188000, HFPLL, 1, 0x2C }, L2(18), 1200000, AVS(0x400015) },
+ { 1, { 1242000, HFPLL, 1, 0x2E }, L2(18), 1200000, AVS(0x400015) },
+ { 0, { 1296000, HFPLL, 1, 0x30 }, L2(18), 1225000, AVS(0x400015) },
+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(18), 1225000, AVS(0x400015) },
+ { 0, { 1404000, HFPLL, 1, 0x34 }, L2(18), 1237500, AVS(0x400015) },
+ { 1, { 1458000, HFPLL, 1, 0x36 }, L2(18), 1237500, AVS(0x100018) },
+ { 1, { 1512000, HFPLL, 1, 0x38 }, L2(18), 1250000, AVS(0x400012) },
{ 0, { 0 } }
};
static struct acpu_level acpu_freq_tbl_nom[] __initdata = {
- { 1, { 384000, PLL_8, 0, 2, 0x00 }, L2(0), 900000, AVS(0x40007F) },
- { 0, { 432000, HFPLL, 2, 0, 0x20 }, L2(6), 925000 },
- { 1, { 486000, HFPLL, 2, 0, 0x24 }, L2(6), 925000 },
- { 0, { 540000, HFPLL, 2, 0, 0x28 }, L2(6), 950000 },
- { 1, { 594000, HFPLL, 1, 0, 0x16 }, L2(6), 950000 },
- { 0, { 648000, HFPLL, 1, 0, 0x18 }, L2(6), 975000 },
- { 1, { 702000, HFPLL, 1, 0, 0x1A }, L2(6), 975000 },
- { 0, { 756000, HFPLL, 1, 0, 0x1C }, L2(6), 1025000 },
- { 1, { 810000, HFPLL, 1, 0, 0x1E }, L2(6), 1025000 },
- { 0, { 864000, HFPLL, 1, 0, 0x20 }, L2(6), 1050000 },
- { 1, { 918000, HFPLL, 1, 0, 0x22 }, L2(6), 1050000 },
- { 0, { 972000, HFPLL, 1, 0, 0x24 }, L2(6), 1075000 },
- { 1, { 1026000, HFPLL, 1, 0, 0x26 }, L2(6), 1075000 },
- { 0, { 1080000, HFPLL, 1, 0, 0x28 }, L2(18), 1125000, AVS(0x400015) },
- { 1, { 1134000, HFPLL, 1, 0, 0x2A }, L2(18), 1125000, AVS(0x400015) },
- { 0, { 1188000, HFPLL, 1, 0, 0x2C }, L2(18), 1150000, AVS(0x400015) },
- { 1, { 1242000, HFPLL, 1, 0, 0x2E }, L2(18), 1150000, AVS(0x400015) },
- { 0, { 1296000, HFPLL, 1, 0, 0x30 }, L2(18), 1175000, AVS(0x400015) },
- { 1, { 1350000, HFPLL, 1, 0, 0x32 }, L2(18), 1175000, AVS(0x400015) },
- { 0, { 1404000, HFPLL, 1, 0, 0x34 }, L2(18), 1187500, AVS(0x400015) },
- { 1, { 1458000, HFPLL, 1, 0, 0x36 }, L2(18), 1187500, AVS(0x100018) },
- { 1, { 1512000, HFPLL, 1, 0, 0x38 }, L2(18), 1200000, AVS(0x400012) },
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 900000, AVS(0x40007F) },
+ { 0, { 432000, HFPLL, 2, 0x20 }, L2(6), 925000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(6), 925000 },
+ { 0, { 540000, HFPLL, 2, 0x28 }, L2(6), 950000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(6), 950000 },
+ { 0, { 648000, HFPLL, 1, 0x18 }, L2(6), 975000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(6), 975000 },
+ { 0, { 756000, HFPLL, 1, 0x1C }, L2(6), 1025000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(6), 1025000 },
+ { 0, { 864000, HFPLL, 1, 0x20 }, L2(6), 1050000 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(6), 1050000 },
+ { 0, { 972000, HFPLL, 1, 0x24 }, L2(6), 1075000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(6), 1075000 },
+ { 0, { 1080000, HFPLL, 1, 0x28 }, L2(18), 1125000, AVS(0x400015) },
+ { 1, { 1134000, HFPLL, 1, 0x2A }, L2(18), 1125000, AVS(0x400015) },
+ { 0, { 1188000, HFPLL, 1, 0x2C }, L2(18), 1150000, AVS(0x400015) },
+ { 1, { 1242000, HFPLL, 1, 0x2E }, L2(18), 1150000, AVS(0x400015) },
+ { 0, { 1296000, HFPLL, 1, 0x30 }, L2(18), 1175000, AVS(0x400015) },
+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(18), 1175000, AVS(0x400015) },
+ { 0, { 1404000, HFPLL, 1, 0x34 }, L2(18), 1187500, AVS(0x400015) },
+ { 1, { 1458000, HFPLL, 1, 0x36 }, L2(18), 1187500, AVS(0x100018) },
+ { 1, { 1512000, HFPLL, 1, 0x38 }, L2(18), 1200000, AVS(0x400012) },
{ 0, { 0 } }
};
static struct acpu_level acpu_freq_tbl_fast[] __initdata = {
- { 1, { 384000, PLL_8, 0, 2, 0x00 }, L2(0), 850000, AVS(0x4000FF) },
- { 0, { 432000, HFPLL, 2, 0, 0x20 }, L2(6), 875000 },
- { 1, { 486000, HFPLL, 2, 0, 0x24 }, L2(6), 875000 },
- { 0, { 540000, HFPLL, 2, 0, 0x28 }, L2(6), 900000 },
- { 1, { 594000, HFPLL, 1, 0, 0x16 }, L2(6), 900000 },
- { 0, { 648000, HFPLL, 1, 0, 0x18 }, L2(6), 925000 },
- { 1, { 702000, HFPLL, 1, 0, 0x1A }, L2(6), 925000 },
- { 0, { 756000, HFPLL, 1, 0, 0x1C }, L2(6), 975000 },
- { 1, { 810000, HFPLL, 1, 0, 0x1E }, L2(6), 975000 },
- { 0, { 864000, HFPLL, 1, 0, 0x20 }, L2(6), 1000000 },
- { 1, { 918000, HFPLL, 1, 0, 0x22 }, L2(6), 1000000 },
- { 0, { 972000, HFPLL, 1, 0, 0x24 }, L2(6), 1025000 },
- { 1, { 1026000, HFPLL, 1, 0, 0x26 }, L2(6), 1025000 },
- { 0, { 1080000, HFPLL, 1, 0, 0x28 }, L2(18), 1075000, AVS(0x10001B) },
- { 1, { 1134000, HFPLL, 1, 0, 0x2A }, L2(18), 1075000, AVS(0x10001B) },
- { 0, { 1188000, HFPLL, 1, 0, 0x2C }, L2(18), 1100000, AVS(0x10001B) },
- { 1, { 1242000, HFPLL, 1, 0, 0x2E }, L2(18), 1100000, AVS(0x10001B) },
- { 0, { 1296000, HFPLL, 1, 0, 0x30 }, L2(18), 1125000, AVS(0x10001B) },
- { 1, { 1350000, HFPLL, 1, 0, 0x32 }, L2(18), 1125000, AVS(0x400012) },
- { 0, { 1404000, HFPLL, 1, 0, 0x34 }, L2(18), 1137500, AVS(0x400012) },
- { 1, { 1458000, HFPLL, 1, 0, 0x36 }, L2(18), 1137500, AVS(0x400012) },
- { 1, { 1512000, HFPLL, 1, 0, 0x38 }, L2(18), 1150000, AVS(0x400012) },
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 850000, AVS(0x4000FF) },
+ { 0, { 432000, HFPLL, 2, 0x20 }, L2(6), 875000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(6), 875000 },
+ { 0, { 540000, HFPLL, 2, 0x28 }, L2(6), 900000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(6), 900000 },
+ { 0, { 648000, HFPLL, 1, 0x18 }, L2(6), 925000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(6), 925000 },
+ { 0, { 756000, HFPLL, 1, 0x1C }, L2(6), 975000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(6), 975000 },
+ { 0, { 864000, HFPLL, 1, 0x20 }, L2(6), 1000000 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(6), 1000000 },
+ { 0, { 972000, HFPLL, 1, 0x24 }, L2(6), 1025000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(6), 1025000 },
+ { 0, { 1080000, HFPLL, 1, 0x28 }, L2(18), 1075000, AVS(0x10001B) },
+ { 1, { 1134000, HFPLL, 1, 0x2A }, L2(18), 1075000, AVS(0x10001B) },
+ { 0, { 1188000, HFPLL, 1, 0x2C }, L2(18), 1100000, AVS(0x10001B) },
+ { 1, { 1242000, HFPLL, 1, 0x2E }, L2(18), 1100000, AVS(0x10001B) },
+ { 0, { 1296000, HFPLL, 1, 0x30 }, L2(18), 1125000, AVS(0x10001B) },
+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(18), 1125000, AVS(0x400012) },
+ { 0, { 1404000, HFPLL, 1, 0x34 }, L2(18), 1137500, AVS(0x400012) },
+ { 1, { 1458000, HFPLL, 1, 0x36 }, L2(18), 1137500, AVS(0x400012) },
+ { 1, { 1512000, HFPLL, 1, 0x38 }, L2(18), 1150000, AVS(0x400012) },
{ 0, { 0 } }
};
diff --git a/arch/arm/mach-msm/acpuclock-8960ab.c b/arch/arm/mach-msm/acpuclock-8960ab.c
index 628e1ba..91ccd37 100644
--- a/arch/arm/mach-msm/acpuclock-8960ab.c
+++ b/arch/arm/mach-msm/acpuclock-8960ab.c
@@ -44,6 +44,7 @@
.hfpll_phys_base = 0x00903200,
.aux_clk_sel_phys = 0x02088014,
.aux_clk_sel = 3,
+ .sec_clk_sel = 2,
.l2cpmr_iaddr = 0x4501,
.vreg[VREG_CORE] = { "krait0", 1300000 },
.vreg[VREG_MEM] = { "krait0_mem", 1150000 },
@@ -55,6 +56,7 @@
.hfpll_phys_base = 0x00903300,
.aux_clk_sel_phys = 0x02098014,
.aux_clk_sel = 3,
+ .sec_clk_sel = 2,
.l2cpmr_iaddr = 0x5501,
.vreg[VREG_CORE] = { "krait1", 1300000 },
.vreg[VREG_MEM] = { "krait1_mem", 1150000 },
@@ -66,6 +68,7 @@
.hfpll_phys_base = 0x00903400,
.aux_clk_sel_phys = 0x02011028,
.aux_clk_sel = 3,
+ .sec_clk_sel = 2,
.l2cpmr_iaddr = 0x0500,
.vreg[VREG_HFPLL_A] = { "l2_s8", 2050000 },
.vreg[VREG_HFPLL_B] = { "l2_l23", 1800000 },
@@ -89,46 +92,46 @@
};
static struct l2_level l2_freq_tbl[] __initdata = {
- [0] = { { 384000, PLL_8, 0, 2, 0x00 }, 1050000, 1050000, 1 },
- [1] = { { 486000, HFPLL, 2, 0, 0x24 }, 1050000, 1050000, 2 },
- [2] = { { 594000, HFPLL, 1, 0, 0x16 }, 1050000, 1050000, 2 },
- [3] = { { 702000, HFPLL, 1, 0, 0x1A }, 1050000, 1050000, 4 },
- [4] = { { 810000, HFPLL, 1, 0, 0x1E }, 1050000, 1050000, 4 },
- [5] = { { 918000, HFPLL, 1, 0, 0x22 }, 1150000, 1150000, 5 },
- [6] = { { 1026000, HFPLL, 1, 0, 0x26 }, 1150000, 1150000, 5 },
- [7] = { { 1134000, HFPLL, 1, 0, 0x2A }, 1150000, 1150000, 5 },
- [8] = { { 1242000, HFPLL, 1, 0, 0x2E }, 1150000, 1150000, 5 },
- [9] = { { 1350000, HFPLL, 1, 0, 0x32 }, 1150000, 1150000, 5 },
+ [0] = { { 384000, PLL_8, 0, 0x00 }, 1050000, 1050000, 1 },
+ [1] = { { 486000, HFPLL, 2, 0x24 }, 1050000, 1050000, 2 },
+ [2] = { { 594000, HFPLL, 1, 0x16 }, 1050000, 1050000, 2 },
+ [3] = { { 702000, HFPLL, 1, 0x1A }, 1050000, 1050000, 4 },
+ [4] = { { 810000, HFPLL, 1, 0x1E }, 1050000, 1050000, 4 },
+ [5] = { { 918000, HFPLL, 1, 0x22 }, 1150000, 1150000, 5 },
+ [6] = { { 1026000, HFPLL, 1, 0x26 }, 1150000, 1150000, 5 },
+ [7] = { { 1134000, HFPLL, 1, 0x2A }, 1150000, 1150000, 5 },
+ [8] = { { 1242000, HFPLL, 1, 0x2E }, 1150000, 1150000, 5 },
+ [9] = { { 1350000, HFPLL, 1, 0x32 }, 1150000, 1150000, 5 },
{ }
};
static struct acpu_level acpu_freq_tbl_slow[] __initdata = {
- { 1, { 384000, PLL_8, 0, 2, 0x00 }, L2(0), 950000 },
- { 0, { 432000, HFPLL, 2, 0, 0x20 }, L2(3), 975000 },
- { 1, { 486000, HFPLL, 2, 0, 0x24 }, L2(3), 975000 },
- { 0, { 540000, HFPLL, 2, 0, 0x28 }, L2(3), 1000000 },
- { 1, { 594000, HFPLL, 1, 0, 0x16 }, L2(3), 1000000 },
- { 0, { 648000, HFPLL, 1, 0, 0x18 }, L2(3), 1025000 },
- { 1, { 702000, HFPLL, 1, 0, 0x1A }, L2(3), 1025000 },
- { 0, { 756000, HFPLL, 1, 0, 0x1C }, L2(3), 1075000 },
- { 1, { 810000, HFPLL, 1, 0, 0x1E }, L2(3), 1075000 },
- { 0, { 864000, HFPLL, 1, 0, 0x20 }, L2(3), 1100000 },
- { 1, { 918000, HFPLL, 1, 0, 0x22 }, L2(3), 1100000 },
- { 0, { 972000, HFPLL, 1, 0, 0x24 }, L2(3), 1125000 },
- { 1, { 1026000, HFPLL, 1, 0, 0x26 }, L2(3), 1125000 },
- { 0, { 1080000, HFPLL, 1, 0, 0x28 }, L2(9), 1175000 },
- { 1, { 1134000, HFPLL, 1, 0, 0x2A }, L2(9), 1175000 },
- { 0, { 1188000, HFPLL, 1, 0, 0x2C }, L2(9), 1200000 },
- { 1, { 1242000, HFPLL, 1, 0, 0x2E }, L2(9), 1200000 },
- { 0, { 1296000, HFPLL, 1, 0, 0x30 }, L2(9), 1225000 },
- { 1, { 1350000, HFPLL, 1, 0, 0x32 }, L2(9), 1225000 },
- { 0, { 1404000, HFPLL, 1, 0, 0x34 }, L2(9), 1237500 },
- { 1, { 1458000, HFPLL, 1, 0, 0x36 }, L2(9), 1237500 },
- { 1, { 1512000, HFPLL, 1, 0, 0x38 }, L2(9), 1250000 },
- { 1, { 1566000, HFPLL, 1, 0, 0x3A }, L2(9), 1250000 },
- { 1, { 1620000, HFPLL, 1, 0, 0x3C }, L2(9), 1250000 },
- { 1, { 1674000, HFPLL, 1, 0, 0x3E }, L2(9), 1250000 },
- { 1, { 1728000, HFPLL, 1, 0, 0x40 }, L2(9), 1250000 },
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 950000 },
+ { 0, { 432000, HFPLL, 2, 0x20 }, L2(3), 975000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(3), 975000 },
+ { 0, { 540000, HFPLL, 2, 0x28 }, L2(3), 1000000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(3), 1000000 },
+ { 0, { 648000, HFPLL, 1, 0x18 }, L2(3), 1025000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(3), 1025000 },
+ { 0, { 756000, HFPLL, 1, 0x1C }, L2(3), 1075000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(3), 1075000 },
+ { 0, { 864000, HFPLL, 1, 0x20 }, L2(3), 1100000 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(3), 1100000 },
+ { 0, { 972000, HFPLL, 1, 0x24 }, L2(3), 1125000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(3), 1125000 },
+ { 0, { 1080000, HFPLL, 1, 0x28 }, L2(9), 1175000 },
+ { 1, { 1134000, HFPLL, 1, 0x2A }, L2(9), 1175000 },
+ { 0, { 1188000, HFPLL, 1, 0x2C }, L2(9), 1200000 },
+ { 1, { 1242000, HFPLL, 1, 0x2E }, L2(9), 1200000 },
+ { 0, { 1296000, HFPLL, 1, 0x30 }, L2(9), 1225000 },
+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(9), 1225000 },
+ { 0, { 1404000, HFPLL, 1, 0x34 }, L2(9), 1237500 },
+ { 1, { 1458000, HFPLL, 1, 0x36 }, L2(9), 1237500 },
+ { 1, { 1512000, HFPLL, 1, 0x38 }, L2(9), 1250000 },
+ { 1, { 1566000, HFPLL, 1, 0x3A }, L2(9), 1250000 },
+ { 1, { 1620000, HFPLL, 1, 0x3C }, L2(9), 1250000 },
+ { 1, { 1674000, HFPLL, 1, 0x3E }, L2(9), 1250000 },
+ { 1, { 1728000, HFPLL, 1, 0x40 }, L2(9), 1250000 },
{ 0, { 0 } }
};
diff --git a/arch/arm/mach-msm/acpuclock-8974.c b/arch/arm/mach-msm/acpuclock-8974.c
index e384d1a..4a755bd 100644
--- a/arch/arm/mach-msm/acpuclock-8974.c
+++ b/arch/arm/mach-msm/acpuclock-8974.c
@@ -52,6 +52,7 @@
[CPU0] = {
.hfpll_phys_base = 0xF908A000,
.l2cpmr_iaddr = 0x4501,
+ .sec_clk_sel = 2,
.vreg[VREG_CORE] = { "krait0", 1050000 },
.vreg[VREG_MEM] = { "krait0_mem", 1050000 },
.vreg[VREG_DIG] = { "krait0_dig", LVL_HIGH },
@@ -61,6 +62,7 @@
[CPU1] = {
.hfpll_phys_base = 0xF909A000,
.l2cpmr_iaddr = 0x5501,
+ .sec_clk_sel = 2,
.vreg[VREG_CORE] = { "krait1", 1050000 },
.vreg[VREG_MEM] = { "krait1_mem", 1050000 },
.vreg[VREG_DIG] = { "krait1_dig", LVL_HIGH },
@@ -70,6 +72,7 @@
[CPU2] = {
.hfpll_phys_base = 0xF90AA000,
.l2cpmr_iaddr = 0x6501,
+ .sec_clk_sel = 2,
.vreg[VREG_CORE] = { "krait2", 1050000 },
.vreg[VREG_MEM] = { "krait2_mem", 1050000 },
.vreg[VREG_DIG] = { "krait2_dig", LVL_HIGH },
@@ -79,6 +82,7 @@
[CPU3] = {
.hfpll_phys_base = 0xF90BA000,
.l2cpmr_iaddr = 0x7501,
+ .sec_clk_sel = 2,
.vreg[VREG_CORE] = { "krait3", 1050000 },
.vreg[VREG_MEM] = { "krait3_mem", 1050000 },
.vreg[VREG_DIG] = { "krait3_dig", LVL_HIGH },
@@ -88,6 +92,7 @@
[L2] = {
.hfpll_phys_base = 0xF9016000,
.l2cpmr_iaddr = 0x0500,
+ .sec_clk_sel = 2,
.vreg[VREG_HFPLL_A] = { "l2_hfpll_a", 2150000 },
.vreg[VREG_HFPLL_B] = { "l2_hfpll_b", 1800000 },
},
@@ -108,60 +113,60 @@
};
static struct l2_level l2_freq_tbl[] __initdata = {
- [0] = { { 300000, PLL_0, 0, 2, 0 }, LVL_LOW, 950000, 0 },
- [1] = { { 384000, HFPLL, 2, 0, 40 }, LVL_NOM, 950000, 1 },
- [2] = { { 460800, HFPLL, 2, 0, 48 }, LVL_NOM, 950000, 1 },
- [3] = { { 537600, HFPLL, 1, 0, 28 }, LVL_NOM, 950000, 2 },
- [4] = { { 576000, HFPLL, 1, 0, 30 }, LVL_NOM, 950000, 2 },
- [5] = { { 652800, HFPLL, 1, 0, 34 }, LVL_NOM, 950000, 2 },
- [6] = { { 729600, HFPLL, 1, 0, 38 }, LVL_NOM, 950000, 2 },
- [7] = { { 806400, HFPLL, 1, 0, 42 }, LVL_NOM, 950000, 2 },
- [8] = { { 883200, HFPLL, 1, 0, 46 }, LVL_HIGH, 1050000, 2 },
- [9] = { { 960000, HFPLL, 1, 0, 50 }, LVL_HIGH, 1050000, 2 },
- [10] = { { 1036800, HFPLL, 1, 0, 54 }, LVL_HIGH, 1050000, 3 },
- [11] = { { 1113600, HFPLL, 1, 0, 58 }, LVL_HIGH, 1050000, 3 },
- [12] = { { 1190400, HFPLL, 1, 0, 62 }, LVL_HIGH, 1050000, 3 },
- [13] = { { 1267200, HFPLL, 1, 0, 66 }, LVL_HIGH, 1050000, 3 },
- [14] = { { 1344000, HFPLL, 1, 0, 70 }, LVL_HIGH, 1050000, 3 },
- [15] = { { 1420800, HFPLL, 1, 0, 74 }, LVL_HIGH, 1050000, 3 },
- [16] = { { 1497600, HFPLL, 1, 0, 78 }, LVL_HIGH, 1050000, 3 },
- [17] = { { 1574400, HFPLL, 1, 0, 82 }, LVL_HIGH, 1050000, 3 },
- [18] = { { 1651200, HFPLL, 1, 0, 86 }, LVL_HIGH, 1050000, 3 },
- [19] = { { 1728000, HFPLL, 1, 0, 90 }, LVL_HIGH, 1050000, 3 },
- [20] = { { 1804800, HFPLL, 1, 0, 94 }, LVL_HIGH, 1050000, 3 },
- [21] = { { 1881600, HFPLL, 1, 0, 98 }, LVL_HIGH, 1050000, 3 },
- [22] = { { 1958400, HFPLL, 1, 0, 102 }, LVL_HIGH, 1050000, 3 },
- [23] = { { 2035200, HFPLL, 1, 0, 106 }, LVL_HIGH, 1050000, 3 },
- [24] = { { 2112000, HFPLL, 1, 0, 110 }, LVL_HIGH, 1050000, 3 },
- [25] = { { 2188800, HFPLL, 1, 0, 114 }, LVL_HIGH, 1050000, 3 },
+ [0] = { { 300000, PLL_0, 0, 0 }, LVL_LOW, 950000, 0 },
+ [1] = { { 384000, HFPLL, 2, 40 }, LVL_NOM, 950000, 1 },
+ [2] = { { 460800, HFPLL, 2, 48 }, LVL_NOM, 950000, 1 },
+ [3] = { { 537600, HFPLL, 1, 28 }, LVL_NOM, 950000, 2 },
+ [4] = { { 576000, HFPLL, 1, 30 }, LVL_NOM, 950000, 2 },
+ [5] = { { 652800, HFPLL, 1, 34 }, LVL_NOM, 950000, 2 },
+ [6] = { { 729600, HFPLL, 1, 38 }, LVL_NOM, 950000, 2 },
+ [7] = { { 806400, HFPLL, 1, 42 }, LVL_NOM, 950000, 2 },
+ [8] = { { 883200, HFPLL, 1, 46 }, LVL_HIGH, 1050000, 2 },
+ [9] = { { 960000, HFPLL, 1, 50 }, LVL_HIGH, 1050000, 2 },
+ [10] = { { 1036800, HFPLL, 1, 54 }, LVL_HIGH, 1050000, 3 },
+ [11] = { { 1113600, HFPLL, 1, 58 }, LVL_HIGH, 1050000, 3 },
+ [12] = { { 1190400, HFPLL, 1, 62 }, LVL_HIGH, 1050000, 3 },
+ [13] = { { 1267200, HFPLL, 1, 66 }, LVL_HIGH, 1050000, 3 },
+ [14] = { { 1344000, HFPLL, 1, 70 }, LVL_HIGH, 1050000, 3 },
+ [15] = { { 1420800, HFPLL, 1, 74 }, LVL_HIGH, 1050000, 3 },
+ [16] = { { 1497600, HFPLL, 1, 78 }, LVL_HIGH, 1050000, 3 },
+ [17] = { { 1574400, HFPLL, 1, 82 }, LVL_HIGH, 1050000, 3 },
+ [18] = { { 1651200, HFPLL, 1, 86 }, LVL_HIGH, 1050000, 3 },
+ [19] = { { 1728000, HFPLL, 1, 90 }, LVL_HIGH, 1050000, 3 },
+ [20] = { { 1804800, HFPLL, 1, 94 }, LVL_HIGH, 1050000, 3 },
+ [21] = { { 1881600, HFPLL, 1, 98 }, LVL_HIGH, 1050000, 3 },
+ [22] = { { 1958400, HFPLL, 1, 102 }, LVL_HIGH, 1050000, 3 },
+ [23] = { { 2035200, HFPLL, 1, 106 }, LVL_HIGH, 1050000, 3 },
+ [24] = { { 2112000, HFPLL, 1, 110 }, LVL_HIGH, 1050000, 3 },
+ [25] = { { 2188800, HFPLL, 1, 114 }, LVL_HIGH, 1050000, 3 },
{ }
};
static struct acpu_level acpu_freq_tbl[] __initdata = {
- { 1, { 300000, PLL_0, 0, 2, 0 }, L2(0), 950000, 3200000 },
- { 1, { 384000, HFPLL, 2, 0, 40 }, L2(3), 950000, 3200000 },
- { 1, { 460800, HFPLL, 2, 0, 48 }, L2(3), 950000, 3200000 },
- { 1, { 537600, HFPLL, 1, 0, 28 }, L2(5), 950000, 3200000 },
- { 1, { 576000, HFPLL, 1, 0, 30 }, L2(5), 950000, 3200000 },
- { 1, { 652800, HFPLL, 1, 0, 34 }, L2(5), 950000, 3200000 },
- { 1, { 729600, HFPLL, 1, 0, 38 }, L2(5), 950000, 3200000 },
- { 1, { 806400, HFPLL, 1, 0, 42 }, L2(7), 950000, 3200000 },
- { 1, { 883200, HFPLL, 1, 0, 46 }, L2(7), 950000, 3200000 },
- { 1, { 960000, HFPLL, 1, 0, 50 }, L2(7), 950000, 3200000 },
- { 1, { 1036800, HFPLL, 1, 0, 54 }, L2(7), 950000, 3200000 },
- { 1, { 1113600, HFPLL, 1, 0, 58 }, L2(12), 1050000, 3200000 },
- { 1, { 1190400, HFPLL, 1, 0, 62 }, L2(12), 1050000, 3200000 },
- { 1, { 1267200, HFPLL, 1, 0, 66 }, L2(12), 1050000, 3200000 },
- { 1, { 1344000, HFPLL, 1, 0, 70 }, L2(15), 1050000, 3200000 },
- { 1, { 1420800, HFPLL, 1, 0, 74 }, L2(15), 1050000, 3200000 },
- { 1, { 1497600, HFPLL, 1, 0, 78 }, L2(16), 1050000, 3200000 },
- { 0, { 1574400, HFPLL, 1, 0, 82 }, L2(20), 1050000, 3200000 },
- { 0, { 1651200, HFPLL, 1, 0, 86 }, L2(20), 1050000, 3200000 },
- { 0, { 1728000, HFPLL, 1, 0, 90 }, L2(20), 1050000, 3200000 },
- { 0, { 1804800, HFPLL, 1, 0, 94 }, L2(25), 1050000, 3200000 },
- { 0, { 1881600, HFPLL, 1, 0, 98 }, L2(25), 1050000, 3200000 },
- { 0, { 1958400, HFPLL, 1, 0, 102 }, L2(25), 1050000, 3200000 },
- { 0, { 1996800, HFPLL, 1, 0, 104 }, L2(25), 1050000, 3200000 },
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 950000, 3200000 },
+ { 1, { 384000, HFPLL, 2, 40 }, L2(3), 950000, 3200000 },
+ { 1, { 460800, HFPLL, 2, 48 }, L2(3), 950000, 3200000 },
+ { 1, { 537600, HFPLL, 1, 28 }, L2(5), 950000, 3200000 },
+ { 1, { 576000, HFPLL, 1, 30 }, L2(5), 950000, 3200000 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(5), 950000, 3200000 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(5), 950000, 3200000 },
+ { 1, { 806400, HFPLL, 1, 42 }, L2(7), 950000, 3200000 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(7), 950000, 3200000 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(7), 950000, 3200000 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(7), 950000, 3200000 },
+ { 1, { 1113600, HFPLL, 1, 58 }, L2(12), 1050000, 3200000 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(12), 1050000, 3200000 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(12), 1050000, 3200000 },
+ { 1, { 1344000, HFPLL, 1, 70 }, L2(15), 1050000, 3200000 },
+ { 1, { 1420800, HFPLL, 1, 74 }, L2(15), 1050000, 3200000 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 1050000, 3200000 },
+ { 0, { 1574400, HFPLL, 1, 82 }, L2(20), 1050000, 3200000 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(20), 1050000, 3200000 },
+ { 0, { 1728000, HFPLL, 1, 90 }, L2(20), 1050000, 3200000 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(25), 1050000, 3200000 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(25), 1050000, 3200000 },
+ { 0, { 1958400, HFPLL, 1, 102 }, L2(25), 1050000, 3200000 },
+ { 0, { 1996800, HFPLL, 1, 104 }, L2(25), 1050000, 3200000 },
{ 0, { 0 } }
};
diff --git a/arch/arm/mach-msm/acpuclock-krait.c b/arch/arm/mach-msm/acpuclock-krait.c
index f4050f2..79c01b2 100644
--- a/arch/arm/mach-msm/acpuclock-krait.c
+++ b/arch/arm/mach-msm/acpuclock-krait.c
@@ -42,8 +42,6 @@
#define PRI_SRC_SEL_SEC_SRC 0
#define PRI_SRC_SEL_HFPLL 1
#define PRI_SRC_SEL_HFPLL_DIV2 2
-#define SEC_SRC_SEL_L2PLL 1
-#define SEC_SRC_SEL_AUX 2
#define SECCLKAGD BIT(4)
@@ -81,7 +79,7 @@
}
/* Select a source on the secondary MUX. */
-static void set_sec_clk_src(struct scalable *sc, u32 sec_src_sel)
+static void __cpuinit set_sec_clk_src(struct scalable *sc, u32 sec_src_sel)
{
u32 regval;
@@ -232,7 +230,6 @@
* Move to an always-on source running at a frequency
* that does not require an elevated CPU voltage.
*/
- set_sec_clk_src(sc, SEC_SRC_SEL_AUX);
set_pri_clk_src(sc, PRI_SRC_SEL_SEC_SRC);
/* Re-program HFPLL. */
@@ -243,15 +240,12 @@
/* Move to HFPLL. */
set_pri_clk_src(sc, tgt_s->pri_src_sel);
} else if (strt_s->src == HFPLL && tgt_s->src != HFPLL) {
- set_sec_clk_src(sc, tgt_s->sec_src_sel);
set_pri_clk_src(sc, tgt_s->pri_src_sel);
hfpll_disable(sc, false);
} else if (strt_s->src != HFPLL && tgt_s->src == HFPLL) {
hfpll_set_rate(sc, tgt_s);
hfpll_enable(sc, false);
set_pri_clk_src(sc, tgt_s->pri_src_sel);
- } else {
- set_sec_clk_src(sc, tgt_s->sec_src_sel);
}
sc->cur_speed = tgt_s;
@@ -721,7 +715,7 @@
}
/* Switch away from the HFPLL while it's re-initialized. */
- set_sec_clk_src(sc, SEC_SRC_SEL_AUX);
+ set_sec_clk_src(sc, sc->sec_clk_sel);
set_pri_clk_src(sc, PRI_SRC_SEL_SEC_SRC);
hfpll_init(sc, tgt_s);
@@ -731,7 +725,6 @@
set_l2_indirect_reg(sc->l2cpmr_iaddr, regval);
/* Switch to the target clock source. */
- set_sec_clk_src(sc, tgt_s->sec_src_sel);
set_pri_clk_src(sc, tgt_s->pri_src_sel);
sc->cur_speed = tgt_s;
@@ -742,7 +735,6 @@
struct scalable *sc)
{
s->pri_src_sel = get_l2_indirect_reg(sc->l2cpmr_iaddr) & 0x3;
- s->sec_src_sel = (get_l2_indirect_reg(sc->l2cpmr_iaddr) >> 2) & 0x3;
s->pll_l_val = readl_relaxed(sc->hfpll_base + drv.hfpll_data->l_offset);
}
@@ -750,7 +742,6 @@
const struct core_speed *s2)
{
return (s1->pri_src_sel == s2->pri_src_sel &&
- s1->sec_src_sel == s2->sec_src_sel &&
s1->pll_l_val == s2->pll_l_val);
}
diff --git a/arch/arm/mach-msm/acpuclock-krait.h b/arch/arm/mach-msm/acpuclock-krait.h
index d615b85..84a5b5e 100644
--- a/arch/arm/mach-msm/acpuclock-krait.h
+++ b/arch/arm/mach-msm/acpuclock-krait.h
@@ -111,14 +111,12 @@
* @khz: Clock rate in KHz.
* @src: Clock source ID.
* @pri_src_sel: Input to select on the primary MUX.
- * @sec_src_sel: Input to select on the secondary MUX.
* @pll_l_val: HFPLL "L" value to be applied when an HFPLL source is selected.
*/
struct core_speed {
unsigned long khz;
int src;
u32 pri_src_sel;
- u32 sec_src_sel;
u32 pll_l_val;
};
@@ -200,6 +198,7 @@
* @hfpll_base: Virtual base address of HFPLL registers.
* @aux_clk_sel_phys: Physical address of auxiliary MUX.
* @aux_clk_sel: Auxiliary mux input to select at boot.
+ * @sec_clk_sel: Secondary mux input to select at boot.
* @l2cpmr_iaddr: Indirect address of the CPMR MUX/divider CP15 register.
* @cur_speed: Pointer to currently-set speed.
* @l2_vote: L2 performance level vote associate with the current CPU speed.
@@ -212,6 +211,7 @@
void __iomem *hfpll_base;
const phys_addr_t aux_clk_sel_phys;
const u32 aux_clk_sel;
+ const u32 sec_clk_sel;
const u32 l2cpmr_iaddr;
const struct core_speed *cur_speed;
unsigned int l2_vote;
diff --git a/arch/arm/mach-msm/batterydata-lib.c b/arch/arm/mach-msm/batterydata-lib.c
new file mode 100644
index 0000000..2be591c
--- /dev/null
+++ b/arch/arm/mach-msm/batterydata-lib.c
@@ -0,0 +1,338 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define pr_fmt(fmt) "%s: " fmt, __func__
+
+#include <linux/module.h>
+#include <linux/mfd/pm8xxx/batterydata-lib.h>
+
+int linear_interpolate(int y0, int x0, int y1, int x1, int x)
+{
+ if (y0 == y1 || x == x0)
+ return y0;
+ if (x1 == x0 || x == x1)
+ return y1;
+
+ return y0 + ((y1 - y0) * (x - x0) / (x1 - x0));
+}
+
+int is_between(int left, int right, int value)
+{
+ if (left >= right && left >= value && value >= right)
+ return 1;
+ if (left <= right && left <= value && value <= right)
+ return 1;
+ return 0;
+}
+
+static int interpolate_single_lut(struct single_row_lut *lut, int x)
+{
+ int i, result;
+
+ if (x < lut->x[0]) {
+ pr_debug("x %d less than known range return y = %d lut = %pS\n",
+ x, lut->y[0], lut);
+ return lut->y[0];
+ }
+ if (x > lut->x[lut->cols - 1]) {
+ pr_debug("x %d more than known range return y = %d lut = %pS\n",
+ x, lut->y[lut->cols - 1], lut);
+ return lut->y[lut->cols - 1];
+ }
+
+ for (i = 0; i < lut->cols; i++)
+ if (x <= lut->x[i])
+ break;
+ if (x == lut->x[i]) {
+ result = lut->y[i];
+ } else {
+ result = linear_interpolate(
+ lut->y[i - 1],
+ lut->x[i - 1],
+ lut->y[i],
+ lut->x[i],
+ x);
+ }
+ return result;
+}
+
+int interpolate_fcc(struct single_row_lut *fcc_temp_lut, int batt_temp)
+{
+ /* batt_temp is in tenths of degC - convert it to degC for lookups */
+ batt_temp = batt_temp/10;
+ return interpolate_single_lut(fcc_temp_lut, batt_temp);
+}
+
+int interpolate_scalingfactor_fcc(struct single_row_lut *fcc_sf_lut,
+ int cycles)
+{
+ /*
+ * sf table could be null when no battery aging data is available, in
+ * that case return 100%
+ */
+ if (fcc_sf_lut)
+ return interpolate_single_lut(fcc_sf_lut, cycles);
+ else
+ return 100;
+}
+
+int interpolate_scalingfactor(struct sf_lut *sf_lut, int row_entry, int pc)
+{
+ int i, scalefactorrow1, scalefactorrow2, scalefactor, rows, cols;
+ int row1 = 0;
+ int row2 = 0;
+
+ /*
+ * sf table could be null when no battery aging data is available, in
+ * that case return 100%
+ */
+ if (!sf_lut)
+ return 100;
+
+ rows = sf_lut->rows;
+ cols = sf_lut->cols;
+ if (pc > sf_lut->percent[0]) {
+ pr_debug("pc %d greater than known pc ranges for sfd\n", pc);
+ row1 = 0;
+ row2 = 0;
+ }
+ if (pc < sf_lut->percent[rows - 1]) {
+ pr_debug("pc %d less than known pc ranges for sf\n", pc);
+ row1 = rows - 1;
+ row2 = rows - 1;
+ }
+ for (i = 0; i < rows; i++) {
+ if (pc == sf_lut->percent[i]) {
+ row1 = i;
+ row2 = i;
+ break;
+ }
+ if (pc > sf_lut->percent[i]) {
+ row1 = i - 1;
+ row2 = i;
+ break;
+ }
+ }
+
+ if (row_entry < sf_lut->row_entries[0])
+ row_entry = sf_lut->row_entries[0];
+ if (row_entry > sf_lut->row_entries[cols - 1])
+ row_entry = sf_lut->row_entries[cols - 1];
+
+ for (i = 0; i < cols; i++)
+ if (row_entry <= sf_lut->row_entries[i])
+ break;
+ if (row_entry == sf_lut->row_entries[i]) {
+ scalefactor = linear_interpolate(
+ sf_lut->sf[row1][i],
+ sf_lut->percent[row1],
+ sf_lut->sf[row2][i],
+ sf_lut->percent[row2],
+ pc);
+ return scalefactor;
+ }
+
+ scalefactorrow1 = linear_interpolate(
+ sf_lut->sf[row1][i - 1],
+ sf_lut->row_entries[i - 1],
+ sf_lut->sf[row1][i],
+ sf_lut->row_entries[i],
+ row_entry);
+
+ scalefactorrow2 = linear_interpolate(
+ sf_lut->sf[row2][i - 1],
+ sf_lut->row_entries[i - 1],
+ sf_lut->sf[row2][i],
+ sf_lut->row_entries[i],
+ row_entry);
+
+ scalefactor = linear_interpolate(
+ scalefactorrow1,
+ sf_lut->percent[row1],
+ scalefactorrow2,
+ sf_lut->percent[row2],
+ pc);
+
+ return scalefactor;
+}
+
+/* get ocv given a soc -- reverse lookup */
+int interpolate_ocv(struct pc_temp_ocv_lut *pc_temp_ocv,
+ int batt_temp_degc, int pc)
+{
+ int i, ocvrow1, ocvrow2, ocv, rows, cols;
+ int row1 = 0;
+ int row2 = 0;
+
+ rows = pc_temp_ocv->rows;
+ cols = pc_temp_ocv->cols;
+ if (pc > pc_temp_ocv->percent[0]) {
+ pr_debug("pc %d greater than known pc ranges for sfd\n", pc);
+ row1 = 0;
+ row2 = 0;
+ }
+ if (pc < pc_temp_ocv->percent[rows - 1]) {
+ pr_debug("pc %d less than known pc ranges for sf\n", pc);
+ row1 = rows - 1;
+ row2 = rows - 1;
+ }
+ for (i = 0; i < rows; i++) {
+ if (pc == pc_temp_ocv->percent[i]) {
+ row1 = i;
+ row2 = i;
+ break;
+ }
+ if (pc > pc_temp_ocv->percent[i]) {
+ row1 = i - 1;
+ row2 = i;
+ break;
+ }
+ }
+
+ if (batt_temp_degc < pc_temp_ocv->temp[0])
+ batt_temp_degc = pc_temp_ocv->temp[0];
+ if (batt_temp_degc > pc_temp_ocv->temp[cols - 1])
+ batt_temp_degc = pc_temp_ocv->temp[cols - 1];
+
+ for (i = 0; i < cols; i++)
+ if (batt_temp_degc <= pc_temp_ocv->temp[i])
+ break;
+ if (batt_temp_degc == pc_temp_ocv->temp[i]) {
+ ocv = linear_interpolate(
+ pc_temp_ocv->ocv[row1][i],
+ pc_temp_ocv->percent[row1],
+ pc_temp_ocv->ocv[row2][i],
+ pc_temp_ocv->percent[row2],
+ pc);
+ return ocv;
+ }
+
+ ocvrow1 = linear_interpolate(
+ pc_temp_ocv->ocv[row1][i - 1],
+ pc_temp_ocv->temp[i - 1],
+ pc_temp_ocv->ocv[row1][i],
+ pc_temp_ocv->temp[i],
+ batt_temp_degc);
+
+ ocvrow2 = linear_interpolate(
+ pc_temp_ocv->ocv[row2][i - 1],
+ pc_temp_ocv->temp[i - 1],
+ pc_temp_ocv->ocv[row2][i],
+ pc_temp_ocv->temp[i],
+ batt_temp_degc);
+
+ ocv = linear_interpolate(
+ ocvrow1,
+ pc_temp_ocv->percent[row1],
+ ocvrow2,
+ pc_temp_ocv->percent[row2],
+ pc);
+
+ return ocv;
+}
+
+int interpolate_pc(struct pc_temp_ocv_lut *pc_temp_ocv,
+ int batt_temp_degc, int ocv)
+{
+ int i, j, pcj, pcj_minus_one, pc;
+ int rows = pc_temp_ocv->rows;
+ int cols = pc_temp_ocv->cols;
+
+ if (batt_temp_degc < pc_temp_ocv->temp[0]) {
+ pr_debug("batt_temp %d < known temp range\n", batt_temp_degc);
+ batt_temp_degc = pc_temp_ocv->temp[0];
+ }
+
+ if (batt_temp_degc > pc_temp_ocv->temp[cols - 1]) {
+ pr_debug("batt_temp %d > known temp range\n", batt_temp_degc);
+ batt_temp_degc = pc_temp_ocv->temp[cols - 1];
+ }
+
+ for (j = 0; j < cols; j++)
+ if (batt_temp_degc <= pc_temp_ocv->temp[j])
+ break;
+ if (batt_temp_degc == pc_temp_ocv->temp[j]) {
+ /* found an exact match for temp in the table */
+ if (ocv >= pc_temp_ocv->ocv[0][j])
+ return pc_temp_ocv->percent[0];
+ if (ocv <= pc_temp_ocv->ocv[rows - 1][j])
+ return pc_temp_ocv->percent[rows - 1];
+ for (i = 0; i < rows; i++) {
+ if (ocv >= pc_temp_ocv->ocv[i][j]) {
+ if (ocv == pc_temp_ocv->ocv[i][j])
+ return pc_temp_ocv->percent[i];
+ pc = linear_interpolate(
+ pc_temp_ocv->percent[i],
+ pc_temp_ocv->ocv[i][j],
+ pc_temp_ocv->percent[i - 1],
+ pc_temp_ocv->ocv[i - 1][j],
+ ocv);
+ return pc;
+ }
+ }
+ }
+
+ /*
+ * batt_temp_degc is within temperature for
+ * column j-1 and j
+ */
+ if (ocv >= pc_temp_ocv->ocv[0][j])
+ return pc_temp_ocv->percent[0];
+ if (ocv <= pc_temp_ocv->ocv[rows - 1][j - 1])
+ return pc_temp_ocv->percent[rows - 1];
+
+ pcj_minus_one = 0;
+ pcj = 0;
+ for (i = 0; i < rows-1; i++) {
+ if (pcj == 0
+ && is_between(pc_temp_ocv->ocv[i][j],
+ pc_temp_ocv->ocv[i+1][j], ocv)) {
+ pcj = linear_interpolate(
+ pc_temp_ocv->percent[i],
+ pc_temp_ocv->ocv[i][j],
+ pc_temp_ocv->percent[i + 1],
+ pc_temp_ocv->ocv[i+1][j],
+ ocv);
+ }
+
+ if (pcj_minus_one == 0
+ && is_between(pc_temp_ocv->ocv[i][j-1],
+ pc_temp_ocv->ocv[i+1][j-1], ocv)) {
+ pcj_minus_one = linear_interpolate(
+ pc_temp_ocv->percent[i],
+ pc_temp_ocv->ocv[i][j-1],
+ pc_temp_ocv->percent[i + 1],
+ pc_temp_ocv->ocv[i+1][j-1],
+ ocv);
+ }
+
+ if (pcj && pcj_minus_one) {
+ pc = linear_interpolate(
+ pcj_minus_one,
+ pc_temp_ocv->temp[j-1],
+ pcj,
+ pc_temp_ocv->temp[j],
+ batt_temp_degc);
+ return pc;
+ }
+ }
+
+ if (pcj)
+ return pcj;
+
+ if (pcj_minus_one)
+ return pcj_minus_one;
+
+ pr_debug("%d ocv wasn't found for temp %d in the LUT returning 100%%\n",
+ ocv, batt_temp_degc);
+ return 100;
+}
diff --git a/arch/arm/mach-msm/bms-batterydata-desay.c b/arch/arm/mach-msm/bms-batterydata-desay.c
index f362a72..d9fa061 100644
--- a/arch/arm/mach-msm/bms-batterydata-desay.c
+++ b/arch/arm/mach-msm/bms-batterydata-desay.c
@@ -10,7 +10,7 @@
* GNU General Public License for more details.
*/
-#include <linux/mfd/pm8xxx/pm8921-bms.h>
+#include <linux/mfd/pm8xxx/batterydata-lib.h>
static struct single_row_lut desay_5200_fcc_temp = {
.x = {-20, 0, 25, 40},
@@ -76,7 +76,7 @@
},
};
-struct pm8921_bms_battery_data desay_5200_data = {
+struct bms_battery_data desay_5200_data = {
.fcc = 5200,
.fcc_temp_lut = &desay_5200_fcc_temp,
.fcc_sf_lut = &desay_5200_fcc_sf,
diff --git a/arch/arm/mach-msm/bms-batterydata.c b/arch/arm/mach-msm/bms-batterydata.c
index 81ab121..fb4f967 100644
--- a/arch/arm/mach-msm/bms-batterydata.c
+++ b/arch/arm/mach-msm/bms-batterydata.c
@@ -10,7 +10,7 @@
* GNU General Public License for more details.
*/
-#include <linux/mfd/pm8xxx/pm8921-bms.h>
+#include <linux/mfd/pm8xxx/batterydata-lib.h>
static struct single_row_lut fcc_temp = {
.x = {-20, 0, 25, 40, 65},
@@ -99,7 +99,7 @@
}
};
-struct pm8921_bms_battery_data palladium_1500_data = {
+struct bms_battery_data palladium_1500_data = {
.fcc = 1500,
.fcc_temp_lut = &fcc_temp,
.pc_temp_ocv_lut = &pc_temp_ocv,
diff --git a/arch/arm/mach-msm/board-8064-gpu.c b/arch/arm/mach-msm/board-8064-gpu.c
index 122505e..68debff 100644
--- a/arch/arm/mach-msm/board-8064-gpu.c
+++ b/arch/arm/mach-msm/board-8064-gpu.c
@@ -251,11 +251,17 @@
{
unsigned int version = socinfo_get_version();
- if ((SOCINFO_VERSION_MAJOR(version) == 1) &&
- (SOCINFO_VERSION_MINOR(version) == 1))
- kgsl_3d0_pdata.chipid = ADRENO_CHIPID(3, 2, 0, 1);
- else
- kgsl_3d0_pdata.chipid = ADRENO_CHIPID(3, 2, 0, 0);
+ if (cpu_is_apq8064ab())
+ kgsl_3d0_pdata.pwrlevel[0].gpu_freq = 450000000;
+ if (SOCINFO_VERSION_MAJOR(version) == 2) {
+ kgsl_3d0_pdata.chipid = ADRENO_CHIPID(3, 2, 0, 2);
+ } else {
+ if ((SOCINFO_VERSION_MAJOR(version) == 1) &&
+ (SOCINFO_VERSION_MINOR(version) == 1))
+ kgsl_3d0_pdata.chipid = ADRENO_CHIPID(3, 2, 0, 1);
+ else
+ kgsl_3d0_pdata.chipid = ADRENO_CHIPID(3, 2, 0, 0);
+ }
platform_device_register(&device_kgsl_3d0);
}
diff --git a/arch/arm/mach-msm/board-8064-storage.c b/arch/arm/mach-msm/board-8064-storage.c
index c81a637..379d7ae 100644
--- a/arch/arm/mach-msm/board-8064-storage.c
+++ b/arch/arm/mach-msm/board-8064-storage.c
@@ -338,6 +338,11 @@
apq8064_add_sdcc(2, apq8064_sdc2_pdata);
if (apq8064_sdc3_pdata) {
+ if (machine_is_mpq8064_hrd() || machine_is_mpq8064_dtv()) {
+ apq8064_sdc3_pdata->uhs_caps &= ~(MMC_CAP_UHS_SDR12 |
+ MMC_CAP_UHS_SDR25 | MMC_CAP_UHS_DDR50 |
+ MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104);
+ }
if (!machine_is_apq8064_cdp()) {
apq8064_sdc3_pdata->wpswitch_gpio = 0;
apq8064_sdc3_pdata->is_wpswitch_active_low = false;
diff --git a/arch/arm/mach-msm/board-8064.c b/arch/arm/mach-msm/board-8064.c
index 1bac198..1efc64b 100644
--- a/arch/arm/mach-msm/board-8064.c
+++ b/arch/arm/mach-msm/board-8064.c
@@ -470,7 +470,8 @@
const struct ion_platform_heap *heap =
&(apq8064_ion_pdata.heaps[i]);
- if (heap->type == ION_HEAP_TYPE_CP && heap->extra_data) {
+ if (heap->type == (enum ion_heap_type) ION_HEAP_TYPE_CP
+ && heap->extra_data) {
struct ion_cp_heap_pdata *data = heap->extra_data;
reusable_count += (data->reusable) ? 1 : 0;
@@ -492,7 +493,7 @@
int fixed_position = NOT_FIXED;
int mem_is_fmem = 0;
- switch (heap->type) {
+ switch ((int)heap->type) {
case ION_HEAP_TYPE_CP:
mem_is_fmem = ((struct ion_cp_heap_pdata *)
heap->extra_data)->mem_is_fmem;
@@ -553,7 +554,7 @@
int fixed_position = NOT_FIXED;
struct ion_cp_heap_pdata *pdata = NULL;
- switch (heap->type) {
+ switch ((int) heap->type) {
case ION_HEAP_TYPE_CP:
pdata =
(struct ion_cp_heap_pdata *)heap->extra_data;
diff --git a/arch/arm/mach-msm/board-8930.c b/arch/arm/mach-msm/board-8930.c
index 05592c2..b84e66e 100644
--- a/arch/arm/mach-msm/board-8930.c
+++ b/arch/arm/mach-msm/board-8930.c
@@ -518,7 +518,8 @@
const struct ion_platform_heap *heap =
&(msm8930_ion_pdata.heaps[i]);
- if (heap->type == ION_HEAP_TYPE_CP && heap->extra_data) {
+ if (heap->type == (enum ion_heap_type) ION_HEAP_TYPE_CP
+ && heap->extra_data) {
struct ion_cp_heap_pdata *data = heap->extra_data;
reusable_count += (data->reusable) ? 1 : 0;
@@ -540,7 +541,7 @@
int fixed_position = NOT_FIXED;
int mem_is_fmem = 0;
- switch (heap->type) {
+ switch ((int) heap->type) {
case ION_HEAP_TYPE_CP:
mem_is_fmem = ((struct ion_cp_heap_pdata *)
heap->extra_data)->mem_is_fmem;
@@ -601,7 +602,7 @@
int fixed_position = NOT_FIXED;
struct ion_cp_heap_pdata *pdata = NULL;
- switch (heap->type) {
+ switch ((int) heap->type) {
case ION_HEAP_TYPE_CP:
pdata =
(struct ion_cp_heap_pdata *)heap->extra_data;
diff --git a/arch/arm/mach-msm/board-8960.c b/arch/arm/mach-msm/board-8960.c
index 710b10f..d93a4fa 100644
--- a/arch/arm/mach-msm/board-8960.c
+++ b/arch/arm/mach-msm/board-8960.c
@@ -562,7 +562,8 @@
const struct ion_platform_heap *heap =
&(msm8960_ion_pdata.heaps[i]);
- if (heap->type == ION_HEAP_TYPE_CP && heap->extra_data) {
+ if (heap->type == (enum ion_heap_type) ION_HEAP_TYPE_CP
+ && heap->extra_data) {
struct ion_cp_heap_pdata *data = heap->extra_data;
reusable_count += (data->reusable) ? 1 : 0;
@@ -587,7 +588,7 @@
int fixed_position = NOT_FIXED;
int mem_is_fmem = 0;
- switch (heap->type) {
+ switch ((int) heap->type) {
case ION_HEAP_TYPE_CP:
mem_is_fmem = ((struct ion_cp_heap_pdata *)
heap->extra_data)->mem_is_fmem;
@@ -666,7 +667,7 @@
int fixed_position = NOT_FIXED;
struct ion_cp_heap_pdata *pdata = NULL;
- switch (heap->type) {
+ switch ((int) heap->type) {
case ION_HEAP_TYPE_CP:
pdata =
(struct ion_cp_heap_pdata *)heap->extra_data;
diff --git a/arch/arm/mach-msm/board-9625-gpiomux.c b/arch/arm/mach-msm/board-9625-gpiomux.c
index 2919f06..fe7670b 100644
--- a/arch/arm/mach-msm/board-9625-gpiomux.c
+++ b/arch/arm/mach-msm/board-9625-gpiomux.c
@@ -18,8 +18,8 @@
#include <mach/gpiomux.h>
static struct gpiomux_setting gpio_uart_config = {
- .func = GPIOMUX_FUNC_2,
- .drv = GPIOMUX_DRV_16MA,
+ .func = GPIOMUX_FUNC_1,
+ .drv = GPIOMUX_DRV_8MA,
.pull = GPIOMUX_PULL_NONE,
.dir = GPIOMUX_OUT_HIGH,
};
@@ -38,13 +38,13 @@
static struct msm_gpiomux_config msm_blsp_configs[] __initdata = {
{
- .gpio = 45, /* BLSP1 UART TX */
+ .gpio = 8, /* BLSP1 UART TX */
.settings = {
[GPIOMUX_SUSPENDED] = &gpio_uart_config,
},
},
{
- .gpio = 46, /* BLSP1 UART RX */
+ .gpio = 9, /* BLSP1 UART RX */
.settings = {
[GPIOMUX_SUSPENDED] = &gpio_uart_config,
},
diff --git a/arch/arm/mach-msm/board-msm7627a-io.c b/arch/arm/mach-msm/board-msm7627a-io.c
index 47e8381..6e3d10a 100644
--- a/arch/arm/mach-msm/board-msm7627a-io.c
+++ b/arch/arm/mach-msm/board-msm7627a-io.c
@@ -266,16 +266,16 @@
/* T6 Object */
0, 0, 0, 0, 0, 0,
/* T38 Object */
- 20, 0, 0, 0, 0, 0, 0, 0,
+ 20, 1, 0, 25, 9, 12, 0, 0,
/* T7 Object */
24, 12, 10,
/* T8 Object */
- 30, 0, 20, 20, 0, 0, 9, 45, 10, 192,
+ 30, 0, 20, 20, 0, 0, 0, 0, 10, 192,
/* T9 Object */
- 3, 0, 0, 18, 11, 0, 16, 60, 3, 1,
- 0, 1, 1, 0, 10, 10, 10, 10, 107, 3,
- 223, 1, 0, 0, 0, 0, 0, 0, 0, 0,
- 20, 15, 0, 0, 2,
+ 131, 0, 0, 18, 11, 0, 16, 70, 2, 1,
+ 0, 2, 1, 62, 10, 10, 10, 10, 107, 3,
+ 223, 1, 2, 2, 20, 20, 172, 40, 139, 110,
+ 10, 15, 0, 0, 0,
/* T15 Object */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0,
@@ -291,7 +291,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0,
/* T40 Object */
- 17, 0, 0, 30, 30,
+ 0, 0, 0, 0, 0,
/* T42 Object */
3, 20, 45, 40, 128, 0, 0, 0,
/* T46 Object */
@@ -299,12 +299,12 @@
/* T47 Object */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* T48 Object */
- 1, 128, 96, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 6, 6, 0, 0, 63, 4, 64,
- 10, 0, 32, 5, 0, 38, 0, 8, 0, 0,
+ 1, 12, 64, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 6, 6, 0, 0, 100, 4, 64,
+ 10, 0, 20, 5, 0, 38, 0, 20, 0, 0,
0, 0, 0, 0, 16, 65, 3, 1, 1, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0,
+ 10, 10, 10, 0, 0, 15, 15, 154, 58, 145,
+ 80, 100, 15, 3,
};
static struct mxt_config_info mxt_config_array[] = {
@@ -822,6 +822,7 @@
mxt_config_array[0].config_length =
ARRAY_SIZE(mxt_config_data_evt);
mxt_platform_data.panel_maxy = 875;
+ mxt_platform_data.need_calibration = true;
mxt_vkey_setup();
}
diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c
index a889d39..d831ad2 100644
--- a/arch/arm/mach-msm/board-msm8x60.c
+++ b/arch/arm/mach-msm/board-msm8x60.c
@@ -5478,7 +5478,8 @@
for (i = 0; i < ion_pdata.nr; i++) {
struct ion_platform_heap *heap = &(ion_pdata.heaps[i]);
- if (heap->extra_data && heap->type == ION_HEAP_TYPE_CP) {
+ if (heap->extra_data &&
+ heap->type == (enum ion_heap_type) ION_HEAP_TYPE_CP) {
int map_all = ((struct ion_cp_heap_pdata *)
heap->extra_data)->iommu_map_all;
diff --git a/arch/arm/mach-msm/clock-8960.c b/arch/arm/mach-msm/clock-8960.c
index b60f693..2cd2cd4 100644
--- a/arch/arm/mach-msm/clock-8960.c
+++ b/arch/arm/mach-msm/clock-8960.c
@@ -1534,6 +1534,11 @@
static CLK_SDC(sdc4_clk, 4, 3, 33000000, 67000000);
static CLK_SDC(sdc5_clk, 5, 2, 33000000, 67000000);
+static unsigned long fmax_sdc1_8064v2[MAX_VDD_LEVELS] __initdata = {
+ [VDD_DIG_LOW] = 100000000,
+ [VDD_DIG_NOMINAL] = 200000000,
+};
+
#define F_TSIF_REF(f, s, d, m, n) \
{ \
.freq_hz = f, \
@@ -1907,6 +1912,7 @@
F_CE3( 0, gnd, 1),
F_CE3( 48000000, pll8, 8),
F_CE3(100000000, pll3, 12),
+ F_CE3(120000000, pll3, 10),
F_END
};
@@ -1929,6 +1935,11 @@
},
};
+static unsigned long fmax_ce3_8064v2[MAX_VDD_LEVELS] __initdata = {
+ [VDD_DIG_LOW] = 57000000,
+ [VDD_DIG_NOMINAL] = 120000000,
+};
+
static struct branch_clk ce3_core_clk = {
.b = {
.ctl_reg = CE3_CORE_CLK_CTL_REG,
@@ -3540,11 +3551,12 @@
F_GFX3D(145455000, pll2, 2, 11),
F_GFX3D(160000000, pll2, 1, 5),
F_GFX3D(177778000, pll2, 2, 9),
+ F_GFX3D(192000000, pll8, 1, 2),
F_GFX3D(200000000, pll2, 1, 4),
F_GFX3D(228571000, pll2, 2, 7),
F_GFX3D(266667000, pll2, 1, 3),
- F_GFX3D(325000000, pll15, 1, 3),
F_GFX3D(400000000, pll2, 1, 2),
+ F_GFX3D(450000000, pll15, 1, 2),
F_END
};
@@ -3570,6 +3582,12 @@
F_END
};
+static unsigned long fmax_gfx3d_8064ab[MAX_VDD_LEVELS] __initdata = {
+ [VDD_DIG_LOW] = 128000000,
+ [VDD_DIG_NOMINAL] = 325000000,
+ [VDD_DIG_HIGH] = 450000000
+};
+
static unsigned long fmax_gfx3d_8064[MAX_VDD_LEVELS] __initdata = {
[VDD_DIG_LOW] = 128000000,
[VDD_DIG_NOMINAL] = 325000000,
@@ -4295,6 +4313,7 @@
F_VCODEC(133330000, pll2, 1, 6),
F_VCODEC(200000000, pll2, 1, 4),
F_VCODEC(228570000, pll2, 2, 7),
+ F_VCODEC(266670000, pll2, 1, 3),
F_END
};
@@ -4325,6 +4344,12 @@
},
};
+static unsigned long fmax_vcodec_8064v2[MAX_VDD_LEVELS] __initdata = {
+ [VDD_DIG_LOW] = 100000000,
+ [VDD_DIG_NOMINAL] = 200000000,
+ [VDD_DIG_HIGH] = 266670000,
+};
+
#define F_VPE(f, s, d) \
{ \
.freq_hz = f, \
@@ -5065,6 +5090,8 @@
writel_relaxed(0x80|BVAL(5, 3, clk_sel), GCC_APCS_CLK_DIAG);
measure->sample_ticks = 0x4000;
measure->multiplier = 2;
+ if (cpu_is_krait_v3())
+ measure->multiplier = 8;
break;
default:
ret = -EPERM;
@@ -6302,7 +6329,7 @@
writel_relaxed(0x3C7097F9, AHB_EN2_REG);
}
- if (cpu_is_apq8064())
+ if (cpu_is_apq8064() || cpu_is_apq8064ab())
rmwreg(0x00000001, AHB_EN3_REG, 0x00000001);
/* Deassert all locally-owned MM AHB resets. */
@@ -6325,7 +6352,7 @@
rmwreg(0x0027FCFF, MAXI_EN3_REG, 0x003FFFFF);
rmwreg(0x0027FCFF, MAXI_EN4_REG, 0x017FFFFF);
- if (cpu_is_apq8064())
+ if (cpu_is_apq8064() || cpu_is_apq8064ab())
rmwreg(0x019FECFF, MAXI_EN5_REG, 0x01FFEFFF);
if (cpu_is_msm8930() || cpu_is_msm8930aa() || cpu_is_msm8627())
rmwreg(0x000004FF, MAXI_EN5_REG, 0x00000FFF);
@@ -6363,7 +6390,8 @@
rmwreg(0x80FF0000, VFE_CC_REG, 0xE0FF4010);
rmwreg(0x800000FF, VFE_CC2_REG, 0xE00000FF);
rmwreg(0x80FF0000, VPE_CC_REG, 0xE0FF0010);
- if (cpu_is_msm8960ab() || cpu_is_msm8960() || cpu_is_apq8064()) {
+ if (cpu_is_msm8960ab() || cpu_is_msm8960() || cpu_is_apq8064()
+ || cpu_is_apq8064ab()) {
rmwreg(0x80FF0000, DSI2_BYTE_CC_REG, 0xE0FF0010);
rmwreg(0x80FF0000, DSI2_PIXEL_CC_REG, 0xE0FF0010);
rmwreg(0x80FF0000, JPEGD_CC_REG, 0xE0FF0010);
@@ -6381,7 +6409,7 @@
rmwreg(0x80FF0000, GFX2D0_CC_REG, 0xE0FF0010);
rmwreg(0x80FF0000, GFX2D1_CC_REG, 0xE0FF0010);
}
- if (cpu_is_apq8064()) {
+ if (cpu_is_apq8064() || cpu_is_apq8064ab()) {
rmwreg(0x00000000, TV_CC_REG, 0x00004010);
rmwreg(0x80FF0000, VCAP_CC_REG, 0xE0FF1010);
}
@@ -6392,7 +6420,7 @@
* and wake-up value to max.
*/
rmwreg(0x0000004F, USB_HS1_HCLK_FS_REG, 0x0000007F);
- if (cpu_is_apq8064()) {
+ if (cpu_is_apq8064() || cpu_is_apq8064ab()) {
rmwreg(0x0000004F, USB_HS3_HCLK_FS_REG, 0x0000007F);
rmwreg(0x0000004F, USB_HS4_HCLK_FS_REG, 0x0000007F);
}
@@ -6414,7 +6442,8 @@
/* Source the dsi_byte_clks from the DSI PHY PLLs */
rmwreg(0x1, DSI1_BYTE_NS_REG, 0x7);
- if (cpu_is_msm8960ab() || cpu_is_msm8960() || cpu_is_apq8064())
+ if (cpu_is_msm8960ab() || cpu_is_msm8960() || cpu_is_apq8064()
+ || cpu_is_apq8064ab())
rmwreg(0x2, DSI2_BYTE_NS_REG, 0x7);
/* Source the dsi1_esc_clk from the DSI1 PHY PLLs */
@@ -6424,7 +6453,7 @@
* Source the sata_phy_ref_clk from PXO and set predivider of
* sata_pmalive_clk to 1.
*/
- if (cpu_is_apq8064()) {
+ if (cpu_is_apq8064() || cpu_is_apq8064ab()) {
rmwreg(0, SATA_PHY_REF_CLK_CTL_REG, 0x1);
rmwreg(0, SATA_PMALIVE_CLK_CTL_REG, 0x3);
}
@@ -6433,7 +6462,7 @@
* TODO: Programming below PLLs and prng_clk is temporary and
* needs to be removed after bootloaders program them.
*/
- if (cpu_is_apq8064()) {
+ if (cpu_is_apq8064() || cpu_is_apq8064ab()) {
u32 is_pll_enabled;
/* Program pxo_src_clk to source from PXO */
@@ -6445,9 +6474,6 @@
/* Ref clk = 27MHz and program pll14 to 480MHz */
configure_sr_pll(&pll14_config, &pll14_regs, 1);
- /* Program PLL15 to 975MHz with ref clk = 27MHz */
- configure_sr_pll(&pll15_config, &pll15_regs, 0);
-
/* Check if PLL4 is active */
is_pll_enabled = readl_relaxed(LCC_PLL0_STATUS_REG) & BIT(16);
if (!is_pll_enabled)
@@ -6462,6 +6488,17 @@
writel_relaxed(0x2B, PRNG_CLK_NS_REG);
}
+ if (cpu_is_apq8064()) {
+ /* Program PLL15 to 975MHz with ref clk = 27MHz */
+ configure_sr_pll(&pll15_config, &pll15_regs, 0);
+ } else if (cpu_is_apq8064ab()) {
+ /* Program PLL15 to 900MHZ */
+ pll15_config.l = 0x21 | BVAL(31, 7, 0x620);
+ pll15_config.m = 0x1;
+ pll15_config.n = 0x3;
+ configure_sr_pll(&pll15_config, &pll15_regs, 0);
+ }
+
/*
* Program PLL15 to 900MHz with ref clk = 27MHz and
* only enable PLL main output.
@@ -6482,7 +6519,7 @@
/* Initialize clock registers. */
reg_init();
- if (cpu_is_apq8064())
+ if (cpu_is_apq8064() || cpu_is_apq8064ab())
vdd_sr2_hdmi_pll.set_vdd = set_vdd_sr2_hdmi_pll_8064;
/* Detect PLL4 programmed for alternate 491.52MHz clock plan. */
@@ -6524,13 +6561,32 @@
}
/*
* Change the freq tables for and voltage requirements for
- * clocks which differ between 8960 and 8064.
+ * clocks which differ between chips.
*/
if (cpu_is_apq8064()) {
gfx3d_clk.freq_tbl = clk_tbl_gfx3d_8064;
memcpy(gfx3d_clk.c.fmax, fmax_gfx3d_8064,
sizeof(gfx3d_clk.c.fmax));
+ }
+ if (cpu_is_apq8064ab()) {
+ gfx3d_clk.freq_tbl = clk_tbl_gfx3d_8064;
+
+ memcpy(gfx3d_clk.c.fmax, fmax_gfx3d_8064ab,
+ sizeof(gfx3d_clk.c.fmax));
+ }
+ if ((cpu_is_apq8064() &&
+ SOCINFO_VERSION_MAJOR(socinfo_get_version()) == 2) ||
+ cpu_is_apq8064ab()) {
+
+ memcpy(vcodec_clk.c.fmax, fmax_vcodec_8064v2,
+ sizeof(vcodec_clk.c.fmax));
+ memcpy(ce3_src_clk.c.fmax, fmax_ce3_8064v2,
+ sizeof(ce3_src_clk.c.fmax));
+ memcpy(sdc1_clk.c.fmax, fmax_sdc1_8064v2,
+ sizeof(sdc1_clk.c.fmax));
+ }
+ if (cpu_is_apq8064() || cpu_is_apq8064ab()) {
memcpy(ijpeg_clk.c.fmax, fmax_ijpeg_8064,
sizeof(ijpeg_clk.c.fmax));
memcpy(mdp_clk.c.fmax, fmax_mdp_8064,
@@ -6606,7 +6662,7 @@
clk_set_rate(&tsif_ref_clk.c, 105000);
clk_set_rate(&tssc_clk.c, 27000000);
clk_set_rate(&usb_hs1_xcvr_clk.c, 60000000);
- if (cpu_is_apq8064()) {
+ if (cpu_is_apq8064() || cpu_is_apq8064ab()) {
clk_set_rate(&usb_hs3_xcvr_clk.c, 60000000);
clk_set_rate(&usb_hs4_xcvr_clk.c, 60000000);
}
diff --git a/arch/arm/mach-msm/clock-8974.c b/arch/arm/mach-msm/clock-8974.c
index e9b4867..92fdc74 100644
--- a/arch/arm/mach-msm/clock-8974.c
+++ b/arch/arm/mach-msm/clock-8974.c
@@ -2183,6 +2183,18 @@
},
};
+struct branch_clk gcc_sys_noc_usb3_axi_clk = {
+ .cbcr_reg = SYS_NOC_USB3_AXI_CBCR,
+ .parent = &usb30_master_clk_src.c,
+ .has_sibling = 1,
+ .base = &virt_bases[GCC_BASE],
+ .c = {
+ .dbg_name = "gcc_sys_noc_usb3_axi_clk",
+ .ops = &clk_ops_branch,
+ CLK_INIT(gcc_sys_noc_usb3_axi_clk.c),
+ },
+};
+
static struct branch_clk gcc_usb30_master_clk = {
.cbcr_reg = USB30_MASTER_CBCR,
.bcr_reg = USB_30_BCR,
@@ -2193,6 +2205,7 @@
.dbg_name = "gcc_usb30_master_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_usb30_master_clk.c),
+ .depends = &gcc_sys_noc_usb3_axi_clk.c,
},
};
@@ -2207,18 +2220,6 @@
},
};
-struct branch_clk gcc_sys_noc_usb3_axi_clk = {
- .cbcr_reg = SYS_NOC_USB3_AXI_CBCR,
- .parent = &usb30_master_clk_src.c,
- .has_sibling = 1,
- .base = &virt_bases[GCC_BASE],
- .c = {
- .dbg_name = "gcc_sys_noc_usb3_axi_clk",
- .ops = &clk_ops_branch,
- CLK_INIT(gcc_sys_noc_usb3_axi_clk.c),
- },
-};
-
struct branch_clk gcc_usb30_sleep_clk = {
.cbcr_reg = USB30_SLEEP_CBCR,
.has_sibling = 1,
@@ -5128,7 +5129,9 @@
CLK_LOOKUP("core_clk", mdss_esc1_clk.c, ""),
CLK_LOOKUP("pixel_clk", mdss_pclk0_clk.c, "fd922800.qcom,mdss_dsi"),
CLK_LOOKUP("pixel_clk", mdss_pclk1_clk.c, ""),
- CLK_LOOKUP("iface_clk", mdss_hdmi_ahb_clk.c, "fd922100.qcom,hdmi_tx"),
+ CLK_LOOKUP("iface_clk", mdss_ahb_clk.c, "fd922100.qcom,hdmi_tx"),
+ CLK_LOOKUP("alt_iface_clk", mdss_hdmi_ahb_clk.c,
+ "fd922100.qcom,hdmi_tx"),
CLK_LOOKUP("core_clk", mdss_hdmi_clk.c, "fd922100.qcom,hdmi_tx"),
CLK_LOOKUP("extp_clk", mdss_extpclk_clk.c, "fd922100.qcom,hdmi_tx"),
CLK_LOOKUP("core_clk", mdss_mdp_clk.c, "mdp.0"),
diff --git a/arch/arm/mach-msm/clock.c b/arch/arm/mach-msm/clock.c
index 1ea18f4..c30bd79 100644
--- a/arch/arm/mach-msm/clock.c
+++ b/arch/arm/mach-msm/clock.c
@@ -72,15 +72,14 @@
/* Vote for a voltage level. */
int vote_vdd_level(struct clk_vdd_class *vdd_class, int level)
{
- unsigned long flags;
int rc;
- spin_lock_irqsave(&vdd_class->lock, flags);
+ mutex_lock(&vdd_class->lock);
vdd_class->level_votes[level]++;
rc = update_vdd(vdd_class);
if (rc)
vdd_class->level_votes[level]--;
- spin_unlock_irqrestore(&vdd_class->lock, flags);
+ mutex_unlock(&vdd_class->lock);
return rc;
}
@@ -88,10 +87,9 @@
/* Remove vote for a voltage level. */
int unvote_vdd_level(struct clk_vdd_class *vdd_class, int level)
{
- unsigned long flags;
int rc = 0;
- spin_lock_irqsave(&vdd_class->lock, flags);
+ mutex_lock(&vdd_class->lock);
if (WARN(!vdd_class->level_votes[level],
"Reference counts are incorrect for %s level %d\n",
vdd_class->class_name, level))
@@ -101,7 +99,7 @@
if (rc)
vdd_class->level_votes[level]++;
out:
- spin_unlock_irqrestore(&vdd_class->lock, flags);
+ mutex_unlock(&vdd_class->lock);
return rc;
}
@@ -135,6 +133,18 @@
unvote_vdd_level(clk->vdd_class, level);
}
+/* Returns true if the rate is valid without voting for it */
+static bool is_rate_valid(struct clk *clk, unsigned long rate)
+{
+ int level;
+
+ if (!clk->vdd_class)
+ return true;
+
+ level = find_vdd_level(clk, rate);
+ return level >= 0;
+}
+
int clk_prepare(struct clk *clk)
{
int ret = 0;
@@ -333,14 +343,16 @@
/* Enforce vdd requirements for target frequency. */
rc = vote_rate_vdd(clk, rate);
if (rc)
- goto err_vote_vdd;
+ goto out;
rc = clk->ops->set_rate(clk, rate);
if (rc)
goto err_set_rate;
/* Release vdd requirements for starting frequency. */
unvote_rate_vdd(clk, start_rate);
- } else {
+ } else if (is_rate_valid(clk, rate)) {
rc = clk->ops->set_rate(clk, rate);
+ } else {
+ rc = -EINVAL;
}
if (!rc)
@@ -351,7 +363,6 @@
err_set_rate:
unvote_rate_vdd(clk, rate);
-err_vote_vdd:
goto out;
}
EXPORT_SYMBOL(clk_set_rate);
diff --git a/arch/arm/mach-msm/devices-8064.c b/arch/arm/mach-msm/devices-8064.c
index 6be8b7ff..c0461e1 100644
--- a/arch/arm/mach-msm/devices-8064.c
+++ b/arch/arm/mach-msm/devices-8064.c
@@ -2734,8 +2734,8 @@
{
.src = MSM_BUS_MASTER_VIDEO_CAP,
.dst = MSM_BUS_SLAVE_EBI_CH0,
- .ab = 1920 * 1080 * 3 * 60,
- .ib = 1920 * 1080 * 3 * 60 * 1.5,
+ .ab = 1920 * 1080 * 10 * 60,
+ .ib = 1920 * 1080 * 10 * 60 * 1.5,
},
};
diff --git a/arch/arm/mach-msm/devices-iommu.c b/arch/arm/mach-msm/devices-iommu.c
index acf577e..6434a63 100644
--- a/arch/arm/mach-msm/devices-iommu.c
+++ b/arch/arm/mach-msm/devices-iommu.c
@@ -1017,13 +1017,13 @@
ARRAY_SIZE(msm_iommu_gfx2d_devs));
}
- if (cpu_is_apq8064() || cpu_is_msm8960ab()) {
+ if (cpu_is_apq8064() || cpu_is_msm8960ab() || cpu_is_apq8064ab()) {
platform_add_devices(msm_iommu_jpegd_devs,
ARRAY_SIZE(msm_iommu_jpegd_devs));
platform_add_devices(msm_iommu_adreno3xx_gfx_devs,
ARRAY_SIZE(msm_iommu_adreno3xx_gfx_devs));
}
- if (cpu_is_apq8064())
+ if (cpu_is_apq8064() || cpu_is_apq8064ab())
platform_add_devices(msm_iommu_vcap_devs,
ARRAY_SIZE(msm_iommu_vcap_devs));
@@ -1039,14 +1039,14 @@
ARRAY_SIZE(msm_iommu_gfx2d_ctx_devs));
}
- if (cpu_is_apq8064() || cpu_is_msm8960ab()) {
+ if (cpu_is_apq8064() || cpu_is_msm8960ab() || cpu_is_apq8064ab()) {
platform_add_devices(msm_iommu_jpegd_ctx_devs,
ARRAY_SIZE(msm_iommu_jpegd_ctx_devs));
platform_add_devices(msm_iommu_adreno3xx_ctx_devs,
ARRAY_SIZE(msm_iommu_adreno3xx_ctx_devs));
}
- if (cpu_is_apq8064())
+ if (cpu_is_apq8064() || cpu_is_apq8064ab())
platform_add_devices(msm_iommu_vcap_ctx_devs,
ARRAY_SIZE(msm_iommu_vcap_ctx_devs));
@@ -1081,12 +1081,12 @@
for (i = 0; i < ARRAY_SIZE(msm_iommu_jpegd_devs); i++)
platform_device_unregister(msm_iommu_jpegd_devs[i]);
}
- if (cpu_is_apq8064()) {
+ if (cpu_is_apq8064() || cpu_is_apq8064ab()) {
for (i = 0; i < ARRAY_SIZE(msm_iommu_vcap_ctx_devs); i++)
platform_device_unregister(msm_iommu_vcap_ctx_devs[i]);
}
- if (cpu_is_apq8064() || cpu_is_msm8960ab()) {
+ if (cpu_is_apq8064() || cpu_is_msm8960ab() || cpu_is_apq8064ab()) {
for (i = 0; i < ARRAY_SIZE(msm_iommu_adreno3xx_ctx_devs);
i++)
platform_device_unregister(
@@ -1097,7 +1097,7 @@
platform_device_unregister(
msm_iommu_jpegd_ctx_devs[i]);
- if (cpu_is_apq8064()) {
+ if (cpu_is_apq8064() || cpu_is_apq8064ab()) {
for (i = 0; i < ARRAY_SIZE(msm_iommu_vcap_devs);
i++)
platform_device_unregister(
diff --git a/arch/arm/mach-msm/devices-msm7x27a.c b/arch/arm/mach-msm/devices-msm7x27a.c
index 65dfc31..01c4a9c 100644
--- a/arch/arm/mach-msm/devices-msm7x27a.c
+++ b/arch/arm/mach-msm/devices-msm7x27a.c
@@ -1709,9 +1709,9 @@
.step_quot = ~0,
.tgt_volt_offset = 0,
.turbo_Vmax = 1350000,
- .turbo_Vmin = 950000,
+ .turbo_Vmin = 1200000,
.nom_Vmax = 1350000,
- .nom_Vmin = 950000,
+ .nom_Vmin = 1050000,
.calibrated_uV = 1300000,
},
};
@@ -1729,7 +1729,7 @@
uint32_t quot;
/* This formula is as per chip characterization data */
- quot = max_quot - (((max_freq - new_freq) * 5) / 10);
+ quot = max_quot - (((max_freq - new_freq) * 7) / 10);
return quot;
}
@@ -1757,7 +1757,7 @@
.ceiling = 40,
.sw_vlevel = 20,
.up_threshold = 1,
- .dn_threshold = 2,
+ .dn_threshold = 3,
.up_margin = 0,
.dn_margin = 0,
.max_nom_freq = 700800,
diff --git a/arch/arm/mach-msm/gss-8064.c b/arch/arm/mach-msm/gss-8064.c
index e528650..ba6af61 100644
--- a/arch/arm/mach-msm/gss-8064.c
+++ b/arch/arm/mach-msm/gss-8064.c
@@ -200,7 +200,7 @@
{
int ret;
- if (!cpu_is_apq8064())
+ if (!(cpu_is_apq8064() || cpu_is_apq8064ab()))
return -ENODEV;
ret = smsm_state_cb_register(SMSM_MODEM_STATE, SMSM_RESET,
diff --git a/arch/arm/mach-msm/include/mach/camera.h b/arch/arm/mach-msm/include/mach/camera.h
index cf36388..f5a158f 100644
--- a/arch/arm/mach-msm/include/mach/camera.h
+++ b/arch/arm/mach-msm/include/mach/camera.h
@@ -95,6 +95,7 @@
VFE_MSG_OUTPUT_SECONDARY,
VFE_MSG_OUTPUT_TERTIARY1,
VFE_MSG_OUTPUT_TERTIARY2,
+ VFE_MSG_V2X_LIVESHOT_PRIMARY,
};
enum vpe_resp_msg {
diff --git a/arch/arm/mach-msm/include/mach/clk-provider.h b/arch/arm/mach-msm/include/mach/clk-provider.h
index 0da0b33..770713d 100644
--- a/arch/arm/mach-msm/include/mach/clk-provider.h
+++ b/arch/arm/mach-msm/include/mach/clk-provider.h
@@ -20,6 +20,7 @@
#include <linux/list.h>
#include <linux/clkdev.h>
#include <linux/spinlock.h>
+#include <linux/mutex.h>
#include <mach/clk.h>
/*
@@ -53,7 +54,7 @@
int (*set_vdd)(struct clk_vdd_class *v_class, int level);
int level_votes[MAX_VDD_LEVELS];
unsigned long cur_level;
- spinlock_t lock;
+ struct mutex lock;
};
#define DEFINE_VDD_CLASS(_name, _set_vdd) \
@@ -61,7 +62,7 @@
.class_name = #_name, \
.set_vdd = _set_vdd, \
.cur_level = ARRAY_SIZE(_name.level_votes), \
- .lock = __SPIN_LOCK_UNLOCKED(lock) \
+ .lock = __MUTEX_INITIALIZER(_name.lock) \
}
enum handoff {
diff --git a/arch/arm/mach-msm/include/mach/socinfo.h b/arch/arm/mach-msm/include/mach/socinfo.h
index 546cbaf..225440c 100644
--- a/arch/arm/mach-msm/include/mach/socinfo.h
+++ b/arch/arm/mach-msm/include/mach/socinfo.h
@@ -89,6 +89,7 @@
MSM_CPU_7X25AA,
MSM_CPU_7X25AB,
MSM_CPU_8064,
+ MSM_CPU_8064AB,
MSM_CPU_8930,
MSM_CPU_8930AA,
MSM_CPU_7X27AA,
@@ -304,6 +305,15 @@
#endif
}
+static inline int cpu_is_apq8064ab(void)
+{
+#ifdef CONFIG_ARCH_APQ8064
+ return read_msm_cpu_type() == MSM_CPU_8064AB;
+#else
+ return 0;
+#endif
+}
+
static inline int cpu_is_msm8930(void)
{
#ifdef CONFIG_ARCH_MSM8930
diff --git a/arch/arm/mach-msm/modem-8960.c b/arch/arm/mach-msm/modem-8960.c
index f0a123b..83b3bc4 100644
--- a/arch/arm/mach-msm/modem-8960.c
+++ b/arch/arm/mach-msm/modem-8960.c
@@ -258,7 +258,7 @@
{
int ret;
- if (cpu_is_apq8064())
+ if (cpu_is_apq8064() || cpu_is_apq8064ab())
return -ENODEV;
ret = smsm_state_cb_register(SMSM_MODEM_STATE, SMSM_RESET,
diff --git a/arch/arm/mach-msm/msm_cpr.c b/arch/arm/mach-msm/msm_cpr.c
index 12f7d96..af74f72 100644
--- a/arch/arm/mach-msm/msm_cpr.c
+++ b/arch/arm/mach-msm/msm_cpr.c
@@ -1,5 +1,4 @@
-/*
- * Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -54,6 +53,26 @@
module_param(enable, bool, 0644);
MODULE_PARM_DESC(enable, "CPR Enable");
+static int msm_cpr_debug_mask;
+module_param_named(
+ debug_mask, msm_cpr_debug_mask, int, S_IRUGO | S_IWUSR
+);
+
+enum {
+ /* configuration log */
+ MSM_CPR_DEBUG_CONFIG = BIT(0),
+ /* step up/down interrupt log */
+ MSM_CPR_DEBUG_STEPS = BIT(1),
+ /* cpu frequency notification log */
+ MSM_CPR_DEBUG_FREQ_TRANS = BIT(2),
+};\
+
+#define msm_cpr_debug(mask, message, ...) \
+ do { \
+ if ((mask) & msm_cpr_debug_mask) \
+ pr_info(message, ##__VA_ARGS__); \
+ } while (0)
+
struct msm_cpr {
int curr_osc;
int cpr_mode;
@@ -65,7 +84,9 @@
unsigned int irq;
uint32_t cur_Vmin;
uint32_t cur_Vmax;
+ uint32_t prev_volt_uV;
struct mutex cpr_mutex;
+ spinlock_t cpr_lock;
struct regulator *vreg_cx;
const struct msm_cpr_config *config;
struct notifier_block freq_transition;
@@ -133,17 +154,17 @@
/* Enable the CPR H/W Block */
static void cpr_enable(struct msm_cpr *cpr)
{
- mutex_lock(&cpr->cpr_mutex);
+ spin_lock(&cpr->cpr_lock);
cpr_modify_reg(cpr, RBCPR_CTL, LOOP_EN_M, ENABLE_CPR);
- mutex_unlock(&cpr->cpr_mutex);
+ spin_unlock(&cpr->cpr_lock);
}
/* Disable the CPR H/W Block */
static void cpr_disable(struct msm_cpr *cpr)
{
- mutex_lock(&cpr->cpr_mutex);
+ spin_lock(&cpr->cpr_lock);
cpr_modify_reg(cpr, RBCPR_CTL, LOOP_EN_M, DISABLE_CPR);
- mutex_unlock(&cpr->cpr_mutex);
+ spin_unlock(&cpr->cpr_lock);
}
static int32_t cpr_poll_result(struct msm_cpr *cpr)
@@ -154,8 +175,7 @@
rc = readl_poll_timeout(cpr->base + RBCPR_RESULT_0, val, ~val & BUSY_M,
10, 1000);
if (rc)
- pr_info("%s: RBCPR_RESULT_0 read error: %d\n",
- __func__, rc);
+ pr_err("RBCPR_RESULT_0 read error: %d\n", rc);
return rc;
}
@@ -167,8 +187,7 @@
rc = readl_poll_timeout(cpr->base + RBIF_IRQ_STATUS, val, val & 0x1,
10, 1000);
if (rc)
- pr_info("%s: RBCPR_IRQ_STATUS read error: %d\n",
- __func__, rc);
+ pr_err("RBCPR_IRQ_STATUS read error: %d\n", rc);
return rc;
}
@@ -200,15 +219,16 @@
*/
level_uV = chip_data->turbo_Vmax -
(chip_data->tgt_volt_offset * cpr->vp->step_size);
- pr_debug("tgt_volt_uV = %d\n", level_uV);
+ msm_cpr_debug(MSM_CPR_DEBUG_CONFIG,
+ "tgt_volt_uV = %d\n", level_uV);
/* Call the PMIC specific routine to set the voltage */
rc = regulator_set_voltage(cpr->vreg_cx, level_uV, level_uV);
if (rc) {
- pr_err("%s: Initial voltage set at %duV failed. %d\n",
- __func__, level_uV, rc);
+ pr_err("Initial voltage set at %duV failed\n", level_uV);
return;
}
+
rc = regulator_enable(cpr->vreg_cx);
if (rc) {
pr_err("failed to enable %s, rc=%d\n", "vdd_cx", rc);
@@ -226,15 +246,13 @@
/* IRQ is already disabled */
rc = cpr_poll_result_done(cpr);
if (rc) {
- pr_err("%s: Quot1: Exiting due to INT_DONE poll timeout\n",
- __func__);
+ pr_err("Quot1: Exiting due to INT_DONE poll timeout\n");
return;
}
rc = cpr_poll_result(cpr);
if (rc) {
- pr_err("%s: Quot1: Exiting due to BUSY poll timeout\n",
- __func__);
+ pr_err("Quot1: Exiting due to BUSY poll timeout\n");
return;
}
@@ -242,14 +260,14 @@
/* Take second CPR measurement at a lower voltage to get QUOT2 */
level_uV -= 4 * cpr->vp->step_size;
- pr_debug("tgt_volt_uV = %d\n", level_uV);
+ msm_cpr_debug(MSM_CPR_DEBUG_CONFIG,
+ "tgt_volt_uV = %d\n", level_uV);
cpr_modify_reg(cpr, RBCPR_CTL, LOOP_EN_M, DISABLE_CPR);
/* Call the PMIC specific routine to set the voltage */
rc = regulator_set_voltage(cpr->vreg_cx, level_uV, level_uV);
if (rc) {
- pr_err("%s: Voltage set at %duV failed. %d\n",
- __func__, level_uV, rc);
+ pr_err("Voltage set at %duV failed\n", level_uV);
return;
}
@@ -259,15 +277,13 @@
/* cpr_write_reg(cpr, RBIF_CONT_NACK_CMD, 0x1); */
rc = cpr_poll_result_done(cpr);
if (rc) {
- pr_err("%s: Quot2: Exiting due to INT_DONE poll timeout\n",
- __func__);
+ pr_err("Quot2: Exiting due to INT_DONE poll timeout\n");
goto err_poll_result_done;
}
/* IRQ is already disabled */
rc = cpr_poll_result(cpr);
if (rc) {
- pr_err("%s: Quot2: Exiting due to BUSY poll timeout\n",
- __func__);
+ pr_err("Quot2: Exiting due to BUSY poll timeout\n");
goto err_poll_result;
}
quot2 = (cpr_read_reg(cpr, RBCPR_DEBUG1) & QUOT_SLOW_M) >> 12;
@@ -283,8 +299,8 @@
chip_data->step_quot > STEP_QUOT_MAX)
chip_data->step_quot = STEP_QUOT_MAX;
- pr_info("%s: Step Quot is %d\n",
- __func__, chip_data->step_quot);
+ msm_cpr_debug(MSM_CPR_DEBUG_CONFIG,
+ "Step Quot is %d\n", chip_data->step_quot);
/* Disable the cpr */
cpr_modify_reg(cpr, RBCPR_CTL, LOOP_EN_M, DISABLE_CPR);
@@ -329,27 +345,31 @@
static void
cpr_up_event_handler(struct msm_cpr *cpr, uint32_t new_volt)
{
- int rc, set_volt_uV;
+ int set_volt_uV, rc;
struct msm_cpr_mode *chip_data;
chip_data = &cpr->config->cpr_mode_data[cpr->cpr_mode];
- /**
- * FIXME: Need to handle a potential race condition between
- * freq switch handler and CPR interrupt handler here
- */
/* Set New PMIC voltage */
+ msm_cpr_debug(MSM_CPR_DEBUG_STEPS,
+ "current Vmin=%d Vmax=%d\n", cpr->cur_Vmin, cpr->cur_Vmax);
set_volt_uV = (new_volt < cpr->cur_Vmax ? new_volt
: cpr->cur_Vmax);
- rc = regulator_set_voltage(cpr->vreg_cx, set_volt_uV,
- set_volt_uV);
+
+ if (cpr->prev_volt_uV == set_volt_uV)
+ rc = regulator_sync_voltage(cpr->vreg_cx);
+ else
+ rc = regulator_set_voltage(cpr->vreg_cx, set_volt_uV,
+ set_volt_uV);
if (rc) {
- pr_err("%s: Voltage set at %duV failed. %d\n",
- __func__, set_volt_uV, rc);
+ pr_err("Unable to set_voltage = %d, rc(%d)\n", set_volt_uV, rc);
cpr_irq_clr_and_nack(cpr, BIT(4) | BIT(0));
return;
}
- pr_info("(railway_voltage: %d uV)\n", set_volt_uV);
+
+ msm_cpr_debug(MSM_CPR_DEBUG_STEPS,
+ "(railway_voltage: %d uV)\n", set_volt_uV);
+ cpr->prev_volt_uV = set_volt_uV;
cpr->max_volt_set = (set_volt_uV == cpr->cur_Vmax) ? 1 : 0;
@@ -371,27 +391,29 @@
static void
cpr_dn_event_handler(struct msm_cpr *cpr, uint32_t new_volt)
{
- int rc, set_volt_uV;
+ int set_volt_uV, rc;
struct msm_cpr_mode *chip_data;
chip_data = &cpr->config->cpr_mode_data[cpr->cpr_mode];
- /**
- * FIXME: Need to handle a potential race condition between
- * freq switch handler and CPR interrupt handler here
- */
/* Set New PMIC volt */
set_volt_uV = (new_volt > cpr->cur_Vmin ? new_volt
: cpr->cur_Vmin);
- rc = regulator_set_voltage(cpr->vreg_cx, set_volt_uV,
- set_volt_uV);
+
+ if (cpr->prev_volt_uV == set_volt_uV)
+ rc = regulator_sync_voltage(cpr->vreg_cx);
+ else
+ rc = regulator_set_voltage(cpr->vreg_cx, set_volt_uV,
+ set_volt_uV);
if (rc) {
- pr_err("%s: Voltage at %duV failed %d\n",
- __func__, set_volt_uV, rc);
+ pr_err("Unable to set_voltage = %d, rc(%d)\n", set_volt_uV, rc);
cpr_irq_clr_and_nack(cpr, BIT(2) | BIT(0));
return;
}
- pr_info("(railway_voltage: %d uV)\n", set_volt_uV);
+
+ msm_cpr_debug(MSM_CPR_DEBUG_STEPS,
+ "(railway_voltage: %d uV)\n", set_volt_uV);
+ cpr->prev_volt_uV = set_volt_uV;
cpr->max_volt_set = 0;
@@ -415,7 +437,8 @@
SW_AUTO_CONT_NACK_DN_EN_M,
SW_AUTO_CONT_NACK_DN_EN);
cpr_irq_set(cpr, DOWN_INT, 0);
- pr_debug("%s: DOWN_INT disabled\n", __func__);
+ msm_cpr_debug(MSM_CPR_DEBUG_STEPS,
+ "DOWN_INT disabled\n");
}
}
/* Acknowledge the Recommendation */
@@ -429,9 +452,18 @@
chip_data = &cpr->config->cpr_mode_data[cpr->cpr_mode];
error_step = cpr_read_reg(cpr, RBCPR_RESULT_0) >> 2;
- error_step &= 0xF;
+ msm_cpr_debug(MSM_CPR_DEBUG_STEPS,
+ "RBCPR_RESULT_0 17:6=%d\n", (cpr_read_reg(cpr,
+ RBCPR_RESULT_0) >> 6) & 0xFFF);
+ msm_cpr_debug(MSM_CPR_DEBUG_STEPS,
+ "RBCPR_RESULT_0 Busy_b19=%d\n", (cpr_read_reg(cpr,
+ RBCPR_RESULT_0) >> 19) & 0x1);
+
+ error_step &= 0xF;
curr_volt = regulator_get_voltage(cpr->vreg_cx);
+ msm_cpr_debug(MSM_CPR_DEBUG_STEPS,
+ "Current voltage=%d\n", curr_volt);
if (action == UP) {
/* Clear IRQ, ACK and return if Vdd already at Vmax */
@@ -447,15 +479,29 @@
*/
if (error_step < (cpr->config->up_threshold +
cpr->config->up_margin)) {
- pr_debug("UP_INT error step too small to set\n");
+ msm_cpr_debug(MSM_CPR_DEBUG_STEPS,
+ "UP_INT error step too small to set\n");
cpr_irq_clr_and_nack(cpr, BIT(4) | BIT(0));
return;
}
+ /**
+ * As per chip characterization recommendation, add a step
+ * to up error steps to increase system stability
+ */
+ error_step += 1;
+
/* Calculte new PMIC voltage */
new_volt = curr_volt + (error_step * cpr->vp->step_size);
- pr_debug("UP_INT: new_volt: %d\n", new_volt);
- pr_info("(UP Voltage recommended by CPR: %d uV)\n", new_volt);
+ msm_cpr_debug(MSM_CPR_DEBUG_STEPS,
+ "UP_INT: new_volt: %d, error_step=%d\n",
+ new_volt, error_step);
+ msm_cpr_debug(MSM_CPR_DEBUG_STEPS,
+ "Current RBCPR_GCNT_TARGET(%d): = 0x%x\n",
+ cpr->curr_osc, readl_relaxed(cpr->base +
+ RBCPR_GCNT_TARGET(cpr->curr_osc)) & TARGET_M);
+ msm_cpr_debug(MSM_CPR_DEBUG_STEPS,
+ "(UP Voltage recommended by CPR: %d uV)\n", new_volt);
cpr_up_event_handler(cpr, new_volt);
} else if (action == DOWN) {
@@ -465,15 +511,31 @@
*/
if (error_step < (cpr->config->dn_threshold +
cpr->config->dn_margin)) {
- pr_debug("DOWN_INT error_step too small to set\n");
+ msm_cpr_debug(MSM_CPR_DEBUG_STEPS,
+ "DOWN_INT error_step=%d is too small to set\n",
+ error_step);
cpr_irq_clr_and_nack(cpr, BIT(2) | BIT(0));
return;
}
+ /**
+ * As per chip characterization recommendation, deduct 2 steps
+ * from down error steps to decrease chances of getting closer
+ * to the system level Vmin, thereby improving stability
+ */
+ error_step -= 2;
+
/* Calculte new PMIC voltage */
new_volt = curr_volt - (error_step * cpr->vp->step_size);
- pr_debug("DOWN_INT: new_volt: %d\n", new_volt);
- pr_info("(DN Voltage recommended by CPR: %d uV)\n", new_volt);
+ msm_cpr_debug(MSM_CPR_DEBUG_STEPS,
+ "DOWN_INT: new_volt: %d, error_step=%d\n",
+ new_volt, error_step);
+ msm_cpr_debug(MSM_CPR_DEBUG_STEPS,
+ "Current RBCPR_GCNT_TARGET(%d): = 0x%x\n",
+ cpr->curr_osc, readl_relaxed(cpr->base +
+ RBCPR_GCNT_TARGET(cpr->curr_osc)) & TARGET_M);
+ msm_cpr_debug(MSM_CPR_DEBUG_STEPS,
+ "(DN Voltage recommended by CPR: %d uV)\n", new_volt);
cpr_dn_event_handler(cpr, new_volt);
}
}
@@ -488,31 +550,36 @@
/* Following sequence of handling is as per each IRQ's priority */
if (reg_val & BIT(4)) {
- pr_debug(" CPR:IRQ %d occured for UP Flag\n", irq);
+ msm_cpr_debug(MSM_CPR_DEBUG_STEPS,
+ "CPR:IRQ %d occured for UP Flag\n", irq);
cpr_set_vdd(cpr, UP);
} else if ((reg_val & BIT(2)) && !(ctl_reg & SW_AUTO_CONT_NACK_DN_EN)) {
- pr_debug(" CPR:IRQ %d occured for Down Flag\n", irq);
+ msm_cpr_debug(MSM_CPR_DEBUG_STEPS,
+ "CPR:IRQ %d occured for Down Flag\n", irq);
cpr_set_vdd(cpr, DOWN);
} else if (reg_val & BIT(1)) {
- pr_debug(" CPR:IRQ %d occured for Min Flag\n", irq);
+ msm_cpr_debug(MSM_CPR_DEBUG_STEPS,
+ "CPR:IRQ %d occured for Min Flag\n", irq);
cpr_irq_clr_and_nack(cpr, BIT(1) | BIT(0));
} else if (reg_val & BIT(5)) {
- pr_debug(" CPR:IRQ %d occured for MAX Flag\n", irq);
+ msm_cpr_debug(MSM_CPR_DEBUG_STEPS,
+ "CPR:IRQ %d occured for MAX Flag\n", irq);
cpr_irq_clr_and_nack(cpr, BIT(5) | BIT(0));
} else if (reg_val & BIT(3)) {
/* SW_AUTO_CONT_ACK_EN is enabled */
- pr_debug(" CPR:IRQ %d occured for Mid Flag\n", irq);
+ msm_cpr_debug(MSM_CPR_DEBUG_STEPS,
+ "CPR:IRQ %d occured for Mid Flag\n", irq);
}
return IRQ_HANDLED;
}
static void cpr_config(struct msm_cpr *cpr)
{
- uint32_t delay_count, cnt = 0, rc, tmp_uV;
+ uint32_t delay_count, cnt = 0, rc;
struct msm_cpr_mode *chip_data;
chip_data = &cpr->config->cpr_mode_data[cpr->cpr_mode];
@@ -543,11 +610,16 @@
* for all the ring oscilators
*/
while (cnt < NUM_OSC) {
+ msm_cpr_debug(MSM_CPR_DEBUG_CONFIG,
+ "Prog:cnt(%d) gcnt=0x%x quot=0x%x\n", cnt,
+ chip_data->ring_osc_data[cnt].gcnt,
+ chip_data->ring_osc_data[cnt].quot);
cpr_modify_reg(cpr, RBCPR_GCNT_TARGET(cnt),
(GCNT_M | TARGET_M),
(chip_data->ring_osc_data[cnt].gcnt << 12 |
chip_data->ring_osc_data[cnt].quot));
- pr_debug("RBCPR_GCNT_TARGET(%d): = 0x%x\n", cnt,
+ msm_cpr_debug(MSM_CPR_DEBUG_CONFIG,
+ "RBCPR_GCNT_TARGET(%d): = 0x%x\n", cnt,
readl_relaxed(cpr->base + RBCPR_GCNT_TARGET(cnt)));
cnt++;
}
@@ -555,16 +627,11 @@
/* Configure the step quot */
cpr_2pt_kv_analysis(cpr, chip_data);
- /**
- * Call the PMIC specific routine to set the voltage
- * Set with an extra step since it helps as per
- * characterization data.
- */
- chip_data->calibrated_uV += cpr->vp->step_size;
- tmp_uV = chip_data->calibrated_uV;
- rc = regulator_set_voltage(cpr->vreg_cx, tmp_uV, tmp_uV);
+ /* Call the PMIC specific routine to set the voltage */
+ rc = regulator_set_voltage(cpr->vreg_cx, chip_data->calibrated_uV,
+ chip_data->calibrated_uV);
if (rc)
- pr_err("%s: Voltage set failed %d\n", __func__, rc);
+ pr_err("Voltage set failed %d\n", rc);
/*
* Program the Timer Register for delay between CPR measurements
@@ -593,19 +660,23 @@
switch (val) {
case CPUFREQ_PRECHANGE:
- pr_debug("pre freq change notification to cpr\n");
-
+ msm_cpr_debug(MSM_CPR_DEBUG_FREQ_TRANS,
+ "pre freq change notification to cpr\n");
/* Disable Measurement to stop generation of CPR IRQs */
cpr_disable(cpr);
/* Disable routing of IRQ to App */
cpr_irq_set(cpr, INT_MASK & ~MID_INT, 0);
disable_irq(cpr->irq);
cpr_write_reg(cpr, RBIF_IRQ_CLEAR, ALL_CPR_IRQ);
- pr_debug("RBCPR_CTL: 0x%x\n",
+
+ msm_cpr_debug(MSM_CPR_DEBUG_FREQ_TRANS,
+ "RBCPR_CTL: 0x%x\n",
readl_relaxed(cpr->base + RBCPR_CTL));
- pr_debug("RBIF_IRQ_STATUS: 0x%x\n",
+ msm_cpr_debug(MSM_CPR_DEBUG_FREQ_TRANS,
+ "RBIF_IRQ_STATUS: 0x%x\n",
cpr_read_reg(cpr, RBIF_IRQ_STATUS));
- pr_debug("RBIF_IRQ_EN(0): 0x%x\n",
+ msm_cpr_debug(MSM_CPR_DEBUG_FREQ_TRANS,
+ "RBIF_IRQ_EN(0): 0x%x\n",
cpr_read_reg(cpr, RBIF_IRQ_EN(cpr->config->irq_line)));
cpr->prev_mode = cpr->cpr_mode;
@@ -634,12 +705,15 @@
new_freq / 1000);
cpr_modify_reg(cpr, RBCPR_GCNT_TARGET(cpr->curr_osc), TARGET_M,
quot);
- pr_debug("RBCPR_GCNT_TARGET(%d): = 0x%x\n", cpr->curr_osc,
+ msm_cpr_debug(MSM_CPR_DEBUG_FREQ_TRANS,
+ "RBCPR_GCNT_TARGET(%d): = 0x%x\n", cpr->curr_osc,
readl_relaxed(cpr->base +
RBCPR_GCNT_TARGET(cpr->curr_osc)));
- pr_debug("%s: new_freq: %d, set_freq: %d, quot: %d\n", __func__,
+ msm_cpr_debug(MSM_CPR_DEBUG_FREQ_TRANS,
+ "new_freq: %d, quot_freq: %d, quot: %d\n",
freqs->new, new_freq, quot);
- pr_info("%s: PVS Voltage setting is: %d\n", __func__,
+ msm_cpr_debug(MSM_CPR_DEBUG_FREQ_TRANS,
+ "PVS Voltage setting is: %d\n",
regulator_get_voltage(cpr->vreg_cx));
enable_irq(cpr->irq);
@@ -656,18 +730,25 @@
if (ctl_reg & SW_AUTO_CONT_NACK_DN_EN)
cpr_modify_reg(cpr, RBCPR_CTL,
SW_AUTO_CONT_NACK_DN_EN_M, 0);
- pr_debug("RBIF_IRQ_EN(0): 0x%x\n",
+ if (cpr->max_volt_set)
+ cpr->max_volt_set = 0;
+
+ msm_cpr_debug(MSM_CPR_DEBUG_FREQ_TRANS,
+ "RBIF_IRQ_EN(0): 0x%x\n",
cpr_read_reg(cpr, RBIF_IRQ_EN(cpr->config->irq_line)));
- pr_debug("RBCPR_CTL: 0x%x\n",
+ msm_cpr_debug(MSM_CPR_DEBUG_FREQ_TRANS,
+ "RBCPR_CTL: 0x%x\n",
readl_relaxed(cpr->base + RBCPR_CTL));
- pr_debug("RBIF_IRQ_STATUS: 0x%x\n",
+ msm_cpr_debug(MSM_CPR_DEBUG_FREQ_TRANS,
+ "RBIF_IRQ_STATUS: 0x%x\n",
cpr_read_reg(cpr, RBIF_IRQ_STATUS));
+
cpr_enable(cpr);
break;
default:
break;
}
- return 0;
+ return NOTIFY_OK;
}
#ifdef CONFIG_PM
@@ -733,12 +814,18 @@
void msm_cpr_pm_resume(void)
{
+ if (!enable)
+ return;
+
msm_cpr_resume(&cpr_pdev->dev);
}
EXPORT_SYMBOL(msm_cpr_pm_resume);
void msm_cpr_pm_suspend(void)
{
+ if (!enable)
+ return;
+
msm_cpr_suspend(&cpr_pdev->dev);
}
EXPORT_SYMBOL(msm_cpr_pm_suspend);
@@ -746,14 +833,26 @@
void msm_cpr_disable(void)
{
- struct msm_cpr *cpr = platform_get_drvdata(cpr_pdev);
+ struct msm_cpr *cpr;
+
+ if (!enable)
+ return;
+
+ cpr = platform_get_drvdata(cpr_pdev);
+
cpr_disable(cpr);
}
EXPORT_SYMBOL(msm_cpr_disable);
void msm_cpr_enable(void)
{
- struct msm_cpr *cpr = platform_get_drvdata(cpr_pdev);
+ struct msm_cpr *cpr;
+
+ if (!enable)
+ return;
+
+ cpr = platform_get_drvdata(cpr_pdev);
+
cpr_enable(cpr);
}
EXPORT_SYMBOL(msm_cpr_enable);
@@ -772,12 +871,15 @@
if (!pdata) {
pr_err("CPR: Platform data is not available\n");
+ enable = false;
return -EIO;
}
cpr = devm_kzalloc(&pdev->dev, sizeof(struct msm_cpr), GFP_KERNEL);
- if (!cpr)
+ if (!cpr) {
+ enable = false;
return -ENOMEM;
+ }
/* Initialize platform_data */
cpr->config = pdata;
@@ -820,7 +922,7 @@
cpr->vp = pdata->vp_data;
- mutex_init(&cpr->cpr_mutex);
+ spin_lock_init(&cpr->cpr_lock);
/* Initialize the Voltage domain for CPR */
cpr->vreg_cx = regulator_get(&pdev->dev, "vddx_cx");
@@ -840,12 +942,15 @@
platform_set_drvdata(pdev, cpr);
chip_data = &cpr->config->cpr_mode_data[cpr->cpr_mode];
- pr_info("CPR Platform Data (upside_steps: %d) (downside_steps: %d) ",
+ msm_cpr_debug(MSM_CPR_DEBUG_CONFIG,
+ "CPR Platform Data (upside_steps: %d) (downside_steps: %d))",
cpr->config->up_threshold, cpr->config->dn_threshold);
- pr_info("(nominal_voltage: %duV) (turbo_voltage: %duV)\n",
+ msm_cpr_debug(MSM_CPR_DEBUG_CONFIG,
+ "(nominal_voltage: %duV) (turbo_voltage: %duV)\n",
cpr->config->cpr_mode_data[NORMAL_MODE].calibrated_uV,
cpr->config->cpr_mode_data[TURBO_MODE].calibrated_uV);
- pr_info("(Current corner: TURBO) (gcnt_target: %d) (quot: %d)\n",
+ msm_cpr_debug(MSM_CPR_DEBUG_CONFIG,
+ "(Current corner: TURBO) (gcnt_target: %d) (quot: %d)\n",
chip_data->ring_osc_data[chip_data->ring_osc].gcnt,
chip_data->ring_osc_data[chip_data->ring_osc].quot);
@@ -880,6 +985,8 @@
cpufreq_register_notifier(&cpr->freq_transition,
CPUFREQ_TRANSITION_NOTIFIER);
+ pr_info("MSM CPR driver successfully registered!\n");
+
return res;
err_reg_get:
@@ -887,6 +994,7 @@
err_ioremap:
iounmap(base);
out:
+ enable = false;
return res;
}
@@ -901,7 +1009,6 @@
regulator_put(cpr->vreg_cx);
free_irq(cpr->irq, cpr);
iounmap(cpr->base);
- mutex_destroy(&cpr->cpr_mutex);
platform_set_drvdata(pdev, NULL);
return 0;
diff --git a/arch/arm/mach-msm/msm_xo.c b/arch/arm/mach-msm/msm_xo.c
index 2d61504..404b350 100644
--- a/arch/arm/mach-msm/msm_xo.c
+++ b/arch/arm/mach-msm/msm_xo.c
@@ -236,7 +236,7 @@
int needs_workaround = cpu_is_msm8960() || cpu_is_apq8064() ||
cpu_is_msm8930() || cpu_is_msm8930aa() ||
cpu_is_msm9615() || cpu_is_msm8627() ||
- cpu_is_msm8960ab();
+ cpu_is_msm8960ab() || cpu_is_apq8064ab();
if (xo_voter->mode == mode)
return 0;
diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c
index f6ed1ea..c9517b6 100644
--- a/arch/arm/mach-msm/platsmp.c
+++ b/arch/arm/mach-msm/platsmp.c
@@ -165,7 +165,8 @@
return krait_release_secondary_sim(0xf9088000, cpu);
if (cpu_is_msm8960() || cpu_is_msm8930() || cpu_is_msm8930aa() ||
- cpu_is_apq8064() || cpu_is_msm8627() || cpu_is_msm8960ab())
+ cpu_is_apq8064() || cpu_is_msm8627() || cpu_is_msm8960ab() ||
+ cpu_is_apq8064ab())
return krait_release_secondary(0x02088000, cpu);
if (cpu_is_msm8974())
diff --git a/arch/arm/mach-msm/qdsp5/audio_mvs.c b/arch/arm/mach-msm/qdsp5/audio_mvs.c
index c0e670c..d45043d 100644
--- a/arch/arm/mach-msm/qdsp5/audio_mvs.c
+++ b/arch/arm/mach-msm/qdsp5/audio_mvs.c
@@ -326,6 +326,7 @@
wait_queue_head_t wait;
wait_queue_head_t mode_wait;
+ wait_queue_head_t in_wait;
wait_queue_head_t out_wait;
struct mutex lock;
@@ -1142,6 +1143,7 @@
mutex_unlock(&audio->in_lock);
+ wake_up(&audio->in_wait);
dl_reply.valid_frame_info_ptr = cpu_to_be32(0x00000001);
dl_reply.frame_mode = cpu_to_be32(audio->frame_mode);
@@ -1449,40 +1451,52 @@
MM_DBG("\n");
- mutex_lock(&audio->in_lock);
- if (audio->state == AUDIO_MVS_STARTED) {
- if (count <= sizeof(struct msm_audio_mvs_frame)) {
- if (!list_empty(&audio->free_in_queue)) {
- buf_node =
- list_first_entry(&audio->free_in_queue,
+ rc = wait_event_interruptible_timeout(audio->in_wait,
+ (!list_empty(&audio->free_in_queue) ||
+ audio->state == AUDIO_MVS_STOPPED), 1 * HZ);
+ if (rc > 0) {
+ mutex_lock(&audio->in_lock);
+ if (audio->state == AUDIO_MVS_STARTED) {
+ if (count <= sizeof(struct msm_audio_mvs_frame)) {
+ if (!list_empty(&audio->free_in_queue)) {
+ buf_node = list_first_entry(
+ &audio->free_in_queue,
struct audio_mvs_buf_node,
list);
- list_del(&buf_node->list);
+ list_del(&buf_node->list);
- rc = copy_from_user(&buf_node->frame,
- buf,
- count);
+ rc = copy_from_user(&buf_node->frame,
+ buf,
+ count);
- list_add_tail(&buf_node->list,
- &audio->in_queue);
+ list_add_tail(&buf_node->list,
+ &audio->in_queue);
+ } else {
+ MM_ERR("No free DL buffs\n");
+ }
} else {
- MM_ERR("No free DL buffs\n");
+ MM_ERR("Write count %d > sizeof(frame) %d",
+ count,
+ sizeof(struct msm_audio_mvs_frame));
+
+ rc = -ENOMEM;
}
} else {
- MM_ERR("Write count %d < sizeof(frame) %d",
- count,
- sizeof(struct msm_audio_mvs_frame));
+ MM_ERR("Write performed in invalid state %d\n",
+ audio->state);
- rc = -ENOMEM;
+ rc = -EPERM;
}
+ mutex_unlock(&audio->in_lock);
+ } else if (rc == 0) {
+ MM_ERR("%s: No free DL buffs\n", __func__);
+
+ rc = -ETIMEDOUT;
} else {
- MM_ERR("Write performed in invalid state %d\n",
- audio->state);
+ MM_ERR("%s: write was interrupted\n", __func__);
- rc = -EPERM;
+ rc = -ERESTARTSYS;
}
- mutex_unlock(&audio->in_lock);
-
return rc;
}
@@ -1599,26 +1613,6 @@
MM_DBG("\n");
- memset(&audio_mvs_info, 0, sizeof(audio_mvs_info));
- mutex_init(&audio_mvs_info.lock);
- mutex_init(&audio_mvs_info.in_lock);
- mutex_init(&audio_mvs_info.out_lock);
-
- init_waitqueue_head(&audio_mvs_info.wait);
- init_waitqueue_head(&audio_mvs_info.mode_wait);
- init_waitqueue_head(&audio_mvs_info.out_wait);
-
- INIT_LIST_HEAD(&audio_mvs_info.in_queue);
- INIT_LIST_HEAD(&audio_mvs_info.free_in_queue);
- INIT_LIST_HEAD(&audio_mvs_info.out_queue);
- INIT_LIST_HEAD(&audio_mvs_info.free_out_queue);
-
- wake_lock_init(&audio_mvs_info.suspend_lock,
- WAKE_LOCK_SUSPEND,
- "audio_mvs_suspend");
- pm_qos_add_request(&audio_mvs_info.pm_qos_req, PM_QOS_CPU_DMA_LATENCY,
- PM_QOS_DEFAULT_VALUE);
-
audio_mvs_info.rpc_endpt = msm_rpc_connect_compatible(MVS_PROG,
MVS_VERS_COMP_VER2,
MSM_RPC_UNINTERRUPTIBLE);
@@ -1702,6 +1696,27 @@
};
static int __init audio_mvs_init(void)
{
+ memset(&audio_mvs_info, 0, sizeof(audio_mvs_info));
+ mutex_init(&audio_mvs_info.lock);
+ mutex_init(&audio_mvs_info.in_lock);
+ mutex_init(&audio_mvs_info.out_lock);
+
+ init_waitqueue_head(&audio_mvs_info.wait);
+ init_waitqueue_head(&audio_mvs_info.mode_wait);
+ init_waitqueue_head(&audio_mvs_info.in_wait);
+ init_waitqueue_head(&audio_mvs_info.out_wait);
+
+ INIT_LIST_HEAD(&audio_mvs_info.in_queue);
+ INIT_LIST_HEAD(&audio_mvs_info.free_in_queue);
+ INIT_LIST_HEAD(&audio_mvs_info.out_queue);
+ INIT_LIST_HEAD(&audio_mvs_info.free_out_queue);
+
+ wake_lock_init(&audio_mvs_info.suspend_lock,
+ WAKE_LOCK_SUSPEND,
+ "audio_mvs_suspend");
+ pm_qos_add_request(&audio_mvs_info.pm_qos_req, PM_QOS_CPU_DMA_LATENCY,
+ PM_QOS_DEFAULT_VALUE);
+
return misc_register(&audio_mvs_misc);
}
diff --git a/arch/arm/mach-msm/qdsp6v2/adsprpc.h b/arch/arm/mach-msm/qdsp6v2/adsprpc.h
index 368b8e6..c6c7d23 100644
--- a/arch/arm/mach-msm/qdsp6v2/adsprpc.h
+++ b/arch/arm/mach-msm/qdsp6v2/adsprpc.h
@@ -24,7 +24,7 @@
#include <linux/cdev.h>
#include <linux/list.h>
#include <linux/hash.h>
-#include <linux/ion.h>
+#include <linux/msm_ion.h>
#include <mach/msm_smd.h>
#include <mach/ion.h>
#include "adsprpc_shared.h"
diff --git a/arch/arm/mach-msm/restart.c b/arch/arm/mach-msm/restart.c
index 5883b0c..2189747 100644
--- a/arch/arm/mach-msm/restart.c
+++ b/arch/arm/mach-msm/restart.c
@@ -36,6 +36,7 @@
#include <mach/scm.h>
#include "msm_watchdog.h"
#include "timer.h"
+#include "wdog_debug.h"
#define WDT0_RST 0x38
#define WDT0_EN 0x40
@@ -250,8 +251,11 @@
__raw_writel(5*0x31F3, msm_tmr0_base + WDT0_BARK_TIME);
__raw_writel(0x31F3, msm_tmr0_base + WDT0_BITE_TIME);
__raw_writel(1, msm_tmr0_base + WDT0_EN);
- } else
+ } else {
+ /* Needed for 8974: Reset GCC_WDOG_DEBUG register */
+ msm_disable_wdog_debug();
__raw_writel(0, MSM_MPM2_PSHOLD_BASE);
+ }
mdelay(10000);
printk(KERN_ERR "Restarting has failed\n");
diff --git a/arch/arm/mach-msm/rpm_resources.c b/arch/arm/mach-msm/rpm_resources.c
index 2a835f7..dfed3aa 100644
--- a/arch/arm/mach-msm/rpm_resources.c
+++ b/arch/arm/mach-msm/rpm_resources.c
@@ -945,7 +945,8 @@
irqs_detectable, gpio_detectable))
continue;
- if (MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE == sleep_mode)
+ if ((MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE == sleep_mode)
+ || (MSM_PM_SLEEP_MODE_POWER_COLLAPSE == sleep_mode))
if (!cpu && msm_rpm_local_request_is_outstanding())
break;
@@ -1131,7 +1132,8 @@
static int __init msm_rpmrs_l2_init(void)
{
if (cpu_is_msm8960() || cpu_is_msm8930() || cpu_is_msm8930aa() ||
- cpu_is_apq8064() || cpu_is_msm8627() || cpu_is_msm8960ab()) {
+ cpu_is_apq8064() || cpu_is_msm8627() || cpu_is_msm8960ab() ||
+ cpu_is_apq8064ab()) {
msm_pm_set_l2_flush_flag(0);
diff --git a/arch/arm/mach-msm/socinfo.c b/arch/arm/mach-msm/socinfo.c
index 86de130..ac077e9 100644
--- a/arch/arm/mach-msm/socinfo.c
+++ b/arch/arm/mach-msm/socinfo.c
@@ -286,6 +286,9 @@
/* 8092 IDs */
[146] = MSM_CPU_8092,
+ /* 8064AB IDs */
+ [153] = MSM_CPU_8064AB,
+
/* Uninitialized IDs are not known to run Linux.
MSM_CPU_UNKNOWN is set to 0 to ensure these IDs are
considered as unknown CPU. */
diff --git a/arch/arm/mach-msm/spm_devices.c b/arch/arm/mach-msm/spm_devices.c
index b87b0f1..feddde8 100644
--- a/arch/arm/mach-msm/spm_devices.c
+++ b/arch/arm/mach-msm/spm_devices.c
@@ -159,7 +159,8 @@
reg = saw_bases[cpu];
if (cpu_is_msm8960() || cpu_is_msm8930() || cpu_is_msm8930aa() ||
- cpu_is_apq8064() || cpu_is_msm8627() || cpu_is_msm8960ab()) {
+ cpu_is_apq8064() || cpu_is_msm8627() || cpu_is_msm8960ab() ||
+ cpu_is_apq8064ab()) {
val = 0xA4;
reg += 0x14;
timeout = 512;
diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
index 668f4cc..b361d9d 100644
--- a/arch/arm/mach-msm/timer.c
+++ b/arch/arm/mach-msm/timer.c
@@ -966,7 +966,7 @@
if (cpu_is_msm8x60() || cpu_is_msm8960() || cpu_is_apq8064() ||
cpu_is_msm8930() || cpu_is_msm8930aa() || cpu_is_msm8627() ||
- cpu_is_msm8960ab())
+ cpu_is_msm8960ab() || cpu_is_apq8064ab())
__raw_writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
if (__get_cpu_var(first_boot)) {
@@ -1064,7 +1064,7 @@
dgt->flags |= MSM_CLOCK_FLAGS_UNSTABLE_COUNT;
} else if (cpu_is_msm8960() || cpu_is_apq8064() || cpu_is_msm8930() ||
cpu_is_msm8930aa() || cpu_is_msm8627() ||
- cpu_is_msm8960ab()) {
+ cpu_is_msm8960ab() || cpu_is_apq8064ab()) {
global_timer_offset = MSM_TMR0_BASE - MSM_TMR_BASE;
dgt->freq = 6750000;
__raw_writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
@@ -1127,7 +1127,7 @@
if (cpu_is_msm8x60() || cpu_is_msm8960() || cpu_is_apq8064() ||
cpu_is_msm8930() || cpu_is_msm9615() || cpu_is_msm8625() ||
cpu_is_msm8627() || cpu_is_msm8930aa() ||
- cpu_is_msm8960ab()) {
+ cpu_is_msm8960ab() || cpu_is_apq8064ab()) {
clock->percpu_evt = alloc_percpu(struct clock_event_device *);
if (!clock->percpu_evt) {
pr_err("msm_timer_init: memory allocation "
diff --git a/arch/arm/mach-msm/wcnss-ssr-8974.c b/arch/arm/mach-msm/wcnss-ssr-8974.c
index d8745fc..b837efc 100644
--- a/arch/arm/mach-msm/wcnss-ssr-8974.c
+++ b/arch/arm/mach-msm/wcnss-ssr-8974.c
@@ -25,7 +25,7 @@
static int wcnss_crash;
static struct subsys_device *wcnss_ssr_dev;
-#define WCNSS_APSS_WDOG_BITE_RESET_RDY_IRQ 231
+#define WCNSS_APSS_WDOG_BITE_RESET_RDY_IRQ 181
static void log_wcnss_sfr(void)
{
diff --git a/arch/arm/mach-msm/wdog_debug.c b/arch/arm/mach-msm/wdog_debug.c
new file mode 100644
index 0000000..82800cf
--- /dev/null
+++ b/arch/arm/mach-msm/wdog_debug.c
@@ -0,0 +1,149 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/mutex.h>
+#include <linux/sched.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <mach/scm.h>
+#include <linux/slab.h>
+
+#define MODULE_NAME "wdog_debug"
+#define WDOG_DEBUG_EN 17
+#define GCC_WDOG_DEBUG_OFFSET 0x780
+
+struct msm_wdog_debug_data {
+ unsigned int __iomem phys_base;
+ size_t size;
+ void __iomem *base;
+ struct device *dev;
+};
+
+static struct msm_wdog_debug_data *wdog_data;
+
+void msm_disable_wdog_debug(void)
+{
+ unsigned long int value;
+
+ if (wdog_data == NULL)
+ return;
+ value = readl_relaxed(wdog_data->base + GCC_WDOG_DEBUG_OFFSET);
+ value &= ~BIT(WDOG_DEBUG_EN);
+ writel_relaxed(value, wdog_data->base + GCC_WDOG_DEBUG_OFFSET);
+}
+EXPORT_SYMBOL(msm_disable_wdog_debug);
+
+void msm_enable_wdog_debug(void)
+{
+ unsigned long int value;
+
+ if (wdog_data == NULL)
+ return;
+ value = readl_relaxed(wdog_data->base + GCC_WDOG_DEBUG_OFFSET);
+ value |= BIT(WDOG_DEBUG_EN);
+ writel_relaxed(value, wdog_data->base + GCC_WDOG_DEBUG_OFFSET);
+}
+EXPORT_SYMBOL(msm_enable_wdog_debug);
+
+static int __devexit msm_wdog_debug_remove(struct platform_device *pdev)
+{
+ kfree(wdog_data);
+ wdog_data = NULL;
+ pr_info("MSM wdog_debug Exit - Deactivated\n");
+ return 0;
+}
+
+static int __devinit msm_wdog_debug_dt_to_pdata(struct platform_device *pdev,
+ struct msm_wdog_debug_data *pdata)
+{
+ struct resource *wdog_resource;
+
+ wdog_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!wdog_resource) {
+ dev_err(&pdev->dev, \
+ "%s cannot allocate resource for wdog_debug\n", \
+ __func__);
+ return -ENXIO;
+ }
+ pdata->size = resource_size(wdog_resource);
+ pdata->phys_base = wdog_resource->start;
+ if (unlikely(!(devm_request_region(&pdev->dev, pdata->phys_base,
+ pdata->size, "msm-wdog-debug")))) {
+ dev_err(&pdev->dev, "%s cannot reserve wdog_debug region\n",
+ __func__);
+ return -ENXIO;
+ }
+ pdata->base = devm_ioremap(&pdev->dev, pdata->phys_base,
+ pdata->size);
+ if (!pdata->base) {
+ dev_err(&pdev->dev, "%s cannot map wdog register space\n",
+ __func__);
+ return -ENXIO;
+ }
+
+ return 0;
+}
+
+static int __devinit msm_wdog_debug_probe(struct platform_device *pdev)
+{
+ int ret;
+ if (!pdev->dev.of_node)
+ return -ENODEV;
+ wdog_data = kzalloc(sizeof(struct msm_wdog_debug_data), GFP_KERNEL);
+ if (!wdog_data)
+ return -ENOMEM;
+ ret = msm_wdog_debug_dt_to_pdata(pdev, wdog_data);
+ if (ret)
+ goto err;
+ wdog_data->dev = &pdev->dev;
+ platform_set_drvdata(pdev, wdog_data);
+ msm_enable_wdog_debug();
+ return 0;
+err:
+ kzfree(wdog_data);
+ wdog_data = NULL;
+ return ret;
+}
+
+static struct of_device_id msm_wdog_debug_match_table[] = {
+ { .compatible = "qcom,msm-wdog-debug" },
+ {}
+};
+
+static struct platform_driver msm_wdog_debug_driver = {
+ .probe = msm_wdog_debug_probe,
+ .remove = msm_wdog_debug_remove,
+ .driver = {
+ .name = MODULE_NAME,
+ .owner = THIS_MODULE,
+ .of_match_table = msm_wdog_debug_match_table,
+ },
+};
+
+static int __devinit wdog_debug_init(void)
+{
+ return platform_driver_register(&msm_wdog_debug_driver);
+}
+module_init(wdog_debug_init);
+
+static void __exit wdog_debug_exit(void)
+{
+ platform_driver_unregister(&msm_wdog_debug_driver);
+}
+module_exit(wdog_debug_exit);
+
+MODULE_DESCRIPTION("MSM Driver to disable debug Image");
+MODULE_LICENSE("GPL v2");
diff --git a/arch/arm/mach-msm/wdog_debug.h b/arch/arm/mach-msm/wdog_debug.h
new file mode 100644
index 0000000..920aa89
--- /dev/null
+++ b/arch/arm/mach-msm/wdog_debug.h
@@ -0,0 +1,24 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __WDOG_DEBUG_H
+#define __WDOG_DEBUG_H
+
+#ifdef CONFIG_MSM_ENABLE_WDOG_DEBUG_CONTROL
+void msm_enable_wdog_debug(void);
+void msm_disable_wdog_debug(void);
+#else
+void msm_enable_wdog_debug(void) { }
+void msm_disable_wdog_debug(void) { }
+#endif
+
+#endif
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 47dab27..ba93e68 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -393,6 +393,16 @@
.size __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info
/*
+ * Qualcomm Inc. Krait processors.
+ */
+ .type __krait_proc_info, #object
+__krait_proc_info:
+ .long 0x510f0400 @ Required ID value
+ .long 0xff0ffc00 @ Mask for ID
+ __v7_proc __v7_setup, hwcaps = HWCAP_IDIV
+ .size __krait_proc_info, . - __krait_proc_info
+
+ /*
* Match any ARMv7 processor core.
*/
.type __v7_proc_info, #object
diff --git a/drivers/char/diag/Makefile b/drivers/char/diag/Makefile
index ea75ffd..6ecc970 100644
--- a/drivers/char/diag/Makefile
+++ b/drivers/char/diag/Makefile
@@ -2,4 +2,4 @@
obj-$(CONFIG_DIAG_SDIO_PIPE) += diagfwd_sdio.o
obj-$(CONFIG_DIAG_BRIDGE_CODE) += diagfwd_hsic.o
obj-$(CONFIG_DIAG_BRIDGE_CODE) += diagfwd_smux.o
-diagchar-objs := diagchar_core.o diagchar_hdlc.o diagfwd.o diagmem.o diagfwd_cntl.o diag_dci.o
+diagchar-objs := diagchar_core.o diagchar_hdlc.o diagfwd.o diagmem.o diagfwd_cntl.o diag_dci.o diag_masks.o diag_debugfs.o
diff --git a/drivers/char/diag/diag_debugfs.c b/drivers/char/diag/diag_debugfs.c
new file mode 100644
index 0000000..ed0f08e
--- /dev/null
+++ b/drivers/char/diag/diag_debugfs.c
@@ -0,0 +1,305 @@
+/* Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifdef CONFIG_DEBUG_FS
+
+#include <linux/slab.h>
+#include <linux/debugfs.h>
+#include "diagchar.h"
+#include "diagfwd.h"
+
+#define DEBUG_BUF_SIZE 4096
+static struct dentry *diag_dbgfs_dent;
+static int diag_dbgfs_table_index;
+
+static ssize_t diag_dbgfs_read_status(struct file *file, char __user *ubuf,
+ size_t count, loff_t *ppos)
+{
+ char *buf;
+ int ret;
+
+ buf = kzalloc(sizeof(char) * DEBUG_BUF_SIZE, GFP_KERNEL);
+ if (!buf) {
+ pr_err("diag: %s, Error allocating memory\n", __func__);
+ return -ENOMEM;
+ }
+
+ ret = scnprintf(buf, DEBUG_BUF_SIZE,
+ "modem ch: 0x%x\n"
+ "lpass ch: 0x%x\n"
+ "riva ch: 0x%x\n"
+ "dci ch: 0x%x\n"
+ "modem cntl_ch: 0x%x\n"
+ "lpass cntl_ch: 0x%x\n"
+ "riva cntl_ch: 0x%x\n"
+ "CPU Tools id: %d\n"
+ "Apps only: %d\n"
+ "Apps master: %d\n"
+ "Check Polling Response: %d\n"
+ "polling_reg_flag: %d\n"
+ "uses device tree: %d\n"
+ "in_busy_1: %d\n"
+ "in_busy_2: %d\n"
+ "in_busy_lpass_1: %d\n"
+ "in_busy_lpass_2: %d\n"
+ "in_busy_wcnss_1: %d\n"
+ "in_busy_wcnss_2: %d\n"
+ "in_busy_dci: %d\n"
+ "logging_mode: %d\n",
+ (unsigned int)driver->ch,
+ (unsigned int)driver->chlpass,
+ (unsigned int)driver->ch_wcnss,
+ (unsigned int)driver->ch_dci,
+ (unsigned int)driver->ch_cntl,
+ (unsigned int)driver->chlpass_cntl,
+ (unsigned int)driver->ch_wcnss_cntl,
+ chk_config_get_id(),
+ chk_apps_only(),
+ chk_apps_master(),
+ chk_polling_response(),
+ driver->polling_reg_flag,
+ driver->use_device_tree,
+ driver->in_busy_1,
+ driver->in_busy_2,
+ driver->in_busy_lpass_1,
+ driver->in_busy_lpass_2,
+ driver->in_busy_wcnss_1,
+ driver->in_busy_wcnss_2,
+ driver->in_busy_dci,
+ driver->logging_mode);
+
+#ifdef CONFIG_DIAG_OVER_USB
+ ret += scnprintf(buf+ret, DEBUG_BUF_SIZE,
+ "usb_connected: %d\n",
+ driver->usb_connected);
+#endif
+ ret = simple_read_from_buffer(ubuf, count, ppos, buf, ret);
+
+ kfree(buf);
+ return ret;
+}
+
+static ssize_t diag_dbgfs_read_workpending(struct file *file,
+ char __user *ubuf, size_t count, loff_t *ppos)
+{
+ char *buf;
+ int ret;
+
+ buf = kzalloc(sizeof(char) * DEBUG_BUF_SIZE, GFP_KERNEL);
+ if (!buf) {
+ pr_err("diag: %s, Error allocating memory\n", __func__);
+ return -ENOMEM;
+ }
+
+ ret = scnprintf(buf, DEBUG_BUF_SIZE,
+ "Pending status for work_stucts:\n"
+ "diag_drain_work: %d\n"
+ "diag_read_smd_work: %d\n"
+ "diag_read_smd_cntl_work: %d\n"
+ "diag_read_smd_lpass_work: %d\n"
+ "diag_read_smd_lpass_cntl_work: %d\n"
+ "diag_read_smd_wcnss_work: %d\n"
+ "diag_read_smd_wcnss_cntl_work: %d\n"
+ "diag_modem_mask_update_work: %d\n"
+ "diag_lpass_mask_update_work: %d\n"
+ "diag_wcnss_mask_update_work: %d\n"
+ "diag_read_smd_dci_work: %d\n",
+ work_pending(&(driver->diag_drain_work)),
+ work_pending(&(driver->diag_read_smd_work)),
+ work_pending(&(driver->diag_read_smd_cntl_work)),
+ work_pending(&(driver->diag_read_smd_lpass_work)),
+ work_pending(&(driver->diag_read_smd_lpass_cntl_work)),
+ work_pending(&(driver->diag_read_smd_wcnss_work)),
+ work_pending(&(driver->diag_read_smd_wcnss_cntl_work)),
+ work_pending(&(driver->diag_modem_mask_update_work)),
+ work_pending(&(driver->diag_lpass_mask_update_work)),
+ work_pending(&(driver->diag_wcnss_mask_update_work)),
+ work_pending(&(driver->diag_read_smd_dci_work)));
+
+#ifdef CONFIG_DIAG_OVER_USB
+ ret += scnprintf(buf+ret, DEBUG_BUF_SIZE,
+ "diag_proc_hdlc_work: %d\n"
+ "diag_read_work: %d\n",
+ work_pending(&(driver->diag_proc_hdlc_work)),
+ work_pending(&(driver->diag_read_work)));
+#endif
+ ret = simple_read_from_buffer(ubuf, count, ppos, buf, ret);
+
+ kfree(buf);
+ return ret;
+}
+
+static ssize_t diag_dbgfs_read_table(struct file *file, char __user *ubuf,
+ size_t count, loff_t *ppos)
+{
+ char *buf;
+ int ret = 0;
+ int i;
+ int bytes_remaining;
+ int bytes_in_buffer = 0;
+ int bytes_written;
+ int buf_size = (DEBUG_BUF_SIZE < count) ? DEBUG_BUF_SIZE : count;
+
+ if (diag_dbgfs_table_index >= diag_max_reg) {
+ /* Done. Reset to prepare for future requests */
+ diag_dbgfs_table_index = 0;
+ return 0;
+ }
+
+ buf = kzalloc(sizeof(char) * buf_size, GFP_KERNEL);
+ if (!buf) {
+ pr_err("diag: %s, Error allocating memory\n", __func__);
+ return -ENOMEM;
+ }
+
+ bytes_remaining = buf_size;
+ for (i = diag_dbgfs_table_index; i < diag_max_reg; i++) {
+ /* Do not process empty entries in the table */
+ if (driver->table[i].process_id == 0)
+ continue;
+
+ bytes_written = scnprintf(buf+bytes_in_buffer, bytes_remaining,
+ "i: %3d, cmd_code: %4x, subsys_id: %4x, "
+ "client: %2d, cmd_code_lo: %4x, "
+ "cmd_code_hi: %4x, process_id: %5d\n",
+ i,
+ driver->table[i].cmd_code,
+ driver->table[i].subsys_id,
+ driver->table[i].client_id,
+ driver->table[i].cmd_code_lo,
+ driver->table[i].cmd_code_hi,
+ driver->table[i].process_id);
+
+ bytes_in_buffer += bytes_written;
+
+ /* Check if there is room to add another table entry */
+ bytes_remaining = buf_size - bytes_in_buffer;
+ if (bytes_remaining < bytes_written)
+ break;
+ }
+ diag_dbgfs_table_index = i;
+
+ *ppos = 0;
+ ret = simple_read_from_buffer(ubuf, count, ppos, buf, bytes_in_buffer);
+
+ kfree(buf);
+ return ret;
+}
+
+#ifdef CONFIG_DIAG_BRIDGE_CODE
+static ssize_t diag_dbgfs_read_hsic(struct file *file, char __user *ubuf,
+ size_t count, loff_t *ppos)
+{
+ char *buf;
+ int ret;
+
+ buf = kzalloc(sizeof(char) * DEBUG_BUF_SIZE, GFP_KERNEL);
+ if (!buf) {
+ pr_err("diag: %s, Error allocating memory\n", __func__);
+ return -ENOMEM;
+ }
+
+ ret = scnprintf(buf, DEBUG_BUF_SIZE,
+ "hsic ch: %d\n"
+ "hsic_inited: %d\n"
+ "hsic enabled: %d\n"
+ "hsic_opened: %d\n"
+ "hsic_suspend: %d\n"
+ "in_busy_hsic_read_on_device: %d\n"
+ "in_busy_hsic_write: %d\n"
+ "count_hsic_pool: %d\n"
+ "count_hsic_write_pool: %d\n"
+ "diag_hsic_pool: %x\n"
+ "diag_hsic_write_pool: %x\n"
+ "write_len_mdm: %d\n"
+ "num_hsic_buf_tbl_entries: %d\n"
+ "usb_mdm_connected: %d\n"
+ "diag_read_mdm_work: %d\n"
+ "diag_read_hsic_work: %d\n"
+ "diag_disconnect_work: %d\n"
+ "diag_usb_read_complete_work: %d\n",
+ driver->hsic_ch,
+ driver->hsic_inited,
+ driver->hsic_device_enabled,
+ driver->hsic_device_opened,
+ driver->hsic_suspend,
+ driver->in_busy_hsic_read_on_device,
+ driver->in_busy_hsic_write,
+ driver->count_hsic_pool,
+ driver->count_hsic_write_pool,
+ (unsigned int)driver->diag_hsic_pool,
+ (unsigned int)driver->diag_hsic_write_pool,
+ driver->write_len_mdm,
+ driver->num_hsic_buf_tbl_entries,
+ driver->usb_mdm_connected,
+ work_pending(&(driver->diag_read_mdm_work)),
+ work_pending(&(driver->diag_read_hsic_work)),
+ work_pending(&(driver->diag_disconnect_work)),
+ work_pending(&(driver->diag_usb_read_complete_work)));
+
+ ret = simple_read_from_buffer(ubuf, count, ppos, buf, ret);
+
+ kfree(buf);
+ return ret;
+}
+
+const struct file_operations diag_dbgfs_hsic_ops = {
+ .read = diag_dbgfs_read_hsic,
+};
+#endif
+
+const struct file_operations diag_dbgfs_status_ops = {
+ .read = diag_dbgfs_read_status,
+};
+
+const struct file_operations diag_dbgfs_table_ops = {
+ .read = diag_dbgfs_read_table,
+};
+
+const struct file_operations diag_dbgfs_workpending_ops = {
+ .read = diag_dbgfs_read_workpending,
+};
+
+void diag_debugfs_init(void)
+{
+ diag_dbgfs_dent = debugfs_create_dir("diag", 0);
+ if (IS_ERR(diag_dbgfs_dent))
+ return;
+
+ debugfs_create_file("status", 0444, diag_dbgfs_dent, 0,
+ &diag_dbgfs_status_ops);
+
+ debugfs_create_file("table", 0444, diag_dbgfs_dent, 0,
+ &diag_dbgfs_table_ops);
+
+ debugfs_create_file("work_pending", 0444, diag_dbgfs_dent, 0,
+ &diag_dbgfs_workpending_ops);
+
+#ifdef CONFIG_DIAG_BRIDGE_CODE
+ debugfs_create_file("hsic", 0444, diag_dbgfs_dent, 0,
+ &diag_dbgfs_hsic_ops);
+#endif
+
+ diag_dbgfs_table_index = 0;
+}
+
+void diag_debugfs_cleanup(void)
+{
+ if (diag_dbgfs_dent) {
+ debugfs_remove_recursive(diag_dbgfs_dent);
+ diag_dbgfs_dent = NULL;
+ }
+}
+#else
+void diag_debugfs_init(void) { }
+void diag_debugfs_cleanup(void) { }
+#endif
diff --git a/drivers/char/diag/diag_debugfs.h b/drivers/char/diag/diag_debugfs.h
new file mode 100644
index 0000000..4bc8b0f
--- /dev/null
+++ b/drivers/char/diag/diag_debugfs.h
@@ -0,0 +1,19 @@
+/* Copyright (c)2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef DIAG_DEBUGFS_H
+#define DIAG_DEBUGFS_H
+
+void diag_debugfs_init(void);
+void diag_debugfs_cleanup(void);
+
+#endif
diff --git a/drivers/char/diag/diag_masks.c b/drivers/char/diag/diag_masks.c
new file mode 100644
index 0000000..5316548
--- /dev/null
+++ b/drivers/char/diag/diag_masks.c
@@ -0,0 +1,790 @@
+/* Copyright (c) 2008-2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/diagchar.h>
+#include <linux/kmemleak.h>
+#include <linux/workqueue.h>
+#include "diagchar.h"
+#include "diagfwd_cntl.h"
+#include "diag_masks.h"
+
+int diag_event_config;
+int diag_event_num_bytes;
+
+#define ALL_EQUIP_ID 100
+#define ALL_SSID -1
+#define MAX_SSID_PER_RANGE 100
+
+struct mask_info {
+ int equip_id;
+ int num_items;
+ int index;
+};
+
+#define CREATE_MSG_MASK_TBL_ROW(XX) \
+do { \
+ *(int *)(msg_mask_tbl_ptr) = MSG_SSID_ ## XX; \
+ msg_mask_tbl_ptr += 4; \
+ *(int *)(msg_mask_tbl_ptr) = MSG_SSID_ ## XX ## _LAST; \
+ msg_mask_tbl_ptr += 4; \
+ /* mimic the last entry as actual_last while creation */ \
+ *(int *)(msg_mask_tbl_ptr) = MSG_SSID_ ## XX ## _LAST; \
+ msg_mask_tbl_ptr += 4; \
+ /* increment by MAX_SSID_PER_RANGE cells */ \
+ msg_mask_tbl_ptr += MAX_SSID_PER_RANGE * sizeof(int); \
+} while (0)
+
+#define WAIT_FOR_SMD(num_delays, delay_time) \
+do { \
+ int count; \
+ for (count = 0; count < (num_delays); count++) \
+ udelay((delay_time)); \
+} while (0)
+
+static void diag_print_mask_table(void)
+{
+/* Enable this to print mask table when updated */
+#ifdef MASK_DEBUG
+ int first, last, actual_last;
+ uint8_t *ptr = driver->msg_masks;
+ int i = 0;
+ pr_info("diag: F3 message mask table\n");
+ while (*(uint32_t *)(ptr + 4)) {
+ first = *(uint32_t *)ptr;
+ ptr += 4;
+ last = *(uint32_t *)ptr;
+ ptr += 4;
+ actual_last = *(uint32_t *)ptr;
+ ptr += 4;
+ pr_info("diag: SSID %d, %d - %d\n", first, last, actual_last);
+ for (i = 0 ; i <= actual_last - first ; i++)
+ pr_info("diag: MASK:%x\n", *((uint32_t *)ptr + i));
+ ptr += MAX_SSID_PER_RANGE*4;
+ }
+#endif
+}
+
+void diag_create_msg_mask_table(void)
+{
+ uint8_t *msg_mask_tbl_ptr = driver->msg_masks;
+
+ CREATE_MSG_MASK_TBL_ROW(0);
+ CREATE_MSG_MASK_TBL_ROW(1);
+ CREATE_MSG_MASK_TBL_ROW(2);
+ CREATE_MSG_MASK_TBL_ROW(3);
+ CREATE_MSG_MASK_TBL_ROW(4);
+ CREATE_MSG_MASK_TBL_ROW(5);
+ CREATE_MSG_MASK_TBL_ROW(6);
+ CREATE_MSG_MASK_TBL_ROW(7);
+ CREATE_MSG_MASK_TBL_ROW(8);
+ CREATE_MSG_MASK_TBL_ROW(9);
+ CREATE_MSG_MASK_TBL_ROW(10);
+ CREATE_MSG_MASK_TBL_ROW(11);
+ CREATE_MSG_MASK_TBL_ROW(12);
+ CREATE_MSG_MASK_TBL_ROW(13);
+ CREATE_MSG_MASK_TBL_ROW(14);
+ CREATE_MSG_MASK_TBL_ROW(15);
+ CREATE_MSG_MASK_TBL_ROW(16);
+ CREATE_MSG_MASK_TBL_ROW(17);
+ CREATE_MSG_MASK_TBL_ROW(18);
+ CREATE_MSG_MASK_TBL_ROW(19);
+ CREATE_MSG_MASK_TBL_ROW(20);
+ CREATE_MSG_MASK_TBL_ROW(21);
+ CREATE_MSG_MASK_TBL_ROW(22);
+ CREATE_MSG_MASK_TBL_ROW(23);
+}
+
+static void diag_set_msg_mask(int rt_mask)
+{
+ int first_ssid, last_ssid, i;
+ uint8_t *parse_ptr, *ptr = driver->msg_masks;
+
+ mutex_lock(&driver->diagchar_mutex);
+ while (*(uint32_t *)(ptr + 4)) {
+ first_ssid = *(uint32_t *)ptr;
+ ptr += 8; /* increment by 8 to skip 'last' */
+ last_ssid = *(uint32_t *)ptr;
+ ptr += 4;
+ parse_ptr = ptr;
+ pr_debug("diag: updating range %d %d\n", first_ssid, last_ssid);
+ for (i = 0; i < last_ssid - first_ssid + 1; i++) {
+ *(int *)parse_ptr = rt_mask;
+ parse_ptr += 4;
+ }
+ ptr += MAX_SSID_PER_RANGE * 4;
+ }
+ mutex_unlock(&driver->diagchar_mutex);
+}
+
+static void diag_update_msg_mask(int start, int end , uint8_t *buf)
+{
+ int found = 0, first, last, actual_last;
+ uint8_t *actual_last_ptr;
+ uint8_t *ptr = driver->msg_masks;
+ uint8_t *ptr_buffer_start = &(*(driver->msg_masks));
+ uint8_t *ptr_buffer_end = &(*(driver->msg_masks)) + MSG_MASK_SIZE;
+
+ mutex_lock(&driver->diagchar_mutex);
+
+ /* First SSID can be zero : So check that last is non-zero */
+ while (*(uint32_t *)(ptr + 4)) {
+ first = *(uint32_t *)ptr;
+ ptr += 4;
+ last = *(uint32_t *)ptr;
+ ptr += 4;
+ actual_last = *(uint32_t *)ptr;
+ actual_last_ptr = ptr;
+ ptr += 4;
+ if (start >= first && start <= actual_last) {
+ ptr += (start - first)*4;
+ if (end > actual_last) {
+ pr_info("diag: ssid range mismatch\n");
+ actual_last = end;
+ *(uint32_t *)(actual_last_ptr) = end;
+ }
+ if (CHK_OVERFLOW(ptr_buffer_start, ptr, ptr_buffer_end,
+ (((end - start)+1)*4))) {
+ pr_debug("diag: update ssid start %d, end %d\n",
+ start, end);
+ memcpy(ptr, buf , ((end - start)+1)*4);
+ } else
+ pr_alert("diag: Not enough space MSG_MASK\n");
+ found = 1;
+ break;
+ } else {
+ ptr += MAX_SSID_PER_RANGE*4;
+ }
+ }
+ /* Entry was not found - add new table */
+ if (!found) {
+ if (CHK_OVERFLOW(ptr_buffer_start, ptr, ptr_buffer_end,
+ 8 + ((end - start) + 1)*4)) {
+ memcpy(ptr, &(start) , 4);
+ ptr += 4;
+ memcpy(ptr, &(end), 4);
+ ptr += 4;
+ memcpy(ptr, &(end), 4); /* create actual_last entry */
+ ptr += 4;
+ pr_debug("diag: adding NEW ssid start %d, end %d\n",
+ start, end);
+ memcpy(ptr, buf , ((end - start) + 1)*4);
+ } else
+ pr_alert("diag: Not enough buffer space for MSG_MASK\n");
+ }
+ mutex_unlock(&driver->diagchar_mutex);
+ diag_print_mask_table();
+}
+
+void diag_toggle_event_mask(int toggle)
+{
+ uint8_t *ptr = driver->event_masks;
+
+ mutex_lock(&driver->diagchar_mutex);
+ if (toggle)
+ memset(ptr, 0xFF, EVENT_MASK_SIZE);
+ else
+ memset(ptr, 0, EVENT_MASK_SIZE);
+ mutex_unlock(&driver->diagchar_mutex);
+}
+
+
+static void diag_update_event_mask(uint8_t *buf, int toggle, int num_bytes)
+{
+ uint8_t *ptr = driver->event_masks;
+ uint8_t *temp = buf + 2;
+
+ mutex_lock(&driver->diagchar_mutex);
+ if (!toggle)
+ memset(ptr, 0 , EVENT_MASK_SIZE);
+ else
+ if (CHK_OVERFLOW(ptr, ptr,
+ ptr+EVENT_MASK_SIZE, num_bytes))
+ memcpy(ptr, temp , num_bytes);
+ else
+ printk(KERN_CRIT "Not enough buffer space for EVENT_MASK\n");
+ mutex_unlock(&driver->diagchar_mutex);
+}
+
+static void diag_disable_log_mask(void)
+{
+ int i = 0;
+ struct mask_info *parse_ptr = (struct mask_info *)(driver->log_masks);
+
+ pr_debug("diag: disable log masks\n");
+ mutex_lock(&driver->diagchar_mutex);
+ for (i = 0; i < MAX_EQUIP_ID; i++) {
+ pr_debug("diag: equip id %d\n", parse_ptr->equip_id);
+ if (!(parse_ptr->equip_id)) /* Reached a null entry */
+ break;
+ memset(driver->log_masks + parse_ptr->index, 0,
+ (parse_ptr->num_items + 7)/8);
+ parse_ptr++;
+ }
+ mutex_unlock(&driver->diagchar_mutex);
+}
+
+int chk_equip_id_and_mask(int equip_id, uint8_t *buf)
+{
+ int i = 0, flag = 0, num_items, offset;
+ unsigned char *ptr_data;
+ struct mask_info *ptr = (struct mask_info *)(driver->log_masks);
+
+ pr_debug("diag: received equip id = %d\n", equip_id);
+ /* Check if this is valid equipment ID */
+ for (i = 0; i < MAX_EQUIP_ID; i++) {
+ if ((ptr->equip_id == equip_id) && (ptr->index != 0)) {
+ offset = ptr->index;
+ num_items = ptr->num_items;
+ flag = 1;
+ break;
+ }
+ ptr++;
+ }
+ if (!flag)
+ return -EPERM;
+ ptr_data = driver->log_masks + offset;
+ memcpy(buf, ptr_data, (num_items+7)/8);
+ return 0;
+}
+
+static void diag_update_log_mask(int equip_id, uint8_t *buf, int num_items)
+{
+ uint8_t *temp = buf;
+ int i = 0;
+ unsigned char *ptr_data;
+ int offset = (sizeof(struct mask_info))*MAX_EQUIP_ID;
+ struct mask_info *ptr = (struct mask_info *)(driver->log_masks);
+
+ pr_debug("diag: received equip id = %d\n", equip_id);
+ mutex_lock(&driver->diagchar_mutex);
+ /* Check if we already know index of this equipment ID */
+ for (i = 0; i < MAX_EQUIP_ID; i++) {
+ if ((ptr->equip_id == equip_id) && (ptr->index != 0)) {
+ offset = ptr->index;
+ break;
+ }
+ if ((ptr->equip_id == 0) && (ptr->index == 0)) {
+ /* Reached a null entry */
+ ptr->equip_id = equip_id;
+ ptr->num_items = num_items;
+ ptr->index = driver->log_masks_length;
+ offset = driver->log_masks_length;
+ driver->log_masks_length += ((num_items+7)/8);
+ break;
+ }
+ ptr++;
+ }
+ ptr_data = driver->log_masks + offset;
+ if (CHK_OVERFLOW(driver->log_masks, ptr_data, driver->log_masks
+ + LOG_MASK_SIZE, (num_items+7)/8))
+ memcpy(ptr_data, temp , (num_items+7)/8);
+ else
+ pr_err("diag: Not enough buffer space for LOG_MASK\n");
+ mutex_unlock(&driver->diagchar_mutex);
+}
+
+void diag_modem_mask_update_fn(struct work_struct *work)
+{
+ diag_send_msg_mask_update(driver->ch_cntl, ALL_SSID,
+ ALL_SSID, MODEM_PROC);
+ diag_send_log_mask_update(driver->ch_cntl, ALL_EQUIP_ID);
+ diag_send_event_mask_update(driver->ch_cntl, diag_event_num_bytes);
+}
+
+void diag_lpass_mask_update_fn(struct work_struct *work)
+{
+ diag_send_msg_mask_update(driver->chlpass_cntl, ALL_SSID,
+ ALL_SSID, LPASS_PROC);
+ diag_send_log_mask_update(driver->chlpass_cntl, ALL_EQUIP_ID);
+ diag_send_event_mask_update(driver->chlpass_cntl, diag_event_num_bytes);
+}
+
+void diag_wcnss_mask_update_fn(struct work_struct *work)
+{
+ diag_send_msg_mask_update(driver->ch_wcnss_cntl, ALL_SSID,
+ ALL_SSID, WCNSS_PROC);
+ diag_send_log_mask_update(driver->ch_wcnss_cntl, ALL_EQUIP_ID);
+ diag_send_event_mask_update(driver->ch_wcnss_cntl,
+ diag_event_num_bytes);
+}
+
+void diag_send_log_mask_update(smd_channel_t *ch, int equip_id)
+{
+ void *buf = driver->buf_log_mask_update;
+ int header_size = sizeof(struct diag_ctrl_log_mask);
+ struct mask_info *ptr = (struct mask_info *)driver->log_masks;
+ int i, size, wr_size = -ENOMEM, retry_count = 0;
+
+ mutex_lock(&driver->diag_cntl_mutex);
+ for (i = 0; i < MAX_EQUIP_ID; i++) {
+ size = (ptr->num_items+7)/8;
+ /* reached null entry */
+ if ((ptr->equip_id == 0) && (ptr->index == 0))
+ break;
+ driver->log_mask->cmd_type = DIAG_CTRL_MSG_LOG_MASK;
+ driver->log_mask->num_items = ptr->num_items;
+ driver->log_mask->data_len = 11 + size;
+ driver->log_mask->stream_id = 1; /* 2, if dual stream */
+ driver->log_mask->status = 3; /* status for valid mask */
+ driver->log_mask->equip_id = ptr->equip_id;
+ driver->log_mask->log_mask_size = size;
+ /* send only desired update, NOT ALL */
+ if (equip_id == ALL_EQUIP_ID || equip_id ==
+ driver->log_mask->equip_id) {
+ memcpy(buf, driver->log_mask, header_size);
+ memcpy(buf+header_size, driver->log_masks+ptr->index,
+ size);
+ if (ch) {
+ while (retry_count < 3) {
+ wr_size = smd_write(ch, buf,
+ header_size + size);
+ if (wr_size == -ENOMEM) {
+ retry_count++;
+ WAIT_FOR_SMD(5, 2000);
+ } else
+ break;
+ }
+ if (wr_size != header_size + size)
+ pr_err("diag: log mask update failed %d, tried %d",
+ wr_size, header_size + size);
+ else
+ pr_debug("diag: updated log equip ID %d,len %d\n",
+ driver->log_mask->equip_id,
+ driver->log_mask->log_mask_size);
+ } else
+ pr_err("diag: ch not valid for log update\n");
+ }
+ ptr++;
+ }
+ mutex_unlock(&driver->diag_cntl_mutex);
+}
+
+void diag_send_event_mask_update(smd_channel_t *ch, int num_bytes)
+{
+ void *buf = driver->buf_event_mask_update;
+ int header_size = sizeof(struct diag_ctrl_event_mask);
+ int wr_size = -ENOMEM, retry_count = 0;
+
+ mutex_lock(&driver->diag_cntl_mutex);
+ if (num_bytes == 0) {
+ pr_debug("diag: event mask not set yet, so no update\n");
+ mutex_unlock(&driver->diag_cntl_mutex);
+ return;
+ }
+ /* send event mask update */
+ driver->event_mask->cmd_type = DIAG_CTRL_MSG_EVENT_MASK;
+ driver->event_mask->data_len = 7 + num_bytes;
+ driver->event_mask->stream_id = 1; /* 2, if dual stream */
+ driver->event_mask->status = 3; /* status for valid mask */
+ driver->event_mask->event_config = diag_event_config; /* event config */
+ driver->event_mask->event_mask_size = num_bytes;
+ memcpy(buf, driver->event_mask, header_size);
+ memcpy(buf+header_size, driver->event_masks, num_bytes);
+ if (ch) {
+ while (retry_count < 3) {
+ wr_size = smd_write(ch, buf, header_size + num_bytes);
+ if (wr_size == -ENOMEM) {
+ retry_count++;
+ WAIT_FOR_SMD(5, 2000);
+ } else
+ break;
+ }
+ if (wr_size != header_size + num_bytes)
+ pr_err("diag: error writing event mask %d, tried %d\n",
+ wr_size, header_size + num_bytes);
+ } else
+ pr_err("diag: ch not valid for event update\n");
+ mutex_unlock(&driver->diag_cntl_mutex);
+}
+
+void diag_send_msg_mask_update(smd_channel_t *ch, int updated_ssid_first,
+ int updated_ssid_last, int proc)
+{
+ void *buf = driver->buf_msg_mask_update;
+ int first, last, actual_last, size = -ENOMEM, retry_count = 0;
+ int header_size = sizeof(struct diag_ctrl_msg_mask);
+ uint8_t *ptr = driver->msg_masks;
+
+ mutex_lock(&driver->diag_cntl_mutex);
+ while (*(uint32_t *)(ptr + 4)) {
+ first = *(uint32_t *)ptr;
+ ptr += 4;
+ last = *(uint32_t *)ptr;
+ ptr += 4;
+ actual_last = *(uint32_t *)ptr;
+ ptr += 4;
+ if ((updated_ssid_first >= first && updated_ssid_last <=
+ actual_last) || (updated_ssid_first == ALL_SSID)) {
+ /* send f3 mask update */
+ driver->msg_mask->cmd_type = DIAG_CTRL_MSG_F3_MASK;
+ driver->msg_mask->msg_mask_size = actual_last -
+ first + 1;
+ driver->msg_mask->data_len = 11 +
+ 4 * (driver->msg_mask->msg_mask_size);
+ driver->msg_mask->stream_id = 1; /* 2, if dual stream */
+ driver->msg_mask->status = 3; /* status valid mask */
+ driver->msg_mask->msg_mode = 0; /* Legcay mode */
+ driver->msg_mask->ssid_first = first;
+ driver->msg_mask->ssid_last = actual_last;
+ memcpy(buf, driver->msg_mask, header_size);
+ memcpy(buf+header_size, ptr,
+ 4 * (driver->msg_mask->msg_mask_size));
+ if (ch) {
+ while (retry_count < 3) {
+ size = smd_write(ch, buf, header_size +
+ 4*(driver->msg_mask->msg_mask_size));
+ if (size == -ENOMEM) {
+ retry_count++;
+ WAIT_FOR_SMD(5, 2000);
+ } else
+ break;
+ }
+ if (size != header_size +
+ 4*(driver->msg_mask->msg_mask_size))
+ pr_err("diag: proc %d, msg mask update fail %d, tried %d\n",
+ proc, size, (header_size +
+ 4*(driver->msg_mask->msg_mask_size)));
+ else
+ pr_debug("diag: sending mask update for ssid first %d, last %d on PROC %d\n",
+ first, actual_last, proc);
+ } else
+ pr_err("diag: proc %d, ch invalid msg mask update\n",
+ proc);
+ }
+ ptr += MAX_SSID_PER_RANGE*4;
+ }
+ mutex_unlock(&driver->diag_cntl_mutex);
+}
+
+int diag_process_apps_masks(unsigned char *buf, int len)
+{
+ int packet_type = 1;
+ int i;
+ int ssid_first, ssid_last, ssid_range;
+ int rt_mask, rt_first_ssid, rt_last_ssid, rt_mask_size;
+ uint8_t *rt_mask_ptr;
+ int equip_id, num_items;
+#if defined(CONFIG_DIAG_OVER_USB)
+ int payload_length;
+#endif
+
+ /* Set log masks */
+ if (*buf == 0x73 && *(int *)(buf+4) == 3) {
+ buf += 8;
+ /* Read Equip ID and pass as first param below*/
+ diag_update_log_mask(*(int *)buf, buf+8, *(int *)(buf+4));
+ diag_update_userspace_clients(LOG_MASKS_TYPE);
+#if defined(CONFIG_DIAG_OVER_USB)
+ if (chk_apps_only()) {
+ driver->apps_rsp_buf[0] = 0x73;
+ *(int *)(driver->apps_rsp_buf + 4) = 0x3; /* op. ID */
+ *(int *)(driver->apps_rsp_buf + 8) = 0x0; /* success */
+ payload_length = 8 + ((*(int *)(buf + 4)) + 7)/8;
+ for (i = 0; i < payload_length; i++)
+ *(int *)(driver->apps_rsp_buf+12+i) = *(buf+i);
+ if (driver->ch_cntl)
+ diag_send_log_mask_update(driver->ch_cntl,
+ *(int *)buf);
+ if (driver->chlpass_cntl)
+ diag_send_log_mask_update(driver->chlpass_cntl,
+ *(int *)buf);
+ if (driver->ch_wcnss_cntl)
+ diag_send_log_mask_update(driver->ch_wcnss_cntl,
+ *(int *)buf);
+ encode_rsp_and_send(12 + payload_length - 1);
+ return 0;
+ }
+#endif
+ } /* Get log masks */
+ else if (*buf == 0x73 && *(int *)(buf+4) == 4) {
+#if defined(CONFIG_DIAG_OVER_USB)
+ if (!(driver->ch) && chk_apps_only()) {
+ equip_id = *(int *)(buf + 8);
+ num_items = *(int *)(buf + 12);
+ driver->apps_rsp_buf[0] = 0x73;
+ driver->apps_rsp_buf[1] = 0x0;
+ driver->apps_rsp_buf[2] = 0x0;
+ driver->apps_rsp_buf[3] = 0x0;
+ *(int *)(driver->apps_rsp_buf + 4) = 0x4;
+ if (!chk_equip_id_and_mask(equip_id,
+ driver->apps_rsp_buf+20))
+ *(int *)(driver->apps_rsp_buf + 8) = 0x0;
+ else
+ *(int *)(driver->apps_rsp_buf + 8) = 0x1;
+ *(int *)(driver->apps_rsp_buf + 12) = equip_id;
+ *(int *)(driver->apps_rsp_buf + 16) = num_items;
+ encode_rsp_and_send(20+(num_items+7)/8-1);
+ return 0;
+ }
+#endif
+ } /* Disable log masks */
+ else if (*buf == 0x73 && *(int *)(buf+4) == 0) {
+ /* Disable mask for each log code */
+ diag_disable_log_mask();
+ diag_update_userspace_clients(LOG_MASKS_TYPE);
+#if defined(CONFIG_DIAG_OVER_USB)
+ if (chk_apps_only()) {
+ driver->apps_rsp_buf[0] = 0x73;
+ driver->apps_rsp_buf[1] = 0x0;
+ driver->apps_rsp_buf[2] = 0x0;
+ driver->apps_rsp_buf[3] = 0x0;
+ *(int *)(driver->apps_rsp_buf + 4) = 0x0;
+ *(int *)(driver->apps_rsp_buf + 8) = 0x0; /* status */
+ if (driver->ch_cntl)
+ diag_send_log_mask_update(driver->ch_cntl,
+ ALL_EQUIP_ID);
+ if (driver->chlpass_cntl)
+ diag_send_log_mask_update(driver->chlpass_cntl,
+ ALL_EQUIP_ID);
+ if (driver->ch_wcnss_cntl)
+ diag_send_log_mask_update(driver->ch_wcnss_cntl,
+ ALL_EQUIP_ID);
+ encode_rsp_and_send(11);
+ return 0;
+ }
+#endif
+ } /* Get runtime message mask */
+ else if ((*buf == 0x7d) && (*(buf+1) == 0x3)) {
+ ssid_first = *(uint16_t *)(buf + 2);
+ ssid_last = *(uint16_t *)(buf + 4);
+#if defined(CONFIG_DIAG_OVER_USB)
+ if (!(driver->ch) && chk_apps_only()) {
+ driver->apps_rsp_buf[0] = 0x7d;
+ driver->apps_rsp_buf[1] = 0x3;
+ *(uint16_t *)(driver->apps_rsp_buf+2) = ssid_first;
+ *(uint16_t *)(driver->apps_rsp_buf+4) = ssid_last;
+ driver->apps_rsp_buf[6] = 0x1; /* Success Status */
+ driver->apps_rsp_buf[7] = 0x0;
+ rt_mask_ptr = driver->msg_masks;
+ while (*(uint32_t *)(rt_mask_ptr + 4)) {
+ rt_first_ssid = *(uint32_t *)rt_mask_ptr;
+ rt_mask_ptr += 8; /* +8 to skip 'last' */
+ rt_last_ssid = *(uint32_t *)rt_mask_ptr;
+ rt_mask_ptr += 4;
+ if (ssid_first == rt_first_ssid && ssid_last ==
+ rt_last_ssid) {
+ rt_mask_size = 4 * (rt_last_ssid -
+ rt_first_ssid + 1);
+ memcpy(driver->apps_rsp_buf+8,
+ rt_mask_ptr, rt_mask_size);
+ encode_rsp_and_send(8+rt_mask_size-1);
+ return 0;
+ }
+ rt_mask_ptr += MAX_SSID_PER_RANGE*4;
+ }
+ }
+#endif
+ } /* Set runtime message mask */
+ else if ((*buf == 0x7d) && (*(buf+1) == 0x4)) {
+ ssid_first = *(uint16_t *)(buf + 2);
+ ssid_last = *(uint16_t *)(buf + 4);
+ ssid_range = 4 * (ssid_last - ssid_first + 1);
+ pr_debug("diag: received mask update for ssid_first = %d, ssid_last = %d",
+ ssid_first, ssid_last);
+ diag_update_msg_mask(ssid_first, ssid_last , buf + 8);
+ diag_update_userspace_clients(MSG_MASKS_TYPE);
+#if defined(CONFIG_DIAG_OVER_USB)
+ if (chk_apps_only()) {
+ for (i = 0; i < 8 + ssid_range; i++)
+ *(driver->apps_rsp_buf + i) = *(buf+i);
+ *(driver->apps_rsp_buf + 6) = 0x1;
+ if (driver->ch_cntl)
+ diag_send_msg_mask_update(driver->ch_cntl,
+ ssid_first, ssid_last, MODEM_PROC);
+ if (driver->chlpass_cntl)
+ diag_send_msg_mask_update(driver->chlpass_cntl,
+ ssid_first, ssid_last, LPASS_PROC);
+ if (driver->ch_wcnss_cntl)
+ diag_send_msg_mask_update(driver->ch_wcnss_cntl,
+ ssid_first, ssid_last, WCNSS_PROC);
+ encode_rsp_and_send(8 + ssid_range - 1);
+ return 0;
+ }
+#endif
+ } /* Set ALL runtime message mask */
+ else if ((*buf == 0x7d) && (*(buf+1) == 0x5)) {
+ rt_mask = *(int *)(buf + 4);
+ diag_set_msg_mask(rt_mask);
+ diag_update_userspace_clients(MSG_MASKS_TYPE);
+#if defined(CONFIG_DIAG_OVER_USB)
+ if (chk_apps_only()) {
+ driver->apps_rsp_buf[0] = 0x7d; /* cmd_code */
+ driver->apps_rsp_buf[1] = 0x5; /* set subcommand */
+ driver->apps_rsp_buf[2] = 1; /* success */
+ driver->apps_rsp_buf[3] = 0; /* rsvd */
+ *(int *)(driver->apps_rsp_buf + 4) = rt_mask;
+ /* send msg mask update to peripheral */
+ if (driver->ch_cntl)
+ diag_send_msg_mask_update(driver->ch_cntl,
+ ALL_SSID, ALL_SSID, MODEM_PROC);
+ if (driver->chlpass_cntl)
+ diag_send_msg_mask_update(driver->chlpass_cntl,
+ ALL_SSID, ALL_SSID, LPASS_PROC);
+ if (driver->ch_wcnss_cntl)
+ diag_send_msg_mask_update(driver->ch_wcnss_cntl,
+ ALL_SSID, ALL_SSID, WCNSS_PROC);
+ encode_rsp_and_send(7);
+ return 0;
+ }
+#endif
+ } else if (*buf == 0x82) { /* event mask change */
+ buf += 4;
+ diag_event_num_bytes = (*(uint16_t *)buf)/8+1;
+ diag_update_event_mask(buf, 1, (*(uint16_t *)buf)/8+1);
+ diag_update_userspace_clients(EVENT_MASKS_TYPE);
+#if defined(CONFIG_DIAG_OVER_USB)
+ if (chk_apps_only()) {
+ driver->apps_rsp_buf[0] = 0x82;
+ driver->apps_rsp_buf[1] = 0x0;
+ *(uint16_t *)(driver->apps_rsp_buf + 2) = 0x0;
+ *(uint16_t *)(driver->apps_rsp_buf + 4) =
+ EVENT_LAST_ID + 1;
+ memcpy(driver->apps_rsp_buf+6, driver->event_masks,
+ EVENT_LAST_ID/8+1);
+ if (driver->ch_cntl)
+ diag_send_event_mask_update(driver->ch_cntl,
+ diag_event_num_bytes);
+ if (driver->chlpass_cntl)
+ diag_send_event_mask_update(
+ driver->chlpass_cntl,
+ diag_event_num_bytes);
+ if (driver->ch_wcnss_cntl)
+ diag_send_event_mask_update(
+ driver->ch_wcnss_cntl, diag_event_num_bytes);
+ encode_rsp_and_send(6 + EVENT_LAST_ID/8);
+ return 0;
+ }
+#endif
+ } else if (*buf == 0x60) {
+ diag_event_config = *(buf+1);
+ diag_toggle_event_mask(*(buf+1));
+ diag_update_userspace_clients(EVENT_MASKS_TYPE);
+#if defined(CONFIG_DIAG_OVER_USB)
+ if (chk_apps_only()) {
+ driver->apps_rsp_buf[0] = 0x60;
+ driver->apps_rsp_buf[1] = 0x0;
+ driver->apps_rsp_buf[2] = 0x0;
+ if (driver->ch_cntl)
+ diag_send_event_mask_update(driver->ch_cntl,
+ diag_event_num_bytes);
+ if (driver->chlpass_cntl)
+ diag_send_event_mask_update(
+ driver->chlpass_cntl,
+ diag_event_num_bytes);
+ if (driver->ch_wcnss_cntl)
+ diag_send_event_mask_update(
+ driver->ch_wcnss_cntl, diag_event_num_bytes);
+ encode_rsp_and_send(2);
+ return 0;
+ }
+#endif
+ }
+
+ return packet_type;
+}
+
+void diag_masks_init(void)
+{
+ if (driver->event_mask == NULL) {
+ driver->event_mask = kzalloc(sizeof(
+ struct diag_ctrl_event_mask), GFP_KERNEL);
+ if (driver->event_mask == NULL)
+ goto err;
+ kmemleak_not_leak(driver->event_mask);
+ }
+ if (driver->msg_mask == NULL) {
+ driver->msg_mask = kzalloc(sizeof(
+ struct diag_ctrl_msg_mask), GFP_KERNEL);
+ if (driver->msg_mask == NULL)
+ goto err;
+ kmemleak_not_leak(driver->msg_mask);
+ }
+ if (driver->log_mask == NULL) {
+ driver->log_mask = kzalloc(sizeof(
+ struct diag_ctrl_log_mask), GFP_KERNEL);
+ if (driver->log_mask == NULL)
+ goto err;
+ kmemleak_not_leak(driver->log_mask);
+ }
+
+ if (driver->buf_msg_mask_update == NULL) {
+ driver->buf_msg_mask_update = kzalloc(APPS_BUF_SIZE,
+ GFP_KERNEL);
+ if (driver->buf_msg_mask_update == NULL)
+ goto err;
+ kmemleak_not_leak(driver->buf_msg_mask_update);
+ }
+ if (driver->buf_log_mask_update == NULL) {
+ driver->buf_log_mask_update = kzalloc(APPS_BUF_SIZE,
+ GFP_KERNEL);
+ if (driver->buf_log_mask_update == NULL)
+ goto err;
+ kmemleak_not_leak(driver->buf_log_mask_update);
+ }
+ if (driver->buf_event_mask_update == NULL) {
+ driver->buf_event_mask_update = kzalloc(APPS_BUF_SIZE,
+ GFP_KERNEL);
+ if (driver->buf_event_mask_update == NULL)
+ goto err;
+ kmemleak_not_leak(driver->buf_event_mask_update);
+ }
+ if (driver->msg_masks == NULL) {
+ driver->msg_masks = kzalloc(MSG_MASK_SIZE, GFP_KERNEL);
+ if (driver->msg_masks == NULL)
+ goto err;
+ kmemleak_not_leak(driver->msg_masks);
+ }
+ diag_create_msg_mask_table();
+ diag_event_num_bytes = 0;
+ if (driver->log_masks == NULL) {
+ driver->log_masks = kzalloc(LOG_MASK_SIZE, GFP_KERNEL);
+ if (driver->log_masks == NULL)
+ goto err;
+ kmemleak_not_leak(driver->log_masks);
+ }
+ driver->log_masks_length = (sizeof(struct mask_info))*MAX_EQUIP_ID;
+ if (driver->event_masks == NULL) {
+ driver->event_masks = kzalloc(EVENT_MASK_SIZE, GFP_KERNEL);
+ if (driver->event_masks == NULL)
+ goto err;
+ kmemleak_not_leak(driver->event_masks);
+ }
+#ifdef CONFIG_DIAG_OVER_USB
+ INIT_WORK(&(driver->diag_modem_mask_update_work),
+ diag_modem_mask_update_fn);
+ INIT_WORK(&(driver->diag_lpass_mask_update_work),
+ diag_lpass_mask_update_fn);
+ INIT_WORK(&(driver->diag_wcnss_mask_update_work),
+ diag_wcnss_mask_update_fn);
+#endif
+ return;
+err:
+ pr_err("diag: Could not initialize diag mask buffers");
+ kfree(driver->event_mask);
+ kfree(driver->log_mask);
+ kfree(driver->msg_mask);
+ kfree(driver->msg_masks);
+ kfree(driver->log_masks);
+ kfree(driver->event_masks);
+}
+
+void diag_masks_exit(void)
+{
+ kfree(driver->event_mask);
+ kfree(driver->log_mask);
+ kfree(driver->msg_mask);
+ kfree(driver->msg_masks);
+ kfree(driver->log_masks);
+ kfree(driver->event_masks);
+}
diff --git a/drivers/char/diag/diag_masks.h b/drivers/char/diag/diag_masks.h
new file mode 100644
index 0000000..bcf5bc2
--- /dev/null
+++ b/drivers/char/diag/diag_masks.h
@@ -0,0 +1,27 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef DIAG_MASKS_H
+#define DIAG_MASKS_H
+
+#include "diagfwd.h"
+
+int chk_equip_id_and_mask(int equip_id, uint8_t *buf);
+void diag_send_event_mask_update(smd_channel_t *, int num_bytes);
+void diag_send_msg_mask_update(smd_channel_t *, int ssid_first,
+ int ssid_last, int proc);
+void diag_send_log_mask_update(smd_channel_t *, int);
+int diag_process_apps_masks(unsigned char *buf, int len);
+void diag_masks_init(void);
+void diag_masks_exit(void);
+extern int diag_event_num_bytes;
+#endif
diff --git a/drivers/char/diag/diagchar_core.c b/drivers/char/diag/diagchar_core.c
index 814fe64..09da40c 100644
--- a/drivers/char/diag/diagchar_core.c
+++ b/drivers/char/diag/diagchar_core.c
@@ -37,6 +37,8 @@
#include "diagfwd_smux.h"
#endif
#include <linux/timer.h>
+#include "diag_debugfs.h"
+#include "diag_masks.h"
MODULE_DESCRIPTION("Diag Char Driver");
MODULE_LICENSE("GPL v2");
@@ -1422,6 +1424,7 @@
diag_debugfs_init();
diagfwd_init();
diagfwd_cntl_init();
+ diag_masks_init();
driver->dci_state = diag_dci_init();
diag_sdio_fn(INIT);
diag_bridge_fn(INIT);
@@ -1457,6 +1460,7 @@
diagchar_cleanup();
diagfwd_exit();
diagfwd_cntl_exit();
+ diag_masks_exit();
diag_sdio_fn(EXIT);
diag_bridge_fn(EXIT);
return -1;
@@ -1470,6 +1474,7 @@
diagmem_exit(driver, POOL_TYPE_ALL);
diagfwd_exit();
diagfwd_cntl_exit();
+ diag_masks_exit();
diag_sdio_fn(EXIT);
diag_bridge_fn(EXIT);
diag_debugfs_cleanup();
diff --git a/drivers/char/diag/diagfwd.c b/drivers/char/diag/diagfwd.c
index 737edbf..a537bb3 100644
--- a/drivers/char/diag/diagfwd.c
+++ b/drivers/char/diag/diagfwd.c
@@ -39,63 +39,38 @@
#include "diagfwd_sdio.h"
#endif
#include "diag_dci.h"
+#include "diag_masks.h"
#define MODE_CMD 41
#define RESET_ID 2
-#define ALL_EQUIP_ID 100
-#define ALL_SSID -1
-#define MAX_SSID_PER_RANGE 100
int diag_debug_buf_idx;
unsigned char diag_debug_buf[1024];
static unsigned int buf_tbl_size = 8; /*Number of entries in table of buffers */
struct diag_master_table entry;
smd_channel_t *ch_temp = NULL, *chlpass_temp = NULL, *ch_wcnss_temp = NULL;
-int diag_event_num_bytes;
-int diag_event_config;
struct diag_send_desc_type send = { NULL, NULL, DIAG_STATE_START, 0 };
struct diag_hdlc_dest_type enc = { NULL, NULL, 0 };
-struct mask_info {
- int equip_id;
- int num_items;
- int index;
-};
-#define CREATE_MSG_MASK_TBL_ROW(XX) \
-do { \
- *(int *)(msg_mask_tbl_ptr) = MSG_SSID_ ## XX; \
- msg_mask_tbl_ptr += 4; \
- *(int *)(msg_mask_tbl_ptr) = MSG_SSID_ ## XX ## _LAST; \
- msg_mask_tbl_ptr += 4; \
- /* mimic the last entry as actual_last while creation */ \
- *(int *)(msg_mask_tbl_ptr) = MSG_SSID_ ## XX ## _LAST; \
- msg_mask_tbl_ptr += 4; \
- /* increment by MAX_SSID_PER_RANGE cells */ \
- msg_mask_tbl_ptr += MAX_SSID_PER_RANGE * sizeof(int); \
-} while (0)
-
-#define ENCODE_RSP_AND_SEND(buf_length) \
-do { \
- send.state = DIAG_STATE_START; \
- send.pkt = driver->apps_rsp_buf; \
- send.last = (void *)(driver->apps_rsp_buf + buf_length); \
- send.terminate = 1; \
- if (!driver->in_busy_1) { \
- enc.dest = driver->buf_in_1; \
- enc.dest_last = (void *)(driver->buf_in_1 + APPS_BUF_SIZE - 1);\
- diag_hdlc_encode(&send, &enc); \
- driver->write_ptr_1->buf = driver->buf_in_1; \
- driver->write_ptr_1->length = (int)(enc.dest - \
- (void *)(driver->buf_in_1)); \
- driver->in_busy_1 = 1; \
- diag_device_write(driver->buf_in_1, MODEM_DATA, \
- driver->write_ptr_1); \
- memset(driver->apps_rsp_buf, '\0', APPS_BUF_SIZE); \
- } \
-} while (0)
-
-#define CHK_OVERFLOW(bufStart, start, end, length) \
-((bufStart <= start) && (end - start >= length)) ? 1 : 0
+void encode_rsp_and_send(int buf_length)
+{
+ send.state = DIAG_STATE_START;
+ send.pkt = driver->apps_rsp_buf;
+ send.last = (void *)(driver->apps_rsp_buf + buf_length);
+ send.terminate = 1;
+ if (!driver->in_busy_1) {
+ enc.dest = driver->buf_in_1;
+ enc.dest_last = (void *)(driver->buf_in_1 + APPS_BUF_SIZE - 1);
+ diag_hdlc_encode(&send, &enc);
+ driver->write_ptr_1->buf = driver->buf_in_1;
+ driver->write_ptr_1->length = (int)(enc.dest -
+ (void *)(driver->buf_in_1));
+ driver->in_busy_1 = 1;
+ diag_device_write(driver->buf_in_1, MODEM_DATA,
+ driver->write_ptr_1);
+ memset(driver->apps_rsp_buf, '\0', APPS_BUF_SIZE);
+ }
+}
/* Determine if this device uses a device tree */
#ifdef CONFIG_OF
@@ -136,6 +111,7 @@
case MSM_CPU_8960AB:
return AO8960_TOOLS_ID;
case MSM_CPU_8064:
+ case MSM_CPU_8064AB:
return APQ8064_TOOLS_ID;
case MSM_CPU_8930:
case MSM_CPU_8930AA:
@@ -163,6 +139,7 @@
case MSM_CPU_8960:
case MSM_CPU_8960AB:
case MSM_CPU_8064:
+ case MSM_CPU_8064AB:
case MSM_CPU_8930:
case MSM_CPU_8930AA:
case MSM_CPU_8627:
@@ -185,7 +162,7 @@
return 1;
else if (cpu_is_msm8960() || cpu_is_msm8930() || cpu_is_msm8930aa() ||
cpu_is_msm9615() || cpu_is_apq8064() || cpu_is_msm8627() ||
- cpu_is_msm8960ab())
+ cpu_is_msm8960ab() || cpu_is_apq8064ab())
return 1;
else
return 0;
@@ -559,248 +536,6 @@
}
}
-static void diag_print_mask_table(void)
-{
-/* Enable this to print mask table when updated */
-#ifdef MASK_DEBUG
- int first, last, actual_last;
- uint8_t *ptr = driver->msg_masks;
- int i = 0;
- pr_info("diag: F3 message mask table\n");
- while (*(uint32_t *)(ptr + 4)) {
- first = *(uint32_t *)ptr;
- ptr += 4;
- last = *(uint32_t *)ptr;
- ptr += 4;
- actual_last = *(uint32_t *)ptr;
- ptr += 4;
- pr_info("diag: SSID %d, %d - %d\n", first, last, actual_last);
- for (i = 0 ; i <= actual_last - first ; i++)
- pr_info("diag: MASK:%x\n", *((uint32_t *)ptr + i));
- ptr += MAX_SSID_PER_RANGE*4;
- }
-#endif
-}
-
-void diag_create_msg_mask_table(void)
-{
- uint8_t *msg_mask_tbl_ptr = driver->msg_masks;
-
- CREATE_MSG_MASK_TBL_ROW(0);
- CREATE_MSG_MASK_TBL_ROW(1);
- CREATE_MSG_MASK_TBL_ROW(2);
- CREATE_MSG_MASK_TBL_ROW(3);
- CREATE_MSG_MASK_TBL_ROW(4);
- CREATE_MSG_MASK_TBL_ROW(5);
- CREATE_MSG_MASK_TBL_ROW(6);
- CREATE_MSG_MASK_TBL_ROW(7);
- CREATE_MSG_MASK_TBL_ROW(8);
- CREATE_MSG_MASK_TBL_ROW(9);
- CREATE_MSG_MASK_TBL_ROW(10);
- CREATE_MSG_MASK_TBL_ROW(11);
- CREATE_MSG_MASK_TBL_ROW(12);
- CREATE_MSG_MASK_TBL_ROW(13);
- CREATE_MSG_MASK_TBL_ROW(14);
- CREATE_MSG_MASK_TBL_ROW(15);
- CREATE_MSG_MASK_TBL_ROW(16);
- CREATE_MSG_MASK_TBL_ROW(17);
- CREATE_MSG_MASK_TBL_ROW(18);
- CREATE_MSG_MASK_TBL_ROW(19);
- CREATE_MSG_MASK_TBL_ROW(20);
- CREATE_MSG_MASK_TBL_ROW(21);
- CREATE_MSG_MASK_TBL_ROW(22);
- CREATE_MSG_MASK_TBL_ROW(23);
-}
-
-static void diag_set_msg_mask(int rt_mask)
-{
- int first_ssid, last_ssid, i;
- uint8_t *parse_ptr, *ptr = driver->msg_masks;
-
- mutex_lock(&driver->diagchar_mutex);
- while (*(uint32_t *)(ptr + 4)) {
- first_ssid = *(uint32_t *)ptr;
- ptr += 8; /* increment by 8 to skip 'last' */
- last_ssid = *(uint32_t *)ptr;
- ptr += 4;
- parse_ptr = ptr;
- pr_debug("diag: updating range %d %d\n", first_ssid, last_ssid);
- for (i = 0; i < last_ssid - first_ssid + 1; i++) {
- *(int *)parse_ptr = rt_mask;
- parse_ptr += 4;
- }
- ptr += MAX_SSID_PER_RANGE * 4;
- }
- mutex_unlock(&driver->diagchar_mutex);
-}
-
-static void diag_update_msg_mask(int start, int end , uint8_t *buf)
-{
- int found = 0, first, last, actual_last;
- uint8_t *actual_last_ptr;
- uint8_t *ptr = driver->msg_masks;
- uint8_t *ptr_buffer_start = &(*(driver->msg_masks));
- uint8_t *ptr_buffer_end = &(*(driver->msg_masks)) + MSG_MASK_SIZE;
-
- mutex_lock(&driver->diagchar_mutex);
-
- /* First SSID can be zero : So check that last is non-zero */
- while (*(uint32_t *)(ptr + 4)) {
- first = *(uint32_t *)ptr;
- ptr += 4;
- last = *(uint32_t *)ptr;
- ptr += 4;
- actual_last = *(uint32_t *)ptr;
- actual_last_ptr = ptr;
- ptr += 4;
- if (start >= first && start <= actual_last) {
- ptr += (start - first)*4;
- if (end > actual_last) {
- pr_info("diag: ssid range mismatch\n");
- actual_last = end;
- *(uint32_t *)(actual_last_ptr) = end;
- }
- if (CHK_OVERFLOW(ptr_buffer_start, ptr, ptr_buffer_end,
- (((end - start)+1)*4))) {
- pr_debug("diag: update ssid start %d, end %d\n",
- start, end);
- memcpy(ptr, buf , ((end - start)+1)*4);
- } else
- pr_alert("diag: Not enough space MSG_MASK\n");
- found = 1;
- break;
- } else {
- ptr += MAX_SSID_PER_RANGE*4;
- }
- }
- /* Entry was not found - add new table */
- if (!found) {
- if (CHK_OVERFLOW(ptr_buffer_start, ptr, ptr_buffer_end,
- 8 + ((end - start) + 1)*4)) {
- memcpy(ptr, &(start) , 4);
- ptr += 4;
- memcpy(ptr, &(end), 4);
- ptr += 4;
- memcpy(ptr, &(end), 4); /* create actual_last entry */
- ptr += 4;
- pr_debug("diag: adding NEW ssid start %d, end %d\n",
- start, end);
- memcpy(ptr, buf , ((end - start) + 1)*4);
- } else
- pr_alert("diag: Not enough buffer space for MSG_MASK\n");
- }
- mutex_unlock(&driver->diagchar_mutex);
- diag_print_mask_table();
-}
-
-void diag_toggle_event_mask(int toggle)
-{
- uint8_t *ptr = driver->event_masks;
-
- mutex_lock(&driver->diagchar_mutex);
- if (toggle)
- memset(ptr, 0xFF, EVENT_MASK_SIZE);
- else
- memset(ptr, 0, EVENT_MASK_SIZE);
- mutex_unlock(&driver->diagchar_mutex);
-}
-
-static void diag_update_event_mask(uint8_t *buf, int toggle, int num_bytes)
-{
- uint8_t *ptr = driver->event_masks;
- uint8_t *temp = buf + 2;
-
- mutex_lock(&driver->diagchar_mutex);
- if (!toggle)
- memset(ptr, 0 , EVENT_MASK_SIZE);
- else
- if (CHK_OVERFLOW(ptr, ptr,
- ptr+EVENT_MASK_SIZE, num_bytes))
- memcpy(ptr, temp , num_bytes);
- else
- printk(KERN_CRIT "Not enough buffer space "
- "for EVENT_MASK\n");
- mutex_unlock(&driver->diagchar_mutex);
-}
-
-static void diag_disable_log_mask(void)
-{
- int i = 0;
- struct mask_info *parse_ptr = (struct mask_info *)(driver->log_masks);
-
- pr_debug("diag: disable log masks\n");
- mutex_lock(&driver->diagchar_mutex);
- for (i = 0; i < MAX_EQUIP_ID; i++) {
- pr_debug("diag: equip id %d\n", parse_ptr->equip_id);
- if (!(parse_ptr->equip_id)) /* Reached a null entry */
- break;
- memset(driver->log_masks + parse_ptr->index, 0,
- (parse_ptr->num_items + 7)/8);
- parse_ptr++;
- }
- mutex_unlock(&driver->diagchar_mutex);
-}
-
-int chk_equip_id_and_mask(int equip_id, uint8_t *buf)
-{
- int i = 0, flag = 0, num_items, offset;
- unsigned char *ptr_data;
- struct mask_info *ptr = (struct mask_info *)(driver->log_masks);
-
- pr_debug("diag: received equip id = %d\n", equip_id);
- /* Check if this is valid equipment ID */
- for (i = 0; i < MAX_EQUIP_ID; i++) {
- if ((ptr->equip_id == equip_id) && (ptr->index != 0)) {
- offset = ptr->index;
- num_items = ptr->num_items;
- flag = 1;
- break;
- }
- ptr++;
- }
- if (!flag)
- return -EPERM;
- ptr_data = driver->log_masks + offset;
- memcpy(buf, ptr_data, (num_items+7)/8);
- return 0;
-}
-
-static void diag_update_log_mask(int equip_id, uint8_t *buf, int num_items)
-{
- uint8_t *temp = buf;
- int i = 0;
- unsigned char *ptr_data;
- int offset = (sizeof(struct mask_info))*MAX_EQUIP_ID;
- struct mask_info *ptr = (struct mask_info *)(driver->log_masks);
-
- pr_debug("diag: received equip id = %d\n", equip_id);
- mutex_lock(&driver->diagchar_mutex);
- /* Check if we already know index of this equipment ID */
- for (i = 0; i < MAX_EQUIP_ID; i++) {
- if ((ptr->equip_id == equip_id) && (ptr->index != 0)) {
- offset = ptr->index;
- break;
- }
- if ((ptr->equip_id == 0) && (ptr->index == 0)) {
- /* Reached a null entry */
- ptr->equip_id = equip_id;
- ptr->num_items = num_items;
- ptr->index = driver->log_masks_length;
- offset = driver->log_masks_length;
- driver->log_masks_length += ((num_items+7)/8);
- break;
- }
- ptr++;
- }
- ptr_data = driver->log_masks + offset;
- if (CHK_OVERFLOW(driver->log_masks, ptr_data, driver->log_masks
- + LOG_MASK_SIZE, (num_items+7)/8))
- memcpy(ptr_data, temp , (num_items+7)/8);
- else
- pr_err("diag: Not enough buffer space for LOG_MASK\n");
- mutex_unlock(&driver->diagchar_mutex);
-}
-
static void diag_update_pkt_buffer(unsigned char *buf)
{
unsigned char *ptr = driver->pkt_buf;
@@ -869,415 +604,21 @@
}
}
-void diag_modem_mask_update_fn(struct work_struct *work)
-{
- diag_send_msg_mask_update(driver->ch_cntl, ALL_SSID,
- ALL_SSID, MODEM_PROC);
- diag_send_log_mask_update(driver->ch_cntl, ALL_EQUIP_ID);
- diag_send_event_mask_update(driver->ch_cntl, diag_event_num_bytes);
-}
-
-void diag_lpass_mask_update_fn(struct work_struct *work)
-{
- diag_send_msg_mask_update(driver->chlpass_cntl, ALL_SSID,
- ALL_SSID, LPASS_PROC);
- diag_send_log_mask_update(driver->chlpass_cntl, ALL_EQUIP_ID);
- diag_send_event_mask_update(driver->chlpass_cntl, diag_event_num_bytes);
-}
-
-void diag_wcnss_mask_update_fn(struct work_struct *work)
-{
- diag_send_msg_mask_update(driver->ch_wcnss_cntl, ALL_SSID,
- ALL_SSID, WCNSS_PROC);
- diag_send_log_mask_update(driver->ch_wcnss_cntl, ALL_EQUIP_ID);
- diag_send_event_mask_update(driver->ch_wcnss_cntl,
- diag_event_num_bytes);
-}
-
-void diag_send_log_mask_update(smd_channel_t *ch, int equip_id)
-{
- void *buf = driver->buf_log_mask_update;
- int header_size = sizeof(struct diag_ctrl_log_mask);
- struct mask_info *ptr = (struct mask_info *)driver->log_masks;
- int i, size, wr_size = -ENOMEM, retry_count = 0, timer;
-
- mutex_lock(&driver->diag_cntl_mutex);
- for (i = 0; i < MAX_EQUIP_ID; i++) {
- size = (ptr->num_items+7)/8;
- /* reached null entry */
- if ((ptr->equip_id == 0) && (ptr->index == 0))
- break;
- driver->log_mask->cmd_type = DIAG_CTRL_MSG_LOG_MASK;
- driver->log_mask->num_items = ptr->num_items;
- driver->log_mask->data_len = 11 + size;
- driver->log_mask->stream_id = 1; /* 2, if dual stream */
- driver->log_mask->status = 3; /* status for valid mask */
- driver->log_mask->equip_id = ptr->equip_id;
- driver->log_mask->log_mask_size = size;
- /* send only desired update, NOT ALL */
- if (equip_id == ALL_EQUIP_ID || equip_id ==
- driver->log_mask->equip_id) {
- memcpy(buf, driver->log_mask, header_size);
- memcpy(buf+header_size, driver->log_masks+ptr->index,
- size);
- if (ch) {
- while (retry_count < 3) {
- wr_size = smd_write(ch, buf,
- header_size + size);
- if (wr_size == -ENOMEM) {
- retry_count++;
- for (timer = 0; timer < 5;
- timer++)
- udelay(2000);
- } else
- break;
- }
- if (wr_size != header_size + size)
- pr_err("diag: log mask update failed"
- " %d, tried %d", wr_size, header_size + size);
- else
- pr_debug("diag: updated log equip ID %d"
- ",len %d\n", driver->log_mask->equip_id,
- driver->log_mask->log_mask_size);
- } else
- pr_err("diag: ch not valid for log update\n");
- }
- ptr++;
- }
- mutex_unlock(&driver->diag_cntl_mutex);
-}
-
-void diag_send_event_mask_update(smd_channel_t *ch, int num_bytes)
-{
- void *buf = driver->buf_event_mask_update;
- int header_size = sizeof(struct diag_ctrl_event_mask);
- int wr_size = -ENOMEM, retry_count = 0, timer;
-
- mutex_lock(&driver->diag_cntl_mutex);
- if (num_bytes == 0) {
- pr_debug("diag: event mask not set yet, so no update\n");
- mutex_unlock(&driver->diag_cntl_mutex);
- return;
- }
- /* send event mask update */
- driver->event_mask->cmd_type = DIAG_CTRL_MSG_EVENT_MASK;
- driver->event_mask->data_len = 7 + num_bytes;
- driver->event_mask->stream_id = 1; /* 2, if dual stream */
- driver->event_mask->status = 3; /* status for valid mask */
- driver->event_mask->event_config = diag_event_config; /* event config */
- driver->event_mask->event_mask_size = num_bytes;
- memcpy(buf, driver->event_mask, header_size);
- memcpy(buf+header_size, driver->event_masks, num_bytes);
- if (ch) {
- while (retry_count < 3) {
- wr_size = smd_write(ch, buf, header_size + num_bytes);
- if (wr_size == -ENOMEM) {
- retry_count++;
- for (timer = 0; timer < 5; timer++)
- udelay(2000);
- } else
- break;
- }
- if (wr_size != header_size + num_bytes)
- pr_err("diag: error writing event mask %d, tried %d\n",
- wr_size, header_size + num_bytes);
- } else
- pr_err("diag: ch not valid for event update\n");
- mutex_unlock(&driver->diag_cntl_mutex);
-}
-
-void diag_send_msg_mask_update(smd_channel_t *ch, int updated_ssid_first,
- int updated_ssid_last, int proc)
-{
- void *buf = driver->buf_msg_mask_update;
- int first, last, actual_last, size = -ENOMEM, retry_count = 0, timer;
- int header_size = sizeof(struct diag_ctrl_msg_mask);
- uint8_t *ptr = driver->msg_masks;
-
- mutex_lock(&driver->diag_cntl_mutex);
- while (*(uint32_t *)(ptr + 4)) {
- first = *(uint32_t *)ptr;
- ptr += 4;
- last = *(uint32_t *)ptr;
- ptr += 4;
- actual_last = *(uint32_t *)ptr;
- ptr += 4;
- if ((updated_ssid_first >= first && updated_ssid_last <=
- actual_last) || (updated_ssid_first == ALL_SSID)) {
- /* send f3 mask update */
- driver->msg_mask->cmd_type = DIAG_CTRL_MSG_F3_MASK;
- driver->msg_mask->msg_mask_size = actual_last -
- first + 1;
- driver->msg_mask->data_len = 11 +
- 4 * (driver->msg_mask->msg_mask_size);
- driver->msg_mask->stream_id = 1; /* 2, if dual stream */
- driver->msg_mask->status = 3; /* status valid mask */
- driver->msg_mask->msg_mode = 0; /* Legcay mode */
- driver->msg_mask->ssid_first = first;
- driver->msg_mask->ssid_last = actual_last;
- memcpy(buf, driver->msg_mask, header_size);
- memcpy(buf+header_size, ptr,
- 4 * (driver->msg_mask->msg_mask_size));
- if (ch) {
- while (retry_count < 3) {
- size = smd_write(ch, buf, header_size +
- 4*(driver->msg_mask->msg_mask_size));
- if (size == -ENOMEM) {
- retry_count++;
- for (timer = 0; timer < 5;
- timer++)
- udelay(2000);
- } else
- break;
- }
- if (size != header_size +
- 4*(driver->msg_mask->msg_mask_size))
- pr_err("diag: proc %d, msg mask update "
- "fail %d, tried %d\n", proc, size,
- header_size + 4*(driver->msg_mask->msg_mask_size));
- else
- pr_debug("diag: sending mask update for ssid first %d, last %d on PROC %d\n",
- first, actual_last, proc);
- } else
- pr_err("diag: proc %d, ch invalid msg mask"
- "update\n", proc);
- }
- ptr += MAX_SSID_PER_RANGE*4;
- }
- mutex_unlock(&driver->diag_cntl_mutex);
-}
-
static int diag_process_apps_pkt(unsigned char *buf, int len)
{
uint16_t subsys_cmd_code;
int subsys_id, ssid_first, ssid_last, ssid_range;
int packet_type = 1, i, cmd_code;
- int rt_mask, rt_first_ssid, rt_last_ssid, rt_mask_size;
unsigned char *temp = buf;
- uint8_t *rt_mask_ptr;
- int data_type, equip_id, num_items;
+ int data_type;
#if defined(CONFIG_DIAG_OVER_USB)
- int payload_length;
unsigned char *ptr;
#endif
- /* Set log masks */
- if (*buf == 0x73 && *(int *)(buf+4) == 3) {
- buf += 8;
- /* Read Equip ID and pass as first param below*/
- diag_update_log_mask(*(int *)buf, buf+8, *(int *)(buf+4));
- diag_update_userspace_clients(LOG_MASKS_TYPE);
-#if defined(CONFIG_DIAG_OVER_USB)
- if (chk_apps_only()) {
- driver->apps_rsp_buf[0] = 0x73;
- *(int *)(driver->apps_rsp_buf + 4) = 0x3; /* op. ID */
- *(int *)(driver->apps_rsp_buf + 8) = 0x0; /* success */
- payload_length = 8 + ((*(int *)(buf + 4)) + 7)/8;
- for (i = 0; i < payload_length; i++)
- *(int *)(driver->apps_rsp_buf+12+i) = *(buf+i);
- if (driver->ch_cntl)
- diag_send_log_mask_update(driver->ch_cntl,
- *(int *)buf);
- if (driver->chlpass_cntl)
- diag_send_log_mask_update(driver->chlpass_cntl,
- *(int *)buf);
- if (driver->ch_wcnss_cntl)
- diag_send_log_mask_update(driver->ch_wcnss_cntl,
- *(int *)buf);
- ENCODE_RSP_AND_SEND(12 + payload_length - 1);
- return 0;
- } else
- buf = temp;
-#endif
- } /* Get log masks */
- else if (*buf == 0x73 && *(int *)(buf+4) == 4) {
-#if defined(CONFIG_DIAG_OVER_USB)
- if (!(driver->ch) && chk_apps_only()) {
- equip_id = *(int *)(buf + 8);
- num_items = *(int *)(buf + 12);
- driver->apps_rsp_buf[0] = 0x73;
- driver->apps_rsp_buf[1] = 0x0;
- driver->apps_rsp_buf[2] = 0x0;
- driver->apps_rsp_buf[3] = 0x0;
- *(int *)(driver->apps_rsp_buf + 4) = 0x4;
- if (!chk_equip_id_and_mask(equip_id,
- driver->apps_rsp_buf+20))
- *(int *)(driver->apps_rsp_buf + 8) = 0x0;
- else
- *(int *)(driver->apps_rsp_buf + 8) = 0x1;
- *(int *)(driver->apps_rsp_buf + 12) = equip_id;
- *(int *)(driver->apps_rsp_buf + 16) = num_items;
- ENCODE_RSP_AND_SEND(20+(num_items+7)/8-1);
- return 0;
- } else
- buf = temp;
-#endif
- } /* Disable log masks */
- else if (*buf == 0x73 && *(int *)(buf+4) == 0) {
- /* Disable mask for each log code */
- diag_disable_log_mask();
- diag_update_userspace_clients(LOG_MASKS_TYPE);
-#if defined(CONFIG_DIAG_OVER_USB)
- if (chk_apps_only()) {
- driver->apps_rsp_buf[0] = 0x73;
- driver->apps_rsp_buf[1] = 0x0;
- driver->apps_rsp_buf[2] = 0x0;
- driver->apps_rsp_buf[3] = 0x0;
- *(int *)(driver->apps_rsp_buf + 4) = 0x0;
- *(int *)(driver->apps_rsp_buf + 8) = 0x0; /* status */
- if (driver->ch_cntl)
- diag_send_log_mask_update(driver->ch_cntl,
- ALL_EQUIP_ID);
- if (driver->chlpass_cntl)
- diag_send_log_mask_update(driver->chlpass_cntl,
- ALL_EQUIP_ID);
- if (driver->ch_wcnss_cntl)
- diag_send_log_mask_update(driver->ch_wcnss_cntl,
- ALL_EQUIP_ID);
- ENCODE_RSP_AND_SEND(11);
- return 0;
- }
-#endif
- } /* Get runtime message mask */
- else if ((*buf == 0x7d) && (*(buf+1) == 0x3)) {
- ssid_first = *(uint16_t *)(buf + 2);
- ssid_last = *(uint16_t *)(buf + 4);
-#if defined(CONFIG_DIAG_OVER_USB)
- if (!(driver->ch) && chk_apps_only()) {
- driver->apps_rsp_buf[0] = 0x7d;
- driver->apps_rsp_buf[1] = 0x3;
- *(uint16_t *)(driver->apps_rsp_buf+2) = ssid_first;
- *(uint16_t *)(driver->apps_rsp_buf+4) = ssid_last;
- driver->apps_rsp_buf[6] = 0x1; /* Success Status */
- driver->apps_rsp_buf[7] = 0x0;
- rt_mask_ptr = driver->msg_masks;
- while (*(uint32_t *)(rt_mask_ptr + 4)) {
- rt_first_ssid = *(uint32_t *)rt_mask_ptr;
- rt_mask_ptr += 8; /* +8 to skip 'last' */
- rt_last_ssid = *(uint32_t *)rt_mask_ptr;
- rt_mask_ptr += 4;
- if (ssid_first == rt_first_ssid && ssid_last ==
- rt_last_ssid) {
- rt_mask_size = 4 * (rt_last_ssid -
- rt_first_ssid + 1);
- memcpy(driver->apps_rsp_buf+8,
- rt_mask_ptr, rt_mask_size);
- ENCODE_RSP_AND_SEND(8+rt_mask_size-1);
- return 0;
- }
- rt_mask_ptr += MAX_SSID_PER_RANGE*4;
- }
- } else
- buf = temp;
-#endif
- } /* Set runtime message mask */
- else if ((*buf == 0x7d) && (*(buf+1) == 0x4)) {
- ssid_first = *(uint16_t *)(buf + 2);
- ssid_last = *(uint16_t *)(buf + 4);
- ssid_range = 4 * (ssid_last - ssid_first + 1);
- pr_debug("diag: received mask update for ssid_first = %d,"
- " ssid_last = %d", ssid_first, ssid_last);
- diag_update_msg_mask(ssid_first, ssid_last , buf + 8);
- diag_update_userspace_clients(MSG_MASKS_TYPE);
-#if defined(CONFIG_DIAG_OVER_USB)
- if (chk_apps_only()) {
- for (i = 0; i < 8 + ssid_range; i++)
- *(driver->apps_rsp_buf + i) = *(buf+i);
- *(driver->apps_rsp_buf + 6) = 0x1;
- if (driver->ch_cntl)
- diag_send_msg_mask_update(driver->ch_cntl,
- ssid_first, ssid_last, MODEM_PROC);
- if (driver->chlpass_cntl)
- diag_send_msg_mask_update(driver->chlpass_cntl,
- ssid_first, ssid_last, LPASS_PROC);
- if (driver->ch_wcnss_cntl)
- diag_send_msg_mask_update(driver->ch_wcnss_cntl,
- ssid_first, ssid_last, WCNSS_PROC);
- ENCODE_RSP_AND_SEND(8 + ssid_range - 1);
- return 0;
- } else
- buf = temp;
-#endif
- } /* Set ALL runtime message mask */
- else if ((*buf == 0x7d) && (*(buf+1) == 0x5)) {
- rt_mask = *(int *)(buf + 4);
- diag_set_msg_mask(rt_mask);
- diag_update_userspace_clients(MSG_MASKS_TYPE);
-#if defined(CONFIG_DIAG_OVER_USB)
- if (chk_apps_only()) {
- driver->apps_rsp_buf[0] = 0x7d; /* cmd_code */
- driver->apps_rsp_buf[1] = 0x5; /* set subcommand */
- driver->apps_rsp_buf[2] = 1; /* success */
- driver->apps_rsp_buf[3] = 0; /* rsvd */
- *(int *)(driver->apps_rsp_buf + 4) = rt_mask;
- /* send msg mask update to peripheral */
- if (driver->ch_cntl)
- diag_send_msg_mask_update(driver->ch_cntl,
- ALL_SSID, ALL_SSID, MODEM_PROC);
- if (driver->chlpass_cntl)
- diag_send_msg_mask_update(driver->chlpass_cntl,
- ALL_SSID, ALL_SSID, LPASS_PROC);
- if (driver->ch_wcnss_cntl)
- diag_send_msg_mask_update(driver->ch_wcnss_cntl,
- ALL_SSID, ALL_SSID, WCNSS_PROC);
- ENCODE_RSP_AND_SEND(7);
- return 0;
- } else
- buf = temp;
-#endif
- } else if (*buf == 0x82) { /* event mask change */
- buf += 4;
- diag_event_num_bytes = (*(uint16_t *)buf)/8+1;
- diag_update_event_mask(buf, 1, (*(uint16_t *)buf)/8+1);
- diag_update_userspace_clients(EVENT_MASKS_TYPE);
-#if defined(CONFIG_DIAG_OVER_USB)
- if (chk_apps_only()) {
- driver->apps_rsp_buf[0] = 0x82;
- driver->apps_rsp_buf[1] = 0x0;
- *(uint16_t *)(driver->apps_rsp_buf + 2) = 0x0;
- *(uint16_t *)(driver->apps_rsp_buf + 4) =
- EVENT_LAST_ID + 1;
- memcpy(driver->apps_rsp_buf+6, driver->event_masks,
- EVENT_LAST_ID/8+1);
- if (driver->ch_cntl)
- diag_send_event_mask_update(driver->ch_cntl,
- diag_event_num_bytes);
- if (driver->chlpass_cntl)
- diag_send_event_mask_update(
- driver->chlpass_cntl,
- diag_event_num_bytes);
- if (driver->ch_wcnss_cntl)
- diag_send_event_mask_update(
- driver->ch_wcnss_cntl, diag_event_num_bytes);
- ENCODE_RSP_AND_SEND(6 + EVENT_LAST_ID/8);
- return 0;
- } else
- buf = temp;
-#endif
- } else if (*buf == 0x60) {
- diag_event_config = *(buf+1);
- diag_toggle_event_mask(*(buf+1));
- diag_update_userspace_clients(EVENT_MASKS_TYPE);
-#if defined(CONFIG_DIAG_OVER_USB)
- if (chk_apps_only()) {
- driver->apps_rsp_buf[0] = 0x60;
- driver->apps_rsp_buf[1] = 0x0;
- driver->apps_rsp_buf[2] = 0x0;
- if (driver->ch_cntl)
- diag_send_event_mask_update(driver->ch_cntl,
- diag_event_num_bytes);
- if (driver->chlpass_cntl)
- diag_send_event_mask_update(
- driver->chlpass_cntl,
- diag_event_num_bytes);
- if (driver->ch_wcnss_cntl)
- diag_send_event_mask_update(
- driver->ch_wcnss_cntl, diag_event_num_bytes);
- ENCODE_RSP_AND_SEND(2);
- return 0;
- }
-#endif
- }
+ /* Check if the command is a supported mask command */
+ if (diag_process_apps_masks(buf, len) == 0)
+ return 0;
+
/* Check for registered clients and forward packet to apropriate proc */
cmd_code = (int)(*(char *)buf);
temp++;
@@ -1334,7 +675,7 @@
for (i = 0; i < 4; i++)
*(driver->apps_rsp_buf+i) = *(buf+i);
*(uint32_t *)(driver->apps_rsp_buf+4) = PKT_SIZE;
- ENCODE_RSP_AND_SEND(7);
+ encode_rsp_and_send(7);
return 0;
}
/* Check for Apps Only & get event mask request */
@@ -1345,7 +686,7 @@
*(uint16_t *)(driver->apps_rsp_buf + 4) = EVENT_LAST_ID + 1;
for (i = 0; i < EVENT_LAST_ID/8 + 1; i++)
*(unsigned char *)(driver->apps_rsp_buf + 6 + i) = 0x0;
- ENCODE_RSP_AND_SEND(6 + EVENT_LAST_ID/8);
+ encode_rsp_and_send(6 + EVENT_LAST_ID/8);
return 0;
}
/* Get log ID range & Check for Apps Only */
@@ -1370,7 +711,7 @@
*(int *)(driver->apps_rsp_buf + 64) = LOG_GET_ITEM_NUM(LOG_13);
*(int *)(driver->apps_rsp_buf + 68) = LOG_GET_ITEM_NUM(LOG_14);
*(int *)(driver->apps_rsp_buf + 72) = LOG_GET_ITEM_NUM(LOG_15);
- ENCODE_RSP_AND_SEND(75);
+ encode_rsp_and_send(75);
return 0;
}
/* Respond to Get SSID Range request message */
@@ -1428,7 +769,7 @@
*(uint16_t *)(driver->apps_rsp_buf + 94) = MSG_SSID_21_LAST;
*(uint16_t *)(driver->apps_rsp_buf + 96) = MSG_SSID_22;
*(uint16_t *)(driver->apps_rsp_buf + 98) = MSG_SSID_22_LAST;
- ENCODE_RSP_AND_SEND(99);
+ encode_rsp_and_send(99);
return 0;
}
/* Check for Apps Only Respond to Get Subsys Build mask */
@@ -1540,14 +881,14 @@
*(int *)(ptr + i) = msg_bld_masks_22[i/4];
break;
}
- ENCODE_RSP_AND_SEND(8 + ssid_range - 1);
+ encode_rsp_and_send(8 + ssid_range - 1);
return 0;
}
/* Check for download command */
else if ((cpu_is_msm8x60() || chk_apps_master()) && (*buf == 0x3A)) {
/* send response back */
driver->apps_rsp_buf[0] = *buf;
- ENCODE_RSP_AND_SEND(0);
+ encode_rsp_and_send(0);
msleep(5000);
/* call download API */
msm_set_restart_mode(RESTART_DLOAD);
@@ -1567,7 +908,7 @@
for (i = 0; i < 13; i++)
driver->apps_rsp_buf[i+3] = 0;
- ENCODE_RSP_AND_SEND(15);
+ encode_rsp_and_send(15);
return 0;
}
}
@@ -1578,7 +919,7 @@
for (i = 0; i < 55; i++)
driver->apps_rsp_buf[i] = 0;
- ENCODE_RSP_AND_SEND(54);
+ encode_rsp_and_send(54);
return 0;
}
/* respond to 0x7c command */
@@ -1591,12 +932,12 @@
chk_config_get_id();
*(unsigned char *)(driver->apps_rsp_buf + 12) = '\0';
*(unsigned char *)(driver->apps_rsp_buf + 13) = '\0';
- ENCODE_RSP_AND_SEND(13);
+ encode_rsp_and_send(13);
return 0;
}
}
#endif
- return packet_type;
+ return packet_type;
}
#ifdef CONFIG_DIAG_OVER_USB
@@ -1611,7 +952,7 @@
driver->apps_rsp_buf[0] = 0x13; /* error code 13 */
for (i = 0; i < index; i++)
driver->apps_rsp_buf[i+1] = *(driver->hdlc_buf+i);
- ENCODE_RSP_AND_SEND(index - 3);
+ encode_rsp_and_send(index - 3);
}
#else
static inline void diag_send_error_rsp(int index) {}
@@ -1994,27 +1335,6 @@
driver->use_device_tree = has_device_tree();
mutex_init(&driver->diag_cntl_mutex);
- if (driver->event_mask == NULL) {
- driver->event_mask = kzalloc(sizeof(
- struct diag_ctrl_event_mask), GFP_KERNEL);
- if (driver->event_mask == NULL)
- goto err;
- kmemleak_not_leak(driver->event_mask);
- }
- if (driver->msg_mask == NULL) {
- driver->msg_mask = kzalloc(sizeof(
- struct diag_ctrl_msg_mask), GFP_KERNEL);
- if (driver->msg_mask == NULL)
- goto err;
- kmemleak_not_leak(driver->msg_mask);
- }
- if (driver->log_mask == NULL) {
- driver->log_mask = kzalloc(sizeof(
- struct diag_ctrl_log_mask), GFP_KERNEL);
- if (driver->log_mask == NULL)
- goto err;
- kmemleak_not_leak(driver->log_mask);
- }
if (driver->buf_in_1 == NULL) {
driver->buf_in_1 = kzalloc(IN_BUF_SIZE, GFP_KERNEL);
if (driver->buf_in_1 == NULL)
@@ -2051,28 +1371,6 @@
goto err;
kmemleak_not_leak(driver->buf_in_wcnss_2);
}
-
- if (driver->buf_msg_mask_update == NULL) {
- driver->buf_msg_mask_update = kzalloc(APPS_BUF_SIZE,
- GFP_KERNEL);
- if (driver->buf_msg_mask_update == NULL)
- goto err;
- kmemleak_not_leak(driver->buf_msg_mask_update);
- }
- if (driver->buf_log_mask_update == NULL) {
- driver->buf_log_mask_update = kzalloc(APPS_BUF_SIZE,
- GFP_KERNEL);
- if (driver->buf_log_mask_update == NULL)
- goto err;
- kmemleak_not_leak(driver->buf_log_mask_update);
- }
- if (driver->buf_event_mask_update == NULL) {
- driver->buf_event_mask_update = kzalloc(APPS_BUF_SIZE,
- GFP_KERNEL);
- if (driver->buf_event_mask_update == NULL)
- goto err;
- kmemleak_not_leak(driver->buf_event_mask_update);
- }
if (driver->usb_buf_out == NULL &&
(driver->usb_buf_out = kzalloc(USB_MAX_OUT_BUF,
GFP_KERNEL)) == NULL)
@@ -2087,23 +1385,6 @@
if (driver->user_space_data == NULL)
goto err;
kmemleak_not_leak(driver->user_space_data);
- if (driver->msg_masks == NULL
- && (driver->msg_masks = kzalloc(MSG_MASK_SIZE,
- GFP_KERNEL)) == NULL)
- goto err;
- kmemleak_not_leak(driver->msg_masks);
- diag_create_msg_mask_table();
- diag_event_num_bytes = 0;
- if (driver->log_masks == NULL &&
- (driver->log_masks = kzalloc(LOG_MASK_SIZE, GFP_KERNEL)) == NULL)
- goto err;
- kmemleak_not_leak(driver->log_masks);
- driver->log_masks_length = (sizeof(struct mask_info))*MAX_EQUIP_ID;
- if (driver->event_masks == NULL &&
- (driver->event_masks = kzalloc(EVENT_MASK_SIZE,
- GFP_KERNEL)) == NULL)
- goto err;
- kmemleak_not_leak(driver->event_masks);
if (driver->client_map == NULL &&
(driver->client_map = kzalloc
((driver->num_clients) * sizeof(struct diag_client_map),
@@ -2192,12 +1473,6 @@
#ifdef CONFIG_DIAG_OVER_USB
INIT_WORK(&(driver->diag_proc_hdlc_work), diag_process_hdlc_fn);
INIT_WORK(&(driver->diag_read_work), diag_read_work_fn);
- INIT_WORK(&(driver->diag_modem_mask_update_work),
- diag_modem_mask_update_fn);
- INIT_WORK(&(driver->diag_lpass_mask_update_work),
- diag_lpass_mask_update_fn);
- INIT_WORK(&(driver->diag_wcnss_mask_update_work),
- diag_wcnss_mask_update_fn);
driver->legacy_ch = usb_diag_open(DIAG_LEGACY, driver,
diag_usb_legacy_notifier);
if (IS_ERR(driver->legacy_ch)) {
@@ -2210,40 +1485,34 @@
return;
err:
- pr_err("diag: Could not initialize diag buffers");
- kfree(driver->event_mask);
- kfree(driver->log_mask);
- kfree(driver->msg_mask);
- kfree(driver->buf_in_1);
- kfree(driver->buf_in_2);
- kfree(driver->buf_in_lpass_1);
- kfree(driver->buf_in_lpass_2);
- kfree(driver->buf_in_wcnss_1);
- kfree(driver->buf_in_wcnss_2);
- kfree(driver->buf_msg_mask_update);
- kfree(driver->buf_log_mask_update);
- kfree(driver->buf_event_mask_update);
- kfree(driver->usb_buf_out);
- kfree(driver->hdlc_buf);
- kfree(driver->msg_masks);
- kfree(driver->log_masks);
- kfree(driver->event_masks);
- kfree(driver->client_map);
- kfree(driver->buf_tbl);
- kfree(driver->data_ready);
- kfree(driver->table);
- kfree(driver->pkt_buf);
- kfree(driver->write_ptr_1);
- kfree(driver->write_ptr_2);
- kfree(driver->write_ptr_lpass_1);
- kfree(driver->write_ptr_lpass_2);
- kfree(driver->write_ptr_wcnss_1);
- kfree(driver->write_ptr_wcnss_2);
- kfree(driver->usb_read_ptr);
- kfree(driver->apps_rsp_buf);
- kfree(driver->user_space_data);
- if (driver->diag_wq)
- destroy_workqueue(driver->diag_wq);
+ pr_err("diag: Could not initialize diag buffers");
+ kfree(driver->buf_in_1);
+ kfree(driver->buf_in_2);
+ kfree(driver->buf_in_lpass_1);
+ kfree(driver->buf_in_lpass_2);
+ kfree(driver->buf_in_wcnss_1);
+ kfree(driver->buf_in_wcnss_2);
+ kfree(driver->buf_msg_mask_update);
+ kfree(driver->buf_log_mask_update);
+ kfree(driver->buf_event_mask_update);
+ kfree(driver->usb_buf_out);
+ kfree(driver->hdlc_buf);
+ kfree(driver->client_map);
+ kfree(driver->buf_tbl);
+ kfree(driver->data_ready);
+ kfree(driver->table);
+ kfree(driver->pkt_buf);
+ kfree(driver->write_ptr_1);
+ kfree(driver->write_ptr_2);
+ kfree(driver->write_ptr_lpass_1);
+ kfree(driver->write_ptr_lpass_2);
+ kfree(driver->write_ptr_wcnss_1);
+ kfree(driver->write_ptr_wcnss_2);
+ kfree(driver->usb_read_ptr);
+ kfree(driver->apps_rsp_buf);
+ kfree(driver->user_space_data);
+ if (driver->diag_wq)
+ destroy_workqueue(driver->diag_wq);
}
void diagfwd_exit(void)
@@ -2262,9 +1531,6 @@
platform_driver_unregister(&msm_smd_ch1_driver);
platform_driver_unregister(&msm_diag_dci_driver);
platform_driver_unregister(&diag_smd_lite_driver);
- kfree(driver->event_mask);
- kfree(driver->log_mask);
- kfree(driver->msg_mask);
kfree(driver->buf_in_1);
kfree(driver->buf_in_2);
kfree(driver->buf_in_lpass_1);
@@ -2276,9 +1542,6 @@
kfree(driver->buf_event_mask_update);
kfree(driver->usb_buf_out);
kfree(driver->hdlc_buf);
- kfree(driver->msg_masks);
- kfree(driver->log_masks);
- kfree(driver->event_masks);
kfree(driver->client_map);
kfree(driver->buf_tbl);
kfree(driver->data_ready);
diff --git a/drivers/char/diag/diagfwd.h b/drivers/char/diag/diagfwd.h
index cf7fda6..a0631d6 100644
--- a/drivers/char/diag/diagfwd.h
+++ b/drivers/char/diag/diagfwd.h
@@ -16,6 +16,9 @@
#define NO_PROCESS 0
#define NON_APPS_PROC -1
+#define CHK_OVERFLOW(bufStart, start, end, length) \
+ ((((bufStart) <= (start)) && ((end) - (start) >= (length))) ? 1 : 0)
+
void diagfwd_init(void);
void diagfwd_exit(void);
void diag_process_hdlc(void *data, unsigned len);
@@ -31,11 +34,9 @@
int chk_apps_only(void);
int chk_apps_master(void);
int chk_polling_response(void);
-void diag_send_event_mask_update(smd_channel_t *, int num_bytes);
-void diag_send_msg_mask_update(smd_channel_t *, int ssid_first,
- int ssid_last, int proc);
-void diag_send_log_mask_update(smd_channel_t *, int);
+void diag_update_userspace_clients(unsigned int type);
void diag_update_sleeping_process(int process_id, int data_type);
+void encode_rsp_and_send(int buf_length);
/* State for diag forwarding */
#ifdef CONFIG_DIAG_OVER_USB
int diagfwd_connect(void);
@@ -43,6 +44,5 @@
#endif
extern int diag_debug_buf_idx;
extern unsigned char diag_debug_buf[1024];
-extern int diag_event_num_bytes;
extern struct platform_driver msm_diag_dci_driver;
#endif
diff --git a/drivers/char/diag/diagfwd_cntl.c b/drivers/char/diag/diagfwd_cntl.c
index 9fc1164..4848a1d 100644
--- a/drivers/char/diag/diagfwd_cntl.c
+++ b/drivers/char/diag/diagfwd_cntl.c
@@ -17,9 +17,6 @@
#include "diagchar.h"
#include "diagfwd.h"
#include "diagfwd_cntl.h"
-#ifdef CONFIG_DEBUG_FS
-#include <linux/debugfs.h>
-#endif
/* tracks which peripheral is undergoing SSR */
static uint16_t reg_dirty;
#define HDR_SIZ 8
@@ -221,6 +218,8 @@
pr_err("diag: drop reg proc %d\n",
proc_num);
kfree(temp);
+ } else if (type != DIAG_CTRL_MSG_REG) {
+ flag = 1;
}
buf = buf + HDR_SIZ + data_len;
}
@@ -363,291 +362,3 @@
kfree(driver->buf_in_lpass_cntl);
kfree(driver->buf_in_wcnss_cntl);
}
-
-#ifdef CONFIG_DEBUG_FS
-#define DEBUG_BUF_SIZE 4096
-static struct dentry *diag_dbgfs_dent;
-static int diag_dbgfs_table_index;
-
-static ssize_t diag_dbgfs_read_status(struct file *file, char __user *ubuf,
- size_t count, loff_t *ppos)
-{
- char *buf;
- int ret;
-
- buf = kzalloc(sizeof(char) * DEBUG_BUF_SIZE, GFP_KERNEL);
- if (!buf) {
- pr_err("diag: %s, Error allocating memory\n", __func__);
- return -ENOMEM;
- }
-
- ret = scnprintf(buf, DEBUG_BUF_SIZE,
- "modem ch: 0x%x\n"
- "lpass ch: 0x%x\n"
- "riva ch: 0x%x\n"
- "dci ch: 0x%x\n"
- "modem cntl_ch: 0x%x\n"
- "lpass cntl_ch: 0x%x\n"
- "riva cntl_ch: 0x%x\n"
- "CPU Tools id: %d\n"
- "Apps only: %d\n"
- "Apps master: %d\n"
- "Check Polling Response: %d\n"
- "polling_reg_flag: %d\n"
- "uses device tree: %d\n"
- "in_busy_1: %d\n"
- "in_busy_2: %d\n"
- "in_busy_lpass_1: %d\n"
- "in_busy_lpass_2: %d\n"
- "in_busy_wcnss_1: %d\n"
- "in_busy_wcnss_2: %d\n"
- "in_busy_dci: %d\n"
- "logging_mode: %d\n",
- (unsigned int)driver->ch,
- (unsigned int)driver->chlpass,
- (unsigned int)driver->ch_wcnss,
- (unsigned int)driver->ch_dci,
- (unsigned int)driver->ch_cntl,
- (unsigned int)driver->chlpass_cntl,
- (unsigned int)driver->ch_wcnss_cntl,
- chk_config_get_id(),
- chk_apps_only(),
- chk_apps_master(),
- chk_polling_response(),
- driver->polling_reg_flag,
- driver->use_device_tree,
- driver->in_busy_1,
- driver->in_busy_2,
- driver->in_busy_lpass_1,
- driver->in_busy_lpass_2,
- driver->in_busy_wcnss_1,
- driver->in_busy_wcnss_2,
- driver->in_busy_dci,
- driver->logging_mode);
-
-#ifdef CONFIG_DIAG_OVER_USB
- ret += scnprintf(buf+ret, DEBUG_BUF_SIZE,
- "usb_connected: %d\n",
- driver->usb_connected);
-#endif
- ret = simple_read_from_buffer(ubuf, count, ppos, buf, ret);
-
- kfree(buf);
- return ret;
-}
-
-static ssize_t diag_dbgfs_read_workpending(struct file *file,
- char __user *ubuf, size_t count, loff_t *ppos)
-{
- char *buf;
- int ret;
-
- buf = kzalloc(sizeof(char) * DEBUG_BUF_SIZE, GFP_KERNEL);
- if (!buf) {
- pr_err("diag: %s, Error allocating memory\n", __func__);
- return -ENOMEM;
- }
-
- ret = scnprintf(buf, DEBUG_BUF_SIZE,
- "Pending status for work_stucts:\n"
- "diag_drain_work: %d\n"
- "diag_read_smd_work: %d\n"
- "diag_read_smd_cntl_work: %d\n"
- "diag_read_smd_lpass_work: %d\n"
- "diag_read_smd_lpass_cntl_work: %d\n"
- "diag_read_smd_wcnss_work: %d\n"
- "diag_read_smd_wcnss_cntl_work: %d\n"
- "diag_modem_mask_update_work: %d\n"
- "diag_lpass_mask_update_work: %d\n"
- "diag_wcnss_mask_update_work: %d\n"
- "diag_read_smd_dci_work: %d\n",
- work_pending(&(driver->diag_drain_work)),
- work_pending(&(driver->diag_read_smd_work)),
- work_pending(&(driver->diag_read_smd_cntl_work)),
- work_pending(&(driver->diag_read_smd_lpass_work)),
- work_pending(&(driver->diag_read_smd_lpass_cntl_work)),
- work_pending(&(driver->diag_read_smd_wcnss_work)),
- work_pending(&(driver->diag_read_smd_wcnss_cntl_work)),
- work_pending(&(driver->diag_modem_mask_update_work)),
- work_pending(&(driver->diag_lpass_mask_update_work)),
- work_pending(&(driver->diag_wcnss_mask_update_work)),
- work_pending(&(driver->diag_read_smd_dci_work)));
-
-#ifdef CONFIG_DIAG_OVER_USB
- ret += scnprintf(buf+ret, DEBUG_BUF_SIZE,
- "diag_proc_hdlc_work: %d\n"
- "diag_read_work: %d\n",
- work_pending(&(driver->diag_proc_hdlc_work)),
- work_pending(&(driver->diag_read_work)));
-#endif
- ret = simple_read_from_buffer(ubuf, count, ppos, buf, ret);
-
- kfree(buf);
- return ret;
-}
-
-static ssize_t diag_dbgfs_read_table(struct file *file, char __user *ubuf,
- size_t count, loff_t *ppos)
-{
- char *buf;
- int ret = 0;
- int i;
- int bytes_remaining;
- int bytes_in_buffer = 0;
- int bytes_written;
- int buf_size = (DEBUG_BUF_SIZE < count) ? DEBUG_BUF_SIZE : count;
-
- if (diag_dbgfs_table_index >= diag_max_reg) {
- /* Done. Reset to prepare for future requests */
- diag_dbgfs_table_index = 0;
- return 0;
- }
-
- buf = kzalloc(sizeof(char) * buf_size, GFP_KERNEL);
- if (!buf) {
- pr_err("diag: %s, Error allocating memory\n", __func__);
- return -ENOMEM;
- }
-
- bytes_remaining = buf_size;
- for (i = diag_dbgfs_table_index; i < diag_max_reg; i++) {
- /* Do not process empty entries in the table */
- if (driver->table[i].process_id == 0)
- continue;
-
- bytes_written = scnprintf(buf+bytes_in_buffer, bytes_remaining,
- "i: %3d, cmd_code: %4x, subsys_id: %4x, "
- "client: %2d, cmd_code_lo: %4x, "
- "cmd_code_hi: %4x, process_id: %5d\n",
- i,
- driver->table[i].cmd_code,
- driver->table[i].subsys_id,
- driver->table[i].client_id,
- driver->table[i].cmd_code_lo,
- driver->table[i].cmd_code_hi,
- driver->table[i].process_id);
-
- bytes_in_buffer += bytes_written;
-
- /* Check if there is room to add another table entry */
- bytes_remaining = buf_size - bytes_in_buffer;
- if (bytes_remaining < bytes_written)
- break;
- }
- diag_dbgfs_table_index = i;
-
- *ppos = 0;
- ret = simple_read_from_buffer(ubuf, count, ppos, buf, bytes_in_buffer);
-
- kfree(buf);
- return ret;
-}
-
-#ifdef CONFIG_DIAG_BRIDGE_CODE
-static ssize_t diag_dbgfs_read_hsic(struct file *file, char __user *ubuf,
- size_t count, loff_t *ppos)
-{
- char *buf;
- int ret;
-
- buf = kzalloc(sizeof(char) * DEBUG_BUF_SIZE, GFP_KERNEL);
- if (!buf) {
- pr_err("diag: %s, Error allocating memory\n", __func__);
- return -ENOMEM;
- }
-
- ret = scnprintf(buf, DEBUG_BUF_SIZE,
- "hsic ch: %d\n"
- "hsic_inited: %d\n"
- "hsic enabled: %d\n"
- "hsic_opened: %d\n"
- "hsic_suspend: %d\n"
- "in_busy_hsic_read_on_device: %d\n"
- "in_busy_hsic_write: %d\n"
- "count_hsic_pool: %d\n"
- "count_hsic_write_pool: %d\n"
- "diag_hsic_pool: %x\n"
- "diag_hsic_write_pool: %x\n"
- "write_len_mdm: %d\n"
- "num_hsic_buf_tbl_entries: %d\n"
- "usb_mdm_connected: %d\n"
- "diag_read_mdm_work: %d\n"
- "diag_read_hsic_work: %d\n"
- "diag_disconnect_work: %d\n"
- "diag_usb_read_complete_work: %d\n",
- driver->hsic_ch,
- driver->hsic_inited,
- driver->hsic_device_enabled,
- driver->hsic_device_opened,
- driver->hsic_suspend,
- driver->in_busy_hsic_read_on_device,
- driver->in_busy_hsic_write,
- driver->count_hsic_pool,
- driver->count_hsic_write_pool,
- (unsigned int)driver->diag_hsic_pool,
- (unsigned int)driver->diag_hsic_write_pool,
- driver->write_len_mdm,
- driver->num_hsic_buf_tbl_entries,
- driver->usb_mdm_connected,
- work_pending(&(driver->diag_read_mdm_work)),
- work_pending(&(driver->diag_read_hsic_work)),
- work_pending(&(driver->diag_disconnect_work)),
- work_pending(&(driver->diag_usb_read_complete_work)));
-
- ret = simple_read_from_buffer(ubuf, count, ppos, buf, ret);
-
- kfree(buf);
- return ret;
-}
-
-const struct file_operations diag_dbgfs_hsic_ops = {
- .read = diag_dbgfs_read_hsic,
-};
-#endif
-
-const struct file_operations diag_dbgfs_status_ops = {
- .read = diag_dbgfs_read_status,
-};
-
-const struct file_operations diag_dbgfs_table_ops = {
- .read = diag_dbgfs_read_table,
-};
-
-const struct file_operations diag_dbgfs_workpending_ops = {
- .read = diag_dbgfs_read_workpending,
-};
-
-void diag_debugfs_init(void)
-{
- diag_dbgfs_dent = debugfs_create_dir("diag", 0);
- if (IS_ERR(diag_dbgfs_dent))
- return;
-
- debugfs_create_file("status", 0444, diag_dbgfs_dent, 0,
- &diag_dbgfs_status_ops);
-
- debugfs_create_file("table", 0444, diag_dbgfs_dent, 0,
- &diag_dbgfs_table_ops);
-
- debugfs_create_file("work_pending", 0444, diag_dbgfs_dent, 0,
- &diag_dbgfs_workpending_ops);
-
-#ifdef CONFIG_DIAG_BRIDGE_CODE
- debugfs_create_file("hsic", 0444, diag_dbgfs_dent, 0,
- &diag_dbgfs_hsic_ops);
-#endif
-
- diag_dbgfs_table_index = 0;
-}
-
-void diag_debugfs_cleanup(void)
-{
- if (diag_dbgfs_dent) {
- debugfs_remove_recursive(diag_dbgfs_dent);
- diag_dbgfs_dent = NULL;
- }
-}
-#else
-void diag_debugfs_init(void) { }
-void diag_debugfs_cleanup(void) { }
-#endif
diff --git a/drivers/char/diag/diagfwd_cntl.h b/drivers/char/diag/diagfwd_cntl.h
index e6f5352..8a0ec3f 100644
--- a/drivers/char/diag/diagfwd_cntl.h
+++ b/drivers/char/diag/diagfwd_cntl.h
@@ -88,7 +88,5 @@
void diag_clean_modem_reg_fn(struct work_struct *);
void diag_clean_lpass_reg_fn(struct work_struct *);
void diag_clean_wcnss_reg_fn(struct work_struct *);
-void diag_debugfs_init(void);
-void diag_debugfs_cleanup(void);
#endif
diff --git a/drivers/coresight/Kconfig b/drivers/coresight/Kconfig
index a23fff0..ea4ad4f 100644
--- a/drivers/coresight/Kconfig
+++ b/drivers/coresight/Kconfig
@@ -31,6 +31,16 @@
For production builds, you should probably say 'N' here to avoid
potential power, performance and memory penalty.
+config MSM_QDSS_ETM_PCSAVE_DEFAULT_ENABLE
+ bool "Turn on PC saving by default"
+ depends on MSM_QDSS
+ help
+ Turns on program counter saving on reset by default. Otherwise,
+ PC saving is disabled by default but can be enabled via sysfs.
+
+ For production builds, you should probably say 'N' here to avoid
+ potential power penalty.
+
config CONTROL_TRACE
tristate "Turn on to control tracing"
help
diff --git a/drivers/coresight/coresight-etm.c b/drivers/coresight/coresight-etm.c
index ce4d7d1..50bae55 100644
--- a/drivers/coresight/coresight-etm.c
+++ b/drivers/coresight/coresight-etm.c
@@ -177,6 +177,15 @@
boot_enable, boot_enable, int, S_IRUGO
);
+#ifdef CONFIG_MSM_QDSS_ETM_PCSAVE_DEFAULT_ENABLE
+static int boot_pcsave_enable = 1;
+#else
+static int boot_pcsave_enable;
+#endif
+module_param_named(
+ boot_pcsave_enable, boot_pcsave_enable, int, S_IRUGO
+);
+
struct etm_drvdata {
void __iomem *base;
struct device *dev;
@@ -194,6 +203,7 @@
uint8_t reset;
uint32_t mode;
uint32_t ctrl;
+ uint8_t ctrl_pwrdwn;
uint32_t trigger_event;
uint32_t startstop_ctrl;
uint32_t enable_event;
@@ -220,12 +230,16 @@
uint32_t ctxid_mask;
uint32_t sync_freq;
uint32_t timestamp_event;
+ uint8_t pdcr_pwrup;
+ bool pcsave_impl;
+ bool pcsave_enable;
};
static struct etm_drvdata *etm0drvdata;
-/* ETM clock is derived from the processor clock and gets enabled on a
- * logical OR of below items on Krait (pass2 onwards):
+/*
+ * ETM clock is derived from the processor clock and gets enabled on a
+ * logical OR of below items on Krait (v2 onwards):
* 1.CPMR[ETMCLKEN] is 1
* 2.ETMCR[PD] is 0
* 3.ETMPDCR[PU] is 1
@@ -235,10 +249,34 @@
* 1., 2. and 3. above are permanent enables whereas 4. and 5. are temporary
* enables
*
- * We rely on 5. to be able to access ETMCR and then use 2. above for ETM
- * clock vote in the driver and the save-restore code uses 1. above
+ * We rely on 5. to be able to access ETMCR/ETMPDCR and then use 2./3. above
+ * for ETM clock vote in the driver and the save-restore code uses 1. above
* for its vote
*/
+static void etm_set_pwrdwn(struct etm_drvdata *drvdata)
+{
+ uint32_t etmcr;
+
+ /* ensure pending cp14 accesses complete before setting pwrdwn */
+ mb();
+ isb();
+ etmcr = etm_readl(drvdata, ETMCR);
+ etmcr |= BIT(0);
+ etm_writel(drvdata, etmcr, ETMCR);
+}
+
+static void etm_clr_pwrdwn(struct etm_drvdata *drvdata)
+{
+ uint32_t etmcr;
+
+ etmcr = etm_readl(drvdata, ETMCR);
+ etmcr &= ~BIT(0);
+ etm_writel(drvdata, etmcr, ETMCR);
+ /* ensure pwrup completes before subsequent cp14 accesses */
+ mb();
+ isb();
+}
+
static void etm_set_pwrup(struct etm_drvdata *drvdata)
{
uint32_t etmpdcr;
@@ -301,17 +339,94 @@
etm_readl(drvdata, ETMSR));
}
-static void __etm_enable(void *info)
+static void etm_save_pwrdwn(struct etm_drvdata *drvdata)
{
- int i;
+ drvdata->ctrl_pwrdwn = BVAL(etm_readl(drvdata, ETMCR), 0);
+}
+
+static void etm_restore_pwrdwn(struct etm_drvdata *drvdata)
+{
+ uint32_t etmcr;
+
+ etmcr = etm_readl(drvdata, ETMCR);
+ etmcr = (etmcr & ~BIT(0)) | drvdata->ctrl_pwrdwn;
+ etm_writel(drvdata, etmcr, ETMCR);
+}
+
+static void etm_save_pwrup(struct etm_drvdata *drvdata)
+{
+ drvdata->pdcr_pwrup = BVAL(etm_readl_mm(drvdata, ETMPDCR), 3);
+}
+
+static void etm_restore_pwrup(struct etm_drvdata *drvdata)
+{
+ uint32_t etmpdcr;
+
+ etmpdcr = etm_readl_mm(drvdata, ETMPDCR);
+ etmpdcr = (etmpdcr & ~BIT(3)) | (drvdata->pdcr_pwrup << 3);
+ etm_writel_mm(drvdata, etmpdcr, ETMPDCR);
+}
+
+static void etm_enable_pcsave(void *info)
+{
struct etm_drvdata *drvdata = info;
ETM_UNLOCK(drvdata);
- /* Vote for ETM power/clock enable */
+
+ etm_save_pwrup(drvdata);
+ /*
+ * ETMPDCR is only accessible via memory mapped interface and so use
+ * it first to enable power/clock to allow subsequent cp14 accesses.
+ */
etm_set_pwrup(drvdata);
+ etm_clr_pwrdwn(drvdata);
+ etm_restore_pwrup(drvdata);
+
+ ETM_LOCK(drvdata);
+}
+
+static void etm_disable_pcsave(void *info)
+{
+ struct etm_drvdata *drvdata = info;
+
+ ETM_UNLOCK(drvdata);
+
+ etm_save_pwrup(drvdata);
+ /*
+ * ETMPDCR is only accessible via memory mapped interface and so use
+ * it first to enable power/clock to allow subsequent cp14 accesses.
+ */
+ etm_set_pwrup(drvdata);
+ etm_set_pwrdwn(drvdata);
+ etm_restore_pwrup(drvdata);
+
+ ETM_LOCK(drvdata);
+}
+
+static void __etm_enable(void *info)
+{
+ int i;
+ uint32_t etmcr;
+ struct etm_drvdata *drvdata = info;
+
+ ETM_UNLOCK(drvdata);
+ /*
+ * Vote for ETM power/clock enable. ETMPDCR is only accessible via
+ * memory mapped interface and so use it first to enable power/clock
+ * to allow subsequent cp14 accesses.
+ */
+ etm_set_pwrup(drvdata);
+ etm_save_pwrdwn(drvdata);
+ /*
+ * Clear power down bit since when this bit is set writes to
+ * certain registers might be ignored.
+ */
+ etm_clr_pwrdwn(drvdata);
etm_set_prog(drvdata);
- etm_writel(drvdata, drvdata->ctrl | BIT(10), ETMCR);
+ etmcr = etm_readl(drvdata, ETMCR);
+ etmcr &= (BIT(10) | BIT(0));
+ etm_writel(drvdata, drvdata->ctrl | etmcr, ETMCR);
etm_writel(drvdata, drvdata->trigger_event, ETMTRIGGER);
etm_writel(drvdata, drvdata->startstop_ctrl, ETMTSSCR);
etm_writel(drvdata, drvdata->enable_event, ETMTEEVR);
@@ -348,6 +463,7 @@
etm_writel(drvdata, 0x00000000, ETMVMIDCVR);
etm_clr_prog(drvdata);
+ etm_restore_pwrdwn(drvdata);
ETM_LOCK(drvdata);
dev_dbg(drvdata->dev, "cpu: %d enable smp call done\n", drvdata->cpu);
@@ -385,11 +501,18 @@
struct etm_drvdata *drvdata = info;
ETM_UNLOCK(drvdata);
+ etm_save_pwrdwn(drvdata);
+ /*
+ * Clear power down bit since when this bit is set writes to
+ * certain registers might be ignored.
+ */
+ etm_clr_pwrdwn(drvdata);
etm_set_prog(drvdata);
/* program trace enable to low by using always false event */
etm_writel(drvdata, 0x6F | BIT(14), ETMTEEVR);
+ etm_restore_pwrdwn(drvdata);
/* Vote for ETM power/clock disable */
etm_clr_pwrup(drvdata);
ETM_LOCK(drvdata);
@@ -1346,6 +1469,7 @@
{
struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
unsigned long val = drvdata->sync_freq;
+
return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
}
@@ -1391,6 +1515,60 @@
static DEVICE_ATTR(timestamp_event, S_IRUGO | S_IWUSR, etm_show_timestamp_event,
etm_store_timestamp_event);
+static ssize_t etm_show_pcsave(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
+ unsigned long val;
+
+ val = drvdata->pcsave_enable;
+ return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
+}
+
+static int __etm_store_pcsave(struct etm_drvdata *drvdata, unsigned long val)
+{
+ int ret;
+
+ ret = clk_prepare_enable(drvdata->clk);
+ if (ret)
+ return ret;
+
+ mutex_lock(&drvdata->mutex);
+ if (val) {
+ smp_call_function_single(drvdata->cpu, etm_enable_pcsave,
+ drvdata, 1);
+ drvdata->pcsave_enable = true;
+ } else {
+ smp_call_function_single(drvdata->cpu, etm_disable_pcsave,
+ drvdata, 1);
+ drvdata->pcsave_enable = false;
+ }
+ mutex_unlock(&drvdata->mutex);
+
+ clk_disable_unprepare(drvdata->clk);
+ return 0;
+}
+
+static ssize_t etm_store_pcsave(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t size)
+{
+ struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
+ unsigned long val;
+ int ret;
+
+ if (sscanf(buf, "%lx", &val) != 1)
+ return -EINVAL;
+
+ ret = __etm_store_pcsave(drvdata, val);
+ if (ret)
+ return ret;
+
+ return size;
+}
+static DEVICE_ATTR(pcsave, S_IRUGO | S_IWUSR, etm_show_pcsave,
+ etm_store_pcsave);
+
static struct attribute *etm_attrs[] = {
&dev_attr_nr_addr_cmp.attr,
&dev_attr_nr_cntr.attr,
@@ -1471,8 +1649,17 @@
struct etm_drvdata *drvdata = info;
ETM_UNLOCK(drvdata);
- /* Vote for ETM power/clock enable */
+ /*
+ * Vote for ETM power/clock enable. ETMPDCR is only accessible via
+ * memory mapped interface and so use it first to enable power/clock
+ * to allow subsequent cp14 accesses.
+ */
etm_set_pwrup(drvdata);
+ /*
+ * Clear power down bit since when this bit is set writes to
+ * certain registers might be ignored.
+ */
+ etm_clr_pwrdwn(drvdata);
/* Set prog bit. It will be set from reset but this is included to
* ensure it is set
*/
@@ -1489,6 +1676,7 @@
drvdata->nr_ext_out = BMVAL(etmccr, 20, 22);
drvdata->nr_ctxid_cmp = BMVAL(etmccr, 24, 25);
+ etm_set_pwrdwn(drvdata);
/* Vote for ETM power/clock disable */
etm_clr_pwrup(drvdata);
ETM_LOCK(drvdata);
@@ -1657,11 +1845,24 @@
goto err0;
}
+ if (pdev->dev.of_node)
+ drvdata->pcsave_impl = of_property_read_bool(pdev->dev.of_node,
+ "qcom,pc-save");
+ if (drvdata->pcsave_impl) {
+ ret = device_create_file(&drvdata->csdev->dev,
+ &dev_attr_pcsave);
+ if (ret)
+ dev_err(dev, "ETM pcsave dev node creation failed\n");
+ }
+
dev_info(dev, "ETM initialized\n");
if (boot_enable)
coresight_enable(drvdata->csdev);
+ if (drvdata->pcsave_impl && boot_pcsave_enable)
+ __etm_store_pcsave(drvdata, true);
+
return 0;
err1:
clk_disable_unprepare(drvdata->clk);
@@ -1675,6 +1876,7 @@
{
struct etm_drvdata *drvdata = platform_get_drvdata(pdev);
+ device_remove_file(&drvdata->csdev->dev, &dev_attr_pcsave);
coresight_unregister(drvdata->csdev);
wake_lock_destroy(&drvdata->wake_lock);
mutex_destroy(&drvdata->mutex);
diff --git a/drivers/coresight/coresight-stm.c b/drivers/coresight/coresight-stm.c
index 70b2c43..f6a948b 100644
--- a/drivers/coresight/coresight-stm.c
+++ b/drivers/coresight/coresight-stm.c
@@ -724,6 +724,13 @@
dev_info(drvdata->dev, "STM initialized\n");
+ /*
+ * Enable and disable STM to undo the temporary default STM enable
+ * done by RPM.
+ */
+ coresight_enable(drvdata->csdev);
+ coresight_disable(drvdata->csdev);
+
if (boot_enable)
coresight_enable(drvdata->csdev);
diff --git a/drivers/coresight/coresight-tmc.c b/drivers/coresight/coresight-tmc.c
index 0be5882..13f69cd 100644
--- a/drivers/coresight/coresight-tmc.c
+++ b/drivers/coresight/coresight-tmc.c
@@ -1060,6 +1060,7 @@
goto err0;
}
memset(drvdata->vaddr, 0, drvdata->size);
+ drvdata->buf = drvdata->vaddr;
drvdata->out_mode = TMC_ETR_OUT_MODE_MEM;
ret = tmc_etr_bam_init(pdev, drvdata);
diff --git a/drivers/coresight/coresight.c b/drivers/coresight/coresight.c
index cccb5a7..3974f2e 100644
--- a/drivers/coresight/coresight.c
+++ b/drivers/coresight/coresight.c
@@ -377,8 +377,10 @@
list_for_each_entry(cd, &coresight_devs, dev_link) {
if (cd->id == curr_sink) {
- if (cd->enable && cd->ops->sink_ops->abort)
+ if (cd->enable && cd->ops->sink_ops->abort) {
cd->ops->sink_ops->abort(cd);
+ cd->enable = false;
+ }
}
}
out:
diff --git a/drivers/gpu/ion/ion.c b/drivers/gpu/ion/ion.c
index b23181f..a48e6b2 100644
--- a/drivers/gpu/ion/ion.c
+++ b/drivers/gpu/ion/ion.c
@@ -430,7 +430,8 @@
if (!((1 << heap->id) & heap_mask))
continue;
/* Do not allow un-secure heap if secure is specified */
- if (secure_allocation && (heap->type != ION_HEAP_TYPE_CP))
+ if (secure_allocation &&
+ (heap->type != (enum ion_heap_type) ION_HEAP_TYPE_CP))
continue;
buffer = ion_buffer_create(heap, dev, len, align, flags);
if (!IS_ERR_OR_NULL(buffer))
@@ -865,7 +866,7 @@
if (type == ION_HEAP_TYPE_SYSTEM_CONTIG ||
type == ION_HEAP_TYPE_CARVEOUT ||
- type == ION_HEAP_TYPE_CP)
+ type == (enum ion_heap_type) ION_HEAP_TYPE_CP)
seq_printf(s, " : %12lx", handle->buffer->priv_phys);
else
seq_printf(s, " : %12s", "N/A");
@@ -1656,7 +1657,7 @@
mutex_lock(&dev->lock);
for (n = rb_first(&dev->heaps); n != NULL; n = rb_next(n)) {
struct ion_heap *heap = rb_entry(n, struct ion_heap, node);
- if (heap->type != ION_HEAP_TYPE_CP)
+ if (heap->type != (enum ion_heap_type) ION_HEAP_TYPE_CP)
continue;
if (ION_HEAP(heap->id) != heap_id)
continue;
@@ -1684,7 +1685,7 @@
mutex_lock(&dev->lock);
for (n = rb_first(&dev->heaps); n != NULL; n = rb_next(n)) {
struct ion_heap *heap = rb_entry(n, struct ion_heap, node);
- if (heap->type != ION_HEAP_TYPE_CP)
+ if (heap->type != (enum ion_heap_type) ION_HEAP_TYPE_CP)
continue;
if (ION_HEAP(heap->id) != heap_id)
continue;
diff --git a/drivers/gpu/ion/ion_cp_heap.c b/drivers/gpu/ion/ion_cp_heap.c
index 9f33859..2070abf 100644
--- a/drivers/gpu/ion/ion_cp_heap.c
+++ b/drivers/gpu/ion/ion_cp_heap.c
@@ -930,7 +930,7 @@
cp_heap->kmap_uncached_count = 0;
cp_heap->total_size = heap_data->size;
cp_heap->heap.ops = &cp_heap_ops;
- cp_heap->heap.type = ION_HEAP_TYPE_CP;
+ cp_heap->heap.type = (enum ion_heap_type) ION_HEAP_TYPE_CP;
cp_heap->heap_protected = HEAP_NOT_PROTECTED;
cp_heap->secure_base = cp_heap->base;
cp_heap->secure_size = heap_data->size;
diff --git a/drivers/gpu/ion/ion_heap.c b/drivers/gpu/ion/ion_heap.c
index 165a7bf..4c83d75 100644
--- a/drivers/gpu/ion/ion_heap.c
+++ b/drivers/gpu/ion/ion_heap.c
@@ -24,7 +24,7 @@
{
struct ion_heap *heap = NULL;
- switch (heap_data->type) {
+ switch ((int) heap_data->type) {
case ION_HEAP_TYPE_SYSTEM_CONTIG:
heap = ion_system_contig_heap_create(heap_data);
break;
@@ -63,7 +63,7 @@
if (!heap)
return;
- switch (heap->type) {
+ switch ((int) heap->type) {
case ION_HEAP_TYPE_SYSTEM_CONTIG:
ion_system_contig_heap_destroy(heap);
break;
diff --git a/drivers/gpu/ion/msm/msm_ion.c b/drivers/gpu/ion/msm/msm_ion.c
index 4c9be1d..deff514 100644
--- a/drivers/gpu/ion/msm/msm_ion.c
+++ b/drivers/gpu/ion/msm/msm_ion.c
@@ -264,7 +264,7 @@
if (!heap->base && heap->extra_data) {
unsigned int align = 0;
- switch (heap->type) {
+ switch ((int) heap->type) {
case ION_HEAP_TYPE_CARVEOUT:
align =
((struct ion_co_heap_pdata *) heap->extra_data)->align;
@@ -346,7 +346,7 @@
{
int ret = 0;
- switch (heap->type) {
+ switch ((int) heap->type) {
case ION_HEAP_TYPE_CP:
{
heap->extra_data = kzalloc(sizeof(struct ion_cp_heap_pdata),
@@ -414,7 +414,7 @@
int ret = of_property_read_u32(node, "qcom,heap-align", &val);
if (!ret) {
- switch (heap->type) {
+ switch ((int) heap->type) {
case ION_HEAP_TYPE_CP:
{
struct ion_cp_heap_pdata *extra =
diff --git a/drivers/gpu/msm/adreno_a2xx.c b/drivers/gpu/msm/adreno_a2xx.c
index 2388fff..8de2c70 100644
--- a/drivers/gpu/msm/adreno_a2xx.c
+++ b/drivers/gpu/msm/adreno_a2xx.c
@@ -1749,9 +1749,6 @@
if (status & (CP_INT_CNTL__IB1_INT_MASK | CP_INT_CNTL__RB_INT_MASK)) {
queue_work(device->work_queue, &device->ts_expired_ws);
wake_up_interruptible_all(&device->wait_queue);
- atomic_notifier_call_chain(&(device->ts_notifier_list),
- device->id,
- NULL);
}
}
diff --git a/drivers/gpu/msm/adreno_a3xx.c b/drivers/gpu/msm/adreno_a3xx.c
index 7bf928f..e5959c1 100644
--- a/drivers/gpu/msm/adreno_a3xx.c
+++ b/drivers/gpu/msm/adreno_a3xx.c
@@ -2587,9 +2587,6 @@
/* Schedule work to free mem and issue ibs */
queue_work(device->work_queue, &device->ts_expired_ws);
-
- atomic_notifier_call_chain(&device->ts_notifier_list,
- device->id, NULL);
}
#define A3XX_IRQ_CALLBACK(_c) { .func = _c }
diff --git a/drivers/gpu/msm/adreno_ringbuffer.c b/drivers/gpu/msm/adreno_ringbuffer.c
index 1ff219b..15ffa9e 100644
--- a/drivers/gpu/msm/adreno_ringbuffer.c
+++ b/drivers/gpu/msm/adreno_ringbuffer.c
@@ -503,7 +503,7 @@
* support, we must use the global timestamp since issueibcmds
* will be returning that one.
*/
- if (context->flags & CTXT_FLAGS_PER_CONTEXT_TS)
+ if (context && context->flags & CTXT_FLAGS_PER_CONTEXT_TS)
context_id = context->id;
/* reserve space to temporarily turn off protected mode
@@ -518,7 +518,7 @@
total_sizedwords += 7;
total_sizedwords += 2; /* scratchpad ts for recovery */
- if (context->flags & CTXT_FLAGS_PER_CONTEXT_TS) {
+ if (context && context->flags & CTXT_FLAGS_PER_CONTEXT_TS) {
total_sizedwords += 3; /* sop timestamp */
total_sizedwords += 4; /* eop timestamp */
total_sizedwords += 3; /* global timestamp without cache
@@ -591,7 +591,7 @@
GSL_RB_WRITE(ringcmds, rcmd_gpu, 0x00);
}
- if (context->flags & CTXT_FLAGS_PER_CONTEXT_TS) {
+ if (context && context->flags & CTXT_FLAGS_PER_CONTEXT_TS) {
/* start-of-pipeline timestamp */
GSL_RB_WRITE(ringcmds, rcmd_gpu,
cp_type3_packet(CP_MEM_WRITE, 2));
diff --git a/drivers/gpu/msm/kgsl.c b/drivers/gpu/msm/kgsl.c
index 5904abb..664d519 100644
--- a/drivers/gpu/msm/kgsl.c
+++ b/drivers/gpu/msm/kgsl.c
@@ -357,7 +357,7 @@
/* MAX - 1, there is one memdesc in memstore for device info */
if (id >= KGSL_MEMSTORE_MAX) {
- KGSL_DRV_ERR(dev_priv->device, "cannot have more than %d "
+ KGSL_DRV_INFO(dev_priv->device, "cannot have more than %d "
"ctxts due to memstore limitation\n",
KGSL_MEMSTORE_MAX);
idr_remove(&dev_priv->device->context_idr, id);
@@ -507,24 +507,6 @@
return ret;
}
-int kgsl_register_ts_notifier(struct kgsl_device *device,
- struct notifier_block *nb)
-{
- BUG_ON(device == NULL);
- return atomic_notifier_chain_register(&device->ts_notifier_list,
- nb);
-}
-EXPORT_SYMBOL(kgsl_register_ts_notifier);
-
-int kgsl_unregister_ts_notifier(struct kgsl_device *device,
- struct notifier_block *nb)
-{
- BUG_ON(device == NULL);
- return atomic_notifier_chain_unregister(&device->ts_notifier_list,
- nb);
-}
-EXPORT_SYMBOL(kgsl_unregister_ts_notifier);
-
int kgsl_check_timestamp(struct kgsl_device *device,
struct kgsl_context *context, unsigned int timestamp)
{
@@ -1080,11 +1062,8 @@
int result;
context = kgsl_find_context(dev_priv, param->context_id);
- if (context == NULL) {
- KGSL_DRV_ERR(dev_priv->device, "invalid context_id %d\n",
- param->context_id);
+ if (context == NULL)
return -EINVAL;
- }
/*
* A reference count is needed here, because waittimestamp may
* block with the device mutex unlocked and userspace could
@@ -1108,17 +1087,11 @@
context = kgsl_find_context(dev_priv, param->drawctxt_id);
if (context == NULL) {
result = -EINVAL;
- KGSL_DRV_ERR(dev_priv->device,
- "invalid context_id %d\n",
- param->drawctxt_id);
goto done;
}
if (param->flags & KGSL_CONTEXT_SUBMIT_IB_LIST) {
if (!param->numibs) {
- KGSL_DRV_ERR(dev_priv->device,
- "Invalid numibs as parameter: %d\n",
- param->numibs);
result = -EINVAL;
goto done;
}
@@ -1129,9 +1102,6 @@
*/
if (param->numibs > 10000) {
- KGSL_DRV_ERR(dev_priv->device,
- "Too many IBs submitted. count: %d max 10000\n",
- param->numibs);
result = -EINVAL;
goto done;
}
@@ -1218,11 +1188,8 @@
struct kgsl_context *context;
context = kgsl_find_context(dev_priv, param->context_id);
- if (context == NULL) {
- KGSL_DRV_ERR(dev_priv->device, "invalid context_id %d\n",
- param->context_id);
+ if (context == NULL)
return -EINVAL;
- }
return _cmdstream_readtimestamp(dev_priv, context,
param->type, ¶m->timestamp);
@@ -1287,11 +1254,8 @@
struct kgsl_context *context;
context = kgsl_find_context(dev_priv, param->context_id);
- if (context == NULL) {
- KGSL_DRV_ERR(dev_priv->device,
- "invalid drawctxt context_id %d\n", param->context_id);
+ if (context == NULL)
return -EINVAL;
- }
return _cmdstream_freememontimestamp(dev_priv, param->gpuaddr,
context, param->timestamp, param->type);
diff --git a/drivers/gpu/msm/kgsl_device.h b/drivers/gpu/msm/kgsl_device.h
index 2ca3a4f..dc597f5 100644
--- a/drivers/gpu/msm/kgsl_device.h
+++ b/drivers/gpu/msm/kgsl_device.h
@@ -155,7 +155,6 @@
struct kgsl_pwrctrl pwrctrl;
int open_count;
- struct atomic_notifier_head ts_notifier_list;
struct mutex mutex;
uint32_t state;
uint32_t requested_state;
@@ -210,7 +209,6 @@
.hwaccess_gate = COMPLETION_INITIALIZER((_dev).hwaccess_gate),\
.suspend_gate = COMPLETION_INITIALIZER((_dev).suspend_gate),\
.recovery_gate = COMPLETION_INITIALIZER((_dev).recovery_gate),\
- .ts_notifier_list = ATOMIC_NOTIFIER_INIT((_dev).ts_notifier_list),\
.idle_check_ws = __WORK_INITIALIZER((_dev).idle_check_ws,\
kgsl_idle_check),\
.ts_expired_ws = __WORK_INITIALIZER((_dev).ts_expired_ws,\
@@ -374,12 +372,6 @@
int kgsl_check_timestamp(struct kgsl_device *device,
struct kgsl_context *context, unsigned int timestamp);
-int kgsl_register_ts_notifier(struct kgsl_device *device,
- struct notifier_block *nb);
-
-int kgsl_unregister_ts_notifier(struct kgsl_device *device,
- struct notifier_block *nb);
-
int kgsl_device_platform_probe(struct kgsl_device *device);
void kgsl_device_platform_remove(struct kgsl_device *device);
diff --git a/drivers/gpu/msm/z180.c b/drivers/gpu/msm/z180.c
index 8ddc991..712bc60 100644
--- a/drivers/gpu/msm/z180.c
+++ b/drivers/gpu/msm/z180.c
@@ -212,10 +212,6 @@
queue_work(device->work_queue, &device->ts_expired_ws);
wake_up_interruptible(&device->wait_queue);
-
- atomic_notifier_call_chain(
- &(device->ts_notifier_list),
- device->id, NULL);
}
}
diff --git a/drivers/input/touchscreen/atmel_mxt_ts.c b/drivers/input/touchscreen/atmel_mxt_ts.c
index f10f433..f671806 100644
--- a/drivers/input/touchscreen/atmel_mxt_ts.c
+++ b/drivers/input/touchscreen/atmel_mxt_ts.c
@@ -1389,7 +1389,8 @@
}
data->t9_max_reportid = t9_object->max_reportid;
data->t9_min_reportid = t9_object->max_reportid -
- t9_object->num_report_ids + 1;
+ (t9_object->num_report_ids *
+ (t9_object->instances + 1)) + 1;
if (data->pdata->key_codes) {
t15_object = mxt_get_object(data, MXT_TOUCH_KEYARRAY_T15);
@@ -1398,7 +1399,8 @@
else {
data->t15_max_reportid = t15_object->max_reportid;
data->t15_min_reportid = t15_object->max_reportid -
- t15_object->num_report_ids + 1;
+ (t15_object->num_report_ids *
+ (t15_object->instances + 1)) + 1;
}
}
@@ -1409,7 +1411,8 @@
else {
data->t42_max_reportid = t42_object->max_reportid;
data->t42_min_reportid = t42_object->max_reportid -
- t42_object->num_report_ids + 1;
+ (t42_object->num_report_ids *
+ (t42_object->instances + 1)) + 1;
}
return 0;
@@ -2231,6 +2234,14 @@
}
}
+ /* calibrate */
+ if (data->pdata->need_calibration) {
+ error = mxt_write_object(data, MXT_GEN_COMMAND_T6,
+ MXT_COMMAND_CALIBRATE, 1);
+ if (error < 0)
+ dev_dbg(dev, "sending calibration command failed\n");
+ }
+
mutex_unlock(&input_dev->mutex);
return 0;
@@ -2447,6 +2458,9 @@
return -EINVAL;
}
+ /* need calibration during wakeup? */
+ pdata->need_calibration = of_property_read_bool(np,
+ "atmel,need-calibration");
/* config array size */
pdata->config_array_size = 0;
temp = NULL;
diff --git a/drivers/leds/leds-qpnp.c b/drivers/leds/leds-qpnp.c
index f42fb5e..13493b8 100644
--- a/drivers/leds/leds-qpnp.c
+++ b/drivers/leds/leds-qpnp.c
@@ -17,6 +17,7 @@
#include <linux/slab.h>
#include <linux/leds.h>
#include <linux/err.h>
+#include <linux/spinlock.h>
#include <linux/of_platform.h>
#include <linux/of_device.h>
#include <linux/spmi.h>
@@ -163,7 +164,7 @@
int id;
u16 base;
u8 reg;
- struct mutex lock;
+ spinlock_t lock;
struct wled_config_data *wled_cfg;
int max_current;
bool default_on;
@@ -299,7 +300,7 @@
return;
}
- mutex_lock(&led->lock);
+ spin_lock(&led->lock);
led->cdev.brightness = value;
switch (led->id) {
@@ -313,7 +314,7 @@
dev_err(led->cdev.dev, "Invalid LED(%d)\n", led->id);
break;
}
- mutex_unlock(&led->lock);
+ spin_unlock(&led->lock);
}
static int __devinit qpnp_led_set_max_brightness(struct qpnp_led_data *led)
@@ -653,7 +654,7 @@
return -EINVAL;
}
- mutex_init(&led->lock);
+ spin_lock_init(&led->lock);
rc = qpnp_led_initialize(led);
if (rc < 0)
@@ -680,7 +681,6 @@
return 0;
fail_id_check:
- mutex_destroy(&led->lock);
led_classdev_unregister(&led->cdev);
return rc;
}
@@ -689,7 +689,6 @@
{
struct qpnp_led_data *led = dev_get_drvdata(&spmi->dev);
- mutex_destroy(&led->lock);
led_classdev_unregister(&led->cdev);
return 0;
diff --git a/drivers/media/dvb/mpq/demux/mpq_dmx_plugin_common.c b/drivers/media/dvb/mpq/demux/mpq_dmx_plugin_common.c
index 7435ab2..18c3767 100644
--- a/drivers/media/dvb/mpq/demux/mpq_dmx_plugin_common.c
+++ b/drivers/media/dvb/mpq/demux/mpq_dmx_plugin_common.c
@@ -812,7 +812,7 @@
*kernel_mem = NULL;
} else {
*kernel_mem = ion_map_kernel(mpq_demux->ion_client,
- ion_handle, ionflag);
+ ion_handle);
if (*kernel_mem == NULL) {
MPQ_DVB_ERR_PRINT("%s: ion_map_kernel failed\n",
__func__);
diff --git a/drivers/media/radio/radio-tavarua.c b/drivers/media/radio/radio-tavarua.c
index af4c2c9..eb16f2d 100644
--- a/drivers/media/radio/radio-tavarua.c
+++ b/drivers/media/radio/radio-tavarua.c
@@ -1940,7 +1940,7 @@
}
/* Check for Bahama V2 variant*/
- if (bahama_version == 0x09) {
+ if ((bahama_version == 0x09) || (bahama_version == 0x0a)) {
/* In case of Bahama v2, forcefully enable the
* internal analog and digital voltage controllers
@@ -2179,7 +2179,8 @@
/* Set the index based on the bt status*/
index = bt_status ? 1 : 0;
/* Check for Bahama's existance and Bahama V2 variant*/
- if (bahama_present && (bahama_version == 0x09)) {
+ if (bahama_present
+ && (bahama_version == 0x09 || bahama_version == 0x0a)) {
radio->marimba->mod_id = SLAVE_ID_BAHAMA;
/* actual value itself used as mask*/
retval = marimba_write_bit_mask(radio->marimba,
@@ -4149,7 +4150,7 @@
/* use xfr for interrupt setup */
if (radio->chipID == MARIMBA_2_1 || radio->chipID == BAHAMA_1_0
- || radio->chipID == BAHAMA_2_0) {
+ || radio->chipID == BAHAMA_2_0 || radio->chipID == BAHAMA_2_1) {
FMDBG("Setting interrupts\n");
retval = sync_write_xfr(radio, INT_CTRL, int_ctrl);
/* use register write to setup interrupts */
@@ -4175,7 +4176,8 @@
* registers and it is not valid for MBA 2.1
*/
if ((radio->chipID != MARIMBA_2_1) && (radio->chipID != BAHAMA_1_0)
- && (radio->chipID != BAHAMA_2_0))
+ && (radio->chipID != BAHAMA_2_0)
+ && (radio->chipID != BAHAMA_2_1))
tavarua_handle_interrupts(radio);
return retval;
@@ -4208,7 +4210,7 @@
/* use xfr for interrupt setup */
wait_timeout = 100;
if (radio->chipID == MARIMBA_2_1 || radio->chipID == BAHAMA_1_0
- || radio->chipID == BAHAMA_2_0)
+ || radio->chipID == BAHAMA_2_0 || radio->chipID == BAHAMA_2_1)
retval = sync_write_xfr(radio, INT_CTRL, lpm_buf);
/* use register write to setup interrupts */
else
diff --git a/drivers/media/video/msm/msm_isp.c b/drivers/media/video/msm/msm_isp.c
index 1e17c5c..2c95ef5 100644
--- a/drivers/media/video/msm/msm_isp.c
+++ b/drivers/media/video/msm/msm_isp.c
@@ -148,6 +148,8 @@
image_mode = MSM_V4L2_EXT_CAPTURE_MODE_RDI1;
else
image_mode = -1;
+ } else if (VFE_MSG_V2X_LIVESHOT_PRIMARY == vfe_msg) {
+ image_mode = MSM_V4L2_EXT_CAPTURE_MODE_V2X_LIVESHOT;
} else
image_mode = -1;
diff --git a/drivers/media/video/msm/msm_mctl_buf.c b/drivers/media/video/msm/msm_mctl_buf.c
index 3083bb2..a3c7243 100644
--- a/drivers/media/video/msm/msm_mctl_buf.c
+++ b/drivers/media/video/msm/msm_mctl_buf.c
@@ -557,37 +557,53 @@
struct msm_cam_v4l2_device *pcam = pmctl->pcam_ptr;
int idx;
- /* Valid image mode. Search the mctl node first.
- * If mctl node doesnt have the instance, then
- * search in the user's video node */
- if (pmctl->vfe_output_mode == VFE_OUTPUTS_MAIN_AND_THUMB
- || pmctl->vfe_output_mode == VFE_OUTPUTS_THUMB_AND_MAIN
- || pmctl->vfe_output_mode == VFE_OUTPUTS_MAIN_AND_PREVIEW) {
- if (pcam->mctl_node.dev_inst_map[img_mode]
- && is_buffer_queued(pcam, img_mode)) {
- idx = pcam->mctl_node.dev_inst_map[img_mode]->my_index;
- pcam_inst = pcam->mctl_node.dev_inst[idx];
- D("%s Found instance %p in mctl node device\n",
+ /* Valid image mode. Search the mctl node first.
+ * If mctl node doesnt have the instance, then
+ * search in the user's video node */
+ if (pmctl->vfe_output_mode == VFE_OUTPUTS_MAIN_AND_THUMB
+ || pmctl->vfe_output_mode == VFE_OUTPUTS_THUMB_AND_MAIN) {
+ if (pcam->mctl_node.dev_inst_map[img_mode]
+ && is_buffer_queued(pcam, img_mode)) {
+ idx = pcam->mctl_node.dev_inst_map[img_mode]
+ ->my_index;
+ pcam_inst = pcam->mctl_node.dev_inst[idx];
+ D("%s Found instance %p in mctl node device\n",
+ __func__, pcam_inst);
+ } else if (pcam->dev_inst_map[img_mode]) {
+ idx = pcam->dev_inst_map[img_mode]->my_index;
+ pcam_inst = pcam->dev_inst[idx];
+ D("%s Found instance %p in video device\n",
__func__, pcam_inst);
- } else if (pcam->dev_inst_map[img_mode]) {
- idx = pcam->dev_inst_map[img_mode]->my_index;
- pcam_inst = pcam->dev_inst[idx];
- D("%s Found instance %p in video device\n",
+ }
+ } else if (img_mode == MSM_V4L2_EXT_CAPTURE_MODE_V2X_LIVESHOT) {
+ img_mode = MSM_V4L2_EXT_CAPTURE_MODE_MAIN;
+ if (pcam->mctl_node.dev_inst_map[img_mode] &&
+ is_buffer_queued(pcam, img_mode)) {
+ idx = pcam->mctl_node.dev_inst_map[img_mode]
+ ->my_index;
+ pcam_inst = pcam->mctl_node.dev_inst[idx];
+ D("%s Found instance %p in mctl node device\n",
+ __func__, pcam_inst);
+ } else if (pcam->dev_inst_map[img_mode]) {
+ idx = pcam->dev_inst_map[img_mode]->my_index;
+ pcam_inst = pcam->dev_inst[idx];
+ D("%s Found instance %p in video device\n",
__func__, pcam_inst);
+ }
+ } else {
+ if (pcam->mctl_node.dev_inst_map[img_mode]) {
+ idx = pcam->mctl_node.dev_inst_map[img_mode]
+ ->my_index;
+ pcam_inst = pcam->mctl_node.dev_inst[idx];
+ D("%s Found instance %p in mctl node device\n",
+ __func__, pcam_inst);
+ } else if (pcam->dev_inst_map[img_mode]) {
+ idx = pcam->dev_inst_map[img_mode]->my_index;
+ pcam_inst = pcam->dev_inst[idx];
+ D("%s Found instance %p in video device\n",
+ __func__, pcam_inst);
+ }
}
- } else {
- if (pcam->mctl_node.dev_inst_map[img_mode]) {
- idx = pcam->mctl_node.dev_inst_map[img_mode]->my_index;
- pcam_inst = pcam->mctl_node.dev_inst[idx];
- D("%s Found instance %p in mctl node device\n",
- __func__, pcam_inst);
- } else if (pcam->dev_inst_map[img_mode]) {
- idx = pcam->dev_inst_map[img_mode]->my_index;
- pcam_inst = pcam->dev_inst[idx];
- D("%s Found instance %p in video device\n",
- __func__, pcam_inst);
- }
- }
return pcam_inst;
}
diff --git a/drivers/media/video/msm/server/msm_cam_server.c b/drivers/media/video/msm/server/msm_cam_server.c
index 74dd3f2..84aaa69 100644
--- a/drivers/media/video/msm/server/msm_cam_server.c
+++ b/drivers/media/video/msm/server/msm_cam_server.c
@@ -311,7 +311,7 @@
if (command->length > 0) {
command->value =
g_server_dev.server_queue[command->queue_idx].ctrl_data;
- if (command->length > max_control_command_size) {
+ if (command->length > MAX_SERVER_PAYLOAD_LENGTH) {
pr_err("%s: user data %d is too big (max %d)\n",
__func__, command->length,
max_control_command_size);
@@ -476,20 +476,22 @@
struct msm_camera_v4l2_ioctl_t *ioctl_ptr)
{
struct msm_ctrl_cmd ctrlcmd;
- void *temp_data;
+ void *temp_data = NULL;
int rc;
- temp_data = kzalloc(ioctl_ptr->len, GFP_KERNEL);
- if (!temp_data) {
- pr_err("%s could not allocate memory\n", __func__);
- rc = -ENOMEM;
- goto end;
- }
- if (copy_from_user((void *)temp_data,
- (void __user *)ioctl_ptr->ioctl_ptr,
- ioctl_ptr->len)) {
- ERR_COPY_FROM_USER();
- rc = -EFAULT;
- goto copy_from_user_failed;
+ if (ioctl_ptr->len > 0) {
+ temp_data = kzalloc(ioctl_ptr->len, GFP_KERNEL);
+ if (!temp_data) {
+ pr_err("%s could not allocate memory\n", __func__);
+ rc = -ENOMEM;
+ goto end;
+ }
+ if (copy_from_user((void *)temp_data,
+ (void __user *)ioctl_ptr->ioctl_ptr,
+ ioctl_ptr->len)) {
+ ERR_COPY_FROM_USER();
+ rc = -EFAULT;
+ goto copy_from_user_failed;
+ }
}
mutex_lock(&pcam->vid_lock);
@@ -505,6 +507,16 @@
rc = msm_server_control(&g_server_dev, 0, &ctrlcmd);
if (rc < 0)
pr_err("%s: send event failed\n", __func__);
+ else {
+ if (ioctl_ptr->len > 0) {
+ if (copy_to_user((void __user *)ioctl_ptr->ioctl_ptr,
+ (void *)temp_data,
+ ioctl_ptr->len)) {
+ ERR_COPY_TO_USER();
+ rc = -EFAULT;
+ }
+ }
+ }
mutex_unlock(&pcam->vid_lock);
kfree(temp_data);
@@ -1519,7 +1531,12 @@
pcam->server_queue_idx = server_q_idx;
queue = &g_server_dev.server_queue[server_q_idx];
queue->ctrl_data = kzalloc(sizeof(uint8_t) *
- max_control_command_size, GFP_KERNEL);
+ MAX_SERVER_PAYLOAD_LENGTH, GFP_KERNEL);
+ if (queue->ctrl_data == NULL) {
+ pr_err("%s: Could not allocate memory\n", __func__);
+ rc = -ENOMEM;
+ goto error;
+ }
msm_queue_init(&queue->ctrl_q, "control");
msm_queue_init(&queue->eventData_q, "eventdata");
queue->queue_active = 1;
@@ -2523,7 +2540,11 @@
*p_qidx = server_q_idx;
queue = &g_server_dev.server_queue[server_q_idx];
queue->ctrl_data = kzalloc(sizeof(uint8_t) *
- max_control_command_size, GFP_KERNEL);
+ MAX_SERVER_PAYLOAD_LENGTH, GFP_KERNEL);
+ if (!queue->ctrl_data) {
+ pr_err("%s: Could not find memory\n", __func__);
+ return -ENOMEM;
+ }
msm_queue_init(&queue->ctrl_q, "control");
msm_queue_init(&queue->eventData_q, "eventdata");
queue->queue_active = 1;
diff --git a/drivers/media/video/msm/vfe/msm_vfe7x27a_v4l2.c b/drivers/media/video/msm/vfe/msm_vfe7x27a_v4l2.c
index 9deae65..6440b8e 100644
--- a/drivers/media/video/msm/vfe/msm_vfe7x27a_v4l2.c
+++ b/drivers/media/video/msm/vfe/msm_vfe7x27a_v4l2.c
@@ -836,7 +836,12 @@
kfree(data);
return;
}
- free_buf = vfe2x_check_free_buffer(
+ if (vfe2x_ctrl->liveshot_enabled)
+ free_buf = vfe2x_check_free_buffer(
+ VFE_MSG_OUTPUT_IRQ,
+ VFE_MSG_V2X_LIVESHOT_PRIMARY);
+ else
+ free_buf = vfe2x_check_free_buffer(
VFE_MSG_OUTPUT_IRQ,
VFE_MSG_OUTPUT_PRIMARY);
CDBG("free_buf = %x\n",
@@ -1353,12 +1358,14 @@
vfe2x_subdev_notify(id, path);
if (op_mode & SNAPSHOT_MASK_MODE) {
- if (path == VFE_MSG_OUTPUT_PRIMARY)
+ if (path == VFE_MSG_OUTPUT_PRIMARY ||
+ path == VFE_MSG_V2X_LIVESHOT_PRIMARY)
outch = &vfe2x_ctrl->snap;
else if (path == VFE_MSG_OUTPUT_SECONDARY)
outch = &vfe2x_ctrl->thumb;
} else {
- if (path == VFE_MSG_OUTPUT_PRIMARY) {
+ if (path == VFE_MSG_OUTPUT_PRIMARY ||
+ path == VFE_MSG_V2X_LIVESHOT_PRIMARY) {
if (vfe2x_ctrl->zsl_mode)
outch = &vfe2x_ctrl->zsl_prim;
else
@@ -1380,12 +1387,14 @@
vfe2x_subdev_notify(id, path);
CDBG("Opmode = %d\n", op_mode);
if (op_mode & SNAPSHOT_MASK_MODE) {
- if (path == VFE_MSG_OUTPUT_PRIMARY)
+ if (path == VFE_MSG_OUTPUT_PRIMARY ||
+ path == VFE_MSG_V2X_LIVESHOT_PRIMARY)
outch = &vfe2x_ctrl->snap;
else if (path == VFE_MSG_OUTPUT_SECONDARY)
outch = &vfe2x_ctrl->thumb;
} else {
- if (path == VFE_MSG_OUTPUT_PRIMARY) {
+ if (path == VFE_MSG_OUTPUT_PRIMARY ||
+ path == VFE_MSG_V2X_LIVESHOT_PRIMARY) {
if (vfe2x_ctrl->zsl_mode)
outch = &vfe2x_ctrl->zsl_prim;
else
@@ -1413,10 +1422,12 @@
if (op_mode & SNAPSHOT_MASK_MODE) {
if (path == VFE_MSG_OUTPUT_SECONDARY)
ch = &vfe2x_ctrl->thumb;
- else if (path == VFE_MSG_OUTPUT_PRIMARY)
+ else if (path == VFE_MSG_OUTPUT_PRIMARY ||
+ path == VFE_MSG_V2X_LIVESHOT_PRIMARY)
ch = &vfe2x_ctrl->snap;
} else {
- if (path == VFE_MSG_OUTPUT_PRIMARY) {
+ if (path == VFE_MSG_OUTPUT_PRIMARY ||
+ path == VFE_MSG_V2X_LIVESHOT_PRIMARY) {
if (vfe2x_ctrl->zsl_mode)
ch = &vfe2x_ctrl->zsl_prim;
else
diff --git a/drivers/media/video/msm_wfd/enc-mfc-subdev.c b/drivers/media/video/msm_wfd/enc-mfc-subdev.c
index 3292d78..09a5e32 100644
--- a/drivers/media/video/msm_wfd/enc-mfc-subdev.c
+++ b/drivers/media/video/msm_wfd/enc-mfc-subdev.c
@@ -2199,7 +2199,7 @@
if (rc)
WFD_MSG_ERR("Failed to free recon buffer\n");
- if (IS_ERR_OR_NULL(
+ if (!IS_ERR_OR_NULL(
client_ctx->recon_buffer_ion_handle[i])) {
if (!inst->secure) {
ion_unmap_iommu(
diff --git a/drivers/media/video/vcap_v4l2.c b/drivers/media/video/vcap_v4l2.c
index e6cbae3..7ac78cb 100644
--- a/drivers/media/video/vcap_v4l2.c
+++ b/drivers/media/video/vcap_v4l2.c
@@ -1265,6 +1265,9 @@
}
rate = c_data->vc_format.clk_freq / 100 * 102;
+ if ((c_data->vc_format.hactive_end -
+ c_data->vc_format.hactive_start) > 539)
+ rate = 200000000;
rate_rc = clk_round_rate(dev->vcap_clk, rate);
if (rate_rc <= 0) {
pr_err("%s: Failed core rnd_rate\n", __func__);
diff --git a/drivers/mfd/marimba-core.c b/drivers/mfd/marimba-core.c
index 70ec2ec..6a8ea6e 100644
--- a/drivers/mfd/marimba-core.c
+++ b/drivers/mfd/marimba-core.c
@@ -76,12 +76,16 @@
rc = marimba_read_bit_mask(marimba, 0x00, &bahama_version, 1, 0x1F);
if (rc < 0)
return rc;
+ pr_debug("%s: Bahama version: 0x%x\n", __func__, bahama_version);
switch (bahama_version) {
case 0x08: /* varient of bahama v1 */
case 0x10:
case 0x00:
return BAHAMA_VER_1_0;
case 0x09: /* variant of bahama v2 */
+ case 0x0a: /* variant of bahama v2.1 */
+ /* Falling through because initialization */
+ /* and configuration for 2.0 and 2.1 are same */
return BAHAMA_VER_2_0;
default:
return BAHAMA_VER_UNSUPPORTED;
diff --git a/drivers/misc/qseecom.c b/drivers/misc/qseecom.c
index 4840e64..703aaa6 100644
--- a/drivers/misc/qseecom.c
+++ b/drivers/misc/qseecom.c
@@ -1697,7 +1697,6 @@
mutex_unlock(&pil_access_lock);
}
kfree(data);
- qsee_disable_clock_vote(CLK_DFAB);
return ret;
}
diff --git a/drivers/mmc/card/block.c b/drivers/mmc/card/block.c
index 63d2fa1..a9f1b53 100644
--- a/drivers/mmc/card/block.c
+++ b/drivers/mmc/card/block.c
@@ -60,6 +60,12 @@
#define MMC_SANITIZE_REQ_TIMEOUT 240000 /* msec */
+#define mmc_req_rel_wr(req) (((req->cmd_flags & REQ_FUA) || \
+ (req->cmd_flags & REQ_META)) && \
+ (rq_data_dir(req) == WRITE))
+#define PACKED_CMD_VER 0x01
+#define PACKED_CMD_WR 0x02
+
static DEFINE_MUTEX(block_mutex);
/*
@@ -125,9 +131,21 @@
MMC_BLK_NOMEDIUM,
};
+enum {
+ MMC_PACKED_N_IDX = -1,
+ MMC_PACKED_N_ZERO,
+ MMC_PACKED_N_SINGLE,
+};
+
module_param(perdev_minors, int, 0444);
MODULE_PARM_DESC(perdev_minors, "Minors numbers to allocate per device");
+static inline void mmc_blk_clear_packed(struct mmc_queue_req *mqrq)
+{
+ mqrq->packed_cmd = MMC_PACKED_NONE;
+ mqrq->packed_num = MMC_PACKED_N_ZERO;
+}
+
static struct mmc_blk_data *mmc_blk_get(struct gendisk *disk)
{
struct mmc_blk_data *md;
@@ -1096,12 +1114,61 @@
if (!brq->data.bytes_xfered)
return MMC_BLK_RETRY;
+ if (mq_mrq->packed_cmd != MMC_PACKED_NONE) {
+ if (unlikely(brq->data.blocks << 9 != brq->data.bytes_xfered))
+ return MMC_BLK_PARTIAL;
+ else
+ return MMC_BLK_SUCCESS;
+ }
+
if (blk_rq_bytes(req) != brq->data.bytes_xfered)
return MMC_BLK_PARTIAL;
return MMC_BLK_SUCCESS;
}
+static int mmc_blk_packed_err_check(struct mmc_card *card,
+ struct mmc_async_req *areq)
+{
+ struct mmc_queue_req *mq_rq = container_of(areq, struct mmc_queue_req,
+ mmc_active);
+ struct request *req = mq_rq->req;
+ int err, check, status;
+ u8 ext_csd[512];
+
+ mq_rq->packed_retries--;
+ check = mmc_blk_err_check(card, areq);
+ err = get_card_status(card, &status, 0);
+ if (err) {
+ pr_err("%s: error %d sending status command\n",
+ req->rq_disk->disk_name, err);
+ return MMC_BLK_ABORT;
+ }
+
+ if (status & R1_EXCEPTION_EVENT) {
+ err = mmc_send_ext_csd(card, ext_csd);
+ if (err) {
+ pr_err("%s: error %d sending ext_csd\n",
+ req->rq_disk->disk_name, err);
+ return MMC_BLK_ABORT;
+ }
+
+ if ((ext_csd[EXT_CSD_EXP_EVENTS_STATUS] &
+ EXT_CSD_PACKED_FAILURE) &&
+ (ext_csd[EXT_CSD_PACKED_CMD_STATUS] &
+ EXT_CSD_PACKED_GENERIC_ERROR)) {
+ if (ext_csd[EXT_CSD_PACKED_CMD_STATUS] &
+ EXT_CSD_PACKED_INDEXED_ERROR) {
+ mq_rq->packed_fail_idx =
+ ext_csd[EXT_CSD_PACKED_FAILURE_INDEX] - 1;
+ return MMC_BLK_PARTIAL;
+ }
+ }
+ }
+
+ return check;
+}
+
static void mmc_blk_rw_rq_prep(struct mmc_queue_req *mqrq,
struct mmc_card *card,
int disable_multi,
@@ -1257,10 +1324,206 @@
mmc_queue_bounce_pre(mqrq);
}
+static u8 mmc_blk_prep_packed_list(struct mmc_queue *mq, struct request *req)
+{
+ struct request_queue *q = mq->queue;
+ struct mmc_card *card = mq->card;
+ struct request *cur = req, *next = NULL;
+ struct mmc_blk_data *md = mq->data;
+ bool en_rel_wr = card->ext_csd.rel_param & EXT_CSD_WR_REL_PARAM_EN;
+ unsigned int req_sectors = 0, phys_segments = 0;
+ unsigned int max_blk_count, max_phys_segs;
+ u8 put_back = 0;
+ u8 max_packed_rw = 0;
+ u8 reqs = 0;
+
+ mmc_blk_clear_packed(mq->mqrq_cur);
+
+ if (!(md->flags & MMC_BLK_CMD23) ||
+ !card->ext_csd.packed_event_en)
+ goto no_packed;
+
+ if ((rq_data_dir(cur) == WRITE) &&
+ (card->host->caps2 & MMC_CAP2_PACKED_WR))
+ max_packed_rw = card->ext_csd.max_packed_writes;
+
+ if (max_packed_rw == 0)
+ goto no_packed;
+
+ if (mmc_req_rel_wr(cur) &&
+ (md->flags & MMC_BLK_REL_WR) &&
+ !en_rel_wr)
+ goto no_packed;
+
+ if (mmc_large_sec(card) &&
+ !IS_ALIGNED(blk_rq_sectors(cur), 8))
+ goto no_packed;
+
+ max_blk_count = min(card->host->max_blk_count,
+ card->host->max_req_size >> 9);
+ if (unlikely(max_blk_count > 0xffff))
+ max_blk_count = 0xffff;
+
+ max_phys_segs = queue_max_segments(q);
+ req_sectors += blk_rq_sectors(cur);
+ phys_segments += cur->nr_phys_segments;
+
+ if (rq_data_dir(cur) == WRITE) {
+ req_sectors++;
+ phys_segments++;
+ }
+
+ while (reqs < max_packed_rw - 1) {
+ spin_lock_irq(q->queue_lock);
+ next = blk_fetch_request(q);
+ spin_unlock_irq(q->queue_lock);
+ if (!next)
+ break;
+
+ if (mmc_large_sec(card) &&
+ !IS_ALIGNED(blk_rq_sectors(next), 8)) {
+ put_back = 1;
+ break;
+ }
+
+ if (next->cmd_flags & REQ_DISCARD ||
+ next->cmd_flags & REQ_FLUSH) {
+ put_back = 1;
+ break;
+ }
+
+ if (rq_data_dir(cur) != rq_data_dir(next)) {
+ put_back = 1;
+ break;
+ }
+
+ if (mmc_req_rel_wr(next) &&
+ (md->flags & MMC_BLK_REL_WR) &&
+ !en_rel_wr) {
+ put_back = 1;
+ break;
+ }
+
+ req_sectors += blk_rq_sectors(next);
+ if (req_sectors > max_blk_count) {
+ put_back = 1;
+ break;
+ }
+
+ phys_segments += next->nr_phys_segments;
+ if (phys_segments > max_phys_segs) {
+ put_back = 1;
+ break;
+ }
+
+ list_add_tail(&next->queuelist, &mq->mqrq_cur->packed_list);
+ cur = next;
+ reqs++;
+ }
+
+ if (put_back) {
+ spin_lock_irq(q->queue_lock);
+ blk_requeue_request(q, next);
+ spin_unlock_irq(q->queue_lock);
+ }
+
+ if (reqs > 0) {
+ list_add(&req->queuelist, &mq->mqrq_cur->packed_list);
+ mq->mqrq_cur->packed_num = ++reqs;
+ mq->mqrq_cur->packed_retries = reqs;
+ return reqs;
+ }
+
+no_packed:
+ mmc_blk_clear_packed(mq->mqrq_cur);
+ return 0;
+}
+
+static void mmc_blk_packed_hdr_wrq_prep(struct mmc_queue_req *mqrq,
+ struct mmc_card *card,
+ struct mmc_queue *mq)
+{
+ struct mmc_blk_request *brq = &mqrq->brq;
+ struct request *req = mqrq->req;
+ struct request *prq;
+ struct mmc_blk_data *md = mq->data;
+ bool do_rel_wr, do_data_tag;
+ u32 *packed_cmd_hdr = mqrq->packed_cmd_hdr;
+ u8 i = 1;
+
+ mqrq->packed_cmd = MMC_PACKED_WRITE;
+ mqrq->packed_blocks = 0;
+ mqrq->packed_fail_idx = MMC_PACKED_N_IDX;
+
+ memset(packed_cmd_hdr, 0, sizeof(mqrq->packed_cmd_hdr));
+ packed_cmd_hdr[0] = (mqrq->packed_num << 16) |
+ (PACKED_CMD_WR << 8) | PACKED_CMD_VER;
+
+ /*
+ * Argument for each entry of packed group
+ */
+ list_for_each_entry(prq, &mqrq->packed_list, queuelist) {
+ do_rel_wr = mmc_req_rel_wr(prq) && (md->flags & MMC_BLK_REL_WR);
+ do_data_tag = (card->ext_csd.data_tag_unit_size) &&
+ (prq->cmd_flags & REQ_META) &&
+ (rq_data_dir(prq) == WRITE) &&
+ ((brq->data.blocks * brq->data.blksz) >=
+ card->ext_csd.data_tag_unit_size);
+ /* Argument of CMD23 */
+ packed_cmd_hdr[(i * 2)] =
+ (do_rel_wr ? MMC_CMD23_ARG_REL_WR : 0) |
+ (do_data_tag ? MMC_CMD23_ARG_TAG_REQ : 0) |
+ blk_rq_sectors(prq);
+ /* Argument of CMD18 or CMD25 */
+ packed_cmd_hdr[((i * 2)) + 1] =
+ mmc_card_blockaddr(card) ?
+ blk_rq_pos(prq) : blk_rq_pos(prq) << 9;
+ mqrq->packed_blocks += blk_rq_sectors(prq);
+ i++;
+ }
+
+ memset(brq, 0, sizeof(struct mmc_blk_request));
+ brq->mrq.cmd = &brq->cmd;
+ brq->mrq.data = &brq->data;
+ brq->mrq.sbc = &brq->sbc;
+ brq->mrq.stop = &brq->stop;
+
+ brq->sbc.opcode = MMC_SET_BLOCK_COUNT;
+ brq->sbc.arg = MMC_CMD23_ARG_PACKED | (mqrq->packed_blocks + 1);
+ brq->sbc.flags = MMC_RSP_R1 | MMC_CMD_AC;
+
+ brq->cmd.opcode = MMC_WRITE_MULTIPLE_BLOCK;
+ brq->cmd.arg = blk_rq_pos(req);
+ if (!mmc_card_blockaddr(card))
+ brq->cmd.arg <<= 9;
+ brq->cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_R1 | MMC_CMD_ADTC;
+
+ brq->data.blksz = 512;
+ brq->data.blocks = mqrq->packed_blocks + 1;
+ brq->data.flags |= MMC_DATA_WRITE;
+
+ brq->stop.opcode = MMC_STOP_TRANSMISSION;
+ brq->stop.arg = 0;
+ brq->stop.flags = MMC_RSP_SPI_R1B | MMC_RSP_R1B | MMC_CMD_AC;
+
+ mmc_set_data_timeout(&brq->data, card);
+
+ brq->data.sg = mqrq->sg;
+ brq->data.sg_len = mmc_queue_map_sg(mq, mqrq);
+
+ mqrq->mmc_active.mrq = &brq->mrq;
+ mqrq->mmc_active.err_check = mmc_blk_packed_err_check;
+
+ mmc_queue_bounce_pre(mqrq);
+}
+
static int mmc_blk_cmd_err(struct mmc_blk_data *md, struct mmc_card *card,
struct mmc_blk_request *brq, struct request *req,
int ret)
{
+ struct mmc_queue_req *mq_rq;
+ mq_rq = container_of(brq, struct mmc_queue_req, brq);
+
/*
* If this is an SD card and we're writing, we can first
* mark the known good sectors as ok.
@@ -1277,11 +1540,75 @@
ret = blk_end_request(req, 0, blocks << 9);
} else
ret = blk_end_request(req, 0, brq->data.bytes_xfered);
- } else
- ret = blk_end_request(req, 0, brq->data.bytes_xfered);
+ } else {
+ if (mq_rq->packed_cmd == MMC_PACKED_NONE)
+ ret = blk_end_request(req, 0, brq->data.bytes_xfered);
+ }
return ret;
}
+static int mmc_blk_end_packed_req(struct mmc_queue_req *mq_rq)
+{
+ struct request *prq;
+ int idx = mq_rq->packed_fail_idx, i = 0;
+ int ret = 0;
+
+ while (!list_empty(&mq_rq->packed_list)) {
+ prq = list_entry_rq(mq_rq->packed_list.next);
+ if (idx == i) {
+ /* retry from error index */
+ mq_rq->packed_num -= idx;
+ mq_rq->req = prq;
+ ret = 1;
+
+ if (mq_rq->packed_num == MMC_PACKED_N_SINGLE) {
+ list_del_init(&prq->queuelist);
+ mmc_blk_clear_packed(mq_rq);
+ }
+ return ret;
+ }
+ list_del_init(&prq->queuelist);
+ blk_end_request(prq, 0, blk_rq_bytes(prq));
+ i++;
+ }
+
+ mmc_blk_clear_packed(mq_rq);
+ return ret;
+}
+static void mmc_blk_abort_packed_req(struct mmc_queue_req *mq_rq)
+{
+ struct request *prq;
+
+ while (!list_empty(&mq_rq->packed_list)) {
+ prq = list_entry_rq(mq_rq->packed_list.next);
+ list_del_init(&prq->queuelist);
+ blk_end_request(prq, -EIO, blk_rq_bytes(prq));
+ }
+
+ mmc_blk_clear_packed(mq_rq);
+}
+
+static void mmc_blk_revert_packed_req(struct mmc_queue *mq,
+ struct mmc_queue_req *mq_rq)
+{
+ struct request *prq;
+ struct request_queue *q = mq->queue;
+
+ while (!list_empty(&mq_rq->packed_list)) {
+ prq = list_entry_rq(mq_rq->packed_list.prev);
+ if (prq->queuelist.prev != &mq_rq->packed_list) {
+ list_del_init(&prq->queuelist);
+ spin_lock_irq(q->queue_lock);
+ blk_requeue_request(mq->queue, prq);
+ spin_unlock_irq(q->queue_lock);
+ } else {
+ list_del_init(&prq->queuelist);
+ }
+ }
+
+ mmc_blk_clear_packed(mq_rq);
+}
+
static int mmc_blk_issue_rw_rq(struct mmc_queue *mq, struct request *rqc)
{
struct mmc_blk_data *md = mq->data;
@@ -1292,13 +1619,22 @@
struct mmc_queue_req *mq_rq;
struct request *req;
struct mmc_async_req *areq;
+ const u8 packed_num = 2;
+ u8 reqs = 0;
if (!rqc && !mq->mqrq_prev->req)
return 0;
+ if (rqc)
+ reqs = mmc_blk_prep_packed_list(mq, rqc);
+
do {
if (rqc) {
- mmc_blk_rw_rq_prep(mq->mqrq_cur, card, 0, mq);
+ if (reqs >= packed_num)
+ mmc_blk_packed_hdr_wrq_prep(mq->mqrq_cur,
+ card, mq);
+ else
+ mmc_blk_rw_rq_prep(mq->mqrq_cur, card, 0, mq);
areq = &mq->mqrq_cur->mmc_active;
} else
areq = NULL;
@@ -1319,8 +1655,15 @@
* A block was successfully transferred.
*/
mmc_blk_reset_success(md, type);
- ret = blk_end_request(req, 0,
+
+ if (mq_rq->packed_cmd != MMC_PACKED_NONE) {
+ ret = mmc_blk_end_packed_req(mq_rq);
+ break;
+ } else {
+ ret = blk_end_request(req, 0,
brq->data.bytes_xfered);
+ }
+
/*
* If the blk_end_request function returns non-zero even
* though all data has been transferred and no errors
@@ -1353,7 +1696,8 @@
err = mmc_blk_reset(md, card->host, type);
if (!err)
break;
- if (err == -ENODEV)
+ if (err == -ENODEV ||
+ mq_rq->packed_cmd != MMC_PACKED_NONE)
goto cmd_abort;
/* Fall through */
}
@@ -1380,26 +1724,46 @@
}
if (ret) {
- /*
- * In case of a incomplete request
- * prepare it again and resend.
- */
- mmc_blk_rw_rq_prep(mq_rq, card, disable_multi, mq);
- mmc_start_req(card->host, &mq_rq->mmc_active, NULL);
+ if (mq_rq->packed_cmd == MMC_PACKED_NONE) {
+ /*
+ * In case of a incomplete request
+ * prepare it again and resend.
+ */
+ mmc_blk_rw_rq_prep(mq_rq, card,
+ disable_multi, mq);
+ mmc_start_req(card->host,
+ &mq_rq->mmc_active, NULL);
+ } else {
+ if (!mq_rq->packed_retries)
+ goto cmd_abort;
+ mmc_blk_packed_hdr_wrq_prep(mq_rq, card, mq);
+ mmc_start_req(card->host,
+ &mq_rq->mmc_active, NULL);
+ }
}
} while (ret);
return 1;
cmd_abort:
- if (mmc_card_removed(card))
- req->cmd_flags |= REQ_QUIET;
- while (ret)
- ret = blk_end_request(req, -EIO,
- blk_rq_cur_bytes(req));
+ if (mq_rq->packed_cmd == MMC_PACKED_NONE) {
+ if (mmc_card_removed(card))
+ req->cmd_flags |= REQ_QUIET;
+ while (ret)
+ ret = blk_end_request(req, -EIO,
+ blk_rq_cur_bytes(req));
+ } else {
+ mmc_blk_abort_packed_req(mq_rq);
+ }
start_new_req:
if (rqc) {
+ /*
+ * If current request is packed, it needs to put back.
+ */
+ if (mq->mqrq_cur->packed_cmd != MMC_PACKED_NONE)
+ mmc_blk_revert_packed_req(mq, mq->mqrq_cur);
+
mmc_blk_rw_rq_prep(mq->mqrq_cur, card, 0, mq);
mmc_start_req(card->host, &mq->mqrq_cur->mmc_active, NULL);
}
diff --git a/drivers/mmc/card/queue.c b/drivers/mmc/card/queue.c
index 9e9dfcd..d818fc4 100644
--- a/drivers/mmc/card/queue.c
+++ b/drivers/mmc/card/queue.c
@@ -181,6 +181,9 @@
if (!mq->queue)
return -ENOMEM;
+ INIT_LIST_HEAD(&mqrq_cur->packed_list);
+ INIT_LIST_HEAD(&mqrq_prev->packed_list);
+
memset(&mq->mqrq_cur, 0, sizeof(mq->mqrq_cur));
memset(&mq->mqrq_prev, 0, sizeof(mq->mqrq_prev));
mq->mqrq_cur = mqrq_cur;
@@ -386,6 +389,35 @@
}
}
+static unsigned int mmc_queue_packed_map_sg(struct mmc_queue *mq,
+ struct mmc_queue_req *mqrq,
+ struct scatterlist *sg)
+{
+ struct scatterlist *__sg;
+ unsigned int sg_len = 0;
+ struct request *req;
+ enum mmc_packed_cmd cmd;
+
+ cmd = mqrq->packed_cmd;
+
+ if (cmd == MMC_PACKED_WRITE) {
+ __sg = sg;
+ sg_set_buf(__sg, mqrq->packed_cmd_hdr,
+ sizeof(mqrq->packed_cmd_hdr));
+ sg_len++;
+ __sg->page_link &= ~0x02;
+ }
+
+ __sg = sg + sg_len;
+ list_for_each_entry(req, &mqrq->packed_list, queuelist) {
+ sg_len += blk_rq_map_sg(mq->queue, req, __sg);
+ __sg = sg + (sg_len - 1);
+ (__sg++)->page_link &= ~0x02;
+ }
+ sg_mark_end(sg + (sg_len - 1));
+ return sg_len;
+}
+
/*
* Prepare the sg list(s) to be handed of to the host driver
*/
@@ -396,12 +428,19 @@
struct scatterlist *sg;
int i;
- if (!mqrq->bounce_buf)
- return blk_rq_map_sg(mq->queue, mqrq->req, mqrq->sg);
+ if (!mqrq->bounce_buf) {
+ if (!list_empty(&mqrq->packed_list))
+ return mmc_queue_packed_map_sg(mq, mqrq, mqrq->sg);
+ else
+ return blk_rq_map_sg(mq->queue, mqrq->req, mqrq->sg);
+ }
BUG_ON(!mqrq->bounce_sg);
- sg_len = blk_rq_map_sg(mq->queue, mqrq->req, mqrq->bounce_sg);
+ if (!list_empty(&mqrq->packed_list))
+ sg_len = mmc_queue_packed_map_sg(mq, mqrq, mqrq->bounce_sg);
+ else
+ sg_len = blk_rq_map_sg(mq->queue, mqrq->req, mqrq->bounce_sg);
mqrq->bounce_sg_len = sg_len;
diff --git a/drivers/mmc/card/queue.h b/drivers/mmc/card/queue.h
index d2a1eb4..5e04938 100644
--- a/drivers/mmc/card/queue.h
+++ b/drivers/mmc/card/queue.h
@@ -12,6 +12,11 @@
struct mmc_data data;
};
+enum mmc_packed_cmd {
+ MMC_PACKED_NONE = 0,
+ MMC_PACKED_WRITE,
+};
+
struct mmc_queue_req {
struct request *req;
struct mmc_blk_request brq;
@@ -20,6 +25,13 @@
struct scatterlist *bounce_sg;
unsigned int bounce_sg_len;
struct mmc_async_req mmc_active;
+ struct list_head packed_list;
+ u32 packed_cmd_hdr[128];
+ unsigned int packed_blocks;
+ enum mmc_packed_cmd packed_cmd;
+ int packed_retries;
+ int packed_fail_idx;
+ u8 packed_num;
};
struct mmc_queue {
diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c
index a9f2ea9..e2172c5 100644
--- a/drivers/mmc/core/mmc.c
+++ b/drivers/mmc/core/mmc.c
@@ -537,6 +537,11 @@
} else {
card->ext_csd.data_tag_unit_size = 0;
}
+
+ card->ext_csd.max_packed_writes =
+ ext_csd[EXT_CSD_MAX_PACKED_WRITES];
+ card->ext_csd.max_packed_reads =
+ ext_csd[EXT_CSD_MAX_PACKED_READS];
}
out:
@@ -1274,6 +1279,26 @@
}
}
+ if ((host->caps2 & MMC_CAP2_PACKED_WR &&
+ card->ext_csd.max_packed_writes > 0) ||
+ (host->caps2 & MMC_CAP2_PACKED_RD &&
+ card->ext_csd.max_packed_reads > 0)) {
+ err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
+ EXT_CSD_EXP_EVENTS_CTRL,
+ EXT_CSD_PACKED_EVENT_EN,
+ card->ext_csd.generic_cmd6_time);
+ if (err && err != -EBADMSG)
+ goto free_card;
+ if (err) {
+ pr_warning("%s: Enabling packed event failed\n",
+ mmc_hostname(card->host));
+ card->ext_csd.packed_event_en = 0;
+ err = 0;
+ } else {
+ card->ext_csd.packed_event_en = 1;
+ }
+ }
+
if (!oldcard)
host->card = card;
diff --git a/drivers/mmc/core/mmc_ops.c b/drivers/mmc/core/mmc_ops.c
index 2d282b5..4f46ed1 100644
--- a/drivers/mmc/core/mmc_ops.c
+++ b/drivers/mmc/core/mmc_ops.c
@@ -335,6 +335,7 @@
return mmc_send_cxd_data(card, card->host, MMC_SEND_EXT_CSD,
ext_csd, 512);
}
+EXPORT_SYMBOL_GPL(mmc_send_ext_csd);
int mmc_spi_read_ocr(struct mmc_host *host, int highcap, u32 *ocrp)
{
diff --git a/drivers/mmc/host/msm_sdcc.c b/drivers/mmc/host/msm_sdcc.c
index ee32298..d910d6c 100644
--- a/drivers/mmc/host/msm_sdcc.c
+++ b/drivers/mmc/host/msm_sdcc.c
@@ -1779,6 +1779,7 @@
msmsdcc_irq(int irq, void *dev_id)
{
struct msmsdcc_host *host = dev_id;
+ struct mmc_host *mmc = host->mmc;
u32 status;
int ret = 0;
int timer = 0;
@@ -1820,6 +1821,12 @@
*/
wake_lock(&host->sdio_wlock);
} else {
+ if (!mmc->card || !mmc_card_sdio(mmc->card)) {
+ WARN(1, "%s: SDCC core interrupt received for non-SDIO cards when SDCC clocks are off\n",
+ mmc_hostname(mmc));
+ ret = 1;
+ break;
+ }
spin_unlock(&host->lock);
mmc_signal_sdio_irq(host->mmc);
spin_lock(&host->lock);
@@ -1848,6 +1855,12 @@
#endif
if (status & MCI_SDIOINTROPE) {
+ if (!mmc->card || mmc_card_sdio(mmc->card)) {
+ WARN(1, "%s: SDIO interrupt received for non-SDIO card\n",
+ mmc_hostname(mmc));
+ ret = 1;
+ break;
+ }
if (host->sdcc_suspending)
wake_lock(&host->sdio_suspend_wlock);
spin_unlock(&host->lock);
@@ -2825,6 +2838,14 @@
msmsdcc_set_vdd_io_vol(host, VDD_IO_LOW, 0);
msmsdcc_update_io_pad_pwr_switch(host);
msmsdcc_setup_pins(host, false);
+ /*
+ * Reset the mask to prevent hitting any pending interrupts
+ * after powering up the card again.
+ */
+ if (atomic_read(&host->clks_on)) {
+ writel_relaxed(0, host->base + MMCIMASK0);
+ mb();
+ }
break;
case MMC_POWER_UP:
/* writing PWR_UP bit is redundant */
diff --git a/drivers/net/ethernet/msm/msm_rmnet_smux.c b/drivers/net/ethernet/msm/msm_rmnet_smux.c
index fbb3489..5f29406 100644
--- a/drivers/net/ethernet/msm/msm_rmnet_smux.c
+++ b/drivers/net/ethernet/msm/msm_rmnet_smux.c
@@ -79,6 +79,7 @@
unsigned long timeout_us;
#endif
spinlock_t lock;
+ spinlock_t tx_queue_lock;
struct tasklet_struct tsklt;
/* IOCTL specified mode (protocol, QoS header) */
u32 operation_mode;
@@ -346,12 +347,15 @@
((struct net_device *)(dev))->name, p->stats.tx_packets,
skb->len, skb->mark);
dev_kfree_skb_any(skb);
+
+ spin_lock_irqsave(&p->tx_queue_lock, flags);
if (netif_queue_stopped(dev) &&
msm_smux_is_ch_low(p->ch_id)) {
DBG0("%s: Low WM hit, waking queue=%p\n",
__func__, skb);
netif_wake_queue(dev);
}
+ spin_unlock_irqrestore(&p->tx_queue_lock, flags);
}
void rmnet_smux_notify(void *priv, int event_type, const void *metadata)
@@ -475,14 +479,20 @@
case SMUX_LOW_WM_HIT:
dev = priv;
+ p = netdev_priv(priv);
DBG0("[%s] Low WM hit dev:%s\n", __func__, dev->name);
+ spin_lock_irqsave(&p->tx_queue_lock, flags);
netif_start_queue(dev);
+ spin_unlock_irqrestore(&p->tx_queue_lock, flags);
break;
case SMUX_HIGH_WM_HIT:
dev = priv;
- DBG0("[%s] Low WM hit dev:%s\n", __func__, dev->name);
+ p = netdev_priv(priv);
+ DBG0("[%s] High WM hit dev:%s\n", __func__, dev->name);
+ spin_lock_irqsave(&p->tx_queue_lock, flags);
netif_stop_queue(dev);
+ spin_unlock_irqrestore(&p->tx_queue_lock, flags);
break;
default:
@@ -573,7 +583,6 @@
static int _rmnet_xmit(struct sk_buff *skb, struct net_device *dev)
{
struct rmnet_private *p = netdev_priv(dev);
- int smux_ret;
struct QMI_QOS_HDR_S *qmih;
u32 opmode;
unsigned long flags;
@@ -593,21 +602,13 @@
dev->trans_start = jiffies;
- /* if write() succeeds, skb access is unsafe in this process */
- smux_ret = msm_smux_write(p->ch_id, skb, skb->data, skb->len);
-
- if (smux_ret != 0 && smux_ret != -EAGAIN) {
- pr_err("[%s] %s: write returned error %d",
- dev->name, __func__, smux_ret);
- return -EPERM;
- }
-
- return smux_ret;
+ return msm_smux_write(p->ch_id, skb, skb->data, skb->len);
}
static int rmnet_xmit(struct sk_buff *skb, struct net_device *dev)
{
struct rmnet_private *p = netdev_priv(dev);
+ unsigned long flags;
int ret = 0;
if (netif_queue_stopped(dev) || (p->device_state == DEVICE_INACTIVE)) {
@@ -616,17 +617,10 @@
return 0;
}
+ spin_lock_irqsave(&p->tx_queue_lock, flags);
ret = _rmnet_xmit(skb, dev);
- if (ret == -EPERM) {
- /* Do not stop the queue here.
- * It will lead to ir-recoverable state.
- */
- ret = NETDEV_TX_BUSY;
- goto exit;
- }
-
- if (msm_smux_is_ch_full(p->ch_id) || (ret == -EAGAIN)) {
+ if (ret == -EAGAIN) {
/*
* EAGAIN means we attempted to overflow the high watermark
* Clearly the queue is not stopped like it should be, so
@@ -636,9 +630,9 @@
*/
netif_stop_queue(dev);
ret = NETDEV_TX_BUSY;
- goto exit;
}
-exit:
+ spin_unlock_irqrestore(&p->tx_queue_lock, flags);
+
return ret;
}
@@ -892,6 +886,7 @@
p->ch_id = n;
p->in_reset = 0;
spin_lock_init(&p->lock);
+ spin_lock_init(&p->tx_queue_lock);
#ifdef CONFIG_MSM_RMNET_DEBUG
p->timeout_us = timeout_us;
p->wakeups_xmit = p->wakeups_rcv = 0;
diff --git a/drivers/net/usb/usbnet.c b/drivers/net/usb/usbnet.c
index 1867fe2..6de0a77 100644
--- a/drivers/net/usb/usbnet.c
+++ b/drivers/net/usb/usbnet.c
@@ -1529,6 +1529,7 @@
spin_lock_irq(&dev->txq.lock);
/* don't autosuspend while transmitting */
if (dev->txq.qlen && PMSG_IS_AUTO(message)) {
+ dev->suspend_count--;
spin_unlock_irq(&dev->txq.lock);
return -EBUSY;
} else {
diff --git a/drivers/platform/msm/usb_bam.c b/drivers/platform/msm/usb_bam.c
index 551c0a7..bf78b1c 100644
--- a/drivers/platform/msm/usb_bam.c
+++ b/drivers/platform/msm/usb_bam.c
@@ -258,6 +258,11 @@
struct usb_bam_connect_info *connection = &usb_bam_connections[idx];
int ret;
+ if (!usb_bam_pdev) {
+ pr_err("%s: usb_bam device not found\n", __func__);
+ return -ENODEV;
+ }
+
if (idx >= CONNECTIONS_NUM) {
pr_err("%s: Invalid connection index\n",
__func__);
@@ -715,12 +720,9 @@
usb_bam_show_enable(struct device *dev, struct device_attribute *attr,
char *buf)
{
- struct platform_device *pdev =
- container_of(dev, struct platform_device, dev);
- struct msm_usb_bam_platform_data *pdata =
- usb_bam_pdev->dev.platform_data;
+ struct msm_usb_bam_platform_data *pdata = dev->platform_data;
- if (!pdev || !pdata)
+ if (!pdata)
return 0;
return scnprintf(buf, PAGE_SIZE, "%s\n",
bam_enable_strings[pdata->usb_active_bam]);
@@ -730,13 +732,15 @@
struct device_attribute *attr,
const char *buf, size_t count)
{
- struct platform_device *pdev = container_of(dev,
- struct platform_device, dev);
- struct msm_usb_bam_platform_data *pdata =
- usb_bam_pdev->dev.platform_data;
+ struct msm_usb_bam_platform_data *pdata = dev->platform_data;
char str[10], *pstr;
int ret, i;
+ if (!pdata) {
+ dev_err(dev, "no usb_bam pdata found\n");
+ return -ENODEV;
+ }
+
strlcpy(str, buf, sizeof(str));
pstr = strim(str);
@@ -745,12 +749,12 @@
pdata->usb_active_bam = i;
}
- dev_dbg(&pdev->dev, "active_bam=%s\n",
+ dev_dbg(dev, "active_bam=%s\n",
bam_enable_strings[pdata->usb_active_bam]);
ret = usb_bam_init();
if (ret) {
- dev_err(&pdev->dev, "failed to initialize usb bam\n");
+ dev_err(dev, "failed to initialize usb bam\n");
return ret;
}
diff --git a/drivers/power/pm8921-bms.c b/drivers/power/pm8921-bms.c
index c63c99f..b107040 100644
--- a/drivers/power/pm8921-bms.c
+++ b/drivers/power/pm8921-bms.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -10,8 +10,8 @@
* GNU General Public License for more details.
*
*/
-#define pr_fmt(fmt) "%s: " fmt, __func__
+#define pr_fmt(fmt) "%s: " fmt, __func__
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/platform_device.h>
@@ -22,6 +22,7 @@
#include <linux/mfd/pm8xxx/pm8xxx-adc.h>
#include <linux/mfd/pm8xxx/pm8921-charger.h>
#include <linux/mfd/pm8xxx/ccadc.h>
+#include <linux/mfd/pm8xxx/batterydata-lib.h>
#include <linux/interrupt.h>
#include <linux/bitops.h>
#include <linux/debugfs.h>
@@ -224,7 +225,6 @@
module_param_cb(bms_end_ocv_uv, &bms_ro_param_ops, &bms_end_ocv_uv, 0644);
module_param_cb(bms_end_cc_uah, &bms_ro_param_ops, &bms_end_cc_uah, 0644);
-static int interpolate_fcc(struct pm8921_bms_chip *chip, int batt_temp);
static void readjust_fcc_table(void)
{
struct single_row_lut *temp, *old;
@@ -241,7 +241,7 @@
return;
}
- fcc = interpolate_fcc(the_chip, last_real_fcc_batt_temp);
+ fcc = interpolate_fcc(the_chip->fcc_temp_lut, last_real_fcc_batt_temp);
temp->cols = the_chip->fcc_temp_lut->cols;
for (i = 0; i < the_chip->fcc_temp_lut->cols; i++) {
@@ -583,342 +583,6 @@
return 0;
}
-static int linear_interpolate(int y0, int x0, int y1, int x1, int x)
-{
- if (y0 == y1 || x == x0)
- return y0;
- if (x1 == x0 || x == x1)
- return y1;
-
- return y0 + ((y1 - y0) * (x - x0) / (x1 - x0));
-}
-
-static int interpolate_single_lut(struct single_row_lut *lut, int x)
-{
- int i, result;
-
- if (x < lut->x[0]) {
- pr_debug("x %d less than known range return y = %d lut = %pS\n",
- x, lut->y[0], lut);
- return lut->y[0];
- }
- if (x > lut->x[lut->cols - 1]) {
- pr_debug("x %d more than known range return y = %d lut = %pS\n",
- x, lut->y[lut->cols - 1], lut);
- return lut->y[lut->cols - 1];
- }
-
- for (i = 0; i < lut->cols; i++)
- if (x <= lut->x[i])
- break;
- if (x == lut->x[i]) {
- result = lut->y[i];
- } else {
- result = linear_interpolate(
- lut->y[i - 1],
- lut->x[i - 1],
- lut->y[i],
- lut->x[i],
- x);
- }
- return result;
-}
-
-static int interpolate_fcc(struct pm8921_bms_chip *chip, int batt_temp)
-{
- /* batt_temp is in tenths of degC - convert it to degC for lookups */
- batt_temp = batt_temp/10;
- return interpolate_single_lut(chip->fcc_temp_lut, batt_temp);
-}
-
-static int interpolate_fcc_adjusted(struct pm8921_bms_chip *chip, int batt_temp)
-{
- /* batt_temp is in tenths of degC - convert it to degC for lookups */
- batt_temp = batt_temp/10;
- return interpolate_single_lut(chip->adjusted_fcc_temp_lut, batt_temp);
-}
-
-static int interpolate_scalingfactor_fcc(struct pm8921_bms_chip *chip,
- int cycles)
-{
- /*
- * sf table could be null when no battery aging data is available, in
- * that case return 100%
- */
- if (chip->fcc_sf_lut)
- return interpolate_single_lut(chip->fcc_sf_lut, cycles);
- else
- return 100;
-}
-
-static int interpolate_scalingfactor(struct pm8921_bms_chip *chip,
- struct sf_lut *sf_lut,
- int row_entry, int pc)
-{
- int i, scalefactorrow1, scalefactorrow2, scalefactor;
- int rows, cols;
- int row1 = 0;
- int row2 = 0;
-
- /*
- * sf table could be null when no battery aging data is available, in
- * that case return 100%
- */
- if (!sf_lut)
- return 100;
-
- rows = sf_lut->rows;
- cols = sf_lut->cols;
- if (pc > sf_lut->percent[0]) {
- pr_debug("pc %d greater than known pc ranges for sfd\n", pc);
- row1 = 0;
- row2 = 0;
- }
- if (pc < sf_lut->percent[rows - 1]) {
- pr_debug("pc %d less than known pc ranges for sf", pc);
- row1 = rows - 1;
- row2 = rows - 1;
- }
- for (i = 0; i < rows; i++) {
- if (pc == sf_lut->percent[i]) {
- row1 = i;
- row2 = i;
- break;
- }
- if (pc > sf_lut->percent[i]) {
- row1 = i - 1;
- row2 = i;
- break;
- }
- }
-
- if (row_entry < sf_lut->row_entries[0])
- row_entry = sf_lut->row_entries[0];
- if (row_entry > sf_lut->row_entries[cols - 1])
- row_entry = sf_lut->row_entries[cols - 1];
-
- for (i = 0; i < cols; i++)
- if (row_entry <= sf_lut->row_entries[i])
- break;
- if (row_entry == sf_lut->row_entries[i]) {
- scalefactor = linear_interpolate(
- sf_lut->sf[row1][i],
- sf_lut->percent[row1],
- sf_lut->sf[row2][i],
- sf_lut->percent[row2],
- pc);
- return scalefactor;
- }
-
- scalefactorrow1 = linear_interpolate(
- sf_lut->sf[row1][i - 1],
- sf_lut->row_entries[i - 1],
- sf_lut->sf[row1][i],
- sf_lut->row_entries[i],
- row_entry);
-
- scalefactorrow2 = linear_interpolate(
- sf_lut->sf[row2][i - 1],
- sf_lut->row_entries[i - 1],
- sf_lut->sf[row2][i],
- sf_lut->row_entries[i],
- row_entry);
-
- scalefactor = linear_interpolate(
- scalefactorrow1,
- sf_lut->percent[row1],
- scalefactorrow2,
- sf_lut->percent[row2],
- pc);
-
- return scalefactor;
-}
-
-static int is_between(int left, int right, int value)
-{
- if (left >= right && left >= value && value >= right)
- return 1;
- if (left <= right && left <= value && value <= right)
- return 1;
-
- return 0;
-}
-
-/* get ocv given a soc -- reverse lookup */
-static int interpolate_ocv(struct pm8921_bms_chip *chip,
- int batt_temp_degc, int pc)
-{
- int i, ocvrow1, ocvrow2, ocv;
- int rows, cols;
- int row1 = 0;
- int row2 = 0;
-
- rows = chip->pc_temp_ocv_lut->rows;
- cols = chip->pc_temp_ocv_lut->cols;
- if (pc > chip->pc_temp_ocv_lut->percent[0]) {
- pr_debug("pc %d greater than known pc ranges for sfd\n", pc);
- row1 = 0;
- row2 = 0;
- }
- if (pc < chip->pc_temp_ocv_lut->percent[rows - 1]) {
- pr_debug("pc %d less than known pc ranges for sf\n", pc);
- row1 = rows - 1;
- row2 = rows - 1;
- }
- for (i = 0; i < rows; i++) {
- if (pc == chip->pc_temp_ocv_lut->percent[i]) {
- row1 = i;
- row2 = i;
- break;
- }
- if (pc > chip->pc_temp_ocv_lut->percent[i]) {
- row1 = i - 1;
- row2 = i;
- break;
- }
- }
-
- if (batt_temp_degc < chip->pc_temp_ocv_lut->temp[0])
- batt_temp_degc = chip->pc_temp_ocv_lut->temp[0];
- if (batt_temp_degc > chip->pc_temp_ocv_lut->temp[cols - 1])
- batt_temp_degc = chip->pc_temp_ocv_lut->temp[cols - 1];
-
- for (i = 0; i < cols; i++)
- if (batt_temp_degc <= chip->pc_temp_ocv_lut->temp[i])
- break;
- if (batt_temp_degc == chip->pc_temp_ocv_lut->temp[i]) {
- ocv = linear_interpolate(
- chip->pc_temp_ocv_lut->ocv[row1][i],
- chip->pc_temp_ocv_lut->percent[row1],
- chip->pc_temp_ocv_lut->ocv[row2][i],
- chip->pc_temp_ocv_lut->percent[row2],
- pc);
- return ocv;
- }
-
- ocvrow1 = linear_interpolate(
- chip->pc_temp_ocv_lut->ocv[row1][i - 1],
- chip->pc_temp_ocv_lut->temp[i - 1],
- chip->pc_temp_ocv_lut->ocv[row1][i],
- chip->pc_temp_ocv_lut->temp[i],
- batt_temp_degc);
-
- ocvrow2 = linear_interpolate(
- chip->pc_temp_ocv_lut->ocv[row2][i - 1],
- chip->pc_temp_ocv_lut->temp[i - 1],
- chip->pc_temp_ocv_lut->ocv[row2][i],
- chip->pc_temp_ocv_lut->temp[i],
- batt_temp_degc);
-
- ocv = linear_interpolate(
- ocvrow1,
- chip->pc_temp_ocv_lut->percent[row1],
- ocvrow2,
- chip->pc_temp_ocv_lut->percent[row2],
- pc);
-
- return ocv;
-}
-
-static int interpolate_pc(struct pm8921_bms_chip *chip,
- int batt_temp_degc, int ocv)
-{
- int i, j, pcj, pcj_minus_one, pc;
- int rows = chip->pc_temp_ocv_lut->rows;
- int cols = chip->pc_temp_ocv_lut->cols;
-
-
- if (batt_temp_degc < chip->pc_temp_ocv_lut->temp[0]) {
- pr_debug("batt_temp %d < known temp range\n", batt_temp_degc);
- batt_temp_degc = chip->pc_temp_ocv_lut->temp[0];
- }
- if (batt_temp_degc > chip->pc_temp_ocv_lut->temp[cols - 1]) {
- pr_debug("batt_temp %d > known temp range\n", batt_temp_degc);
- batt_temp_degc = chip->pc_temp_ocv_lut->temp[cols - 1];
- }
-
- for (j = 0; j < cols; j++)
- if (batt_temp_degc <= chip->pc_temp_ocv_lut->temp[j])
- break;
- if (batt_temp_degc == chip->pc_temp_ocv_lut->temp[j]) {
- /* found an exact match for temp in the table */
- if (ocv >= chip->pc_temp_ocv_lut->ocv[0][j])
- return chip->pc_temp_ocv_lut->percent[0];
- if (ocv <= chip->pc_temp_ocv_lut->ocv[rows - 1][j])
- return chip->pc_temp_ocv_lut->percent[rows - 1];
- for (i = 0; i < rows; i++) {
- if (ocv >= chip->pc_temp_ocv_lut->ocv[i][j]) {
- if (ocv == chip->pc_temp_ocv_lut->ocv[i][j])
- return
- chip->pc_temp_ocv_lut->percent[i];
- pc = linear_interpolate(
- chip->pc_temp_ocv_lut->percent[i],
- chip->pc_temp_ocv_lut->ocv[i][j],
- chip->pc_temp_ocv_lut->percent[i - 1],
- chip->pc_temp_ocv_lut->ocv[i - 1][j],
- ocv);
- return pc;
- }
- }
- }
-
- /*
- * batt_temp_degc is within temperature for
- * column j-1 and j
- */
- if (ocv >= chip->pc_temp_ocv_lut->ocv[0][j])
- return chip->pc_temp_ocv_lut->percent[0];
- if (ocv <= chip->pc_temp_ocv_lut->ocv[rows - 1][j - 1])
- return chip->pc_temp_ocv_lut->percent[rows - 1];
-
- pcj_minus_one = 0;
- pcj = 0;
- for (i = 0; i < rows-1; i++) {
- if (pcj == 0
- && is_between(chip->pc_temp_ocv_lut->ocv[i][j],
- chip->pc_temp_ocv_lut->ocv[i+1][j], ocv)) {
- pcj = linear_interpolate(
- chip->pc_temp_ocv_lut->percent[i],
- chip->pc_temp_ocv_lut->ocv[i][j],
- chip->pc_temp_ocv_lut->percent[i + 1],
- chip->pc_temp_ocv_lut->ocv[i+1][j],
- ocv);
- }
-
- if (pcj_minus_one == 0
- && is_between(chip->pc_temp_ocv_lut->ocv[i][j-1],
- chip->pc_temp_ocv_lut->ocv[i+1][j-1], ocv)) {
-
- pcj_minus_one = linear_interpolate(
- chip->pc_temp_ocv_lut->percent[i],
- chip->pc_temp_ocv_lut->ocv[i][j-1],
- chip->pc_temp_ocv_lut->percent[i + 1],
- chip->pc_temp_ocv_lut->ocv[i+1][j-1],
- ocv);
- }
-
- if (pcj && pcj_minus_one) {
- pc = linear_interpolate(
- pcj_minus_one,
- chip->pc_temp_ocv_lut->temp[j-1],
- pcj,
- chip->pc_temp_ocv_lut->temp[j],
- batt_temp_degc);
- return pc;
- }
- }
-
- if (pcj)
- return pcj;
-
- if (pcj_minus_one)
- return pcj_minus_one;
-
- pr_debug("%d ocv wasn't found for temp %d in the LUT returning 100%%",
- ocv, batt_temp_degc);
- return 100;
-}
-
#define BMS_MODE_BIT BIT(6)
#define EN_VBAT_BIT BIT(5)
#define OVERRIDE_MODE_DELAY_MS 20
@@ -1042,7 +706,7 @@
}
/* Convert the batt_temp to DegC from deciDegC */
batt_temp = batt_temp / 10;
- scalefactor = interpolate_scalingfactor(chip, chip->rbatt_sf_lut,
+ scalefactor = interpolate_scalingfactor(chip->rbatt_sf_lut,
batt_temp, soc_rbatt);
pr_debug("rbatt sf = %d for batt_temp = %d, soc_rbatt = %d\n",
scalefactor, batt_temp, soc_rbatt);
@@ -1069,16 +733,18 @@
int initfcc, result, scalefactor = 0;
if (chip->adjusted_fcc_temp_lut == NULL) {
- initfcc = interpolate_fcc(chip, batt_temp);
+ initfcc = interpolate_fcc(chip->fcc_temp_lut, batt_temp);
- scalefactor = interpolate_scalingfactor_fcc(chip, chargecycles);
+ scalefactor = interpolate_scalingfactor_fcc(chip->fcc_sf_lut,
+ chargecycles);
/* Multiply the initial FCC value by the scale factor. */
result = (initfcc * scalefactor * 1000) / 100;
pr_debug("fcc = %d uAh\n", result);
return result;
} else {
- return 1000 * interpolate_fcc_adjusted(chip, batt_temp);
+ return 1000 * interpolate_fcc(chip->adjusted_fcc_temp_lut,
+ batt_temp);
}
}
@@ -1120,17 +786,18 @@
return 0;
}
-static int calculate_pc(struct pm8921_bms_chip *chip, int ocv_uv, int batt_temp,
- int chargecycles)
+static int calculate_pc(struct pm8921_bms_chip *chip, int ocv_uv,
+ int batt_temp, int chargecycles)
{
int pc, scalefactor;
- pc = interpolate_pc(chip, batt_temp / 10, ocv_uv / 1000);
+ pc = interpolate_pc(chip->pc_temp_ocv_lut,
+ batt_temp / 10, ocv_uv / 1000);
pr_debug("pc = %u for ocv = %dmicroVolts batt_temp = %d\n",
pc, ocv_uv, batt_temp);
- scalefactor = interpolate_scalingfactor(chip,
- chip->pc_sf_lut, chargecycles, pc);
+ scalefactor = interpolate_scalingfactor(chip->pc_sf_lut,
+ chargecycles, pc);
pr_debug("scalefactor = %u batt_temp = %d\n", scalefactor, batt_temp);
/* Multiply the initial FCC value by the scale factor. */
@@ -1183,7 +850,8 @@
int uuc_rbatt_uv;
for (i = 0; i <= 100; i++) {
- ocv_mv = interpolate_ocv(chip, batt_temp_degc, i);
+ ocv_mv = interpolate_ocv(chip->pc_temp_ocv_lut,
+ batt_temp_degc, i);
rbatt_mohm = get_rbatt(chip, i, batt_temp);
unusable_uv = (rbatt_mohm * i_ma) + (chip->v_cutoff * 1000);
delta_uv = ocv_mv * 1000 - unusable_uv;
@@ -1239,8 +907,8 @@
new_uuc = (fcc_uah * chip->prev_pc_unusable) / 100;
/* also find update the iavg_ma accordingly */
- new_unusable_mv = interpolate_ocv(chip, batt_temp_degc,
- chip->prev_pc_unusable);
+ new_unusable_mv = interpolate_ocv(chip->pc_temp_ocv_lut,
+ batt_temp_degc, chip->prev_pc_unusable);
if (new_unusable_mv < chip->v_cutoff)
new_unusable_mv = chip->v_cutoff;
@@ -1531,11 +1199,11 @@
pc = DIV_ROUND_CLOSEST((int)rc * 100, fcc_uah);
pc = clamp(pc, 0, 100);
- ocv = interpolate_ocv(chip, batt_temp_degc, pc);
+ ocv = interpolate_ocv(chip->pc_temp_ocv_lut, batt_temp_degc, pc);
pr_debug("s_soc = %d, fcc = %d uuc = %d rc = %d, pc = %d, ocv mv = %d\n",
shutdown_soc, fcc_uah, uuc_uah, (int)rc, pc, ocv);
- new_pc = interpolate_pc(chip, batt_temp_degc, ocv);
+ new_pc = interpolate_pc(chip->pc_temp_ocv_lut, batt_temp_degc, ocv);
pr_debug("test revlookup pc = %d for ocv = %d\n", new_pc, ocv);
while (abs(new_pc - pc) > 1) {
@@ -1545,7 +1213,8 @@
delta_mv = -1 * delta_mv;
ocv = ocv + delta_mv;
- new_pc = interpolate_pc(chip, batt_temp_degc, ocv);
+ new_pc = interpolate_pc(chip->pc_temp_ocv_lut,
+ batt_temp_degc, ocv);
pr_debug("test revlookup pc = %d for ocv = %d\n", new_pc, ocv);
}
diff --git a/drivers/power/pm8921-charger.c b/drivers/power/pm8921-charger.c
index e4e0004..e983081 100644
--- a/drivers/power/pm8921-charger.c
+++ b/drivers/power/pm8921-charger.c
@@ -2308,12 +2308,6 @@
return IRQ_HANDLED;
}
-static irqreturn_t usbin_ov_irq_handler(int irq, void *data)
-{
- pr_err("USB OverVoltage\n");
- return IRQ_HANDLED;
-}
-
static irqreturn_t batt_inserted_irq_handler(int irq, void *data)
{
struct pm8921_chg_chip *chip = data;
@@ -2358,12 +2352,6 @@
return IRQ_HANDLED;
}
-static irqreturn_t usbin_uv_irq_handler(int irq, void *data)
-{
- pr_err("USB UnderVoltage\n");
- return IRQ_HANDLED;
-}
-
static irqreturn_t vbat_ov_irq_handler(int irq, void *data)
{
pr_debug("fsm_state=%d\n", pm_chg_get_fsm_state(data));
@@ -3325,8 +3313,6 @@
pm8921_chg_enable_irq(chip, USBIN_VALID_IRQ);
pm8921_chg_enable_irq(chip, BATT_REMOVED_IRQ);
pm8921_chg_enable_irq(chip, BATT_INSERTED_IRQ);
- pm8921_chg_enable_irq(chip, USBIN_OV_IRQ);
- pm8921_chg_enable_irq(chip, USBIN_UV_IRQ);
pm8921_chg_enable_irq(chip, DCIN_OV_IRQ);
pm8921_chg_enable_irq(chip, DCIN_UV_IRQ);
pm8921_chg_enable_irq(chip, CHGFAIL_IRQ);
@@ -3374,13 +3360,10 @@
struct pm_chg_irq_init_data chg_irq_data[] = {
CHG_IRQ(USBIN_VALID_IRQ, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
usbin_valid_irq_handler),
- CHG_IRQ(USBIN_OV_IRQ, IRQF_TRIGGER_RISING, usbin_ov_irq_handler),
CHG_IRQ(BATT_INSERTED_IRQ, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
batt_inserted_irq_handler),
CHG_IRQ(VBATDET_LOW_IRQ, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
vbatdet_low_irq_handler),
- CHG_IRQ(USBIN_UV_IRQ, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
- usbin_uv_irq_handler),
CHG_IRQ(VBAT_OV_IRQ, IRQF_TRIGGER_RISING, vbat_ov_irq_handler),
CHG_IRQ(CHGWDOG_IRQ, IRQF_TRIGGER_RISING, chgwdog_irq_handler),
CHG_IRQ(VCP_IRQ, IRQF_TRIGGER_RISING, vcp_irq_handler),
@@ -4149,8 +4132,6 @@
enable_irq_wake(chip->pmic_chg_irq[USBIN_VALID_IRQ]);
enable_irq_wake(chip->pmic_chg_irq[DCIN_VALID_IRQ]);
- enable_irq_wake(chip->pmic_chg_irq[USBIN_OV_IRQ]);
- enable_irq_wake(chip->pmic_chg_irq[USBIN_UV_IRQ]);
enable_irq_wake(chip->pmic_chg_irq[BAT_TEMP_OK_IRQ]);
enable_irq_wake(chip->pmic_chg_irq[VBATDET_LOW_IRQ]);
enable_irq_wake(chip->pmic_chg_irq[FASTCHG_IRQ]);
diff --git a/drivers/usb/gadget/ci13xxx_udc.c b/drivers/usb/gadget/ci13xxx_udc.c
index b8b7f68..0ace679 100644
--- a/drivers/usb/gadget/ci13xxx_udc.c
+++ b/drivers/usb/gadget/ci13xxx_udc.c
@@ -2661,6 +2661,7 @@
mEp->desc = NULL;
mEp->ep.desc = NULL;
+ mEp->ep.maxpacket = USHRT_MAX;
spin_unlock_irqrestore(mEp->lock, flags);
return retval;
@@ -3135,7 +3136,8 @@
mEp->ep.name = mEp->name;
mEp->ep.ops = &usb_ep_ops;
- mEp->ep.maxpacket = CTRL_PAYLOAD_MAX;
+ mEp->ep.maxpacket =
+ k ? USHRT_MAX : CTRL_PAYLOAD_MAX;
INIT_LIST_HEAD(&mEp->qh.queue);
spin_unlock_irqrestore(udc->lock, flags);
diff --git a/drivers/usb/gadget/f_rmnet_smd.c b/drivers/usb/gadget/f_rmnet_smd.c
index b71f646..5e2c6ed 100644
--- a/drivers/usb/gadget/f_rmnet_smd.c
+++ b/drivers/usb/gadget/f_rmnet_smd.c
@@ -907,13 +907,14 @@
* Register platform driver to be notified in case SMD channels
* later becomes ready to be opened.
*/
- ret = platform_driver_register(&dev->pdrv);
- if (ret)
- ERROR(cdev, "Platform driver %s register failed %d\n",
- dev->pdrv.driver.name, ret);
- else
- dev->is_pdrv_used = 1;
-
+ if (!dev->is_pdrv_used) {
+ ret = platform_driver_register(&dev->pdrv);
+ if (ret)
+ ERROR(cdev, "pdrv %s register failed %d\n",
+ dev->pdrv.driver.name, ret);
+ else
+ dev->is_pdrv_used = 1;
+ }
return;
}
wait_event(dev->smd_ctl.wait, test_bit(CH_OPENED,
diff --git a/drivers/usb/gadget/u_data_hsuart.c b/drivers/usb/gadget/u_data_hsuart.c
index 74bb93f..4d88ea5 100644
--- a/drivers/usb/gadget/u_data_hsuart.c
+++ b/drivers/usb/gadget/u_data_hsuart.c
@@ -244,9 +244,7 @@
pr_debug("%s: port:%p tom:%lu pno:%d\n", __func__,
port, port->to_modem, port->port_num);
- spin_unlock_irqrestore(&port->rx_lock, flags);
ret = msm_smux_write(port->ch_id, skb, skb->data, skb->len);
- spin_lock_irqsave(&port->rx_lock, flags);
if (ret < 0) {
if (ret == -EAGAIN) {
/*flow control*/
diff --git a/drivers/usb/host/ehci-msm-hsic.c b/drivers/usb/host/ehci-msm-hsic.c
index a887c61..6fe9e58 100644
--- a/drivers/usb/host/ehci-msm-hsic.c
+++ b/drivers/usb/host/ehci-msm-hsic.c
@@ -926,6 +926,8 @@
return 0;
}
+#ifdef CONFIG_PM
+
static int ehci_hsic_bus_suspend(struct usb_hcd *hcd)
{
struct msm_hsic_hcd *mehci = hcd_to_hsic(hcd);
@@ -1135,6 +1137,13 @@
return 0;
}
+#else
+
+#define ehci_hsic_bus_suspend NULL
+#define ehci_hsic_bus_resume NULL
+
+#endif /* CONFIG_PM */
+
static struct hc_driver msm_hsic_driver = {
.description = hcd_name,
.product_desc = "Qualcomm EHCI Host Controller using HSIC",
diff --git a/drivers/usb/otg/msm72k_otg.c b/drivers/usb/otg/msm72k_otg.c
index f62ae76..ca1b155 100644
--- a/drivers/usb/otg/msm72k_otg.c
+++ b/drivers/usb/otg/msm72k_otg.c
@@ -1229,7 +1229,7 @@
static irqreturn_t msm_otg_irq(int irq, void *data)
{
struct msm_otg *dev = data;
- u32 otgsc, sts, pc, sts_mask;
+ u32 otgsc, sts, pc;
irqreturn_t ret = IRQ_HANDLED;
int work = 0;
enum usb_otg_state state;
@@ -1250,12 +1250,16 @@
otgsc = readl(USB_OTGSC);
sts = readl(USB_USBSTS);
- sts_mask = (otgsc & OTGSC_INTR_MASK) >> 8;
-
- if (!((otgsc & sts_mask) || (sts & STS_PCI))) {
+ /* At times during USB disconnect, hardware generates 1MSIS interrupt
+ * during PHY reset, which leads to irq not handled error as IRQ_NONE
+ * is notified. To workaround this issue, check for all the
+ * OTG_INTR_STS_MASK bits and if set, clear them and notify IRQ_HANDLED.
+ */
+ if (!((otgsc & OTGSC_INTR_STS_MASK) || (sts & STS_PCI))) {
ret = IRQ_NONE;
goto out;
}
+ writel_relaxed(otgsc, USB_OTGSC);
spin_lock_irqsave(&dev->lock, flags);
state = dev->phy.state;
@@ -1277,10 +1281,8 @@
set_bit(A_BUS_REQ, &dev->inputs);
clear_bit(ID, &dev->inputs);
}
- writel(otgsc, USB_OTGSC);
work = 1;
} else if (otgsc & OTGSC_BSVIS) {
- writel(otgsc, USB_OTGSC);
/* BSV interrupt comes when operating as an A-device
* (VBUS on/off).
* But, handle BSV when charger is removed from ACA in ID_A
@@ -1298,7 +1300,6 @@
work = 1;
} else if (otgsc & OTGSC_DPIS) {
pr_debug("DPIS detected\n");
- writel(otgsc, USB_OTGSC);
set_bit(A_SRP_DET, &dev->inputs);
set_bit(A_BUS_REQ, &dev->inputs);
work = 1;
diff --git a/drivers/usb/otg/msm_otg.c b/drivers/usb/otg/msm_otg.c
index 60018bf..813fc94 100644
--- a/drivers/usb/otg/msm_otg.c
+++ b/drivers/usb/otg/msm_otg.c
@@ -77,6 +77,11 @@
USB_PHY_REG_LPM_OFF,
};
+static char *override_phy_init;
+module_param(override_phy_init, charp, S_IRUGO|S_IWUSR);
+MODULE_PARM_DESC(override_phy_init,
+ "Override HSUSB PHY Init Settings");
+
static DECLARE_COMPLETION(pmic_vbus_init);
static struct msm_otg *the_msm_otg;
static bool debug_aca_enabled;
@@ -384,12 +389,26 @@
static void ulpi_init(struct msm_otg *motg)
{
struct msm_otg_platform_data *pdata = motg->pdata;
- int *seq = pdata->phy_init_seq;
+ int aseq[10];
+ int *seq = NULL;
+
+ if (override_phy_init) {
+ pr_debug("%s(): HUSB PHY Init:%s\n", __func__,
+ override_phy_init);
+ get_options(override_phy_init, ARRAY_SIZE(aseq), aseq);
+ seq = &aseq[1];
+ } else {
+ seq = pdata->phy_init_seq;
+ }
if (!seq)
return;
while (seq[0] >= 0) {
+ if (override_phy_init)
+ pr_debug("ulpi: write 0x%02x to 0x%02x\n",
+ seq[0], seq[1]);
+
dev_vdbg(motg->phy.dev, "ulpi: write 0x%02x to 0x%02x\n",
seq[0], seq[1]);
ulpi_write(&motg->phy, seq[0], seq[1]);
diff --git a/drivers/video/msm/hdmi_msm.c b/drivers/video/msm/hdmi_msm.c
index 902e92c..3b1610a 100644
--- a/drivers/video/msm/hdmi_msm.c
+++ b/drivers/video/msm/hdmi_msm.c
@@ -60,6 +60,9 @@
struct workqueue_struct *hdmi_work_queue;
struct hdmi_msm_state_type *hdmi_msm_state;
+/* Enable HDCP by default */
+static bool hdcp_feature_on = true;
+
DEFINE_MUTEX(hdmi_msm_state_mutex);
EXPORT_SYMBOL(hdmi_msm_state_mutex);
static DEFINE_MUTEX(hdcp_auth_state_mutex);
@@ -4874,6 +4877,27 @@
platform_driver_unregister(&this_driver);
}
+static int set_hdcp_feature_on(const char *val, const struct kernel_param *kp)
+{
+ int rv = param_set_bool(val, kp);
+
+ if (rv)
+ return rv;
+
+ pr_debug("%s: HDCP feature = %d\n", __func__, hdcp_feature_on);
+
+ return 0;
+}
+
+static struct kernel_param_ops hdcp_feature_on_param_ops = {
+ .set = set_hdcp_feature_on,
+ .get = param_get_bool,
+};
+
+module_param_cb(hdcp, &hdcp_feature_on_param_ops, &hdcp_feature_on,
+ S_IRUGO | S_IWUSR);
+MODULE_PARM_DESC(hdcp, "Enable or Disable HDCP");
+
module_init(hdmi_msm_init);
module_exit(hdmi_msm_exit);
diff --git a/drivers/video/msm/mdp.c b/drivers/video/msm/mdp.c
index 79e3808..6c0d08d 100644
--- a/drivers/video/msm/mdp.c
+++ b/drivers/video/msm/mdp.c
@@ -184,7 +184,7 @@
base = 0x18000;
break;
case MDP_BLOCK_OVERLAY_2:
- base = (mdp_rev >= MDP_REV_44) ? 0x88000 : 0;
+ base = (mdp_rev >= MDP_REV_43) ? 0x88000 : 0;
break;
default:
break;
@@ -1325,27 +1325,32 @@
}
#endif
-static void send_vsync_work(struct work_struct *work)
-{
- char buf[64];
- char *envp[2];
-
- snprintf(buf, sizeof(buf), "VSYNC=%llu",
- ktime_to_ns(vsync_cntrl.vsync_time));
- envp[0] = buf;
- envp[1] = NULL;
- kobject_uevent_env(&(vsync_cntrl.dev->kobj), KOBJ_CHANGE, envp);
-}
-
#ifdef CONFIG_FB_MSM_MDP303
/* vsync_isr_handler: Called from isr context*/
static void vsync_isr_handler(void)
{
vsync_cntrl.vsync_time = ktime_get();
- schedule_work(&(vsync_cntrl.vsync_work));
}
#endif
+static ssize_t vsync_show_event(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ ssize_t ret = 0;
+
+ if (atomic_read(&vsync_cntrl.suspend) > 0 ||
+ atomic_read(&vsync_cntrl.vsync_resume) == 0)
+ return 0;
+
+ INIT_COMPLETION(vsync_cntrl.vsync_wait);
+
+ wait_for_completion(&vsync_cntrl.vsync_wait);
+ ret = snprintf(buf, PAGE_SIZE, "VSYNC=%llu",
+ ktime_to_ns(vsync_cntrl.vsync_time));
+ buf[strlen(buf) + 1] = '\0';
+ return ret;
+}
+
/* Returns < 0 on error, 0 on timeout, or > 0 on successful wait */
int mdp_ppp_pipe_wait(void)
{
@@ -1912,6 +1917,8 @@
if (!vsync_isr && !disabled_clocks)
mdp_pipe_ctrl(MDP_CMD_BLOCK,
MDP_BLOCK_POWER_OFF, TRUE);
+
+ complete_all(&vsync_cntrl.vsync_wait);
}
/* DMA3 TV-Out Start */
@@ -1974,6 +1981,8 @@
if (!vsync_isr)
mdp_pipe_ctrl(MDP_CMD_BLOCK,
MDP_BLOCK_POWER_OFF, TRUE);
+
+ complete_all(&vsync_cntrl.vsync_wait);
}
/* DMA2 LCD-Out Complete */
@@ -2105,8 +2114,9 @@
for (i = 0; i < MDP_MAX_BLOCK; i++) {
atomic_set(&mdp_block_power_cnt[i], 0);
}
- INIT_WORK(&(vsync_cntrl.vsync_work), send_vsync_work);
vsync_cntrl.disabled_clocks = 1;
+ init_completion(&vsync_cntrl.vsync_wait);
+ atomic_set(&vsync_cntrl.vsync_resume, 1);
#ifdef MSM_FB_ENABLE_DBGFS
{
struct dentry *root;
@@ -2192,7 +2202,9 @@
pr_debug("%s:+\n", __func__);
mdp_histogram_ctrl_all(FALSE);
-
+ atomic_set(&vsync_cntrl.suspend, 1);
+ atomic_set(&vsync_cntrl.vsync_resume, 0);
+ complete_all(&vsync_cntrl.vsync_wait);
mdp_clk_ctrl(1);
if (mfd->panel.type == MIPI_CMD_PANEL)
mdp4_dsi_cmd_off(pdev);
@@ -2223,7 +2235,16 @@
{
/* empty */
}
+
#endif
+static DEVICE_ATTR(vsync_event, S_IRUGO, vsync_show_event, NULL);
+static struct attribute *vsync_fs_attrs[] = {
+ &dev_attr_vsync_event.attr,
+ NULL,
+};
+static struct attribute_group vsync_fs_attr_group = {
+ .attrs = vsync_fs_attrs,
+};
static int mdp_on(struct platform_device *pdev)
{
@@ -2253,10 +2274,26 @@
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
}
- if ((mdp_rev == MDP_REV_303) &&
- (mfd->panel.type == MIPI_CMD_PANEL))
+ if (mdp_rev == MDP_REV_303 && mfd->panel.type == MIPI_CMD_PANEL) {
+
vsync_cntrl.dev = mfd->fbi->dev;
+ if (!vsync_cntrl.sysfs_created) {
+ ret = sysfs_create_group(&vsync_cntrl.dev->kobj,
+ &vsync_fs_attr_group);
+ if (ret) {
+ pr_err("%s: sysfs creation failed, ret=%d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ kobject_uevent(&vsync_cntrl.dev->kobj, KOBJ_ADD);
+ pr_debug("%s: kobject_uevent(KOBJ_ADD)\n", __func__);
+ vsync_cntrl.sysfs_created = 1;
+ }
+ atomic_set(&vsync_cntrl.suspend, 0);
+ }
+
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
ret = panel_next_on(pdev);
@@ -2488,6 +2525,7 @@
#endif
static int contSplash_update_done;
char *cp;
+ unsigned int mdp_r = 0;
if ((pdev->id == 0) && (pdev->num_resources > 0)) {
mdp_init_pdev = pdev;
@@ -2509,6 +2547,15 @@
}
mdp_rev = mdp_pdata->mdp_rev;
+ if (mdp_rev == MDP_REV_42) {
+ mdp_r = inpdw(MDP_BASE + 0x0);
+ mdp_r = ((mdp_r & 0x30000) >> 16);
+ if (mdp_r == 3) {
+ mdp_rev = MDP_REV_43;
+ mdp_pdata->mdp_rev = MDP_REV_43;
+ }
+ }
+
mdp_iommu_split_domain = mdp_pdata->mdp_iommu_split_domain;
rc = mdp_irq_clk_setup(pdev, mdp_pdata->cont_splash_enabled);
diff --git a/drivers/video/msm/mdp.h b/drivers/video/msm/mdp.h
index b86116d..d939c62 100644
--- a/drivers/video/msm/mdp.h
+++ b/drivers/video/msm/mdp.h
@@ -100,6 +100,10 @@
int vsync_irq_enabled;
int vsync_dma_enabled;
int disabled_clocks;
+ struct completion vsync_wait;
+ atomic_t suspend;
+ atomic_t vsync_resume;
+ int sysfs_created;
};
extern struct vsync vsync_cntrl;
diff --git a/drivers/video/msm/mdp4.h b/drivers/video/msm/mdp4.h
index 005e87c..b7d4c32 100644
--- a/drivers/video/msm/mdp4.h
+++ b/drivers/video/msm/mdp4.h
@@ -349,7 +349,7 @@
uint32 ov_cnt;
uint32 dmap_cnt;
uint32 dmae_cnt;
- uint32 blt_end;
+ uint32 blt_end; /* used by mddi only */
uint32 blt_ov_koff;
uint32 blt_ov_done;
uint32 blt_dmap_koff;
@@ -543,12 +543,9 @@
void mdp4_overlay0_done_dsi_cmd(int cndx);
void mdp4_primary_rdptr(void);
void mdp4_dsi_cmd_overlay(struct msm_fb_data_type *mfd);
-int mdp4_overlay_commit(struct fb_info *info, int mixer);
-int mdp4_dsi_video_pipe_commit(void);
-int mdp4_dsi_cmd_pipe_commit(void);
+int mdp4_lcdc_pipe_commit(int cndx, int wait);
+int mdp4_dtv_pipe_commit(int cndx, int wait);
int mdp4_dsi_cmd_update_cnt(int cndx);
-int mdp4_lcdc_pipe_commit(void);
-int mdp4_dtv_pipe_commit(void);
void mdp4_dsi_rdptr_init(int cndx);
void mdp4_dsi_vsync_init(int cndx);
void mdp4_lcdc_vsync_init(int cndx);
@@ -577,6 +574,7 @@
int mdp4_overlay_play_wait(struct fb_info *info,
struct msmfb_overlay_data *req);
int mdp4_overlay_play(struct fb_info *info, struct msmfb_overlay_data *req);
+int mdp4_overlay_commit(struct fb_info *info, int mixer);
struct mdp4_overlay_pipe *mdp4_overlay_pipe_alloc(int ptype, int mixer);
void mdp4_overlay_dma_commit(int mixer);
void mdp4_overlay_vsync_commit(struct mdp4_overlay_pipe *pipe);
@@ -763,6 +761,8 @@
void mdp4_dsi_video_wait4vsync(int cndx, long long *vtime);
void mdp4_dsi_cmd_pipe_queue(int cndx, struct mdp4_overlay_pipe *pipe);
void mdp4_dsi_video_pipe_queue(int cndx, struct mdp4_overlay_pipe *pipe);
+int mdp4_dsi_video_pipe_commit(int cndx, int wait);
+int mdp4_dsi_cmd_pipe_commit(int cndx, int wait);
void mdp4_dsi_cmd_vsync_ctrl(struct fb_info *info, int enable);
void mdp4_dsi_video_vsync_ctrl(struct fb_info *info, int enable);
#ifdef CONFIG_FB_MSM_MDP303
@@ -812,6 +812,14 @@
struct mdp4_overlay_pipe *pipe)
{
}
+static inline int mdp4_dsi_video_pipe_commit(int cndx, int wait)
+{
+ return 0;
+}
+static inline int mdp4_dsi_cmd_pipe_commit(int cndx, int wait)
+{
+ return 0;
+}
static inline void mdp4_dsi_cmd_vsync_ctrl(struct fb_info *info,
int enable)
{
diff --git a/drivers/video/msm/mdp4_overlay.c b/drivers/video/msm/mdp4_overlay.c
index a5307e6..2aafa6f 100644
--- a/drivers/video/msm/mdp4_overlay.c
+++ b/drivers/video/msm/mdp4_overlay.c
@@ -1636,6 +1636,8 @@
data |= stage;
}
+ mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
+ mdp_clk_ctrl(1);
mdp4_mixer_blend_setup(mixer);
off = 0;
@@ -1655,7 +1657,6 @@
mixer, data, ctrl->flush[mixer], current->pid);
}
- mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
local_irq_save(flags);
if (off)
outpdw(MDP_BASE + off, data);
@@ -1666,6 +1667,7 @@
}
local_irq_restore(flags);
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
+ mdp_clk_ctrl(0);
}
@@ -2331,6 +2333,18 @@
return -ERANGE;
}
+ if (mdp_rev <= MDP_REV_41) {
+ if ((mdp4_overlay_format2type(req->src.format) ==
+ OVERLAY_TYPE_RGB) &&
+ !(req->flags & MDP_OV_PIPE_SHARE) &&
+ ((req->src_rect.w > req->dst_rect.w) ||
+ (req->src_rect.h > req->dst_rect.h))) {
+ mdp4_stat.err_size++;
+ pr_err("%s: downscale on RGB pipe!\n", __func__);
+ return -EINVAL;
+ }
+ }
+
if (mdp_hw_revision == MDP4_REVISION_V1) {
/* non integer down saceling ratio smaller than 1/4
* is not supportted
@@ -3450,8 +3464,7 @@
if (ctrl->panel_mode & MDP4_PANEL_DSI_CMD) {
/* cndx = 0 */
mdp4_dsi_cmd_pipe_queue(0, pipe);
- }
- if (ctrl->panel_mode & MDP4_PANEL_DSI_VIDEO) {
+ } else if (ctrl->panel_mode & MDP4_PANEL_DSI_VIDEO) {
/* cndx = 0 */
mdp4_dsi_video_pipe_queue(0, pipe);
} else if (ctrl->panel_mode & MDP4_PANEL_LCDC) {
@@ -3513,6 +3526,46 @@
return ret;
}
+int mdp4_overlay_commit(struct fb_info *info, int mixer)
+{
+ struct msm_fb_data_type *mfd = (struct msm_fb_data_type *)info->par;
+
+ if (mfd == NULL)
+ return -ENODEV;
+
+ if (!mfd->panel_power_on) /* suspended */
+ return -EINVAL;
+
+ if (mixer >= MDP4_MIXER_MAX)
+ return -EPERM;
+
+ mutex_lock(&mfd->dma->ov_mutex);
+
+ mdp4_overlay_mdp_perf_upd(mfd, 1);
+
+ if (mixer == MDP4_MIXER0) {
+ if (ctrl->panel_mode & MDP4_PANEL_DSI_CMD) {
+ /* cndx = 0 */
+ mdp4_dsi_cmd_pipe_commit(0, 1);
+ } else if (ctrl->panel_mode & MDP4_PANEL_DSI_VIDEO) {
+ /* cndx = 0 */
+ mdp4_dsi_video_pipe_commit(0, 1);
+ } else if (ctrl->panel_mode & MDP4_PANEL_LCDC) {
+ /* cndx = 0 */
+ mdp4_lcdc_pipe_commit(0, 1);
+ }
+ } else if (mixer == MDP4_MIXER1) {
+ if (ctrl->panel_mode & MDP4_PANEL_DTV)
+ mdp4_dtv_pipe_commit(0, 1);
+ }
+
+ mdp4_overlay_mdp_perf_upd(mfd, 0);
+
+ mutex_unlock(&mfd->dma->ov_mutex);
+
+ return 0;
+}
+
struct msm_iommu_ctx {
char *name;
int domain;
diff --git a/drivers/video/msm/mdp4_overlay_dsi_cmd.c b/drivers/video/msm/mdp4_overlay_dsi_cmd.c
index 3320d11..a937734 100644
--- a/drivers/video/msm/mdp4_overlay_dsi_cmd.c
+++ b/drivers/video/msm/mdp4_overlay_dsi_cmd.c
@@ -39,7 +39,7 @@
static int vsync_start_y_adjust = 4;
#define MAX_CONTROLLER 1
-#define VSYNC_EXPIRE_TICK 8
+#define VSYNC_EXPIRE_TICK 4
static struct vsycn_ctrl {
struct device *dev;
@@ -54,11 +54,12 @@
uint32 rdptr_intr_tot;
uint32 rdptr_sirq_tot;
atomic_t suspend;
+ atomic_t vsync_resume;
int wait_vsync_cnt;
int blt_change;
int blt_free;
int blt_end;
- int uevent;
+ int sysfs_created;
struct mutex update_lock;
struct completion ov_comp;
struct completion dmap_comp;
@@ -72,7 +73,6 @@
int clk_control;
int new_update;
ktime_t vsync_time;
- struct work_struct vsync_work;
struct work_struct clk_work;
} vsync_ctrl_db[MAX_CONTROLLER];
@@ -250,7 +250,7 @@
static void mdp4_dsi_cmd_blt_ov_update(struct mdp4_overlay_pipe *pipe);
-int mdp4_dsi_cmd_pipe_commit(void)
+int mdp4_dsi_cmd_pipe_commit(int cndx, int wait)
{
int i, undx;
int mixer = 0;
@@ -377,6 +377,12 @@
mdp4_stat.overlay_commit[pipe->mixer_num]++;
+ if (wait) {
+ long long tick;
+
+ mdp4_dsi_cmd_wait4vsync(cndx, &tick);
+ }
+
return cnt;
}
@@ -384,7 +390,6 @@
void mdp4_dsi_cmd_vsync_ctrl(struct fb_info *info, int enable)
{
- struct msm_fb_data_type *mfd = (struct msm_fb_data_type *)info->par;
struct vsycn_ctrl *vctrl;
unsigned long flags;
int clk_set_on = 0;
@@ -415,24 +420,23 @@
spin_lock_irqsave(&vctrl->spin_lock, flags);
vctrl->clk_control = 0;
vctrl->expire_tick = 0;
- vctrl->uevent = 1;
vctrl->new_update = 1;
if (clk_set_on) {
vsync_irq_enable(INTR_PRIMARY_RDPTR,
MDP_PRIM_RDPTR_TERM);
}
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
-
- mdp4_overlay_update_dsi_cmd(mfd);
} else {
spin_lock_irqsave(&vctrl->spin_lock, flags);
vctrl->clk_control = 1;
- vctrl->uevent = 0;
if (vctrl->clk_enabled)
vctrl->expire_tick = VSYNC_EXPIRE_TICK;
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
}
mutex_unlock(&vctrl->update_lock);
+
+ if (vctrl->vsync_enabled && atomic_read(&vctrl->suspend) == 0)
+ atomic_set(&vctrl->vsync_resume, 1);
}
void mdp4_dsi_cmd_wait4vsync(int cndx, long long *vtime)
@@ -515,13 +519,9 @@
vctrl->vsync_time = ktime_get();
spin_lock(&vctrl->spin_lock);
- if (vctrl->uevent)
- schedule_work(&vctrl->vsync_work);
- if (vctrl->wait_vsync_cnt) {
- complete(&vctrl->vsync_comp);
- vctrl->wait_vsync_cnt = 0;
- }
+ complete_all(&vctrl->vsync_comp);
+ vctrl->wait_vsync_cnt = 0;
if (vctrl->expire_tick) {
vctrl->expire_tick--;
@@ -636,21 +636,35 @@
mutex_unlock(&vctrl->update_lock);
}
-static void send_vsync_work(struct work_struct *work)
+static ssize_t vsync_show_event(struct device *dev,
+ struct device_attribute *attr, char *buf)
{
- struct vsycn_ctrl *vctrl =
- container_of(work, typeof(*vctrl), vsync_work);
- char buf[64];
- char *envp[2];
+ int cndx;
+ struct vsycn_ctrl *vctrl;
+ ssize_t ret = 0;
+ unsigned long flags;
- snprintf(buf, sizeof(buf), "VSYNC=%llu",
+ cndx = 0;
+ vctrl = &vsync_ctrl_db[0];
+
+ if (atomic_read(&vctrl->suspend) > 0 ||
+ atomic_read(&vctrl->vsync_resume) == 0)
+ return 0;
+
+ spin_lock_irqsave(&vctrl->spin_lock, flags);
+ if (vctrl->wait_vsync_cnt == 0)
+ INIT_COMPLETION(vctrl->vsync_comp);
+ vctrl->wait_vsync_cnt++;
+ spin_unlock_irqrestore(&vctrl->spin_lock, flags);
+
+ wait_for_completion(&vctrl->vsync_comp);
+
+ ret = snprintf(buf, PAGE_SIZE, "VSYNC=%llu",
ktime_to_ns(vctrl->vsync_time));
- envp[0] = buf;
- envp[1] = NULL;
- kobject_uevent_env(&vctrl->dev->kobj, KOBJ_CHANGE, envp);
+ buf[strlen(buf) + 1] = '\0';
+ return ret;
}
-
void mdp4_dsi_rdptr_init(int cndx)
{
struct vsycn_ctrl *vctrl;
@@ -671,7 +685,7 @@
init_completion(&vctrl->dmap_comp);
init_completion(&vctrl->vsync_comp);
spin_lock_init(&vctrl->spin_lock);
- INIT_WORK(&vctrl->vsync_work, send_vsync_work);
+ atomic_set(&vctrl->vsync_resume, 1);
INIT_WORK(&vctrl->clk_work, clk_ctrl_work);
}
@@ -952,6 +966,14 @@
mdp4_dsi_cmd_do_blt(mfd, req->enable);
}
+static DEVICE_ATTR(vsync_event, S_IRUGO, vsync_show_event, NULL);
+static struct attribute *vsync_fs_attrs[] = {
+ &dev_attr_vsync_event.attr,
+ NULL,
+};
+static struct attribute_group vsync_fs_attr_group = {
+ .attrs = vsync_fs_attrs,
+};
int mdp4_dsi_cmd_on(struct platform_device *pdev)
{
int ret = 0;
@@ -976,6 +998,19 @@
atomic_set(&vctrl->suspend, 0);
pr_debug("%s-:\n", __func__);
+ if (!vctrl->sysfs_created) {
+ ret = sysfs_create_group(&vctrl->dev->kobj,
+ &vsync_fs_attr_group);
+ if (ret) {
+ pr_err("%s: sysfs group creation failed, ret=%d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ kobject_uevent(&vctrl->dev->kobj, KOBJ_ADD);
+ pr_debug("%s: kobject_uevent(KOBJ_ADD)\n", __func__);
+ vctrl->sysfs_created = 1;
+ }
return ret;
}
@@ -1000,6 +1035,9 @@
}
atomic_set(&vctrl->suspend, 1);
+ atomic_set(&vctrl->vsync_resume, 0);
+
+ complete_all(&vctrl->vsync_comp);
/* sanity check, free pipes besides base layer */
mdp4_overlay_unset_mixer(pipe->mixer_num);
@@ -1020,7 +1058,6 @@
vctrl->vsync_enabled = 0;
vctrl->clk_control = 0;
vctrl->expire_tick = 0;
- vctrl->uevent = 0;
vsync_irq_disable(INTR_PRIMARY_RDPTR, MDP_PRIM_RDPTR_TERM);
@@ -1068,7 +1105,7 @@
struct vsycn_ctrl *vctrl;
struct mdp4_overlay_pipe *pipe;
unsigned long flags;
- long long xx;
+ long long tick;
vctrl = &vsync_ctrl_db[cndx];
@@ -1109,10 +1146,10 @@
mdp4_overlay_mdp_perf_upd(mfd, 1);
mutex_lock(&mfd->dma->ov_mutex);
- mdp4_dsi_cmd_pipe_commit();
+ mdp4_dsi_cmd_pipe_commit(cndx, 0);
mutex_unlock(&mfd->dma->ov_mutex);
- mdp4_dsi_cmd_wait4vsync(0, &xx);
+ mdp4_dsi_cmd_wait4vsync(cndx, &tick);
mdp4_overlay_mdp_perf_upd(mfd, 0);
}
diff --git a/drivers/video/msm/mdp4_overlay_dsi_video.c b/drivers/video/msm/mdp4_overlay_dsi_video.c
index e448d08..736a353 100644
--- a/drivers/video/msm/mdp4_overlay_dsi_video.c
+++ b/drivers/video/msm/mdp4_overlay_dsi_video.c
@@ -52,10 +52,11 @@
int ov_koff;
int ov_done;
atomic_t suspend;
+ atomic_t vsync_resume;
int wait_vsync_cnt;
int blt_change;
int blt_free;
- int fake_vsync;
+ int sysfs_created;
struct mutex update_lock;
struct completion ov_comp;
struct completion dmap_comp;
@@ -66,7 +67,6 @@
struct vsync_update vlist[2];
int vsync_irq_enabled;
ktime_t vsync_time;
- struct work_struct vsync_work;
} vsync_ctrl_db[MAX_CONTROLLER];
static void vsync_irq_enable(int intr, int term)
@@ -147,7 +147,7 @@
static void mdp4_dsi_video_wait4dmap(int cndx);
static void mdp4_dsi_video_wait4ov(int cndx);
-int mdp4_dsi_video_pipe_commit(void)
+int mdp4_dsi_video_pipe_commit(int cndx, int wait)
{
int i, undx;
@@ -159,7 +159,7 @@
unsigned long flags;
int cnt = 0;
- vctrl = &vsync_ctrl_db[0];
+ vctrl = &vsync_ctrl_db[cndx];
mutex_lock(&vctrl->update_lock);
undx = vctrl->update_ndx;
@@ -253,6 +253,13 @@
mdp4_stat.overlay_commit[pipe->mixer_num]++;
+ if (wait) {
+ if (pipe->ov_blt_addr)
+ mdp4_dsi_video_wait4ov(cndx);
+ else
+ mdp4_dsi_video_wait4dmap(cndx);
+ }
+
return cnt;
}
@@ -263,11 +270,6 @@
vctrl = &vsync_ctrl_db[cndx];
- if (vctrl->fake_vsync) {
- vctrl->fake_vsync = 0;
- schedule_work(&vctrl->vsync_work);
- }
-
if (vctrl->vsync_irq_enabled == enable)
return;
@@ -279,6 +281,9 @@
vsync_irq_enable(INTR_PRIMARY_VSYNC, MDP_PRIM_VSYNC_TERM);
else
vsync_irq_disable(INTR_PRIMARY_VSYNC, MDP_PRIM_VSYNC_TERM);
+
+ if (vctrl->vsync_irq_enabled && atomic_read(&vctrl->suspend) == 0)
+ atomic_set(&vctrl->vsync_resume, 1);
}
void mdp4_dsi_video_wait4vsync(int cndx, long long *vtime)
@@ -350,7 +355,6 @@
vsync_irq_enable(INTR_DMA_P_DONE, MDP_DMAP_TERM);
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
mdp4_dsi_video_wait4dmap(cndx);
- vsync_irq_disable(INTR_DMA_P_DONE, MDP_DMAP_TERM);
}
@@ -371,18 +375,32 @@
wait_for_completion(&vctrl->ov_comp);
}
-static void send_vsync_work(struct work_struct *work)
+static ssize_t vsync_show_event(struct device *dev,
+ struct device_attribute *attr, char *buf)
{
- struct vsycn_ctrl *vctrl =
- container_of(work, typeof(*vctrl), vsync_work);
- char buf[64];
- char *envp[2];
+ int cndx;
+ struct vsycn_ctrl *vctrl;
+ ssize_t ret = 0;
+ unsigned long flags;
- snprintf(buf, sizeof(buf), "VSYNC=%llu",
+ cndx = 0;
+ vctrl = &vsync_ctrl_db[0];
+
+ if (atomic_read(&vctrl->suspend) > 0 ||
+ atomic_read(&vctrl->vsync_resume) == 0)
+ return 0;
+
+ spin_lock_irqsave(&vctrl->spin_lock, flags);
+ if (vctrl->wait_vsync_cnt == 0)
+ INIT_COMPLETION(vctrl->vsync_comp);
+ vctrl->wait_vsync_cnt++;
+ spin_unlock_irqrestore(&vctrl->spin_lock, flags);
+ wait_for_completion(&vctrl->vsync_comp);
+
+ ret = snprintf(buf, PAGE_SIZE, "VSYNC=%llu",
ktime_to_ns(vctrl->vsync_time));
- envp[0] = buf;
- envp[1] = NULL;
- kobject_uevent_env(&vctrl->dev->kobj, KOBJ_CHANGE, envp);
+ buf[strlen(buf) + 1] = '\0';
+ return ret;
}
void mdp4_dsi_vsync_init(int cndx)
@@ -407,8 +425,8 @@
init_completion(&vctrl->dmap_comp);
init_completion(&vctrl->ov_comp);
atomic_set(&vctrl->suspend, 0);
+ atomic_set(&vctrl->vsync_resume, 1);
spin_lock_init(&vctrl->spin_lock);
- INIT_WORK(&vctrl->vsync_work, send_vsync_work);
}
void mdp4_dsi_video_base_swap(int cndx, struct mdp4_overlay_pipe *pipe)
@@ -424,6 +442,16 @@
vctrl->base_pipe = pipe;
}
+static DEVICE_ATTR(vsync_event, S_IRUGO, vsync_show_event, NULL);
+
+static struct attribute *vsync_fs_attrs[] = {
+ &dev_attr_vsync_event.attr,
+ NULL,
+};
+
+static struct attribute_group vsync_fs_attr_group = {
+ .attrs = vsync_fs_attrs,
+};
int mdp4_dsi_video_on(struct platform_device *pdev)
{
int dsi_width;
@@ -478,7 +506,6 @@
vctrl->mfd = mfd;
vctrl->dev = mfd->fbi->dev;
- vctrl->fake_vsync = 1;
/* mdp clock on */
mdp_clk_ctrl(1);
@@ -637,6 +664,21 @@
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
mdp_histogram_ctrl_all(TRUE);
+
+ if (!vctrl->sysfs_created) {
+ ret = sysfs_create_group(&vctrl->dev->kobj,
+ &vsync_fs_attr_group);
+ if (ret) {
+ pr_err("%s: sysfs group creation failed, ret=%d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ kobject_uevent(&vctrl->dev->kobj, KOBJ_ADD);
+ pr_debug("%s: kobject_uevent(KOBJ_ADD)\n", __func__);
+ vctrl->sysfs_created = 1;
+ }
+
return ret;
}
@@ -655,9 +697,12 @@
pipe = vctrl->base_pipe;
atomic_set(&vctrl->suspend, 1);
+ atomic_set(&vctrl->vsync_resume, 0);
msleep(20); /* >= 17 ms */
+ complete_all(&vctrl->vsync_comp);
+
if (pipe->ov_blt_addr) {
spin_lock_irqsave(&vctrl->spin_lock, flags);
if (vctrl->ov_koff != vctrl->ov_done)
@@ -699,8 +744,6 @@
}
}
- vctrl->fake_vsync = 1;
-
/* mdp clock off */
mdp_clk_ctrl(0);
mdp_pipe_ctrl(MDP_OVERLAY0_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
@@ -865,7 +908,6 @@
vctrl = &vsync_ctrl_db[cndx];
pr_debug("%s: cpu=%d\n", __func__, smp_processor_id());
vctrl->vsync_time = ktime_get();
- schedule_work(&vctrl->vsync_work);
spin_lock(&vctrl->spin_lock);
if (vctrl->wait_vsync_cnt) {
@@ -1040,13 +1082,13 @@
mdp4_overlay_mdp_perf_upd(mfd, 1);
mutex_lock(&mfd->dma->ov_mutex);
- mdp4_dsi_video_pipe_commit();
+ mdp4_dsi_video_pipe_commit(cndx, 0);
mutex_unlock(&mfd->dma->ov_mutex);
if (pipe->ov_blt_addr)
- mdp4_dsi_video_wait4ov(0);
+ mdp4_dsi_video_wait4ov(cndx);
else
- mdp4_dsi_video_wait4dmap(0);
+ mdp4_dsi_video_wait4dmap(cndx);
mdp4_overlay_mdp_perf_upd(mfd, 0);
}
diff --git a/drivers/video/msm/mdp4_overlay_dtv.c b/drivers/video/msm/mdp4_overlay_dtv.c
index ffb1416..c70f83d 100644
--- a/drivers/video/msm/mdp4_overlay_dtv.c
+++ b/drivers/video/msm/mdp4_overlay_dtv.c
@@ -29,6 +29,7 @@
#include "mdp.h"
#include "msm_fb.h"
+#include "hdmi_msm.h"
#include "mdp4.h"
#define DTV_BASE 0xD0000
@@ -70,10 +71,11 @@
int update_ndx;
int dmae_intr_cnt;
atomic_t suspend;
+ atomic_t vsync_resume;
int dmae_wait_cnt;
int wait_vsync_cnt;
int blt_change;
- int fake_vsync;
+ int sysfs_created;
struct mutex update_lock;
struct completion ov_comp;
struct completion dmae_comp;
@@ -83,7 +85,6 @@
struct vsync_update vlist[2];
int vsync_irq_enabled;
ktime_t vsync_time;
- struct work_struct vsync_work;
} vsync_ctrl_db[MAX_CONTROLLER];
static void vsync_irq_enable(int intr, int term)
@@ -164,7 +165,7 @@
static void mdp4_dtv_blt_ov_update(struct mdp4_overlay_pipe *pipe);
static void mdp4_dtv_wait4dmae(int cndx);
-int mdp4_dtv_pipe_commit(void)
+int mdp4_dtv_pipe_commit(int cndx, int wait)
{
int i, undx;
@@ -176,7 +177,7 @@
unsigned long flags;
int cnt = 0;
- vctrl = &vsync_ctrl_db[0];
+ vctrl = &vsync_ctrl_db[cndx];
mutex_lock(&vctrl->update_lock);
undx = vctrl->update_ndx;
vp = &vctrl->vlist[undx];
@@ -235,6 +236,9 @@
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
mdp4_stat.overlay_commit[pipe->mixer_num]++;
+ if (wait)
+ mdp4_dtv_wait4dmae(cndx);
+
return cnt;
}
@@ -245,10 +249,8 @@
vctrl = &vsync_ctrl_db[cndx];
- if (vctrl->fake_vsync) {
- vctrl->fake_vsync = 0;
- schedule_work(&vctrl->vsync_work);
- }
+ if (!external_common_state->hpd_state)
+ complete_all(&vctrl->vsync_comp);
if (vctrl->vsync_irq_enabled == enable)
return;
@@ -261,6 +263,9 @@
vsync_irq_enable(INTR_EXTERNAL_VSYNC, MDP_EXTER_VSYNC_TERM);
else
vsync_irq_disable(INTR_EXTERNAL_VSYNC, MDP_EXTER_VSYNC_TERM);
+
+ if (vctrl->vsync_irq_enabled && atomic_read(&vctrl->suspend) == 0)
+ atomic_set(&vctrl->vsync_resume, 1);
}
void mdp4_dtv_wait4vsync(int cndx, long long *vtime)
@@ -310,20 +315,34 @@
wait_for_completion(&vctrl->dmae_comp);
}
-static void send_vsync_work(struct work_struct *work)
+static ssize_t vsync_show_event(struct device *dev,
+ struct device_attribute *attr, char *buf)
{
- struct vsycn_ctrl *vctrl =
- container_of(work, typeof(*vctrl), vsync_work);
- char buf[64];
- char *envp[2];
+ int cndx;
+ struct vsycn_ctrl *vctrl;
+ ssize_t ret = 0;
+ unsigned long flags;
- snprintf(buf, sizeof(buf), "VSYNC=%llu",
+ cndx = 0;
+ vctrl = &vsync_ctrl_db[0];
+
+ if (atomic_read(&vctrl->suspend) > 0 ||
+ !external_common_state->hpd_state ||
+ atomic_read(&vctrl->vsync_resume) == 0)
+ return 0;
+
+ spin_lock_irqsave(&vctrl->spin_lock, flags);
+ if (vctrl->wait_vsync_cnt == 0)
+ INIT_COMPLETION(vctrl->vsync_comp);
+ vctrl->wait_vsync_cnt++;
+ spin_unlock_irqrestore(&vctrl->spin_lock, flags);
+ wait_for_completion(&vctrl->vsync_comp);
+
+ ret = snprintf(buf, PAGE_SIZE, "VSYNC=%llu",
ktime_to_ns(vctrl->vsync_time));
- envp[0] = buf;
- envp[1] = NULL;
- kobject_uevent_env(&vctrl->dev->kobj, KOBJ_CHANGE, envp);
+ buf[strlen(buf) + 1] = '\0';
+ return ret;
}
-
void mdp4_dtv_vsync_init(int cndx)
{
struct vsycn_ctrl *vctrl;
@@ -346,8 +365,8 @@
init_completion(&vctrl->ov_comp);
init_completion(&vctrl->dmae_comp);
atomic_set(&vctrl->suspend, 0);
+ atomic_set(&vctrl->vsync_resume, 1);
spin_lock_init(&vctrl->spin_lock);
- INIT_WORK(&vctrl->vsync_work, send_vsync_work);
}
static int mdp4_dtv_start(struct msm_fb_data_type *mfd)
@@ -506,6 +525,15 @@
return 0;
}
+static DEVICE_ATTR(vsync_event, S_IRUGO, vsync_show_event, NULL);
+static struct attribute *vsync_fs_attrs[] = {
+ &dev_attr_vsync_event.attr,
+ NULL,
+};
+static struct attribute_group vsync_fs_attr_group = {
+ .attrs = vsync_fs_attrs,
+};
+
int mdp4_dtv_on(struct platform_device *pdev)
{
struct msm_fb_data_type *mfd;
@@ -524,7 +552,6 @@
return -EINVAL;
vctrl->dev = mfd->fbi->dev;
- vctrl->fake_vsync = 1;
mdp_footswitch_ctrl(TRUE);
/* Mdp clock enable */
@@ -547,6 +574,19 @@
atomic_set(&vctrl->suspend, 0);
+ if (!vctrl->sysfs_created) {
+ ret = sysfs_create_group(&vctrl->dev->kobj,
+ &vsync_fs_attr_group);
+ if (ret) {
+ pr_err("%s: sysfs group creation failed, ret=%d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ kobject_uevent(&vctrl->dev->kobj, KOBJ_ADD);
+ pr_debug("%s: kobject_uevent(KOBJ_ADD)\n", __func__);
+ vctrl->sysfs_created = 1;
+ }
pr_info("%s:\n", __func__);
return ret;
@@ -565,9 +605,14 @@
vctrl = &vsync_ctrl_db[cndx];
atomic_set(&vctrl->suspend, 1);
+ atomic_set(&vctrl->vsync_resume, 0);
- while (vctrl->wait_vsync_cnt)
- msleep(20); /* >= 17 ms */
+ if (vctrl->vsync_irq_enabled) {
+ while (vctrl->wait_vsync_cnt)
+ msleep(20); /* >= 17 ms */
+ }
+
+ complete_all(&vctrl->vsync_comp);
pipe = vctrl->base_pipe;
if (pipe != NULL) {
@@ -601,7 +646,6 @@
ret = panel_next_off(pdev);
mdp_footswitch_ctrl(FALSE);
- vctrl->fake_vsync = 1;
/* Mdp clock disable */
mdp_clk_ctrl(0);
@@ -800,7 +844,6 @@
vctrl = &vsync_ctrl_db[cndx];
pr_debug("%s: cpu=%d\n", __func__, smp_processor_id());
vctrl->vsync_time = ktime_get();
- schedule_work(&vctrl->vsync_work);
spin_lock(&vctrl->spin_lock);
if (vctrl->wait_vsync_cnt) {
@@ -1020,7 +1063,7 @@
mutex_lock(&mfd->dma->ov_mutex);
mdp4_overlay_mdp_perf_upd(mfd, 1);
- mdp4_dtv_pipe_commit();
+ mdp4_dtv_pipe_commit(cndx, 0);
mdp4_overlay_mdp_perf_upd(mfd, 0);
mutex_unlock(&mfd->dma->ov_mutex);
}
diff --git a/drivers/video/msm/mdp4_overlay_lcdc.c b/drivers/video/msm/mdp4_overlay_lcdc.c
index f700da9..a5ce869 100644
--- a/drivers/video/msm/mdp4_overlay_lcdc.c
+++ b/drivers/video/msm/mdp4_overlay_lcdc.c
@@ -53,10 +53,11 @@
int ov_koff;
int ov_done;
atomic_t suspend;
+ atomic_t vsync_resume;
int wait_vsync_cnt;
int blt_change;
int blt_free;
- int fake_vsync;
+ int sysfs_created;
struct mutex update_lock;
struct completion ov_comp;
struct completion dmap_comp;
@@ -67,7 +68,6 @@
struct vsync_update vlist[2];
int vsync_irq_enabled;
ktime_t vsync_time;
- struct work_struct vsync_work;
} vsync_ctrl_db[MAX_CONTROLLER];
@@ -152,7 +152,7 @@
static void mdp4_lcdc_wait4dmap(int cndx);
static void mdp4_lcdc_wait4ov(int cndx);
-int mdp4_lcdc_pipe_commit(void)
+int mdp4_lcdc_pipe_commit(int cndx, int wait)
{
int i, undx;
@@ -164,7 +164,7 @@
unsigned long flags;
int cnt = 0;
- vctrl = &vsync_ctrl_db[0];
+ vctrl = &vsync_ctrl_db[cndx];
mutex_lock(&vctrl->update_lock);
undx = vctrl->update_ndx;
@@ -257,6 +257,13 @@
mdp4_stat.overlay_commit[pipe->mixer_num]++;
+ if (wait) {
+ if (pipe->ov_blt_addr)
+ mdp4_lcdc_wait4ov(cndx);
+ else
+ mdp4_lcdc_wait4dmap(cndx);
+ }
+
return cnt;
}
@@ -267,11 +274,6 @@
vctrl = &vsync_ctrl_db[cndx];
- if (vctrl->fake_vsync) {
- vctrl->fake_vsync = 0;
- schedule_work(&vctrl->vsync_work);
- }
-
if (vctrl->vsync_irq_enabled == enable)
return;
@@ -283,6 +285,9 @@
vsync_irq_enable(INTR_PRIMARY_VSYNC, MDP_PRIM_VSYNC_TERM);
else
vsync_irq_disable(INTR_PRIMARY_VSYNC, MDP_PRIM_VSYNC_TERM);
+
+ if (vctrl->vsync_irq_enabled && atomic_read(&vctrl->suspend) == 0)
+ atomic_set(&vctrl->vsync_resume, 1);
}
void mdp4_lcdc_wait4vsync(int cndx, long long *vtime)
@@ -354,18 +359,32 @@
wait_for_completion(&vctrl->ov_comp);
}
-static void send_vsync_work(struct work_struct *work)
+static ssize_t vsync_show_event(struct device *dev,
+ struct device_attribute *attr, char *buf)
{
- struct vsycn_ctrl *vctrl =
- container_of(work, typeof(*vctrl), vsync_work);
- char buf[64];
- char *envp[2];
+ int cndx;
+ struct vsycn_ctrl *vctrl;
+ ssize_t ret = 0;
+ unsigned long flags;
- snprintf(buf, sizeof(buf), "VSYNC=%llu",
- ktime_to_ns(vctrl->vsync_time));
- envp[0] = buf;
- envp[1] = NULL;
- kobject_uevent_env(&vctrl->dev->kobj, KOBJ_CHANGE, envp);
+ cndx = 0;
+ vctrl = &vsync_ctrl_db[0];
+
+ if (atomic_read(&vctrl->suspend) > 0 ||
+ atomic_read(&vctrl->vsync_resume) == 0)
+ return 0;
+
+ spin_lock_irqsave(&vctrl->spin_lock, flags);
+ if (vctrl->wait_vsync_cnt == 0)
+ INIT_COMPLETION(vctrl->vsync_comp);
+ vctrl->wait_vsync_cnt++;
+ spin_unlock_irqrestore(&vctrl->spin_lock, flags);
+ wait_for_completion(&vctrl->vsync_comp);
+
+ ret = snprintf(buf, PAGE_SIZE, "VSYNC=%llu",
+ ktime_to_ns(vctrl->vsync_time));
+ buf[strlen(buf) + 1] = '\0';
+ return ret;
}
void mdp4_lcdc_vsync_init(int cndx)
@@ -390,8 +409,8 @@
init_completion(&vctrl->dmap_comp);
init_completion(&vctrl->ov_comp);
atomic_set(&vctrl->suspend, 0);
+ atomic_set(&vctrl->vsync_resume, 1);
spin_lock_init(&vctrl->spin_lock);
- INIT_WORK(&vctrl->vsync_work, send_vsync_work);
}
void mdp4_lcdc_base_swap(int cndx, struct mdp4_overlay_pipe *pipe)
@@ -407,6 +426,15 @@
vctrl->base_pipe = pipe;
}
+static DEVICE_ATTR(vsync_event, S_IRUGO, vsync_show_event, NULL);
+static struct attribute *vsync_fs_attrs[] = {
+ &dev_attr_vsync_event.attr,
+ NULL,
+};
+static struct attribute_group vsync_fs_attr_group = {
+ .attrs = vsync_fs_attrs,
+};
+
int mdp4_lcdc_on(struct platform_device *pdev)
{
int lcdc_width;
@@ -461,7 +489,6 @@
vctrl->mfd = mfd;
vctrl->dev = mfd->fbi->dev;
- vctrl->fake_vsync = 1;
/* mdp clock on */
mdp_clk_ctrl(1);
@@ -621,6 +648,21 @@
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
mdp_histogram_ctrl_all(TRUE);
+
+ if (!vctrl->sysfs_created) {
+ ret = sysfs_create_group(&vctrl->dev->kobj,
+ &vsync_fs_attr_group);
+ if (ret) {
+ pr_err("%s: sysfs group creation failed, ret=%d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ kobject_uevent(&vctrl->dev->kobj, KOBJ_ADD);
+ pr_debug("%s: kobject_uevent(KOBJ_ADD)\n", __func__);
+ vctrl->sysfs_created = 1;
+ }
+
return ret;
}
@@ -639,9 +681,12 @@
pipe = vctrl->base_pipe;
atomic_set(&vctrl->suspend, 1);
+ atomic_set(&vctrl->vsync_resume, 0);
msleep(20); /* >= 17 ms */
+ complete_all(&vctrl->vsync_comp);
+
if (pipe->ov_blt_addr) {
spin_lock_irqsave(&vctrl->spin_lock, flags);
if (vctrl->ov_koff != vctrl->ov_done)
@@ -683,8 +728,6 @@
}
}
- vctrl->fake_vsync = 1;
-
/* MDP clock disable */
mdp_clk_ctrl(0);
mdp_pipe_ctrl(MDP_OVERLAY0_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
@@ -751,7 +794,6 @@
vctrl = &vsync_ctrl_db[cndx];
pr_debug("%s: cpu=%d\n", __func__, smp_processor_id());
vctrl->vsync_time = ktime_get();
- schedule_work(&vctrl->vsync_work);
spin_lock(&vctrl->spin_lock);
if (vctrl->wait_vsync_cnt) {
@@ -927,13 +969,13 @@
mdp4_overlay_mdp_perf_upd(mfd, 1);
mutex_lock(&mfd->dma->ov_mutex);
- mdp4_lcdc_pipe_commit();
+ mdp4_lcdc_pipe_commit(cndx, 0);
mutex_unlock(&mfd->dma->ov_mutex);
if (pipe->ov_blt_addr)
- mdp4_lcdc_wait4ov(0);
+ mdp4_lcdc_wait4ov(cndx);
else
- mdp4_lcdc_wait4dmap(0);
+ mdp4_lcdc_wait4dmap(cndx);
mdp4_overlay_mdp_perf_upd(mfd, 0);
}
diff --git a/drivers/video/msm/mdp4_util.c b/drivers/video/msm/mdp4_util.c
index 80ef22a..87921e6 100644
--- a/drivers/video/msm/mdp4_util.c
+++ b/drivers/video/msm/mdp4_util.c
@@ -110,21 +110,22 @@
.csc_data = {
(0),
{
- 0x0200, 0x0000, 0x0000,
- 0x0000, 0x0200, 0x0000,
- 0x0000, 0x0000, 0x0200,
+ 0x0083, 0x0102, 0x0032,
+ 0x1fb5, 0x1f6c, 0x00e1,
+ 0x00e1, 0x1f45, 0x1fdc,
},
{
0x0, 0x0, 0x0,
},
{
- 0, 0, 0,
+ 0x0010, 0x0080, 0x0080,
},
{
0, 0xff, 0, 0xff, 0, 0xff,
},
{
- 0, 0xff, 0, 0xff, 0, 0xff,
+ 0x0010, 0x00eb, 0x0010,
+ 0x00f0, 0x0010, 0x00f0,
},
},
},
@@ -133,21 +134,22 @@
.csc_data = {
(0),
{
- 0x0200, 0x0000, 0x0000,
- 0x0000, 0x0200, 0x0000,
- 0x0000, 0x0000, 0x0200,
+ 0x0083, 0x0102, 0x0032,
+ 0x1fb5, 0x1f6c, 0x00e1,
+ 0x00e1, 0x1f45, 0x1fdc,
},
{
0x0, 0x0, 0x0,
},
{
- 0, 0, 0,
+ 0x0010, 0x0080, 0x0080,
},
{
0, 0xff, 0, 0xff, 0, 0xff,
},
{
- 0, 0xff, 0, 0xff, 0, 0xff,
+ 0x0010, 0x00eb, 0x0010,
+ 0x00f0, 0x0010, 0x00f0,
},
},
},
@@ -176,7 +178,6 @@
},
};
-
unsigned is_mdp4_hw_reset(void)
{
unsigned hw_reset = 0;
@@ -2138,7 +2139,7 @@
base = 0x1A000;
break;
case MDP_BLOCK_OVERLAY_2:
- base = (mdp_rev >= MDP_REV_44) ? 0x8A000 : 0x0;
+ base = (mdp_rev >= MDP_REV_43) ? 0x8A000 : 0x0;
break;
case MDP_BLOCK_VG_1:
base = 0x24000;
@@ -2658,7 +2659,7 @@
break;
case MDP_BLOCK_OVERLAY_2:
- valid = (mdp_rev >= MDP_REV_44) ? 1 : 0;
+ valid = (mdp_rev >= MDP_REV_43) ? 1 : 0;
break;
default:
diff --git a/drivers/video/msm/mdp_dma.c b/drivers/video/msm/mdp_dma.c
index 826453b..4d4b05f 100644
--- a/drivers/video/msm/mdp_dma.c
+++ b/drivers/video/msm/mdp_dma.c
@@ -548,6 +548,9 @@
return;
spin_lock_irqsave(&mdp_spin_lock, flag);
+ if (!enable)
+ INIT_COMPLETION(vsync_cntrl.vsync_wait);
+
vsync_cntrl.vsync_irq_enabled = enable;
disabled_clocks = vsync_cntrl.disabled_clocks;
spin_unlock_irqrestore(&mdp_spin_lock, flag);
@@ -568,6 +571,9 @@
vsync_cntrl.disabled_clocks = 0;
}
spin_unlock_irqrestore(&mdp_spin_lock, flag);
+ if (vsync_cntrl.vsync_irq_enabled &&
+ atomic_read(&vsync_cntrl.suspend) == 0)
+ atomic_set(&vsync_cntrl.vsync_resume, 1);
}
void mdp_lcd_update_workqueue_handler(struct work_struct *work)
diff --git a/drivers/video/msm/mdp_dma_dsi_video.c b/drivers/video/msm/mdp_dma_dsi_video.c
index ed224c2..e2fb8ba 100644
--- a/drivers/video/msm/mdp_dma_dsi_video.c
+++ b/drivers/video/msm/mdp_dma_dsi_video.c
@@ -34,6 +34,33 @@
static int first_pixel_start_x;
static int first_pixel_start_y;
+static ssize_t vsync_show_event(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ ssize_t ret = 0;
+
+ INIT_COMPLETION(vsync_cntrl.vsync_wait);
+
+ if (atomic_read(&vsync_cntrl.suspend) > 0 ||
+ atomic_read(&vsync_cntrl.vsync_resume) == 0)
+ return 0;
+
+ wait_for_completion(&vsync_cntrl.vsync_wait);
+ ret = snprintf(buf, PAGE_SIZE, "VSYNC=%llu",
+ ktime_to_ns(vsync_cntrl.vsync_time));
+ buf[strlen(buf) + 1] = '\0';
+ return ret;
+}
+
+static DEVICE_ATTR(vsync_event, S_IRUGO, vsync_show_event, NULL);
+static struct attribute *vsync_fs_attrs[] = {
+ &dev_attr_vsync_event.attr,
+ NULL,
+};
+static struct attribute_group vsync_fs_attr_group = {
+ .attrs = vsync_fs_attrs,
+};
+
int mdp_dsi_video_on(struct platform_device *pdev)
{
int dsi_width;
@@ -88,6 +115,7 @@
var = &fbi->var;
vsync_cntrl.dev = mfd->fbi->dev;
+ atomic_set(&vsync_cntrl.suspend, 0);
bpp = fbi->var.bits_per_pixel / 8;
buf = (uint8 *) fbi->fix.smem_start;
@@ -226,6 +254,20 @@
/* MDP cmd block disable */
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
+ if (!vsync_cntrl.sysfs_created) {
+ ret = sysfs_create_group(&vsync_cntrl.dev->kobj,
+ &vsync_fs_attr_group);
+ if (ret) {
+ pr_err("%s: sysfs creation failed, ret=%d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ kobject_uevent(&vsync_cntrl.dev->kobj, KOBJ_ADD);
+ pr_debug("%s: kobject_uevent(KOBJ_ADD)\n", __func__);
+ vsync_cntrl.sysfs_created = 1;
+ }
+
return ret;
}
@@ -241,6 +283,10 @@
mdp_pipe_ctrl(MDP_DMA2_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
ret = panel_next_off(pdev);
+
+ atomic_set(&vsync_cntrl.suspend, 1);
+ atomic_set(&vsync_cntrl.vsync_resume, 0);
+ complete_all(&vsync_cntrl.vsync_wait);
/* delay to make sure the last frame finishes */
msleep(20);
@@ -255,6 +301,9 @@
return;
spin_lock_irqsave(&mdp_spin_lock, flag);
+ if (!enable)
+ INIT_COMPLETION(vsync_cntrl.vsync_wait);
+
vsync_cntrl.vsync_irq_enabled = enable;
if (!enable)
vsync_cntrl.disabled_clocks = 0;
@@ -270,6 +319,9 @@
mdp_enable_irq(MDP_VSYNC_TERM);
spin_unlock_irqrestore(&mdp_spin_lock, flag);
}
+ if (vsync_cntrl.vsync_irq_enabled &&
+ atomic_read(&vsync_cntrl.suspend) == 0)
+ atomic_set(&vsync_cntrl.vsync_resume, 1);
}
void mdp_dsi_video_update(struct msm_fb_data_type *mfd)
diff --git a/drivers/video/msm/mdp_dma_lcdc.c b/drivers/video/msm/mdp_dma_lcdc.c
index 6146b45..fbfe35f 100644
--- a/drivers/video/msm/mdp_dma_lcdc.c
+++ b/drivers/video/msm/mdp_dma_lcdc.c
@@ -51,6 +51,33 @@
int first_pixel_start_x;
int first_pixel_start_y;
+static ssize_t vsync_show_event(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ ssize_t ret = 0;
+
+ if (atomic_read(&vsync_cntrl.suspend) > 0 ||
+ atomic_read(&vsync_cntrl.vsync_resume) == 0)
+ return 0;
+
+ INIT_COMPLETION(vsync_cntrl.vsync_wait);
+
+ wait_for_completion(&vsync_cntrl.vsync_wait);
+ ret = snprintf(buf, PAGE_SIZE, "VSYNC=%llu",
+ ktime_to_ns(vsync_cntrl.vsync_time));
+ buf[strlen(buf) + 1] = '\0';
+ return ret;
+}
+
+static DEVICE_ATTR(vsync_event, S_IRUGO, vsync_show_event, NULL);
+static struct attribute *vsync_fs_attrs[] = {
+ &dev_attr_vsync_event.attr,
+ NULL,
+};
+static struct attribute_group vsync_fs_attr_group = {
+ .attrs = vsync_fs_attrs,
+};
+
int mdp_lcdc_on(struct platform_device *pdev)
{
int lcdc_width;
@@ -106,6 +133,7 @@
fbi = mfd->fbi;
var = &fbi->var;
vsync_cntrl.dev = mfd->fbi->dev;
+ atomic_set(&vsync_cntrl.suspend, 0);
/* MDP cmd block enable */
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
@@ -292,6 +320,20 @@
/* MDP cmd block disable */
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
+ if (!vsync_cntrl.sysfs_created) {
+ ret = sysfs_create_group(&vsync_cntrl.dev->kobj,
+ &vsync_fs_attr_group);
+ if (ret) {
+ pr_err("%s: sysfs creation failed, ret=%d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ kobject_uevent(&vsync_cntrl.dev->kobj, KOBJ_ADD);
+ pr_debug("%s: kobject_uevent(KOBJ_ADD)\n", __func__);
+ vsync_cntrl.sysfs_created = 1;
+ }
+
return ret;
}
@@ -321,6 +363,9 @@
ret = panel_next_off(pdev);
up(&mfd->dma->mutex);
+ atomic_set(&vsync_cntrl.suspend, 1);
+ atomic_set(&vsync_cntrl.vsync_resume, 0);
+ complete_all(&vsync_cntrl.vsync_wait);
/* delay to make sure the last frame finishes */
msleep(16);
@@ -336,6 +381,9 @@
return;
spin_lock_irqsave(&mdp_spin_lock, flag);
+ if (!enable)
+ INIT_COMPLETION(vsync_cntrl.vsync_wait);
+
vsync_cntrl.vsync_irq_enabled = enable;
if (!enable)
vsync_cntrl.disabled_clocks = 0;
@@ -351,6 +399,10 @@
mdp_enable_irq(MDP_VSYNC_TERM);
spin_unlock_irqrestore(&mdp_spin_lock, flag);
}
+
+ if (vsync_cntrl.vsync_irq_enabled &&
+ atomic_read(&vsync_cntrl.suspend) == 0)
+ atomic_set(&vsync_cntrl.vsync_resume, 1);
}
void mdp_lcdc_update(struct msm_fb_data_type *mfd)
diff --git a/drivers/video/msm/mdss/mdss_dsi.c b/drivers/video/msm/mdss/mdss_dsi.c
index a9f810f..8f4f4d5 100644
--- a/drivers/video/msm/mdss/mdss_dsi.c
+++ b/drivers/video/msm/mdss/mdss_dsi.c
@@ -303,6 +303,7 @@
MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x5C, data);
}
+ mdss_dsi_sw_reset(pdata);
mdss_dsi_host_init(mipi, pdata);
if (mipi->force_clk_lane_hs) {
diff --git a/drivers/video/msm/mdss/mdss_dsi_host.c b/drivers/video/msm/mdss/mdss_dsi_host.c
index 3abf4d0..125644e 100644
--- a/drivers/video/msm/mdss/mdss_dsi_host.c
+++ b/drivers/video/msm/mdss/mdss_dsi_host.c
@@ -813,6 +813,7 @@
void mdss_dsi_sw_reset(struct mdss_panel_data *pdata)
{
struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL;
+ u32 dsi_ctrl;
ctrl_pdata = container_of(pdata, struct mdss_dsi_ctrl_pdata,
panel_data);
@@ -821,6 +822,16 @@
return;
}
+ dsi_ctrl = MIPI_INP((ctrl_pdata->ctrl_base) + 0x0004);
+ dsi_ctrl &= ~0x01;
+ MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x0004, dsi_ctrl);
+ wmb();
+
+ /* turn esc, byte, dsi, pclk, sclk, hclk on */
+ MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x11c,
+ 0x23f); /* DSI_CLK_CTRL */
+ wmb();
+
MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x118, 0x01);
wmb();
MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x118, 0x00);
diff --git a/drivers/video/msm/mdss/mdss_dsi_panel.c b/drivers/video/msm/mdss/mdss_dsi_panel.c
index b247e4d..fd52e1c 100644
--- a/drivers/video/msm/mdss/mdss_dsi_panel.c
+++ b/drivers/video/msm/mdss/mdss_dsi_panel.c
@@ -106,8 +106,6 @@
pr_debug("%s:%d, debug info (mode) : %d\n", __func__, __LINE__,
mipi->mode);
- mdss_dsi_sw_reset(pdata);
-
if (mipi->mode == DSI_VIDEO_MODE) {
mdss_dsi_cmds_tx(pdata, &dsi_panel_tx_buf, dsi_panel_on_cmds,
num_of_on_cmds);
diff --git a/drivers/video/msm/mdss/mdss_fb.c b/drivers/video/msm/mdss/mdss_fb.c
index 7400a7b..efb4da6 100644
--- a/drivers/video/msm/mdss/mdss_fb.c
+++ b/drivers/video/msm/mdss/mdss_fb.c
@@ -946,7 +946,6 @@
struct fb_info *info)
{
struct msm_fb_data_type *mfd = (struct msm_fb_data_type *)info->par;
- u32 len;
if (var->rotate != FB_ROTATE_UR)
return -EINVAL;
@@ -1025,9 +1024,12 @@
if ((var->xres_virtual <= 0) || (var->yres_virtual <= 0))
return -EINVAL;
- len = var->xres_virtual * var->yres_virtual * (var->bits_per_pixel / 8);
- if (len > info->fix.smem_len)
- return -EINVAL;
+ if (info->fix.smem_start) {
+ u32 len = var->xres_virtual * var->yres_virtual *
+ (var->bits_per_pixel / 8);
+ if (len > info->fix.smem_len)
+ return -EINVAL;
+ }
if ((var->xres == 0) || (var->yres == 0))
return -EINVAL;
diff --git a/drivers/video/msm/mdss/mdss_hdmi_edid.c b/drivers/video/msm/mdss/mdss_hdmi_edid.c
index f720a2f..8db38d6 100644
--- a/drivers/video/msm/mdss/mdss_hdmi_edid.c
+++ b/drivers/video/msm/mdss/mdss_hdmi_edid.c
@@ -358,34 +358,25 @@
DEV_DBG("EDID: reading block(%d) with block-size=%d\n",
block, block_size);
for (i = 0; i < 0x80; i += block_size) {
- /*Read EDID twice with 32bit alighnment too */
- if (block < 2) {
- memset(&ddc_data, 0, sizeof(ddc_data));
- ddc_data.dev_addr = 0xA0;
- ddc_data.offset = block*0x80 + i;
- ddc_data.data_buf = edid_buf+i;
- ddc_data.data_len = block_size;
- ddc_data.retry = 1;
- ddc_data.what = "EDID";
- ddc_data.no_align = false;
+ memset(&ddc_data, 0, sizeof(ddc_data));
+ ddc_data.dev_addr = 0xA0;
+ ddc_data.offset = block*0x80 + i;
+ ddc_data.data_buf = edid_buf+i;
+ ddc_data.data_len = block_size;
+ ddc_data.request_len = block_size;
+ ddc_data.retry = 1;
+ ddc_data.what = "EDID";
+ ddc_data.no_align = false;
+ /*Read EDID twice with 32bit alighnment too */
+ if (block < 2)
status = hdmi_ddc_read(
edid_ctrl->init_data.ddc_ctrl,
&ddc_data);
- } else {
- memset(&ddc_data, 0, sizeof(ddc_data));
- ddc_data.dev_addr = 0xA0;
- ddc_data.offset = block*0x80 + i;
- ddc_data.data_buf = edid_buf+i;
- ddc_data.data_len = block_size;
- ddc_data.request_len = block_size;
- ddc_data.retry = 1;
- ddc_data.what = "EDID";
-
+ else
status = hdmi_ddc_read_seg(
edid_ctrl->init_data.ddc_ctrl,
&ddc_data);
- }
if (status)
break;
}
@@ -413,7 +404,7 @@
}
print_len = 0x80;
- for (ndx = 0; ndx < print_len; ndx += 16)
+ for (ndx = 0; ndx < print_len; ndx += 4)
DEV_DBG("EDID[%02x-%02x] %02x %02x %02x %02x\n",
ndx, ndx+3,
b[ndx+0], b[ndx+1], b[ndx+2], b[ndx+3]);
@@ -1392,7 +1383,7 @@
{
struct hdmi_edid_ctrl *edid_ctrl = NULL;
- if (!init_data || !init_data->base ||
+ if (!init_data || !init_data->io ||
!init_data->mutex || !init_data->sysfs_kobj ||
!init_data->ddc_ctrl) {
DEV_ERR("%s: invalid input\n", __func__);
diff --git a/drivers/video/msm/mdss/mdss_hdmi_edid.h b/drivers/video/msm/mdss/mdss_hdmi_edid.h
index d10ae49..5c51e7e 100644
--- a/drivers/video/msm/mdss/mdss_hdmi_edid.h
+++ b/drivers/video/msm/mdss/mdss_hdmi_edid.h
@@ -16,7 +16,7 @@
#include "mdss_hdmi_util.h"
struct hdmi_edid_init_data {
- void __iomem *base;
+ struct dss_io_data *io;
struct mutex *mutex;
struct kobject *sysfs_kobj;
diff --git a/drivers/video/msm/mdss/mdss_hdmi_tx.c b/drivers/video/msm/mdss/mdss_hdmi_tx.c
index 9278029..7f41221 100644
--- a/drivers/video/msm/mdss/mdss_hdmi_tx.c
+++ b/drivers/video/msm/mdss/mdss_hdmi_tx.c
@@ -12,7 +12,6 @@
*/
#include <linux/bitops.h>
-#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/mutex.h>
@@ -20,7 +19,7 @@
#include <linux/of_gpio.h>
#include <linux/types.h>
-/* #define DEBUG */
+#define REG_DUMP 0
#include "mdss_fb.h"
#include "mdss_hdmi_tx.h"
@@ -91,19 +90,19 @@
0x07, 0x07, 0x07, 0x07, 0x02, 0x02, 0x02} /*12*/
};
-static const char *hdmi_tx_clk_name(u32 clk)
+const char *hdmi_tx_pm_name(enum hdmi_tx_power_module_type module)
{
- switch (clk) {
- case HDMI_TX_AHB_CLK: return "hdmi_ahb_clk";
- case HDMI_TX_APP_CLK: return "hdmi_app_clk";
- case HDMI_TX_EXTP_CLK: return "hdmi_extp_clk";
- default: return "???";
+ switch (module) {
+ case HDMI_TX_HPD_PM: return "HDMI_TX_HPD_PM";
+ case HDMI_TX_CORE_PM: return "HDMI_TX_CORE_PM";
+ case HDMI_TX_CEC_PM: return "HDMI_TX_CEC_PM";
+ default: return "???";
}
-} /* hdmi_tx_clk_name */
+} /* hdmi_tx_pm_name */
-static const char *hdmi_tx_io_name(u32 io)
+static const char *hdmi_tx_io_name(u32 type)
{
- switch (io) {
+ switch (type) {
case HDMI_TX_CORE_IO: return "core_physical";
case HDMI_TX_PHY_IO: return "phy_physical";
case HDMI_TX_QFPROM_IO: return "qfprom_physical";
@@ -190,75 +189,6 @@
return ret;
} /* hdmi_tx_sysfs_rda_connected */
-static ssize_t hdmi_tx_sysfs_rda_fake_hpd(struct device *dev,
- struct device_attribute *attr, char *buf)
-{
- ssize_t ret;
- struct hdmi_tx_ctrl *hdmi_ctrl =
- hdmi_tx_get_drvdata_from_sysfs_dev(dev);
-
- if (!hdmi_ctrl) {
- DEV_ERR("%s: invalid input\n", __func__);
- return -EINVAL;
- }
-
- mutex_lock(&hdmi_ctrl->mutex);
- ret = snprintf(buf, PAGE_SIZE, "%d\n", hdmi_ctrl->hpd_state);
- DEV_DBG("%s: '%d'\n", __func__, hdmi_ctrl->hpd_state);
- mutex_unlock(&hdmi_ctrl->mutex);
-
- return ret;
-} /* hdmi_tx_sysfs_rda_fake_hpd */
-
-static ssize_t hdmi_tx_sysfs_wta_fake_hpd(struct device *dev,
- struct device_attribute *attr, const char *buf, size_t count)
-{
- int fake_hpd, rc = 0;
- ssize_t ret = strnlen(buf, PAGE_SIZE);
- struct hdmi_tx_ctrl *hdmi_ctrl = NULL;
-
- DEV_DBG("%s:\n", __func__);
- hdmi_ctrl = hdmi_tx_get_drvdata_from_sysfs_dev(dev);
-
- if (!hdmi_ctrl) {
- DEV_ERR("%s: invalid input\n", __func__);
- return -EINVAL;
- }
-
- rc = kstrtoint(buf, 10, &fake_hpd);
- if (rc) {
- DEV_ERR("%s: kstrtoint failed. rc=%d\n", __func__, rc);
- return rc;
- }
-
- mutex_lock(&hdmi_ctrl->mutex);
- DEV_INFO("%s: fake_hpd=%d\n", __func__, fake_hpd);
- if (fake_hpd) {
- hdmi_ctrl->hpd_state = true;
-
- /* todo: Remove this once HPD line is available in HW */
- DEV_INFO("HDMI HPD: sense CONNECTED: send ONLINE\n");
- if (kobject_uevent(hdmi_ctrl->kobj, KOBJ_ONLINE))
- DEV_ERR("%s: failed sending online event\n", __func__);
- switch_set_state(&hdmi_ctrl->sdev, 1);
- DEV_INFO("%s: Hdmi state switch to %d\n", __func__,
- hdmi_ctrl->sdev.state);
- } else {
- hdmi_ctrl->hpd_state = false;
-
- /* todo: Remove this once HPD line is available in HW */
- DEV_INFO("HDMI HPD: sense CONNECTED: send ONLINE\n");
- if (kobject_uevent(hdmi_ctrl->kobj, KOBJ_OFFLINE))
- DEV_ERR("%s: failed sending online event\n", __func__);
- switch_set_state(&hdmi_ctrl->sdev, 0);
- DEV_INFO("%s: Hdmi state switch to %d\n", __func__,
- hdmi_ctrl->sdev.state);
- }
- mutex_unlock(&hdmi_ctrl->mutex);
-
- return ret;
-} /* hdmi_tx_sysfs_wta_fake_hpd */
-
static ssize_t hdmi_tx_sysfs_rda_hpd(struct device *dev,
struct device_attribute *attr, char *buf)
{
@@ -298,16 +228,13 @@
return rc;
}
- /* todo: Remove this once HPD line is available in HW */
- if (0) {
- if (0 == hpd && hdmi_ctrl->hpd_feature_on) {
- rc = hdmi_tx_sysfs_enable_hpd(hdmi_ctrl, false);
- } else if (1 == hpd && !hdmi_ctrl->hpd_feature_on) {
- rc = hdmi_tx_sysfs_enable_hpd(hdmi_ctrl, true);
- } else {
- rc = -EPERM;
- ret = rc;
- }
+ if (0 == hpd && hdmi_ctrl->hpd_feature_on) {
+ rc = hdmi_tx_sysfs_enable_hpd(hdmi_ctrl, false);
+ } else if (1 == hpd && !hdmi_ctrl->hpd_feature_on) {
+ rc = hdmi_tx_sysfs_enable_hpd(hdmi_ctrl, true);
+ } else {
+ rc = -EPERM;
+ ret = rc;
}
if (!rc) {
@@ -325,13 +252,10 @@
static DEVICE_ATTR(connected, S_IRUGO, hdmi_tx_sysfs_rda_connected, NULL);
static DEVICE_ATTR(hpd, S_IRUGO | S_IWUSR, hdmi_tx_sysfs_rda_hpd,
hdmi_tx_sysfs_wta_hpd);
-static DEVICE_ATTR(fake_hpd, S_IRUGO | S_IWUSR, hdmi_tx_sysfs_rda_fake_hpd,
- hdmi_tx_sysfs_wta_fake_hpd);
static struct attribute *hdmi_tx_fs_attrs[] = {
&dev_attr_connected.attr,
&dev_attr_hpd.attr,
- &dev_attr_fake_hpd.attr,
NULL,
};
static struct attribute_group hdmi_tx_fs_attrs_group = {
@@ -385,7 +309,7 @@
return -EINVAL;
}
- edid_init_data.base = hdmi_ctrl->pdata.io[HDMI_TX_CORE_IO].base;
+ edid_init_data.io = &hdmi_ctrl->pdata.io[HDMI_TX_CORE_IO];
edid_init_data.mutex = &hdmi_ctrl->mutex;
edid_init_data.sysfs_kobj = hdmi_ctrl->kobj;
edid_init_data.ddc_ctrl = &hdmi_ctrl->ddc_ctrl;
@@ -405,14 +329,14 @@
static inline u32 hdmi_tx_is_controller_on(struct hdmi_tx_ctrl *hdmi_ctrl)
{
- return HDMI_REG_R_ND(hdmi_ctrl->pdata.io[HDMI_TX_CORE_IO].base,
- HDMI_CTRL) & BIT(0);
+ struct dss_io_data *io = &hdmi_ctrl->pdata.io[HDMI_TX_CORE_IO];
+ return DSS_REG_R_ND(io, HDMI_CTRL) & BIT(0);
} /* hdmi_tx_is_controller_on */
static inline u32 hdmi_tx_is_dvi_mode(struct hdmi_tx_ctrl *hdmi_ctrl)
{
- return !(HDMI_REG_R_ND(hdmi_ctrl->pdata.io[HDMI_TX_CORE_IO].base,
- HDMI_CTRL) & BIT(1));
+ struct dss_io_data *io = &hdmi_ctrl->pdata.io[HDMI_TX_CORE_IO];
+ return !(DSS_REG_R_ND(io, HDMI_CTRL) & BIT(1));
} /* hdmi_tx_is_dvi_mode */
static int hdmi_tx_init_panel_info(uint32_t resolution,
@@ -473,44 +397,6 @@
hdmi_set_supported_mode(HDMI_VFRMT_1920x1080p60_16_9);
} /* hdmi_tx_setup_video_mode_lut */
-static inline struct clk *hdmi_tx_get_clk(struct hdmi_tx_platform_data *pdata,
- u32 clk_idx)
-{
- if (!pdata || clk_idx > HDMI_TX_MAX_CLK) {
- DEV_ERR("%s: invalid input\n", __func__);
- return NULL;
- }
-
- return pdata->clk[clk_idx];
-} /* hdmi_tx_get_clk */
-
-static int hdmi_tx_clk_set_rate(struct hdmi_tx_platform_data *pdata,
- u32 clk_idx, unsigned long clk_rate)
-{
- int rc = 0;
- struct clk *clk = NULL;
-
- if (!pdata) {
- DEV_ERR("%s: invalid input\n", __func__);
- return -EINVAL;
- }
-
- clk = hdmi_tx_get_clk(pdata, clk_idx);
- if (clk) {
- rc = clk_set_rate(clk, clk_rate);
- if (IS_ERR_VALUE(rc))
- DEV_ERR("%s: failed rc=%d\n", __func__, rc);
- else
- DEV_DBG("%s: name='%s' rate=%lu\n", __func__,
- hdmi_tx_clk_name(clk_idx), clk_rate);
- } else {
- DEV_ERR("%s: FAILED: invalid clk_idx=%d\n", __func__, clk_idx);
- rc = -EINVAL;
- }
-
- return rc;
-} /* hdmi_tx_clk_set_rate */
-
static int hdmi_tx_read_sink_info(struct hdmi_tx_ctrl *hdmi_ctrl)
{
int status;
@@ -551,9 +437,14 @@
}
io = &hdmi_ctrl->pdata.io[HDMI_TX_CORE_IO];
+ if (!io->base) {
+ DEV_ERR("%s: Core io is not initialized\n", __func__);
+ return;
+ }
+
DEV_DBG("%s: Got HPD interrupt\n", __func__);
- hpd_state = (HDMI_REG_R(io->base, HDMI_HPD_INT_STATUS) & BIT(1)) >> 1;
+ hpd_state = (DSS_REG_R(io, HDMI_HPD_INT_STATUS) & BIT(1)) >> 1;
mutex_lock(&hdmi_ctrl->mutex);
if ((hdmi_ctrl->hpd_prev_state != hdmi_ctrl->hpd_state) ||
(hdmi_ctrl->hpd_state != hpd_state)) {
@@ -605,22 +496,62 @@
}
/* Set IRQ for HPD */
- HDMI_REG_W(io->base, HDMI_HPD_INT_CTRL, 4 | (hpd_state ? 0 : 2));
+ DSS_REG_W(io, HDMI_HPD_INT_CTRL, 4 | (hpd_state ? 0 : 2));
} /* hdmi_tx_hpd_state_work */
-static int hdmi_tx_check_capability(void __iomem *base)
+static void hdmi_tx_hpd_int_work(struct work_struct *work)
+{
+ u32 hpd_int_status;
+ u32 hpd_int_ctrl;
+ u32 cable_detected;
+ struct hdmi_tx_ctrl *hdmi_ctrl = NULL;
+ struct dss_io_data *io = NULL;
+
+ hdmi_ctrl = container_of(work, struct hdmi_tx_ctrl, hpd_int_work);
+ if (!hdmi_ctrl || !hdmi_ctrl->hpd_initialized) {
+ DEV_DBG("%s: invalid input\n", __func__);
+ return;
+ }
+
+ io = &hdmi_ctrl->pdata.io[HDMI_TX_CORE_IO];
+ if (!io->base) {
+ DEV_ERR("%s: Core io is not initialized\n", __func__);
+ return;
+ }
+
+ /* Process HPD Interrupt */
+ hpd_int_status = DSS_REG_R(io, HDMI_HPD_INT_STATUS);
+ hpd_int_ctrl = DSS_REG_R(io, HDMI_HPD_INT_CTRL);
+
+ DSS_REG_W(io, HDMI_HPD_INT_CTRL, BIT(2));
+
+ cable_detected = hpd_int_status & BIT(1);
+ mutex_lock(&hdmi_ctrl->mutex);
+ hdmi_ctrl->hpd_cable_chg_detected = true;
+ hdmi_ctrl->hpd_prev_state = cable_detected ? 0 : 1;
+ hdmi_ctrl->hpd_stable = 0;
+ mutex_unlock(&hdmi_ctrl->mutex);
+
+ mod_timer(&hdmi_ctrl->hpd_state_timer, jiffies + HZ/2);
+
+ DEV_DBG("%s: HPD<Ctrl=%04x, State=%04x>\n", __func__, hpd_int_ctrl,
+ hpd_int_status);
+} /* hdmi_tx_hpd_int_work */
+
+static int hdmi_tx_check_capability(struct dss_io_data *io)
{
u32 hdmi_disabled, hdcp_disabled;
- if (!base) {
+ if (!io) {
DEV_ERR("%s: invalid input\n", __func__);
return -EINVAL;
}
- /* QFPROM_RAW_FEAT_CONFIG_ROW0_LSB */
- hdcp_disabled = HDMI_REG_R_ND(base, 0x000000F8) & BIT(31);
- /* QFPROM_RAW_FEAT_CONFIG_ROW0_MSB */
- hdmi_disabled = HDMI_REG_R_ND(base, 0x000000FC) & BIT(0);
+ hdcp_disabled = DSS_REG_R_ND(io,
+ QFPROM_RAW_FEAT_CONFIG_ROW0_LSB) & BIT(31);
+
+ hdmi_disabled = DSS_REG_R_ND(io,
+ QFPROM_RAW_FEAT_CONFIG_ROW0_MSB) & BIT(0);
DEV_DBG("%s: Features <HDMI:%s, HDCP:%s>\n", __func__,
hdmi_disabled ? "OFF" : "ON", hdcp_disabled ? "OFF" : "ON");
@@ -710,25 +641,9 @@
goto end;
}
- /*
- * extpclk is driven by hdmi phy pll. This phy pll programming requires
- * hdmi_ahb_clk. So enable it and then disable.
- */
- rc = clk_prepare_enable(pdata->clk[HDMI_TX_AHB_CLK]);
- if (rc) {
- DEV_ERR("%s: failed to enable '%s' clk\n", __func__,
- hdmi_tx_clk_name(HDMI_TX_AHB_CLK));
- goto end;
- }
- rc = hdmi_tx_clk_set_rate(pdata, HDMI_TX_EXTP_CLK,
- timing->pixel_freq * 1000);
- if (rc) {
- DEV_ERR("%s: FAILED: '%s' clk set rate\n", __func__,
- hdmi_tx_clk_name(HDMI_TX_EXTP_CLK));
- clk_disable_unprepare(pdata->clk[HDMI_TX_AHB_CLK]);
- goto end;
- }
- clk_disable_unprepare(pdata->clk[HDMI_TX_AHB_CLK]);
+ /* todo: find a better way */
+ hdmi_ctrl->pdata.power_data[HDMI_TX_CORE_PM].clk_config[0].rate =
+ timing->pixel_freq * 1000;
hdmi_ctrl->video_resolution = format;
hdmi_edid_set_video_resolution(
@@ -772,35 +687,35 @@
timing->back_porch_h + timing->pulse_width_h - 1;
total_v = timing->active_v + timing->front_porch_v +
timing->back_porch_v + timing->pulse_width_v - 1;
- HDMI_REG_W(io->base, HDMI_TOTAL,
+ DSS_REG_W(io, HDMI_TOTAL,
((total_v << 16) & 0x0FFF0000) |
((total_h << 0) & 0x00000FFF));
start_h = timing->back_porch_h + timing->pulse_width_h;
end_h = (total_h + 1) - timing->front_porch_h;
- HDMI_REG_W(io->base, HDMI_ACTIVE_H,
+ DSS_REG_W(io, HDMI_ACTIVE_H,
((end_h << 16) & 0x0FFF0000) |
((start_h << 0) & 0x00000FFF));
start_v = timing->back_porch_v + timing->pulse_width_v - 1;
end_v = total_v - timing->front_porch_v;
- HDMI_REG_W(io->base, HDMI_ACTIVE_V,
+ DSS_REG_W(io, HDMI_ACTIVE_V,
((end_v << 16) & 0x0FFF0000) |
((start_v << 0) & 0x00000FFF));
if (timing->interlaced) {
- HDMI_REG_W(io->base, HDMI_V_TOTAL_F2,
+ DSS_REG_W(io, HDMI_V_TOTAL_F2,
((total_v + 1) << 0) & 0x00000FFF);
- HDMI_REG_W(io->base, HDMI_ACTIVE_V_F2,
+ DSS_REG_W(io, HDMI_ACTIVE_V_F2,
(((start_v + 1) << 0) & 0x00000FFF) |
(((end_v + 1) << 16) & 0x0FFF0000));
} else {
- HDMI_REG_W(io->base, HDMI_V_TOTAL_F2, 0);
- HDMI_REG_W(io->base, HDMI_ACTIVE_V_F2, 0);
+ DSS_REG_W(io, HDMI_V_TOTAL_F2, 0);
+ DSS_REG_W(io, HDMI_ACTIVE_V_F2, 0);
}
- HDMI_REG_W(io->base, HDMI_FRAME_CTRL,
+ DSS_REG_W(io, HDMI_FRAME_CTRL,
((timing->interlaced << 31) & 0x80000000) |
((timing->active_low_h << 29) & 0x20000000) |
((timing->active_low_v << 28) & 0x10000000));
@@ -929,28 +844,28 @@
regVal = regVal << 8 | avi_iframe[4];
regVal = regVal << 8 | avi_iframe[3];
regVal = regVal << 8 | checksum;
- HDMI_REG_W(io->base, HDMI_AVI_INFO0, regVal);
+ DSS_REG_W(io, HDMI_AVI_INFO0, regVal);
regVal = avi_iframe[9];
regVal = regVal << 8 | avi_iframe[8];
regVal = regVal << 8 | avi_iframe[7];
regVal = regVal << 8 | avi_iframe[6];
- HDMI_REG_W(io->base, HDMI_AVI_INFO1, regVal);
+ DSS_REG_W(io, HDMI_AVI_INFO1, regVal);
regVal = avi_iframe[13];
regVal = regVal << 8 | avi_iframe[12];
regVal = regVal << 8 | avi_iframe[11];
regVal = regVal << 8 | avi_iframe[10];
- HDMI_REG_W(io->base, HDMI_AVI_INFO2, regVal);
+ DSS_REG_W(io, HDMI_AVI_INFO2, regVal);
regVal = avi_iframe[1];
regVal = regVal << 16 | avi_iframe[15];
regVal = regVal << 8 | avi_iframe[14];
- HDMI_REG_W(io->base, HDMI_AVI_INFO3, regVal);
+ DSS_REG_W(io, HDMI_AVI_INFO3, regVal);
/* 0x3 for AVI InfFrame enable (every frame) */
- HDMI_REG_W(io->base, HDMI_INFOFRAME_CTRL0,
- HDMI_REG_R(io->base, HDMI_INFOFRAME_CTRL0) |
+ DSS_REG_W(io, HDMI_INFOFRAME_CTRL0,
+ DSS_REG_R(io, HDMI_INFOFRAME_CTRL0) |
0x00000003L);
} /* hdmi_tx_set_avi_infoframe */
@@ -986,14 +901,14 @@
* 0x19 Length of Source Product Description InfoFrame
*/
packet_header = 0x83 | (0x01 << 8) | (0x19 << 16);
- HDMI_REG_W(io->base, HDMI_GENERIC1_HDR, packet_header);
+ DSS_REG_W(io, HDMI_GENERIC1_HDR, packet_header);
check_sum += IFRAME_CHECKSUM_32(packet_header);
packet_payload = (vendor_name[3] & 0x7f)
| ((vendor_name[4] & 0x7f) << 8)
| ((vendor_name[5] & 0x7f) << 16)
| ((vendor_name[6] & 0x7f) << 24);
- HDMI_REG_W(io->base, HDMI_GENERIC1_1, packet_payload);
+ DSS_REG_W(io, HDMI_GENERIC1_1, packet_payload);
check_sum += IFRAME_CHECKSUM_32(packet_payload);
/* Product Description (7-bit ASCII code) */
@@ -1001,28 +916,28 @@
| ((product_description[0] & 0x7f) << 8)
| ((product_description[1] & 0x7f) << 16)
| ((product_description[2] & 0x7f) << 24);
- HDMI_REG_W(io->base, HDMI_GENERIC1_2, packet_payload);
+ DSS_REG_W(io, HDMI_GENERIC1_2, packet_payload);
check_sum += IFRAME_CHECKSUM_32(packet_payload);
packet_payload = (product_description[3] & 0x7f)
| ((product_description[4] & 0x7f) << 8)
| ((product_description[5] & 0x7f) << 16)
| ((product_description[6] & 0x7f) << 24);
- HDMI_REG_W(io->base, HDMI_GENERIC1_3, packet_payload);
+ DSS_REG_W(io, HDMI_GENERIC1_3, packet_payload);
check_sum += IFRAME_CHECKSUM_32(packet_payload);
packet_payload = (product_description[7] & 0x7f)
| ((product_description[8] & 0x7f) << 8)
| ((product_description[9] & 0x7f) << 16)
| ((product_description[10] & 0x7f) << 24);
- HDMI_REG_W(io->base, HDMI_GENERIC1_4, packet_payload);
+ DSS_REG_W(io, HDMI_GENERIC1_4, packet_payload);
check_sum += IFRAME_CHECKSUM_32(packet_payload);
packet_payload = (product_description[11] & 0x7f)
| ((product_description[12] & 0x7f) << 8)
| ((product_description[13] & 0x7f) << 16)
| ((product_description[14] & 0x7f) << 24);
- HDMI_REG_W(io->base, HDMI_GENERIC1_5, packet_payload);
+ DSS_REG_W(io, HDMI_GENERIC1_5, packet_payload);
check_sum += IFRAME_CHECKSUM_32(packet_payload);
/*
@@ -1039,7 +954,7 @@
* 09h PC general
*/
packet_payload = (product_description[15] & 0x7f) | 0x00 << 8;
- HDMI_REG_W(io->base, HDMI_GENERIC1_6, packet_payload);
+ DSS_REG_W(io, HDMI_GENERIC1_6, packet_payload);
check_sum += IFRAME_CHECKSUM_32(packet_payload);
/* Vendor Name (7bit ASCII code) */
@@ -1048,7 +963,7 @@
| ((vendor_name[2] & 0x7f) << 24);
check_sum += IFRAME_CHECKSUM_32(packet_payload);
packet_payload |= ((0x100 - (0xff & check_sum)) & 0xff);
- HDMI_REG_W(io->base, HDMI_GENERIC1_0, packet_payload);
+ DSS_REG_W(io, HDMI_GENERIC1_0, packet_payload);
/*
* GENERIC1_LINE | GENERIC1_CONT | GENERIC1_SEND
@@ -1056,9 +971,9 @@
* Enable this packet to transmit every frame
* Enable HDMI TX engine to transmit Generic packet 1
*/
- packet_control = HDMI_REG_R_ND(io->base, HDMI_GEN_PKT_CTRL);
+ packet_control = DSS_REG_R_ND(io, HDMI_GEN_PKT_CTRL);
packet_control |= ((0x1 << 24) | (1 << 5) | (1 << 4));
- HDMI_REG_W(io->base, HDMI_GEN_PKT_CTRL, packet_control);
+ DSS_REG_W(io, HDMI_GEN_PKT_CTRL, packet_control);
} /* hdmi_tx_set_spd_infoframe */
/* todo: revisit when new HPD debouncing logic is avialble */
@@ -1075,11 +990,17 @@
static void hdmi_tx_set_mode(struct hdmi_tx_ctrl *hdmi_ctrl, u32 power_on)
{
u32 reg_val = 0;
+ struct dss_io_data *io = NULL;
if (!hdmi_ctrl) {
DEV_ERR("%s: invalid input\n", __func__);
return;
}
+ io = &hdmi_ctrl->pdata.io[HDMI_TX_CORE_IO];
+ if (!io->base) {
+ DEV_ERR("%s: Core io is not initialized\n", __func__);
+ return;
+ }
if (power_on) {
/* ENABLE */
@@ -1101,77 +1022,12 @@
reg_val = BIT(1);
}
- HDMI_REG_W(hdmi_ctrl->pdata.io[HDMI_TX_CORE_IO].base, HDMI_CTRL,
- reg_val);
+ DSS_REG_W(io, HDMI_CTRL, reg_val);
DEV_DBG("HDMI Core: %s, HDMI_CTRL=0x%08x\n",
power_on ? "Enable" : "Disable", reg_val);
} /* hdmi_tx_set_mode */
-static int hdmi_tx_clk_update(struct hdmi_tx_platform_data *pdata, u32 clk_idx,
- u32 enable)
-{
- int rc = 0;
- struct clk *clk = hdmi_tx_get_clk(pdata, clk_idx);
-
- if (clk) {
- DEV_DBG("%s: clk=%d en=%d\n", __func__, clk_idx, enable);
- if (enable) {
- rc = clk_prepare_enable(clk);
- if (rc)
- DEV_ERR("%s: clk=%d enable failed\n",
- __func__, clk_idx);
- } else {
- clk_disable_unprepare(clk);
- }
- } else {
- DEV_ERR("%s: FAILED: invalid input for clk='%s'\n", __func__,
- hdmi_tx_clk_name(clk_idx));
- rc = -EINVAL;
- }
-
- return rc;
-} /* hdmi_tx_clk_update */
-
-/* Note: Before accessing extpclk, always make sure that hdmi_ahb_clk is on */
-static int hdmi_tx_clk_ctrl_update(struct hdmi_tx_platform_data *pdata, int on)
-{
- int rc = 0;
- DEV_DBG("%s: HDMI Clk: %s\n", __func__, on ? "Enable" : "Disable");
-
- rc = hdmi_tx_clk_update(pdata, HDMI_TX_APP_CLK, on);
- if (on && rc) {
- DEV_ERR("%s: '%s' on failed\n", __func__,
- hdmi_tx_clk_name(HDMI_TX_APP_CLK));
- goto fail_hdmi_app_clk;
- }
- if (on) {
- rc = hdmi_tx_clk_update(pdata, HDMI_TX_AHB_CLK, on);
- if (rc) {
- DEV_ERR("%s: '%s' on failed\n", __func__,
- hdmi_tx_clk_name(HDMI_TX_AHB_CLK));
- goto fail_hdmi_ahb_clk;
- }
- rc = hdmi_tx_clk_update(pdata, HDMI_TX_EXTP_CLK, on);
- if (rc) {
- DEV_ERR("%s: '%s' on failed\n", __func__,
- hdmi_tx_clk_name(HDMI_TX_EXTP_CLK));
- goto fail_hdmi_extp_clk;
- }
- } else {
- hdmi_tx_clk_update(pdata, HDMI_TX_EXTP_CLK, on);
- hdmi_tx_clk_update(pdata, HDMI_TX_AHB_CLK, on);
- }
- return rc;
-
-fail_hdmi_extp_clk:
- hdmi_tx_clk_update(pdata, HDMI_TX_AHB_CLK, 0);
-fail_hdmi_ahb_clk:
- hdmi_tx_clk_update(pdata, HDMI_TX_APP_CLK, 0);
-fail_hdmi_app_clk:
- return rc;
-} /* hdmi_tx_clk_ctrl_update */
-
static int hdmi_tx_config_power(struct hdmi_tx_ctrl *hdmi_ctrl,
enum hdmi_tx_power_module_type module, int config)
{
@@ -1191,17 +1047,33 @@
goto exit;
}
- if (config)
+ if (config) {
rc = msm_dss_config_vreg(&hdmi_ctrl->pdev->dev,
power_data->vreg_config, power_data->num_vreg, 1);
- else
+ if (rc) {
+ DEV_ERR("%s: Failed to config %s vreg. Err=%d\n",
+ __func__, hdmi_tx_pm_name(module), rc);
+ goto exit;
+ }
+
+ rc = msm_dss_get_clk(&hdmi_ctrl->pdev->dev,
+ power_data->clk_config, power_data->num_clk);
+ if (rc) {
+ DEV_ERR("%s: Failed to get %s clk. Err=%d\n",
+ __func__, hdmi_tx_pm_name(module), rc);
+
+ msm_dss_config_vreg(&hdmi_ctrl->pdev->dev,
+ power_data->vreg_config, power_data->num_vreg, 0);
+ }
+ } else {
+ msm_dss_put_clk(power_data->clk_config, power_data->num_clk);
+
rc = msm_dss_config_vreg(&hdmi_ctrl->pdev->dev,
power_data->vreg_config, power_data->num_vreg, 0);
-
- if (rc)
- DEV_ERR("%s: Failed to %s %s vreg. Error=%d\n",
- __func__, config ? "config" : "deconfig",
- hdmi_pm_name(module), rc);
+ if (rc)
+ DEV_ERR("%s: Fail to deconfig %s vreg. Err=%d\n",
+ __func__, hdmi_tx_pm_name(module), rc);
+ }
exit:
return rc;
@@ -1231,18 +1103,36 @@
power_data->num_vreg, 1);
if (rc) {
DEV_ERR("%s: Failed to enable %s vreg. Error=%d\n",
- __func__, hdmi_pm_name(module), rc);
+ __func__, hdmi_tx_pm_name(module), rc);
goto error;
}
rc = msm_dss_enable_gpio(power_data->gpio_config,
- power_data->num_gpio, enable);
+ power_data->num_gpio, 1);
if (rc) {
DEV_ERR("%s: Failed to enable %s gpio. Error=%d\n",
- __func__, hdmi_pm_name(module), rc);
+ __func__, hdmi_tx_pm_name(module), rc);
goto disable_vreg;
}
+
+ rc = msm_dss_clk_set_rate(power_data->clk_config,
+ power_data->num_clk);
+ if (rc) {
+ DEV_ERR("%s: failed to set clks rate for %s. err=%d\n",
+ __func__, hdmi_tx_pm_name(module), rc);
+ goto disable_gpio;
+ }
+
+ rc = msm_dss_enable_clk(power_data->clk_config,
+ power_data->num_clk, 1);
+ if (rc) {
+ DEV_ERR("%s: Failed to enable clks for %s. Error=%d\n",
+ __func__, hdmi_tx_pm_name(module), rc);
+ goto disable_gpio;
+ }
} else {
+ msm_dss_enable_clk(power_data->clk_config,
+ power_data->num_clk, 0);
msm_dss_enable_gpio(power_data->gpio_config,
power_data->num_gpio, 0);
msm_dss_enable_vreg(power_data->vreg_config,
@@ -1251,6 +1141,8 @@
return rc;
+disable_gpio:
+ msm_dss_enable_gpio(power_data->gpio_config, power_data->num_gpio, 0);
disable_vreg:
msm_dss_enable_vreg(power_data->vreg_config, power_data->num_vreg, 0);
error:
@@ -1281,7 +1173,7 @@
if (rc) {
DEV_ERR("%s: core hdmi_msm_enable_power failed rc = %d\n",
__func__, rc);
- goto error;
+ goto disable_hpd_power;
}
rc = hdmi_tx_enable_power(hdmi_ctrl, HDMI_TX_CEC_PM, 1);
if (rc) {
@@ -1293,7 +1185,8 @@
return rc;
disable_core_power:
hdmi_tx_enable_power(hdmi_ctrl, HDMI_TX_CORE_PM, 0);
-error:
+disable_hpd_power:
+ hdmi_tx_enable_power(hdmi_ctrl, HDMI_TX_HPD_PM, 0);
return rc;
} /* hdmi_tx_core_on */
@@ -1311,36 +1204,34 @@
io = &hdmi_ctrl->pdata.io[HDMI_TX_CORE_IO];
if (!io->base) {
- DEV_ERR("%s: io not inititalized\n", __func__);
+ DEV_ERR("%s: core io not inititalized\n", __func__);
return;
}
- val = HDMI_REG_R_ND(io->base, HDMI_PHY_CTRL);
+ val = DSS_REG_R_ND(io, HDMI_PHY_CTRL);
phy_reset_polarity = val >> 3 & 0x1;
pll_reset_polarity = val >> 1 & 0x1;
if (phy_reset_polarity == 0)
- HDMI_REG_W_ND(io->base, HDMI_PHY_CTRL, val | SW_RESET);
+ DSS_REG_W_ND(io, HDMI_PHY_CTRL, val | SW_RESET);
else
- HDMI_REG_W_ND(io->base, HDMI_PHY_CTRL, val & (~SW_RESET));
+ DSS_REG_W_ND(io, HDMI_PHY_CTRL, val & (~SW_RESET));
if (pll_reset_polarity == 0)
- HDMI_REG_W_ND(io->base, HDMI_PHY_CTRL, val | SW_RESET_PLL);
+ DSS_REG_W_ND(io, HDMI_PHY_CTRL, val | SW_RESET_PLL);
else
- HDMI_REG_W_ND(io->base,
- HDMI_PHY_CTRL, val & (~SW_RESET_PLL));
+ DSS_REG_W_ND(io, HDMI_PHY_CTRL, val & (~SW_RESET_PLL));
if (phy_reset_polarity == 0)
- HDMI_REG_W_ND(io->base, HDMI_PHY_CTRL, val & (~SW_RESET));
+ DSS_REG_W_ND(io, HDMI_PHY_CTRL, val & (~SW_RESET));
else
- HDMI_REG_W_ND(io->base, HDMI_PHY_CTRL, val | SW_RESET);
+ DSS_REG_W_ND(io, HDMI_PHY_CTRL, val | SW_RESET);
if (pll_reset_polarity == 0)
- HDMI_REG_W_ND(io->base,
- HDMI_PHY_CTRL, val & (~SW_RESET_PLL));
+ DSS_REG_W_ND(io, HDMI_PHY_CTRL, val & (~SW_RESET_PLL));
else
- HDMI_REG_W_ND(io->base, HDMI_PHY_CTRL, val | SW_RESET_PLL);
+ DSS_REG_W_ND(io, HDMI_PHY_CTRL, val | SW_RESET_PLL);
} /* hdmi_tx_phy_reset */
static void hdmi_tx_init_phy(struct hdmi_tx_ctrl *hdmi_ctrl)
@@ -1354,55 +1245,58 @@
io = &hdmi_ctrl->pdata.io[HDMI_TX_PHY_IO];
if (!io->base) {
- DEV_ERR("%s: Core io is not initialized\n", __func__);
+ DEV_ERR("%s: phy io is not initialized\n", __func__);
return;
}
- HDMI_REG_W_ND(io->base, HDMI_PHY_ANA_CFG0, 0x1B);
- HDMI_REG_W_ND(io->base, HDMI_PHY_ANA_CFG1, 0xF2);
- HDMI_REG_W_ND(io->base, HDMI_PHY_BIST_CFG0, 0x0);
- HDMI_REG_W_ND(io->base, HDMI_PHY_BIST_PATN0, 0x0);
- HDMI_REG_W_ND(io->base, HDMI_PHY_BIST_PATN1, 0x0);
- HDMI_REG_W_ND(io->base, HDMI_PHY_BIST_PATN2, 0x0);
- HDMI_REG_W_ND(io->base, HDMI_PHY_BIST_PATN3, 0x0);
+ DSS_REG_W_ND(io, HDMI_PHY_ANA_CFG0, 0x1B);
+ DSS_REG_W_ND(io, HDMI_PHY_ANA_CFG1, 0xF2);
+ DSS_REG_W_ND(io, HDMI_PHY_BIST_CFG0, 0x0);
+ DSS_REG_W_ND(io, HDMI_PHY_BIST_PATN0, 0x0);
+ DSS_REG_W_ND(io, HDMI_PHY_BIST_PATN1, 0x0);
+ DSS_REG_W_ND(io, HDMI_PHY_BIST_PATN2, 0x0);
+ DSS_REG_W_ND(io, HDMI_PHY_BIST_PATN3, 0x0);
- HDMI_REG_W_ND(io->base, HDMI_PHY_PD_CTRL1, 0x20);
+ DSS_REG_W_ND(io, HDMI_PHY_PD_CTRL1, 0x20);
} /* hdmi_tx_init_phy */
static void hdmi_tx_powerdown_phy(struct hdmi_tx_ctrl *hdmi_ctrl)
{
+ struct dss_io_data *io = NULL;
+
if (!hdmi_ctrl) {
DEV_ERR("%s: invalid input\n", __func__);
return;
}
+ io = &hdmi_ctrl->pdata.io[HDMI_TX_PHY_IO];
+ if (!io->base) {
+ DEV_ERR("%s: phy io is not initialized\n", __func__);
+ return;
+ }
- HDMI_REG_W_ND(hdmi_ctrl->pdata.io[HDMI_TX_PHY_IO].base,
- HDMI_PHY_PD_CTRL0, 0x7F);
+ DSS_REG_W_ND(io, HDMI_PHY_PD_CTRL0, 0x7F);
} /* hdmi_tx_powerdown_phy */
static int hdmi_tx_start(struct hdmi_tx_ctrl *hdmi_ctrl)
{
int rc = 0;
+ struct dss_io_data *io = NULL;
if (!hdmi_ctrl) {
DEV_ERR("%s: invalid input\n", __func__);
return -EINVAL;
}
+ io = &hdmi_ctrl->pdata.io[HDMI_TX_CORE_IO];
+ if (!io->base) {
+ DEV_ERR("%s: core io is not initialized\n", __func__);
+ return -EINVAL;
+ }
+
/* todo: Audio */
hdmi_tx_set_mode(hdmi_ctrl, false);
- mutex_lock(&hdmi_ctrl->mutex);
- rc = hdmi_tx_clk_ctrl_update(&hdmi_ctrl->pdata, 1);
- if (rc) {
- DEV_ERR("%s: hdmi_tx_clk_enable failed.\n", __func__);
- mutex_unlock(&hdmi_ctrl->mutex);
- return rc;
- }
- mutex_unlock(&hdmi_ctrl->mutex);
-
hdmi_tx_init_phy(hdmi_ctrl);
- HDMI_REG_W(hdmi_ctrl->pdata.io[HDMI_TX_CORE_IO].base,
- HDMI_USEC_REFTIMER, 0x0001001B);
+ DSS_REG_W(io, HDMI_USEC_REFTIMER, 0x0001001B);
hdmi_tx_set_mode(hdmi_ctrl, true);
@@ -1413,8 +1307,7 @@
hdmi_tx_set_spd_infoframe(hdmi_ctrl);
/* Set IRQ for HPD */
- HDMI_REG_W(hdmi_ctrl->pdata.io[HDMI_TX_CORE_IO].base,
- HDMI_HPD_INT_CTRL, 4 | (hdmi_ctrl->hpd_state ? 0 : 2));
+ DSS_REG_W(io, HDMI_HPD_INT_CTRL, 4 | (hdmi_ctrl->hpd_state ? 0 : 2));
/* todo: HDCP/CEC */
@@ -1437,12 +1330,6 @@
/* todo: Audio */
hdmi_tx_powerdown_phy(hdmi_ctrl);
hdmi_ctrl->panel_power_on = false;
-
- mutex_lock(&hdmi_ctrl->mutex);
- if (hdmi_tx_clk_ctrl_update(&hdmi_ctrl->pdata, 0))
- DEV_ERR("%s: hdmi_tx_clk_disable failed.\n", __func__);
- mutex_unlock(&hdmi_ctrl->mutex);
-
hdmi_tx_core_off(hdmi_ctrl);
return 0;
@@ -1451,6 +1338,7 @@
static int hdmi_tx_power_on(struct mdss_panel_data *panel_data)
{
int rc = 0;
+ struct dss_io_data *io = NULL;
struct hdmi_tx_ctrl *hdmi_ctrl =
hdmi_tx_get_drvdata_from_panel_data(panel_data);
@@ -1458,11 +1346,10 @@
DEV_ERR("%s: invalid input\n", __func__);
return -EINVAL;
}
-
- rc = hdmi_tx_core_on(hdmi_ctrl);
- if (rc) {
- DEV_ERR("%s: hdmi_msm_core_on failed\n", __func__);
- return rc;
+ io = &hdmi_ctrl->pdata.io[HDMI_TX_CORE_IO];
+ if (!io->base) {
+ DEV_ERR("%s: core io is not initialized\n", __func__);
+ return -EINVAL;
}
DEV_INFO("power: ON (%dx%d %ld)\n", hdmi_ctrl->xres, hdmi_ctrl->yres,
@@ -1471,7 +1358,12 @@
rc = hdmi_tx_set_video_fmt(hdmi_ctrl);
if (rc) {
DEV_ERR("%s: cannot set video_fmt.rc=%d\n", __func__, rc);
- hdmi_tx_core_off(hdmi_ctrl);
+ return rc;
+ }
+
+ rc = hdmi_tx_core_on(hdmi_ctrl);
+ if (rc) {
+ DEV_ERR("%s: hdmi_msm_core_on failed\n", __func__);
return rc;
}
@@ -1494,8 +1386,7 @@
mutex_unlock(&hdmi_ctrl->mutex);
}
- hdmi_reg_dump(hdmi_ctrl->pdata.io[HDMI_TX_CORE_IO].base,
- hdmi_ctrl->pdata.io[HDMI_TX_CORE_IO].len, "HDMI-ON: ");
+ dss_reg_dump(io->base, io->len, "HDMI-ON: ", REG_DUMP);
DEV_INFO("%s: HDMI=%s DVI= %s\n", __func__,
hdmi_tx_is_controller_on(hdmi_ctrl) ? "ON" : "OFF" ,
@@ -1524,13 +1415,6 @@
hdmi_tx_set_mode(hdmi_ctrl, false);
- mutex_lock(&hdmi_ctrl->mutex);
- rc = hdmi_tx_clk_ctrl_update(&hdmi_ctrl->pdata, 0);
- if (rc)
- DEV_INFO("%s: Failed to disable clock. Error=%d\n",
- __func__, rc);
- mutex_unlock(&hdmi_ctrl->mutex);
-
rc = hdmi_tx_enable_power(hdmi_ctrl, HDMI_TX_HPD_PM, 0);
if (rc)
DEV_INFO("%s: Failed to disable hpd power. Error=%d\n",
@@ -1552,7 +1436,7 @@
io = &hdmi_ctrl->pdata.io[HDMI_TX_CORE_IO];
if (!io->base) {
- DEV_ERR("%s: io not inititalized\n", __func__);
+ DEV_ERR("%s: core io not inititalized\n", __func__);
return -EINVAL;
}
@@ -1566,31 +1450,21 @@
return rc;
}
- mutex_lock(&hdmi_ctrl->mutex);
- rc = hdmi_tx_clk_ctrl_update(&hdmi_ctrl->pdata, true);
- if (rc) {
- DEV_ERR("%s: Failed to enable clocks. rc=%d\n",
- __func__, rc);
- mutex_unlock(&hdmi_ctrl->mutex);
- goto disable_hpd_power;
- }
- mutex_unlock(&hdmi_ctrl->mutex);
-
- hdmi_reg_dump(io->base, io->len, "HDMI-INIT: ");
+ dss_reg_dump(io->base, io->len, "HDMI-INIT: ", REG_DUMP);
hdmi_tx_set_mode(hdmi_ctrl, false);
hdmi_tx_phy_reset(hdmi_ctrl);
hdmi_tx_set_mode(hdmi_ctrl, true);
- HDMI_REG_W(io->base, HDMI_USEC_REFTIMER, 0x0001001B);
+ DSS_REG_W(io, HDMI_USEC_REFTIMER, 0x0001001B);
/* set timeout to 4.1ms (max) for hardware debounce */
- reg_val = HDMI_REG_R(io->base, HDMI_HPD_CTRL) | 0x1FFF;
+ reg_val = DSS_REG_R(io, HDMI_HPD_CTRL) | 0x1FFF;
/* Toggle HPD circuit to trigger HPD sense */
- HDMI_REG_W(io->base, HDMI_HPD_CTRL,
+ DSS_REG_W(io, HDMI_HPD_CTRL,
~(1 << 28) & reg_val);
- HDMI_REG_W(io->base, HDMI_HPD_CTRL, (1 << 28) | reg_val);
+ DSS_REG_W(io, HDMI_HPD_CTRL, (1 << 28) | reg_val);
hdmi_ctrl->hpd_initialized = true;
@@ -1607,11 +1481,6 @@
mutex_unlock(&hdmi_ctrl->mutex);
mod_timer(&hdmi_ctrl->hpd_state_timer, jiffies + HZ/2);
- return 0;
-
-disable_hpd_power:
- hdmi_tx_enable_power(hdmi_ctrl, HDMI_TX_HPD_PM, false);
-
return rc;
} /* hdmi_tx_hpd_on */
@@ -1629,7 +1498,6 @@
rc = hdmi_tx_hpd_on(hdmi_ctrl);
} else {
hdmi_tx_hpd_off(hdmi_ctrl);
- /* Set HDMI switch node to 0 on HPD feature disable */
switch_set_state(&hdmi_ctrl->sdev, 0);
DEV_INFO("%s: Hdmi state switch to %d\n", __func__,
hdmi_ctrl->sdev.state);
@@ -1640,8 +1508,6 @@
static irqreturn_t hdmi_tx_isr(int irq, void *data)
{
- u32 hpd_int_status;
- u32 hpd_int_ctrl;
struct dss_io_data *io = NULL;
struct hdmi_tx_ctrl *hdmi_ctrl = (struct hdmi_tx_ctrl *)data;
@@ -1652,108 +1518,26 @@
io = &hdmi_ctrl->pdata.io[HDMI_TX_CORE_IO];
if (!io->base) {
- DEV_WARN("%s: io not initialized, ISR ignored\n", __func__);
+ DEV_WARN("%s: core io not initialized, ISR ignored\n",
+ __func__);
return IRQ_HANDLED;
}
- /* Process HPD Interrupt */
- hpd_int_status = HDMI_REG_R(io->base, HDMI_HPD_INT_STATUS);
- hpd_int_ctrl = HDMI_REG_R(io->base, HDMI_HPD_INT_CTRL);
- if ((hpd_int_ctrl & BIT(2)) && (hpd_int_status & BIT(0))) {
- u32 cable_detected = hpd_int_status & BIT(1);
-
+ if (DSS_REG_R(io, HDMI_HPD_INT_STATUS) & BIT(0)) {
/*
- * Clear all interrupts, timer will turn IRQ back on
- * Leaving the bit[2] on, else core goes off
- * on getting HPD during power off.
+ * Turn off HPD irq and clear all interrupts,
+ * worker will turn IRQ back on
*/
- HDMI_REG_W(io->base, HDMI_HPD_INT_CTRL, BIT(2) | BIT(0));
-
- DEV_DBG("%s: HPD IRQ, Ctrl=%04x, State=%04x\n", __func__,
- hpd_int_ctrl, hpd_int_status);
-
- mutex_lock(&hdmi_ctrl->mutex);
- hdmi_ctrl->hpd_cable_chg_detected = true;
- hdmi_ctrl->hpd_prev_state = cable_detected ? 0 : 1;
- hdmi_ctrl->hpd_stable = 0;
- mutex_unlock(&hdmi_ctrl->mutex);
-
- mod_timer(&hdmi_ctrl->hpd_state_timer, jiffies + HZ/2);
-
- return IRQ_HANDLED;
+ DSS_REG_W(io, HDMI_HPD_INT_CTRL, ~BIT(2) | BIT(0));
+ queue_work(hdmi_ctrl->workq, &hdmi_ctrl->hpd_int_work);
}
- if (!hdmi_ddc_isr(&hdmi_ctrl->ddc_ctrl))
- return IRQ_HANDLED;
-
- DEV_DBG("%s: HPD<Ctrl=%04x, State=%04x>\n", __func__, hpd_int_ctrl,
- hpd_int_status);
+ if (hdmi_ddc_isr(&hdmi_ctrl->ddc_ctrl) < 0)
+ DEV_ERR("%s: hdmi_ddc_isr failed\n", __func__);
return IRQ_HANDLED;
} /* hdmi_tx_isr */
-static void hdmi_tx_clk_deinit(struct hdmi_tx_platform_data *pdata)
-{
- int i;
- if (!pdata) {
- DEV_ERR("%s: invalid input\n", __func__);
- return;
- }
-
- for (i = HDMI_TX_MAX_CLK - 1; i >= 0; i--) {
- if (pdata->clk[i])
- clk_put(pdata->clk[i]);
- pdata->clk[i] = NULL;
- }
-} /* hdmi_tx_clk_deinit */
-
-static int hdmi_tx_clk_init(struct platform_device *pdev,
- struct hdmi_tx_platform_data *pdata)
-{
- int rc = 0;
- struct device *dev = NULL;
- struct clk *clk = NULL;
-
- if (!pdev || !pdata) {
- DEV_ERR("%s: invalid input\n", __func__);
- return -EINVAL;
- }
- dev = &pdev->dev;
-
- clk = clk_get(dev, "iface_clk");
- rc = IS_ERR(clk);
- if (rc) {
- DEV_ERR("%s: ERROR: '%s' clk not found\n", __func__,
- hdmi_tx_clk_name(HDMI_TX_AHB_CLK));
- goto error;
- }
- pdata->clk[HDMI_TX_AHB_CLK] = clk;
-
- clk = clk_get(dev, "core_clk");
- rc = IS_ERR(clk);
- if (rc) {
- DEV_ERR("%s: ERROR: '%s' clk not found\n", __func__,
- hdmi_tx_clk_name(HDMI_TX_APP_CLK));
- goto error;
- }
- pdata->clk[HDMI_TX_APP_CLK] = clk;
-
- clk = clk_get(dev, "extp_clk");
- rc = IS_ERR(clk);
- if (rc) {
- DEV_ERR("%s: ERROR: '%s' clk not found\n", __func__,
- hdmi_tx_clk_name(HDMI_TX_EXTP_CLK));
- goto error;
- }
- pdata->clk[HDMI_TX_EXTP_CLK] = clk;
-
- return rc;
-
-error:
- hdmi_tx_clk_deinit(pdata);
- return rc;
-} /* hdmi_tx_clk_init */
-
static void hdmi_tx_dev_deinit(struct hdmi_tx_ctrl *hdmi_ctrl)
{
if (!hdmi_ctrl) {
@@ -1785,7 +1569,7 @@
pdata = &hdmi_ctrl->pdata;
- rc = hdmi_tx_check_capability(pdata->io[HDMI_TX_QFPROM_IO].base);
+ rc = hdmi_tx_check_capability(&pdata->io[HDMI_TX_QFPROM_IO]);
if (rc) {
DEV_ERR("%s: no HDMI device\n", __func__);
goto fail_no_hdmi;
@@ -1802,11 +1586,11 @@
goto fail_create_workq;
}
- /* todo: May be move this ? */
- hdmi_ctrl->ddc_ctrl.base = pdata->io[HDMI_TX_CORE_IO].base;
+ hdmi_ctrl->ddc_ctrl.io = &pdata->io[HDMI_TX_CORE_IO];
init_completion(&hdmi_ctrl->ddc_ctrl.ddc_sw_done);
INIT_WORK(&hdmi_ctrl->hpd_state_work, hdmi_tx_hpd_state_work);
+ INIT_WORK(&hdmi_ctrl->hpd_int_work, hdmi_tx_hpd_int_work);
init_timer(&hdmi_ctrl->hpd_state_timer);
hdmi_ctrl->hpd_state_timer.function = hdmi_tx_hpd_state_timer;
hdmi_ctrl->hpd_state_timer.data = (u32)hdmi_ctrl;
@@ -1868,23 +1652,16 @@
return;
}
- /* CLK */
- hdmi_tx_clk_deinit(&hdmi_ctrl->pdata);
-
- /* VREG */
+ /* VREG & CLK */
for (i = HDMI_TX_MAX_PM - 1; i >= 0; i--) {
if (hdmi_tx_config_power(hdmi_ctrl, i, 0))
DEV_ERR("%s: '%s' power deconfig fail\n",
- __func__, hdmi_pm_name(i));
+ __func__, hdmi_tx_pm_name(i));
}
/* IO */
- for (i = HDMI_TX_MAX_IO - 1; i >= 0; i--) {
- if (hdmi_ctrl->pdata.io[i].base)
- iounmap(hdmi_ctrl->pdata.io[i].base);
- hdmi_ctrl->pdata.io[i].base = NULL;
- hdmi_ctrl->pdata.io[i].len = 0;
- }
+ for (i = HDMI_TX_MAX_IO - 1; i >= 0; i--)
+ msm_dss_iounmap(&hdmi_ctrl->pdata.io[i]);
} /* hdmi_tx_deinit_resource */
static int hdmi_tx_init_resource(struct hdmi_tx_ctrl *hdmi_ctrl)
@@ -1913,23 +1690,16 @@
pdata->io[i].len);
}
- /* VREG */
+ /* VREG & CLK */
for (i = 0; i < HDMI_TX_MAX_PM; i++) {
rc = hdmi_tx_config_power(hdmi_ctrl, i, 1);
if (rc) {
DEV_ERR("%s: '%s' power config failed.rc=%d\n",
- __func__, hdmi_pm_name(i), rc);
+ __func__, hdmi_tx_pm_name(i), rc);
goto error;
}
}
- /* CLK */
- rc = hdmi_tx_clk_init(hdmi_ctrl->pdev, pdata);
- if (rc) {
- DEV_ERR("%s: FAILED: clk init. rc=%d\n", __func__, rc);
- goto error;
- }
-
return rc;
error:
@@ -1937,6 +1707,98 @@
return rc;
} /* hdmi_tx_init_resource */
+static void hdmi_tx_put_dt_clk_data(struct device *dev,
+ struct dss_module_power *module_power)
+{
+ if (!module_power) {
+ DEV_ERR("%s: invalid input\n", __func__);
+ return;
+ }
+
+ if (module_power->clk_config) {
+ devm_kfree(dev, module_power->clk_config);
+ module_power->clk_config = NULL;
+ }
+ module_power->num_clk = 0;
+} /* hdmi_tx_put_dt_clk_data */
+
+/* todo: once clk are moved to device tree then change this implementation */
+static int hdmi_tx_get_dt_clk_data(struct device *dev,
+ struct dss_module_power *mp, u32 module_type)
+{
+ int rc = 0;
+
+ if (!dev || !mp) {
+ DEV_ERR("%s: invalid input\n", __func__);
+ rc = -EINVAL;
+ goto error;
+ }
+
+ DEV_DBG("%s: module: '%s'\n", __func__, hdmi_tx_pm_name(module_type));
+
+ switch (module_type) {
+ case HDMI_TX_HPD_PM:
+ mp->num_clk = 2;
+ mp->clk_config = devm_kzalloc(dev, sizeof(struct dss_clk) *
+ mp->num_clk, GFP_KERNEL);
+ if (!mp->clk_config) {
+ DEV_ERR("%s: can't alloc '%s' clk mem\n", __func__,
+ hdmi_tx_pm_name(module_type));
+ goto error;
+ }
+
+ snprintf(mp->clk_config[0].clk_name, 32, "%s", "iface_clk");
+ mp->clk_config[0].type = DSS_CLK_AHB;
+ mp->clk_config[0].rate = 0;
+
+ snprintf(mp->clk_config[1].clk_name, 32, "%s", "core_clk");
+ mp->clk_config[1].type = DSS_CLK_OTHER;
+ mp->clk_config[1].rate = 19200000;
+ break;
+
+ case HDMI_TX_CORE_PM:
+ mp->num_clk = 2;
+ mp->clk_config = devm_kzalloc(dev, sizeof(struct dss_clk) *
+ mp->num_clk, GFP_KERNEL);
+ if (!mp->clk_config) {
+ DEV_ERR("%s: can't alloc '%s' clk mem\n", __func__,
+ hdmi_tx_pm_name(module_type));
+ goto error;
+ }
+
+ snprintf(mp->clk_config[0].clk_name, 32, "%s", "extp_clk");
+ mp->clk_config[0].type = DSS_CLK_PCLK;
+ /* This rate will be overwritten when core is powered on */
+ mp->clk_config[0].rate = 148500000;
+
+ snprintf(mp->clk_config[1].clk_name, 32, "%s", "alt_iface_clk");
+ mp->clk_config[1].type = DSS_CLK_AHB;
+ mp->clk_config[1].rate = 0;
+ break;
+
+ case HDMI_TX_CEC_PM:
+ mp->num_clk = 0;
+ DEV_DBG("%s: no clk\n", __func__);
+ break;
+
+ default:
+ DEV_ERR("%s: invalid module type=%d\n", __func__,
+ module_type);
+ return -EINVAL;
+ }
+
+ return rc;
+
+error:
+ if (mp->clk_config) {
+ devm_kfree(dev, mp->clk_config);
+ mp->clk_config = NULL;
+ }
+ mp->num_clk = 0;
+
+ return rc;
+} /* hdmi_tx_get_dt_clk_data */
+
static void hdmi_tx_put_dt_vreg_data(struct device *dev,
struct dss_module_power *module_power)
{
@@ -1985,7 +1847,7 @@
return -EINVAL;
}
- DEV_DBG("%s: module: '%s'\n", __func__, hdmi_pm_name(module_type));
+ DEV_DBG("%s: module: '%s'\n", __func__, hdmi_tx_pm_name(module_type));
of_node = dev->of_node;
@@ -2025,7 +1887,7 @@
mod_vreg_total, GFP_KERNEL);
if (!mp->vreg_config) {
DEV_ERR("%s: can't alloc '%s' vreg mem\n", __func__,
- hdmi_pm_name(module_type));
+ hdmi_tx_pm_name(module_type));
goto error;
}
} else {
@@ -2070,7 +1932,7 @@
prop_name, val_array, dt_vreg_total);
if (rc) {
DEV_ERR("%s: error read '%s' vreg type. rc=%d\n",
- __func__, hdmi_pm_name(module_type), rc);
+ __func__, hdmi_tx_pm_name(module_type), rc);
goto error;
}
mp->vreg_config[j].type = val_array[i];
@@ -2085,7 +1947,7 @@
dt_vreg_total);
if (rc) {
DEV_ERR("%s: error read '%s' min volt. rc=%d\n",
- __func__, hdmi_pm_name(module_type), rc);
+ __func__, hdmi_tx_pm_name(module_type), rc);
goto error;
}
mp->vreg_config[j].min_voltage = val_array[i];
@@ -2100,7 +1962,7 @@
dt_vreg_total);
if (rc) {
DEV_ERR("%s: error read '%s' max volt. rc=%d\n",
- __func__, hdmi_pm_name(module_type), rc);
+ __func__, hdmi_tx_pm_name(module_type), rc);
goto error;
}
mp->vreg_config[j].max_voltage = val_array[i];
@@ -2115,7 +1977,7 @@
dt_vreg_total);
if (rc) {
DEV_ERR("%s: error read '%s' min volt. rc=%d\n",
- __func__, hdmi_pm_name(module_type), rc);
+ __func__, hdmi_tx_pm_name(module_type), rc);
goto error;
}
mp->vreg_config[j].optimum_voltage = val_array[i];
@@ -2136,8 +1998,12 @@
return rc;
error:
- for (i = HDMI_TX_MAX_PM - 1; i >= 0; i--)
- hdmi_tx_put_dt_vreg_data(dev, mp);
+ if (mp->vreg_config) {
+ devm_kfree(dev, mp->vreg_config);
+ mp->vreg_config = NULL;
+ }
+ mp->num_vreg = 0;
+
if (val_array)
devm_kfree(dev, val_array);
return rc;
@@ -2191,7 +2057,7 @@
return -EINVAL;
}
- DEV_DBG("%s: module: '%s'\n", __func__, hdmi_pm_name(module_type));
+ DEV_DBG("%s: module: '%s'\n", __func__, hdmi_tx_pm_name(module_type));
of_node = dev->of_node;
@@ -2227,7 +2093,7 @@
mod_gpio_total, GFP_KERNEL);
if (!mp->gpio_config) {
DEV_ERR("%s: can't alloc '%s' gpio mem\n", __func__,
- hdmi_pm_name(module_type));
+ hdmi_tx_pm_name(module_type));
goto error;
}
} else {
@@ -2268,8 +2134,11 @@
return rc;
error:
- for (i = HDMI_TX_MAX_PM - 1; i >= 0; i--)
- hdmi_tx_put_dt_gpio_data(dev, mp);
+ if (mp->gpio_config) {
+ devm_kfree(dev, mp->gpio_config);
+ mp->gpio_config = NULL;
+ }
+ mp->num_gpio = 0;
return rc;
} /* hdmi_tx_get_dt_gpio_data */
@@ -2284,6 +2153,9 @@
}
for (i = HDMI_TX_MAX_PM - 1; i >= 0; i--)
+ hdmi_tx_put_dt_clk_data(dev, &pdata->power_data[i]);
+
+ for (i = HDMI_TX_MAX_PM - 1; i >= 0; i--)
hdmi_tx_put_dt_vreg_data(dev, &pdata->power_data[i]);
for (i = HDMI_TX_MAX_PM - 1; i >= 0; i--)
@@ -2317,7 +2189,7 @@
&pdata->power_data[i], i);
if (rc) {
DEV_ERR("%s: '%s' get_dt_gpio_data failed.rc=%d\n",
- __func__, hdmi_pm_name(i), rc);
+ __func__, hdmi_tx_pm_name(i), rc);
goto error;
}
}
@@ -2328,7 +2200,18 @@
&pdata->power_data[i], i);
if (rc) {
DEV_ERR("%s: '%s' get_dt_vreg_data failed.rc=%d\n",
- __func__, hdmi_pm_name(i), rc);
+ __func__, hdmi_tx_pm_name(i), rc);
+ goto error;
+ }
+ }
+
+ /* CLK */
+ for (i = 0; i < HDMI_TX_MAX_PM; i++) {
+ rc = hdmi_tx_get_dt_clk_data(&pdev->dev,
+ &pdata->power_data[i], i);
+ if (rc) {
+ DEV_ERR("%s: '%s' get_dt_clk_data failed.rc=%d\n",
+ __func__, hdmi_tx_pm_name(i), rc);
goto error;
}
}
diff --git a/drivers/video/msm/mdss/mdss_hdmi_tx.h b/drivers/video/msm/mdss/mdss_hdmi_tx.h
index 7e37d28..94e0fda 100644
--- a/drivers/video/msm/mdss/mdss_hdmi_tx.h
+++ b/drivers/video/msm/mdss/mdss_hdmi_tx.h
@@ -15,14 +15,6 @@
#include <linux/switch.h>
#include "mdss_hdmi_util.h"
-#include "mdss_io_util.h"
-
-enum hdmi_tx_clk_type {
- HDMI_TX_AHB_CLK,
- HDMI_TX_APP_CLK,
- HDMI_TX_EXTP_CLK,
- HDMI_TX_MAX_CLK
-};
enum hdmi_tx_io_type {
HDMI_TX_CORE_IO,
@@ -42,9 +34,6 @@
/* Data filled from device tree nodes */
struct dss_io_data io[HDMI_TX_MAX_IO];
struct dss_module_power power_data[HDMI_TX_MAX_PM];
-
- /* clk and regulator handles */
- struct clk *clk[HDMI_TX_MAX_CLK];
};
struct hdmi_tx_ctrl {
@@ -67,6 +56,7 @@
u32 hpd_state;
u32 hpd_feature_on;
struct work_struct hpd_state_work;
+ struct work_struct hpd_int_work;
struct timer_list hpd_state_timer;
unsigned long pixel_clk;
diff --git a/drivers/video/msm/mdss/mdss_hdmi_util.c b/drivers/video/msm/mdss/mdss_hdmi_util.c
index 3ba9f89..e7ea8c9 100644
--- a/drivers/video/msm/mdss/mdss_hdmi_util.c
+++ b/drivers/video/msm/mdss/mdss_hdmi_util.c
@@ -15,226 +15,6 @@
#include <mach/board.h>
#include "mdss_hdmi_util.h"
-const char *hdmi_reg_name(u32 offset)
-{
- switch (offset) {
- case 0x00000000: return "HDMI_CTRL";
- case 0x00000010: return "HDMI_TEST_PATTERN";
- case 0x00000014: return "HDMI_RANDOM_PATTERN";
- case 0x00000018: return "HDMI_PKT_BLK_CTRL";
- case 0x0000001C: return "HDMI_STATUS";
- case 0x00000020: return "HDMI_AUDIO_PKT_CTRL";
- case 0x00000024: return "HDMI_ACR_PKT_CTRL";
- case 0x00000028: return "HDMI_VBI_PKT_CTRL";
- case 0x0000002C: return "HDMI_INFOFRAME_CTRL0";
- case 0x00000030: return "HDMI_INFOFRAME_CTRL1";
- case 0x00000034: return "HDMI_GEN_PKT_CTRL";
- case 0x0000003C: return "HDMI_ACP";
- case 0x00000040: return "HDMI_GC";
- case 0x00000044: return "HDMI_AUDIO_PKT_CTRL2";
- case 0x00000048: return "HDMI_ISRC1_0";
- case 0x0000004C: return "HDMI_ISRC1_1";
- case 0x00000050: return "HDMI_ISRC1_2";
- case 0x00000054: return "HDMI_ISRC1_3";
- case 0x00000058: return "HDMI_ISRC1_4";
- case 0x0000005C: return "HDMI_ISRC2_0";
- case 0x00000060: return "HDMI_ISRC2_1";
- case 0x00000064: return "HDMI_ISRC2_2";
- case 0x00000068: return "HDMI_ISRC2_3";
- case 0x0000006C: return "HDMI_AVI_INFO0";
- case 0x00000070: return "HDMI_AVI_INFO1";
- case 0x00000074: return "HDMI_AVI_INFO2";
- case 0x00000078: return "HDMI_AVI_INFO3";
- case 0x0000007C: return "HDMI_MPEG_INFO0";
- case 0x00000080: return "HDMI_MPEG_INFO1";
- case 0x00000084: return "HDMI_GENERIC0_HDR";
- case 0x00000088: return "HDMI_GENERIC0_0";
- case 0x0000008C: return "HDMI_GENERIC0_1";
- case 0x00000090: return "HDMI_GENERIC0_2";
- case 0x00000094: return "HDMI_GENERIC0_3";
- case 0x00000098: return "HDMI_GENERIC0_4";
- case 0x0000009C: return "HDMI_GENERIC0_5";
- case 0x000000A0: return "HDMI_GENERIC0_6";
- case 0x000000A4: return "HDMI_GENERIC1_HDR";
- case 0x000000A8: return "HDMI_GENERIC1_0";
- case 0x000000AC: return "HDMI_GENERIC1_1";
- case 0x000000B0: return "HDMI_GENERIC1_2";
- case 0x000000B4: return "HDMI_GENERIC1_3";
- case 0x000000B8: return "HDMI_GENERIC1_4";
- case 0x000000BC: return "HDMI_GENERIC1_5";
- case 0x000000C0: return "HDMI_GENERIC1_6";
- case 0x000000C4: return "HDMI_ACR_32_0";
- case 0x000000C8: return "HDMI_ACR_32_1";
- case 0x000000CC: return "HDMI_ACR_44_0";
- case 0x000000D0: return "HDMI_ACR_44_1";
- case 0x000000D4: return "HDMI_ACR_48_0";
- case 0x000000D8: return "HDMI_ACR_48_1";
- case 0x000000DC: return "HDMI_ACR_STATUS_0";
- case 0x000000E0: return "HDMI_ACR_STATUS_1";
- case 0x000000E4: return "HDMI_AUDIO_INFO0";
- case 0x000000E8: return "HDMI_AUDIO_INFO1";
- case 0x000000EC: return "HDMI_CS_60958_0";
- case 0x000000F0: return "HDMI_CS_60958_1";
- case 0x000000F8: return "HDMI_RAMP_CTRL0";
- case 0x000000FC: return "HDMI_RAMP_CTRL1";
- case 0x00000100: return "HDMI_RAMP_CTRL2";
- case 0x00000104: return "HDMI_RAMP_CTRL3";
- case 0x00000108: return "HDMI_CS_60958_2";
- case 0x00000110: return "HDMI_HDCP_CTRL";
- case 0x00000114: return "HDMI_HDCP_DEBUG_CTRL";
- case 0x00000118: return "HDMI_HDCP_INT_CTRL";
- case 0x0000011C: return "HDMI_HDCP_LINK0_STATUS";
- case 0x00000120: return "HDMI_HDCP_DDC_CTRL_0";
- case 0x00000124: return "HDMI_HDCP_DDC_CTRL_1";
- case 0x00000128: return "HDMI_HDCP_DDC_STATUS";
- case 0x0000012C: return "HDMI_HDCP_ENTROPY_CTRL0";
- case 0x00000130: return "HDMI_HDCP_RESET";
- case 0x00000134: return "HDMI_HDCP_RCVPORT_DATA0";
- case 0x00000138: return "HDMI_HDCP_RCVPORT_DATA1";
- case 0x0000013C: return "HDMI_HDCP_RCVPORT_DATA2_0";
- case 0x00000140: return "HDMI_HDCP_RCVPORT_DATA2_1";
- case 0x00000144: return "HDMI_HDCP_RCVPORT_DATA3";
- case 0x00000148: return "HDMI_HDCP_RCVPORT_DATA4";
- case 0x0000014C: return "HDMI_HDCP_RCVPORT_DATA5";
- case 0x00000150: return "HDMI_HDCP_RCVPORT_DATA6";
- case 0x00000154: return "HDMI_HDCP_RCVPORT_DATA7";
- case 0x00000158: return "HDMI_HDCP_RCVPORT_DATA8";
- case 0x0000015C: return "HDMI_HDCP_RCVPORT_DATA9";
- case 0x00000160: return "HDMI_HDCP_RCVPORT_DATA10";
- case 0x00000164: return "HDMI_HDCP_RCVPORT_DATA11";
- case 0x00000168: return "HDMI_HDCP_RCVPORT_DATA12";
- case 0x0000016C: return "HDMI_VENSPEC_INFO0";
- case 0x00000170: return "HDMI_VENSPEC_INFO1";
- case 0x00000174: return "HDMI_VENSPEC_INFO2";
- case 0x00000178: return "HDMI_VENSPEC_INFO3";
- case 0x0000017C: return "HDMI_VENSPEC_INFO4";
- case 0x00000180: return "HDMI_VENSPEC_INFO5";
- case 0x00000184: return "HDMI_VENSPEC_INFO6";
- case 0x00000194: return "HDMI_HDCP_DEBUG";
- case 0x0000019C: return "HDMI_TMDS_CTRL_CHAR";
- case 0x000001A4: return "HDMI_TMDS_CTRL_SEL";
- case 0x000001A8: return "HDMI_TMDS_SYNCCHAR01";
- case 0x000001AC: return "HDMI_TMDS_SYNCCHAR23";
- case 0x000001B4: return "HDMI_TMDS_DEBUG";
- case 0x000001B8: return "HDMI_TMDS_CTL_BITS";
- case 0x000001BC: return "HDMI_TMDS_DCBAL_CTRL";
- case 0x000001C0: return "HDMI_TMDS_DCBAL_CHAR";
- case 0x000001C8: return "HDMI_TMDS_CTL01_GEN";
- case 0x000001CC: return "HDMI_TMDS_CTL23_GEN";
- case 0x000001D0: return "HDMI_AUDIO_CFG";
- case 0x00000204: return "HDMI_DEBUG";
- case 0x00000208: return "HDMI_USEC_REFTIMER";
- case 0x0000020C: return "HDMI_DDC_CTRL";
- case 0x00000210: return "HDMI_DDC_ARBITRATION";
- case 0x00000214: return "HDMI_DDC_INT_CTRL";
- case 0x00000218: return "HDMI_DDC_SW_STATUS";
- case 0x0000021C: return "HDMI_DDC_HW_STATUS";
- case 0x00000220: return "HDMI_DDC_SPEED";
- case 0x00000224: return "HDMI_DDC_SETUP";
- case 0x00000228: return "HDMI_DDC_TRANS0";
- case 0x0000022C: return "HDMI_DDC_TRANS1";
- case 0x00000230: return "HDMI_DDC_TRANS2";
- case 0x00000234: return "HDMI_DDC_TRANS3";
- case 0x00000238: return "HDMI_DDC_DATA";
- case 0x0000023C: return "HDMI_HDCP_SHA_CTRL";
- case 0x00000240: return "HDMI_HDCP_SHA_STATUS";
- case 0x00000244: return "HDMI_HDCP_SHA_DATA";
- case 0x00000248: return "HDMI_HDCP_SHA_DBG_M0_0";
- case 0x0000024C: return "HDMI_HDCP_SHA_DBG_M0_1";
- case 0x00000250: return "HDMI_HPD_INT_STATUS";
- case 0x00000254: return "HDMI_HPD_INT_CTRL";
- case 0x00000258: return "HDMI_HPD_CTRL";
- case 0x0000025C: return "HDMI_HDCP_ENTROPY_CTRL1";
- case 0x00000260: return "HDMI_HDCP_SW_UPPER_AN";
- case 0x00000264: return "HDMI_HDCP_SW_LOWER_AN";
- case 0x00000268: return "HDMI_CRC_CTRL";
- case 0x0000026C: return "HDMI_VID_CRC";
- case 0x00000270: return "HDMI_AUD_CRC";
- case 0x00000274: return "HDMI_VBI_CRC";
- case 0x0000027C: return "HDMI_DDC_REF";
- case 0x00000284: return "HDMI_HDCP_SW_UPPER_AKSV";
- case 0x00000288: return "HDMI_HDCP_SW_LOWER_AKSV";
- case 0x0000028C: return "HDMI_CEC_CTRL";
- case 0x00000290: return "HDMI_CEC_WR_DATA";
- case 0x00000294: return "HDMI_CEC_RETRANSMIT";
- case 0x00000298: return "HDMI_CEC_STATUS";
- case 0x0000029C: return "HDMI_CEC_INT";
- case 0x000002A0: return "HDMI_CEC_ADDR";
- case 0x000002A4: return "HDMI_CEC_TIME";
- case 0x000002A8: return "HDMI_CEC_REFTIMER";
- case 0x000002AC: return "HDMI_CEC_RD_DATA";
- case 0x000002B0: return "HDMI_CEC_RD_FILTER";
- case 0x000002B4: return "HDMI_ACTIVE_H";
- case 0x000002B8: return "HDMI_ACTIVE_V";
- case 0x000002BC: return "HDMI_ACTIVE_V_F2";
- case 0x000002C0: return "HDMI_TOTAL";
- case 0x000002C4: return "HDMI_V_TOTAL_F2";
- case 0x000002C8: return "HDMI_FRAME_CTRL";
- case 0x000002CC: return "HDMI_AUD_INT";
- case 0x000002D0: return "HDMI_DEBUG_BUS_CTRL";
- case 0x000002D4: return "HDMI_PHY_CTRL";
- case 0x000002DC: return "HDMI_CEC_WR_RANGE";
- case 0x000002E0: return "HDMI_CEC_RD_RANGE";
- case 0x000002E4: return "HDMI_VERSION";
- case 0x000002F4: return "HDMI_BIST_ENABLE";
- case 0x000002F8: return "HDMI_TIMING_ENGINE_EN";
- case 0x000002FC: return "HDMI_INTF_CONFIG";
- case 0x00000300: return "HDMI_HSYNC_CTL";
- case 0x00000304: return "HDMI_VSYNC_PERIOD_F0";
- case 0x00000308: return "HDMI_VSYNC_PERIOD_F1";
- case 0x0000030C: return "HDMI_VSYNC_PULSE_WIDTH_F0";
- case 0x00000310: return "HDMI_VSYNC_PULSE_WIDTH_F1";
- case 0x00000314: return "HDMI_DISPLAY_V_START_F0";
- case 0x00000318: return "HDMI_DISPLAY_V_START_F1";
- case 0x0000031C: return "HDMI_DISPLAY_V_END_F0";
- case 0x00000320: return "HDMI_DISPLAY_V_END_F1";
- case 0x00000324: return "HDMI_ACTIVE_V_START_F0";
- case 0x00000328: return "HDMI_ACTIVE_V_START_F1";
- case 0x0000032C: return "HDMI_ACTIVE_V_END_F0";
- case 0x00000330: return "HDMI_ACTIVE_V_END_F1";
- case 0x00000334: return "HDMI_DISPLAY_HCTL";
- case 0x00000338: return "HDMI_ACTIVE_HCTL";
- case 0x0000033C: return "HDMI_HSYNC_SKEW";
- case 0x00000340: return "HDMI_POLARITY_CTL";
- case 0x00000344: return "HDMI_TPG_MAIN_CONTROL";
- case 0x00000348: return "HDMI_TPG_VIDEO_CONFIG";
- case 0x0000034C: return "HDMI_TPG_COMPONENT_LIMITS";
- case 0x00000350: return "HDMI_TPG_RECTANGLE";
- case 0x00000354: return "HDMI_TPG_INITIAL_VALUE";
- case 0x00000358: return "HDMI_TPG_BLK_WHT_PATTERN_FRAMES";
- case 0x0000035C: return "HDMI_TPG_RGB_MAPPING";
- default: return "???";
- }
-} /* hdmi_reg_name */
-
-void hdmi_reg_w(void __iomem *addr, u32 offset, u32 value, u32 debug)
-{
- u32 in_val;
-
- writel_relaxed(value, addr+offset);
- if (debug && PORT_DEBUG) {
- in_val = readl_relaxed(addr+offset);
- DEV_DBG("HDMI[%04x] => %08x [%08x] %s\n", offset, value,
- in_val, hdmi_reg_name(offset));
- }
-} /* hdmi_reg_w */
-
-u32 hdmi_reg_r(void __iomem *addr, u32 offset, u32 debug)
-{
- u32 value = readl_relaxed(addr+offset);
- if (debug && PORT_DEBUG)
- DEV_DBG("HDMI[%04x] <= %08x %s\n", offset, value,
- hdmi_reg_name(offset));
- return value;
-} /* hdmi_reg_r */
-
-void hdmi_reg_dump(void __iomem *base, u32 length, const char *prefix)
-{
- if (REG_DUMP)
- print_hex_dump(KERN_INFO, prefix, DUMP_PREFIX_OFFSET, 32, 4,
- (void *)base, length, false);
-} /* hdmi_reg_dump */
-
static struct hdmi_disp_mode_timing_type
hdmi_supported_video_mode_lut[HDMI_VFRMT_MAX] = {
HDMI_SETTINGS_640x480p60_4_3,
@@ -505,7 +285,7 @@
{
u32 reg_val, time_out_count;
- if (!ddc_ctrl || !ddc_ctrl->base) {
+ if (!ddc_ctrl || !ddc_ctrl->io) {
DEV_ERR("%s: invalid input\n", __func__);
return -EINVAL;
}
@@ -515,9 +295,9 @@
do {
--time_out_count;
/* Clear and Enable DDC interrupt */
- HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_INT_CTRL,
+ DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_INT_CTRL,
BIT(2) | BIT(1));
- reg_val = HDMI_REG_R_ND(ddc_ctrl->base, HDMI_DDC_INT_CTRL);
+ reg_val = DSS_REG_R_ND(ddc_ctrl->io, HDMI_DDC_INT_CTRL);
} while ((reg_val & BIT(0)) && time_out_count);
if (!time_out_count) {
@@ -535,7 +315,7 @@
int status = 0;
int log_retry_fail;
- if (!ddc_ctrl || !ddc_ctrl->base || !ddc_data) {
+ if (!ddc_ctrl || !ddc_ctrl->io || !ddc_data) {
DEV_ERR("%s: invalid input\n", __func__);
return -EINVAL;
}
@@ -565,7 +345,7 @@
* INDEX = 0x0 (initial offset into buffer)
* INDEX_WRITE = 0x1 (setting initial offset)
*/
- HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_DATA,
+ DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_DATA,
BIT(31) | (ddc_data->dev_addr << 8));
/*
@@ -576,7 +356,7 @@
* INDEX = 0x0
* INDEX_WRITE = 0x0 (auto-increment by hardware)
*/
- HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_DATA, ddc_data->offset << 8);
+ DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_DATA, ddc_data->offset << 8);
/*
* 3. Write to HDMI_I2C_DATA with the following fields set in order to
@@ -586,7 +366,7 @@
* INDEX = 0x0
* INDEX_WRITE = 0x0 (auto-increment by hardware)
*/
- HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_DATA,
+ DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_DATA,
(ddc_data->dev_addr | BIT(0)) << 8);
/* Data setup is complete, now setup the transaction characteristics */
@@ -599,7 +379,7 @@
* STOP0 = 0x0 (do NOT insert STOP bit)
* CNT0 = 0x1 (single byte transaction excluding address)
*/
- HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_TRANS0, BIT(12) | BIT(16));
+ DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_TRANS0, BIT(12) | BIT(16));
/*
* 5. Write to HDMI_I2C_TRANSACTION1 with the following fields set in
@@ -609,7 +389,7 @@
* STOP1 = 0x1 (insert STOP bit)
* CNT1 = data_len (it's 128 (0x80) for a blk read)
*/
- HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_TRANS1,
+ DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_TRANS1,
BIT(0) | BIT(12) | BIT(13) | (ddc_data->request_len << 16));
/* Trigger the I2C transfer */
@@ -624,11 +404,11 @@
* GO = 0x1 (kicks off hardware)
*/
INIT_COMPLETION(ddc_ctrl->ddc_sw_done);
- HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_CTRL, BIT(0) | BIT(20));
+ DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_CTRL, BIT(0) | BIT(20));
time_out_count = wait_for_completion_interruptible_timeout(
&ddc_ctrl->ddc_sw_done, HZ/2);
- HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_INT_CTRL, BIT(1));
+ DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_INT_CTRL, BIT(1));
if (!time_out_count) {
if (ddc_data->retry-- > 0) {
DEV_INFO("%s: failed timout, retry=%d\n", __func__,
@@ -637,26 +417,26 @@
}
status = -ETIMEDOUT;
DEV_ERR("%s: timedout(7), Int Ctrl=%08x\n", __func__,
- HDMI_REG_R(ddc_ctrl->base, HDMI_DDC_INT_CTRL));
+ DSS_REG_R(ddc_ctrl->io, HDMI_DDC_INT_CTRL));
DEV_ERR("%s: DDC SW Status=%08x, HW Status=%08x\n",
__func__,
- HDMI_REG_R(ddc_ctrl->base, HDMI_DDC_SW_STATUS),
- HDMI_REG_R(ddc_ctrl->base, HDMI_DDC_HW_STATUS));
+ DSS_REG_R(ddc_ctrl->io, HDMI_DDC_SW_STATUS),
+ DSS_REG_R(ddc_ctrl->io, HDMI_DDC_HW_STATUS));
goto error;
}
/* Read DDC status */
- reg_val = HDMI_REG_R(ddc_ctrl->base, HDMI_DDC_SW_STATUS);
+ reg_val = DSS_REG_R(ddc_ctrl->io, HDMI_DDC_SW_STATUS);
reg_val &= BIT(12) | BIT(13) | BIT(14) | BIT(15);
/* Check if any NACK occurred */
if (reg_val) {
/* SW_STATUS_RESET */
- HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_CTRL, BIT(3));
+ DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_CTRL, BIT(3));
if (ddc_data->retry == 1)
/* SOFT_RESET */
- HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_CTRL, BIT(1));
+ DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_CTRL, BIT(1));
if (ddc_data->retry-- > 0) {
DEV_DBG("%s(%s): failed NACK=0x%08x, retry=%d\n",
@@ -687,13 +467,13 @@
* INDEX_WRITE = 0x1 (explicitly define offset)
*/
/* Write this data to DDC buffer */
- HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_DATA,
+ DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_DATA,
BIT(0) | (3 << 16) | BIT(31));
/* Discard first byte */
- HDMI_REG_R_ND(ddc_ctrl->base, HDMI_DDC_DATA);
+ DSS_REG_R_ND(ddc_ctrl->io, HDMI_DDC_DATA);
for (ndx = 0; ndx < ddc_data->data_len; ++ndx) {
- reg_val = HDMI_REG_R_ND(ddc_ctrl->base, HDMI_DDC_DATA);
+ reg_val = DSS_REG_R_ND(ddc_ctrl->io, HDMI_DDC_DATA);
ddc_data->data_buf[ndx] = (u8)((reg_val & 0x0000FF00) >> 8);
}
@@ -705,46 +485,44 @@
void hdmi_ddc_config(struct hdmi_tx_ddc_ctrl *ddc_ctrl)
{
- if (!ddc_ctrl || !ddc_ctrl->base) {
+ if (!ddc_ctrl || !ddc_ctrl->io) {
DEV_ERR("%s: invalid input\n", __func__);
return;
}
/* Configure Pre-Scale multiplier & Threshold */
- HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_SPEED, (10 << 16) | (2 << 0));
+ DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_SPEED, (10 << 16) | (2 << 0));
/*
* Setting 31:24 bits : Time units to wait before timeout
* when clock is being stalled by external sink device
*/
- HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_SETUP, 0xFF000000);
+ DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_SETUP, 0xFF000000);
/* Enable reference timer to 27 micro-seconds */
- HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_REF, (1 << 16) | (27 << 0));
+ DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_REF, (1 << 16) | (27 << 0));
} /* hdmi_ddc_config */
int hdmi_ddc_isr(struct hdmi_tx_ddc_ctrl *ddc_ctrl)
{
- int rc = -1;
u32 ddc_int_ctrl;
- if (!ddc_ctrl || !ddc_ctrl->base) {
+ if (!ddc_ctrl || !ddc_ctrl->io) {
DEV_ERR("%s: invalid input\n", __func__);
return -EINVAL;
}
- ddc_int_ctrl = HDMI_REG_R_ND(ddc_ctrl->base, HDMI_DDC_INT_CTRL);
+ ddc_int_ctrl = DSS_REG_R_ND(ddc_ctrl->io, HDMI_DDC_INT_CTRL);
if ((ddc_int_ctrl & BIT(2)) && (ddc_int_ctrl & BIT(0))) {
/* SW_DONE INT occured, clr it */
- HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_INT_CTRL,
+ DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_INT_CTRL,
ddc_int_ctrl | BIT(1));
complete(&ddc_ctrl->ddc_sw_done);
- return 0;
}
DEV_DBG("%s: ddc_int_ctrl=%04x\n", __func__, ddc_int_ctrl);
- return rc;
+ return 0;
} /* hdmi_ddc_isr */
int hdmi_ddc_read(struct hdmi_tx_ddc_ctrl *ddc_ctrl,
@@ -779,7 +557,7 @@
int log_retry_fail;
int seg_addr = 0x60, seg_num = 0x01;
- if (!ddc_ctrl || !ddc_ctrl->base || !ddc_data) {
+ if (!ddc_ctrl || !ddc_ctrl->io || !ddc_data) {
DEV_ERR("%s: invalid input\n", __func__);
return -EINVAL;
}
@@ -808,7 +586,7 @@
* INDEX = 0x0 (initial offset into buffer)
* INDEX_WRITE = 0x1 (setting initial offset)
*/
- HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_DATA, BIT(31) | (seg_addr << 8));
+ DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_DATA, BIT(31) | (seg_addr << 8));
/*
* 2. Write to HDMI_I2C_DATA with the following fields set in order to
@@ -818,7 +596,7 @@
* INDEX = 0x0
* INDEX_WRITE = 0x0 (auto-increment by hardware)
*/
- HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_DATA, seg_num << 8);
+ DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_DATA, seg_num << 8);
/*
* 3. Write to HDMI_I2C_DATA with the following fields set in order to
@@ -828,9 +606,9 @@
* INDEX = 0x0
* INDEX_WRITE = 0x0 (auto-increment by hardware)
*/
- HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_DATA, ddc_data->dev_addr << 8);
- HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_DATA, ddc_data->offset << 8);
- HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_DATA,
+ DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_DATA, ddc_data->dev_addr << 8);
+ DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_DATA, ddc_data->offset << 8);
+ DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_DATA,
(ddc_data->dev_addr | BIT(0)) << 8);
/* Data setup is complete, now setup the transaction characteristics */
@@ -843,7 +621,7 @@
* STOP0 = 0x0 (do NOT insert STOP bit)
* CNT0 = 0x1 (single byte transaction excluding address)
*/
- HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_TRANS0, BIT(12) | BIT(16));
+ DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_TRANS0, BIT(12) | BIT(16));
/*
* 5. Write to HDMI_I2C_TRANSACTION1 with the following fields set in
@@ -853,7 +631,7 @@
* STOP1 = 0x1 (insert STOP bit)
* CNT1 = data_len (it's 128 (0x80) for a blk read)
*/
- HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_TRANS1, BIT(12) | BIT(16));
+ DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_TRANS1, BIT(12) | BIT(16));
/*
* 5. Write to HDMI_I2C_TRANSACTION1 with the following fields set in
@@ -863,7 +641,7 @@
* STOP1 = 0x1 (insert STOP bit)
* CNT1 = data_len (it's 128 (0x80) for a blk read)
*/
- HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_TRANS2,
+ DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_TRANS2,
BIT(0) | BIT(12) | BIT(13) | (ddc_data->request_len << 16));
/* Trigger the I2C transfer */
@@ -877,13 +655,13 @@
* GO = 0x1 (kicks off hardware)
*/
INIT_COMPLETION(ddc_ctrl->ddc_sw_done);
- HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_CTRL, BIT(0) | BIT(21));
+ DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_CTRL, BIT(0) | BIT(21));
time_out_count = wait_for_completion_interruptible_timeout(
&ddc_ctrl->ddc_sw_done, HZ/2);
- reg_val = HDMI_REG_R(ddc_ctrl->base, HDMI_DDC_INT_CTRL);
- HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_INT_CTRL, reg_val & (~BIT(2)));
+ reg_val = DSS_REG_R(ddc_ctrl->io, HDMI_DDC_INT_CTRL);
+ DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_INT_CTRL, reg_val & (~BIT(2)));
if (!time_out_count) {
if (ddc_data->retry-- > 0) {
DEV_INFO("%s: failed timout, retry=%d\n", __func__,
@@ -892,25 +670,25 @@
}
status = -ETIMEDOUT;
DEV_ERR("%s: timedout(7), Int Ctrl=%08x\n", __func__,
- HDMI_REG_R(ddc_ctrl->base, HDMI_DDC_INT_CTRL));
+ DSS_REG_R(ddc_ctrl->io, HDMI_DDC_INT_CTRL));
DEV_ERR("%s: DDC SW Status=%08x, HW Status=%08x\n",
__func__,
- HDMI_REG_R(ddc_ctrl->base, HDMI_DDC_SW_STATUS),
- HDMI_REG_R(ddc_ctrl->base, HDMI_DDC_HW_STATUS));
+ DSS_REG_R(ddc_ctrl->io, HDMI_DDC_SW_STATUS),
+ DSS_REG_R(ddc_ctrl->io, HDMI_DDC_HW_STATUS));
goto error;
}
/* Read DDC status */
- reg_val = HDMI_REG_R(ddc_ctrl->base, HDMI_DDC_SW_STATUS);
+ reg_val = DSS_REG_R(ddc_ctrl->io, HDMI_DDC_SW_STATUS);
reg_val &= BIT(12) | BIT(13) | BIT(14) | BIT(15);
/* Check if any NACK occurred */
if (reg_val) {
/* SW_STATUS_RESET */
- HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_CTRL, BIT(3));
+ DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_CTRL, BIT(3));
if (ddc_data->retry == 1)
/* SOFT_RESET */
- HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_CTRL, BIT(1));
+ DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_CTRL, BIT(1));
if (ddc_data->retry-- > 0) {
DEV_DBG("%s(%s): failed NACK=0x%08x, retry=%d\n",
__func__, ddc_data->what, reg_val,
@@ -940,14 +718,14 @@
* INDEX_WRITE = 0x1 (explicitly define offset)
*/
/* Write this data to DDC buffer */
- HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_DATA,
+ DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_DATA,
BIT(0) | (5 << 16) | BIT(31));
/* Discard first byte */
- HDMI_REG_R_ND(ddc_ctrl->base, HDMI_DDC_DATA);
+ DSS_REG_R_ND(ddc_ctrl->io, HDMI_DDC_DATA);
for (ndx = 0; ndx < ddc_data->data_len; ++ndx) {
- reg_val = HDMI_REG_R_ND(ddc_ctrl->base, HDMI_DDC_DATA);
+ reg_val = DSS_REG_R_ND(ddc_ctrl->io, HDMI_DDC_DATA);
ddc_data->data_buf[ndx] = (u8) ((reg_val & 0x0000FF00) >> 8);
}
@@ -964,7 +742,7 @@
int status = 0, retry = 10;
u32 time_out_count;
- if (!ddc_ctrl || !ddc_ctrl->base || !ddc_data) {
+ if (!ddc_ctrl || !ddc_ctrl->io || !ddc_data) {
DEV_ERR("%s: invalid input\n", __func__);
return -EINVAL;
}
@@ -991,7 +769,7 @@
* INDEX = 0x0 (initial offset into buffer)
* INDEX_WRITE = 0x1 (setting initial offset)
*/
- HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_DATA,
+ DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_DATA,
BIT(31) | (ddc_data->dev_addr << 8));
/*
@@ -1002,7 +780,7 @@
* INDEX = 0x0
* INDEX_WRITE = 0x0 (auto-increment by hardware)
*/
- HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_DATA, ddc_data->offset << 8);
+ DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_DATA, ddc_data->offset << 8);
/*
* 3. Write to HDMI_I2C_DATA with the following fields set in order to
@@ -1013,7 +791,7 @@
* INDEX_WRITE = 0x0 (auto-increment by hardware)
*/
for (ndx = 0; ndx < ddc_data->data_len; ++ndx)
- HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_DATA,
+ DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_DATA,
((u32)ddc_data->data_buf[ndx]) << 8);
/* Data setup is complete, now setup the transaction characteristics */
@@ -1026,7 +804,7 @@
* STOP0 = 0x0 (do NOT insert STOP bit)
* CNT0 = 0x1 (single byte transaction excluding address)
*/
- HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_TRANS0, BIT(12) | BIT(16));
+ DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_TRANS0, BIT(12) | BIT(16));
/*
* 5. Write to HDMI_I2C_TRANSACTION1 with the following fields set in
@@ -1038,7 +816,7 @@
* Byte count for second transition (excluding the first
* Byte which is usually the address)
*/
- HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_TRANS1,
+ DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_TRANS1,
BIT(13) | ((ddc_data->data_len-1) << 16));
/* Trigger the I2C transfer */
@@ -1051,13 +829,13 @@
* GO = 0x1 (kicks off hardware)
*/
INIT_COMPLETION(ddc_ctrl->ddc_sw_done);
- HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_CTRL, BIT(0) | BIT(20));
+ DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_CTRL, BIT(0) | BIT(20));
time_out_count = wait_for_completion_interruptible_timeout(
&ddc_ctrl->ddc_sw_done, HZ/2);
- reg_val = HDMI_REG_R(ddc_ctrl->base, HDMI_DDC_INT_CTRL);
- HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_INT_CTRL, reg_val & (~BIT(2)));
+ reg_val = DSS_REG_R(ddc_ctrl->io, HDMI_DDC_INT_CTRL);
+ DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_INT_CTRL, reg_val & (~BIT(2)));
if (!time_out_count) {
if (retry-- > 0) {
DEV_INFO("%s[%s]: failed timout, retry=%d\n", __func__,
@@ -1067,26 +845,26 @@
status = -ETIMEDOUT;
DEV_ERR("%s[%s]: timedout, Int Ctrl=%08x\n",
__func__, ddc_data->what,
- HDMI_REG_R(ddc_ctrl->base, HDMI_DDC_INT_CTRL));
+ DSS_REG_R(ddc_ctrl->io, HDMI_DDC_INT_CTRL));
DEV_ERR("%s: DDC SW Status=%08x, HW Status=%08x\n",
__func__,
- HDMI_REG_R(ddc_ctrl->base, HDMI_DDC_SW_STATUS),
- HDMI_REG_R(ddc_ctrl->base, HDMI_DDC_HW_STATUS));
+ DSS_REG_R(ddc_ctrl->io, HDMI_DDC_SW_STATUS),
+ DSS_REG_R(ddc_ctrl->io, HDMI_DDC_HW_STATUS));
goto error;
}
/* Read DDC status */
- reg_val = HDMI_REG_R_ND(ddc_ctrl->base, HDMI_DDC_SW_STATUS);
+ reg_val = DSS_REG_R_ND(ddc_ctrl->io, HDMI_DDC_SW_STATUS);
reg_val &= 0x00001000 | 0x00002000 | 0x00004000 | 0x00008000;
/* Check if any NACK occurred */
if (reg_val) {
if (retry > 1)
/* SW_STATUS_RESET */
- HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_CTRL, BIT(3));
+ DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_CTRL, BIT(3));
else
/* SOFT_RESET */
- HDMI_REG_W_ND(ddc_ctrl->base, HDMI_DDC_CTRL, BIT(1));
+ DSS_REG_W_ND(ddc_ctrl->io, HDMI_DDC_CTRL, BIT(1));
if (retry-- > 0) {
DEV_DBG("%s[%s]: failed NACK=%08x, retry=%d\n",
diff --git a/drivers/video/msm/mdss/mdss_hdmi_util.h b/drivers/video/msm/mdss/mdss_hdmi_util.h
index 47515ba..852a93c 100644
--- a/drivers/video/msm/mdss/mdss_hdmi_util.h
+++ b/drivers/video/msm/mdss/mdss_hdmi_util.h
@@ -12,26 +12,7 @@
#ifndef __HDMI_UTIL_H__
#define __HDMI_UTIL_H__
-
-#define DEV_INFO(fmt, args...) pr_info(fmt, ##args)
-#define DEV_WARN(fmt, args...) pr_warn(fmt, ##args)
-#define DEV_ERR(fmt, args...) pr_err(fmt, ##args)
-
-#ifdef DEBUG
-#define DEV_DBG(fmt, args...) pr_err(fmt, ##args)
-#else
-#define DEV_DBG(args...) (void)0
-#endif
-
-#define PORT_DEBUG 0
-#define REG_DUMP 0
-void hdmi_reg_w(void __iomem *addr, u32 offset, u32 value, u32 debug);
-u32 hdmi_reg_r(void __iomem *addr, u32 offset, u32 debug);
-
-#define HDMI_REG_W_ND(addr, offset, val) hdmi_reg_w(addr, offset, val, false)
-#define HDMI_REG_W(addr, offset, val) hdmi_reg_w(addr, offset, val, true)
-#define HDMI_REG_R_ND(addr, offset) hdmi_reg_r(addr, offset, false)
-#define HDMI_REG_R(addr, offset) hdmi_reg_r(addr, offset, true)
+#include "mdss_io_util.h"
/* HDMI_TX Registers */
#define HDMI_CTRL (0x00000000)
@@ -220,7 +201,7 @@
#define HDMI_TPG_BLK_WHT_PATTERN_FRAMES (0x00000358)
#define HDMI_TPG_RGB_MAPPING (0x0000035C)
-/* HDMI PHY Registers, use them with PHY base and _ND macro */
+/* HDMI PHY Registers */
#define HDMI_PHY_ANA_CFG0 (0x00000000)
#define HDMI_PHY_ANA_CFG1 (0x00000004)
#define HDMI_PHY_PD_CTRL0 (0x00000010)
@@ -231,6 +212,10 @@
#define HDMI_PHY_BIST_PATN2 (0x00000044)
#define HDMI_PHY_BIST_PATN3 (0x00000048)
+/* QFPROM Registers for HDMI/HDCP */
+#define QFPROM_RAW_FEAT_CONFIG_ROW0_LSB (0x000000F8)
+#define QFPROM_RAW_FEAT_CONFIG_ROW0_MSB (0x000000FC)
+
/* all video formats defined by EIA CEA 861D */
#define HDMI_VFRMT_640x480p60_4_3 0
#define HDMI_VFRMT_720x480p60_4_3 1
@@ -397,7 +382,7 @@
};
struct hdmi_tx_ddc_ctrl {
- void __iomem *base;
+ struct dss_io_data *io;
struct completion ddc_sw_done;
};
@@ -412,9 +397,6 @@
int retry;
};
-void hdmi_reg_dump(void __iomem *base, u32 length, const char *prefix);
-const char *hdmi_reg_name(u32 offset);
-
const struct hdmi_disp_mode_timing_type *hdmi_get_supported_mode(u32 mode);
void hdmi_set_supported_mode(u32 mode);
const char *hdmi_get_video_fmt_2string(u32 format);
diff --git a/drivers/video/msm/mdss/mdss_io_util.c b/drivers/video/msm/mdss/mdss_io_util.c
index 65d08d3..5778525 100644
--- a/drivers/video/msm/mdss/mdss_io_util.c
+++ b/drivers/video/msm/mdss/mdss_io_util.c
@@ -10,10 +10,65 @@
* GNU General Public License for more details.
*/
+#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include "mdss_io_util.h"
+void dss_reg_w(struct dss_io_data *io, u32 offset, u32 value, u32 debug)
+{
+ u32 in_val;
+
+ if (!io || !io->base) {
+ DEV_ERR("%pS->%s: invalid input\n",
+ __builtin_return_address(0), __func__);
+ return;
+ }
+
+ if (offset > io->len) {
+ DEV_ERR("%pS->%s: offset out of range\n",
+ __builtin_return_address(0), __func__);
+ return;
+ }
+
+ writel_relaxed(value, io->base + offset);
+ if (debug) {
+ in_val = readl_relaxed(io->base + offset);
+ DEV_DBG("[%08x] => %08x [%08x]\n", (u32)(io->base + offset),
+ value, in_val);
+ }
+} /* dss_reg_w */
+
+u32 dss_reg_r(struct dss_io_data *io, u32 offset, u32 debug)
+{
+ u32 value;
+ if (!io || !io->base) {
+ DEV_ERR("%pS->%s: invalid input\n",
+ __builtin_return_address(0), __func__);
+ return -EINVAL;
+ }
+
+ if (offset > io->len) {
+ DEV_ERR("%pS->%s: offset out of range\n",
+ __builtin_return_address(0), __func__);
+ return -EINVAL;
+ }
+
+ value = readl_relaxed(io->base + offset);
+ if (debug)
+ DEV_DBG("[%08x] <= %08x\n", (u32)(io->base + offset), value);
+
+ return value;
+} /* dss_reg_r */
+
+void dss_reg_dump(void __iomem *base, u32 length, const char *prefix,
+ u32 debug)
+{
+ if (debug)
+ print_hex_dump(KERN_INFO, prefix, DUMP_PREFIX_OFFSET, 32, 4,
+ (void *)base, length, false);
+} /* dss_reg_dump */
+
static struct resource *msm_dss_get_res_byname(struct platform_device *pdev,
unsigned int type, const char *name)
{
@@ -21,11 +76,10 @@
res = platform_get_resource_byname(pdev, type, name);
if (!res)
- pr_err("%s: '%s' resource not found\n", __func__, name);
+ DEV_ERR("%s: '%s' resource not found\n", __func__, name);
return res;
-}
-
+} /* msm_dss_get_res_byname */
int msm_dss_ioremap_byname(struct platform_device *pdev,
struct dss_io_data *io_data, const char *name)
@@ -33,32 +87,49 @@
struct resource *res = NULL;
if (!pdev || !io_data) {
- pr_err("%s: invalid input\n", __func__);
+ DEV_ERR("%pS->%s: invalid input\n",
+ __builtin_return_address(0), __func__);
return -EINVAL;
}
res = msm_dss_get_res_byname(pdev, IORESOURCE_MEM, name);
if (!res) {
- pr_err("%s: '%s' msm_dss_get_res_byname failed\n",
- __func__, name);
+ DEV_ERR("%pS->%s: '%s' msm_dss_get_res_byname failed\n",
+ __builtin_return_address(0), __func__, name);
return -ENODEV;
}
io_data->len = resource_size(res);
io_data->base = ioremap(res->start, io_data->len);
if (!io_data->base) {
- pr_err("%s: '%s' ioremap failed\n", __func__, name);
+ DEV_ERR("%pS->%s: '%s' ioremap failed\n",
+ __builtin_return_address(0), __func__, name);
return -EIO;
}
return 0;
-}
+} /* msm_dss_ioremap_byname */
+
+void msm_dss_iounmap(struct dss_io_data *io_data)
+{
+ if (!io_data) {
+ DEV_ERR("%pS->%s: invalid input\n",
+ __builtin_return_address(0), __func__);
+ return;
+ }
+
+ if (io_data->base) {
+ iounmap(io_data->base);
+ io_data->base = NULL;
+ }
+ io_data->len = 0;
+} /* msm_dss_iounmap */
int msm_dss_config_vreg(struct device *dev, struct dss_vreg *in_vreg,
int num_vreg, int config)
{
int i = 0, rc = 0;
- struct dss_vreg *curr_vreg;
+ struct dss_vreg *curr_vreg = NULL;
if (config) {
for (i = 0; i < num_vreg; i++) {
@@ -67,8 +138,8 @@
curr_vreg->vreg_name);
rc = IS_ERR(curr_vreg->vreg);
if (rc) {
- pr_err("%s: %s get failed. rc=%d\n",
- __func__,
+ DEV_ERR("%pS->%s: %s get failed. rc=%d\n",
+ __builtin_return_address(0), __func__,
curr_vreg->vreg_name, rc);
curr_vreg->vreg = NULL;
goto vreg_get_fail;
@@ -79,7 +150,8 @@
curr_vreg->min_voltage,
curr_vreg->max_voltage);
if (rc < 0) {
- pr_err("%s: %s set voltage failed\n",
+ DEV_ERR("%pS->%s: %s set vltg fail\n",
+ __builtin_return_address(0),
__func__,
curr_vreg->vreg_name);
goto vreg_set_voltage_fail;
@@ -89,8 +161,9 @@
curr_vreg->vreg,
curr_vreg->optimum_voltage);
if (rc < 0) {
- pr_err(
- "%s: %s set opt mode failed\n",
+ DEV_ERR(
+ "%pS->%s: %s set opt m fail\n",
+ __builtin_return_address(0),
__func__,
curr_vreg->vreg_name);
goto vreg_set_opt_mode_fail;
@@ -144,14 +217,16 @@
for (i = 0; i < num_vreg; i++) {
rc = IS_ERR(in_vreg[i].vreg);
if (rc) {
- pr_err("%s: %s regulator error. rc=%d\n",
- __func__, in_vreg[i].vreg_name, rc);
+ DEV_ERR("%pS->%s: %s regulator error. rc=%d\n",
+ __builtin_return_address(0), __func__,
+ in_vreg[i].vreg_name, rc);
goto disable_vreg;
}
rc = regulator_enable(in_vreg[i].vreg);
if (rc < 0) {
- pr_err("%s: %s enable failed\n",
- __func__, in_vreg[i].vreg_name);
+ DEV_ERR("%pS->%s: %s enable failed\n",
+ __builtin_return_address(0), __func__,
+ in_vreg[i].vreg_name);
goto disable_vreg;
}
}
@@ -176,8 +251,9 @@
rc = gpio_request(in_gpio[i].gpio,
in_gpio[i].gpio_name);
if (rc < 0) {
- pr_err("%s: %s enable failed\n",
- __func__, in_gpio[i].gpio_name);
+ DEV_ERR("%pS->%s: %s enable failed\n",
+ __builtin_return_address(0), __func__,
+ in_gpio[i].gpio_name);
goto disable_gpio;
}
}
@@ -192,3 +268,117 @@
gpio_free(in_gpio[i].gpio);
return rc;
} /* msm_dss_enable_gpio */
+
+void msm_dss_put_clk(struct dss_clk *clk_arry, int num_clk)
+{
+ int i;
+
+ for (i = num_clk - 1; i >= 0; i--) {
+ if (clk_arry[i].clk)
+ clk_put(clk_arry[i].clk);
+ clk_arry[i].clk = NULL;
+ }
+} /* msm_dss_put_clk */
+
+int msm_dss_get_clk(struct device *dev, struct dss_clk *clk_arry, int num_clk)
+{
+ int i, rc = 0;
+
+ for (i = 0; i < num_clk; i++) {
+ clk_arry[i].clk = clk_get(dev, clk_arry[i].clk_name);
+ rc = IS_ERR(clk_arry[i].clk);
+ if (rc) {
+ DEV_ERR("%pS->%s: '%s' get failed. rc=%d\n",
+ __builtin_return_address(0), __func__,
+ clk_arry[i].clk_name, rc);
+ goto error;
+ }
+ }
+
+ return rc;
+
+error:
+ msm_dss_put_clk(clk_arry, num_clk);
+
+ return rc;
+} /* msm_dss_get_clk */
+
+int msm_dss_clk_set_rate(struct dss_clk *clk_arry, int num_clk)
+{
+ int i, rc = 0;
+
+ for (i = 0; i < num_clk; i++) {
+ if (clk_arry[i].clk) {
+ if (DSS_CLK_AHB != clk_arry[i].type) {
+ DEV_DBG("%pS->%s: '%s' rate %ld\n",
+ __builtin_return_address(0), __func__,
+ clk_arry[i].clk_name,
+ clk_arry[i].rate);
+ rc = clk_set_rate(clk_arry[i].clk,
+ clk_arry[i].rate);
+ if (rc) {
+ DEV_ERR("%pS->%s: %s failed. rc=%d\n",
+ __builtin_return_address(0),
+ __func__,
+ clk_arry[i].clk_name, rc);
+ break;
+ }
+ }
+ } else {
+ DEV_ERR("%pS->%s: '%s' is not available\n",
+ __builtin_return_address(0), __func__,
+ clk_arry[i].clk_name);
+ rc = -EPERM;
+ break;
+ }
+ }
+
+ return rc;
+} /* msm_dss_clk_set_rate */
+
+int msm_dss_enable_clk(struct dss_clk *clk_arry, int num_clk, int enable)
+{
+ int i, rc = 0;
+
+ if (enable) {
+ for (i = 0; i < num_clk; i++) {
+ DEV_DBG("%pS->%s: enable '%s'\n",
+ __builtin_return_address(0), __func__,
+ clk_arry[i].clk_name);
+ if (clk_arry[i].clk) {
+ rc = clk_prepare_enable(clk_arry[i].clk);
+ if (rc)
+ DEV_ERR("%pS->%s: %s en fail. rc=%d\n",
+ __builtin_return_address(0),
+ __func__,
+ clk_arry[i].clk_name, rc);
+ } else {
+ DEV_ERR("%pS->%s: '%s' is not available\n",
+ __builtin_return_address(0), __func__,
+ clk_arry[i].clk_name);
+ rc = -EPERM;
+ }
+
+ if (rc) {
+ msm_dss_enable_clk(&clk_arry[i],
+ i, false);
+ break;
+ }
+ }
+ } else {
+ for (i = num_clk - 1; i >= 0; i--) {
+ DEV_DBG("%pS->%s: disable '%s'\n",
+ __builtin_return_address(0), __func__,
+ clk_arry[i].clk_name);
+
+ if (clk_arry[i].clk)
+ clk_disable_unprepare(clk_arry[i].clk);
+ else
+ DEV_ERR("%pS->%s: '%s' is not available\n",
+ __builtin_return_address(0), __func__,
+ clk_arry[i].clk_name);
+ }
+ }
+
+ return rc;
+} /* msm_dss_enable_clk */
diff --git a/drivers/video/msm/mdss/mdss_io_util.h b/drivers/video/msm/mdss/mdss_io_util.h
index 9671414..51e9e54 100644
--- a/drivers/video/msm/mdss/mdss_io_util.h
+++ b/drivers/video/msm/mdss/mdss_io_util.h
@@ -17,11 +17,29 @@
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
+#ifdef DEBUG
+#define DEV_DBG(fmt, args...) pr_err(fmt, ##args)
+#else
+#define DEV_DBG(fmt, args...) pr_debug(fmt, ##args)
+#endif
+#define DEV_INFO(fmt, args...) pr_info(fmt, ##args)
+#define DEV_WARN(fmt, args...) pr_warn(fmt, ##args)
+#define DEV_ERR(fmt, args...) pr_err(fmt, ##args)
+
struct dss_io_data {
u32 len;
void __iomem *base;
};
+void dss_reg_w(struct dss_io_data *io, u32 offset, u32 value, u32 debug);
+u32 dss_reg_r(struct dss_io_data *io, u32 offset, u32 debug);
+void dss_reg_dump(void __iomem *base, u32 len, const char *prefix, u32 debug);
+
+#define DSS_REG_W_ND(io, offset, val) dss_reg_w(io, offset, val, false)
+#define DSS_REG_W(io, offset, val) dss_reg_w(io, offset, val, true)
+#define DSS_REG_R_ND(io, offset) dss_reg_r(io, offset, false)
+#define DSS_REG_R(io, offset) dss_reg_r(io, offset, true)
+
enum dss_vreg_type {
DSS_REG_LDO,
DSS_REG_VS,
@@ -41,19 +59,42 @@
char gpio_name[32];
};
+enum dss_clk_type {
+ DSS_CLK_AHB, /* no set rate. rate controlled through rpm */
+ DSS_CLK_PCLK,
+ DSS_CLK_OTHER,
+};
+
+struct dss_clk {
+ struct clk *clk; /* clk handle */
+ char clk_name[32];
+ enum dss_clk_type type;
+ unsigned long rate;
+};
+
struct dss_module_power {
unsigned num_vreg;
struct dss_vreg *vreg_config;
unsigned num_gpio;
struct dss_gpio *gpio_config;
+ unsigned num_clk;
+ struct dss_clk *clk_config;
};
int msm_dss_ioremap_byname(struct platform_device *pdev,
struct dss_io_data *io_data, const char *name);
+void msm_dss_iounmap(struct dss_io_data *io_data);
+
int msm_dss_enable_gpio(struct dss_gpio *in_gpio, int num_gpio, int enable);
int msm_dss_gpio_enable(struct dss_gpio *in_gpio, int num_gpio, int enable);
+
int msm_dss_config_vreg(struct device *dev, struct dss_vreg *in_vreg,
int num_vreg, int config);
int msm_dss_enable_vreg(struct dss_vreg *in_vreg, int num_vreg, int enable);
+int msm_dss_get_clk(struct device *dev, struct dss_clk *clk_arry, int num_clk);
+void msm_dss_put_clk(struct dss_clk *clk_arry, int num_clk);
+int msm_dss_clk_set_rate(struct dss_clk *clk_arry, int num_clk);
+int msm_dss_enable_clk(struct dss_clk *clk_arry, int num_clk, int enable);
+
#endif /* __MDSS_IO_UTIL_H__ */
diff --git a/drivers/video/msm/mdss/mdss_mdp.h b/drivers/video/msm/mdss/mdss_mdp.h
index 2493570..6fd642f 100644
--- a/drivers/video/msm/mdss/mdss_mdp.h
+++ b/drivers/video/msm/mdss/mdss_mdp.h
@@ -29,7 +29,7 @@
#define MDP_CLK_DEFAULT_RATE 37500000
#define PHASE_STEP_SHIFT 21
#define MAX_MIXER_WIDTH 2048
-#define MAX_MIXER_HEIGHT 2048
+#define MAX_MIXER_HEIGHT 2400
#define MAX_IMG_WIDTH 0x3FFF
#define MAX_IMG_HEIGHT 0x3FFF
#define MIN_DST_W 10
diff --git a/drivers/video/msm/mdss/mdss_mdp_ctl.c b/drivers/video/msm/mdss/mdss_mdp_ctl.c
index f72ff8d..5966989 100644
--- a/drivers/video/msm/mdss/mdss_mdp_ctl.c
+++ b/drivers/video/msm/mdss/mdss_mdp_ctl.c
@@ -351,6 +351,7 @@
{
struct mdss_mdp_ctl *ctl;
u32 width, height;
+ int ret = 0;
if (!mfd)
return -ENODEV;
@@ -363,43 +364,54 @@
return -EINVAL;
}
- ctl = mdss_mdp_ctl_alloc();
-
- if (!ctl) {
- pr_err("unable to allocate ctl\n");
- return -ENOMEM;
+ if (!mfd->ctl) {
+ ctl = mdss_mdp_ctl_alloc();
+ if (!ctl) {
+ pr_err("unable to allocate ctl\n");
+ return -ENOMEM;
+ }
+ ctl->mfd = mfd;
+ mfd->ctl = ctl;
+ } else {
+ ctl = mfd->ctl;
}
- ctl->mfd = mfd;
ctl->width = width;
ctl->height = height;
ctl->dst_format = mfd->panel_info.out_format;
- ctl->mixer_left = mdss_mdp_mixer_alloc(MDSS_MDP_MIXER_TYPE_INTF);
if (!ctl->mixer_left) {
- pr_err("unable to allocate layer mixer\n");
- mdss_mdp_ctl_free(ctl);
- return -ENOMEM;
+ ctl->mixer_left =
+ mdss_mdp_mixer_alloc(MDSS_MDP_MIXER_TYPE_INTF);
+ if (!ctl->mixer_left) {
+ pr_err("unable to allocate layer mixer\n");
+ ret = -ENOMEM;
+ goto ctl_init_fail;
+ }
}
- ctl->mixer_left->width = MIN(width, MAX_MIXER_WIDTH);
+ if (width > MAX_MIXER_WIDTH)
+ width /= 2;
+
+ ctl->mixer_left->width = width;
ctl->mixer_left->height = height;
ctl->mixer_left->ctl = ctl;
- width -= ctl->mixer_left->width;
-
- if (width) {
- ctl->mixer_right =
- mdss_mdp_mixer_alloc(MDSS_MDP_MIXER_TYPE_INTF);
- if (!ctl->mixer_right) {
- pr_err("unable to allocate layer mixer\n");
- mdss_mdp_mixer_free(ctl->mixer_left);
- mdss_mdp_ctl_free(ctl);
- return -ENOMEM;
+ if (width < ctl->width) {
+ if (ctl->mixer_right == NULL) {
+ ctl->mixer_right =
+ mdss_mdp_mixer_alloc(MDSS_MDP_MIXER_TYPE_INTF);
+ if (!ctl->mixer_right) {
+ pr_err("unable to allocate right mixer\n");
+ ret = -ENOMEM;
+ goto ctl_init_fail;
+ }
}
ctl->mixer_right->width = width;
ctl->mixer_right->height = height;
ctl->mixer_right->ctl = ctl;
+ } else if (ctl->mixer_right) {
+ mdss_mdp_mixer_free(ctl->mixer_right);
}
switch (mfd->panel_info.type) {
@@ -431,9 +443,8 @@
break;
default:
pr_err("unsupported panel type (%d)\n", mfd->panel_info.type);
- mdss_mdp_ctl_free(ctl);
- return -EINVAL;
-
+ ret = -EINVAL;
+ goto ctl_init_fail;
}
ctl->opmode |= (ctl->intf_num << 4);
@@ -443,9 +454,17 @@
MDSS_MDP_CTL_OP_PACK_3D_H_ROW_INT;
}
- mfd->ctl = ctl;
+ctl_init_fail:
+ if (IS_ERR_VALUE(ret)) {
+ if (ctl->mixer_left)
+ mdss_mdp_mixer_free(ctl->mixer_left);
+ if (ctl->mixer_right)
+ mdss_mdp_mixer_free(ctl->mixer_right);
+ mdss_mdp_ctl_free(ctl);
+ mfd->ctl = NULL;
+ }
- return 0;
+ return ret;
}
static int mdss_mdp_ctl_destroy(struct msm_fb_data_type *mfd)
@@ -486,12 +505,11 @@
return -ENODEV;
}
- if (!mfd->ctl) {
- if (mdss_mdp_ctl_init(mfd)) {
- pr_err("unable to initialize ctl\n");
- return -ENODEV;
- }
+ if (mdss_mdp_ctl_init(mfd)) {
+ pr_err("unable to initialize ctl\n");
+ return -ENODEV;
}
+
ctl = mfd->ctl;
if (ctl->power_on) {
diff --git a/drivers/video/msm/mdss/mdss_mdp_overlay.c b/drivers/video/msm/mdss/mdss_mdp_overlay.c
index 91f94ea..ee1b350 100644
--- a/drivers/video/msm/mdss/mdss_mdp_overlay.c
+++ b/drivers/video/msm/mdss/mdss_mdp_overlay.c
@@ -326,7 +326,6 @@
}
pipe->params_changed++;
- pipe->play_cnt = 0;
req->id = pipe->ndx;
@@ -636,8 +635,15 @@
if (pipe == NULL) {
struct mdp_overlay req;
struct fb_info *fbi = mfd->fbi;
+ struct mdss_mdp_mixer *mixer;
int ret, bpp;
+ mixer = mdss_mdp_mixer_get(mfd->ctl, MDSS_MDP_MIXER_MUX_LEFT);
+ if (!mixer) {
+ pr_err("unable to retrieve mixer\n");
+ return -ENODEV;
+ }
+
memset(&req, 0, sizeof(req));
bpp = fbi->var.bits_per_pixel / 8;
@@ -646,20 +652,22 @@
req.src.height = fbi->var.yres;
req.src.width = fbi->fix.line_length / bpp;
if (mixer_mux == MDSS_MDP_MIXER_MUX_RIGHT) {
- if (req.src.width <= MAX_MIXER_WIDTH)
- return -ENODEV;
+ if (req.src.width <= mixer->width) {
+ pr_warn("right fb pipe not needed\n");
+ return -EINVAL;
+ }
req.flags |= MDSS_MDP_RIGHT_MIXER;
- req.src_rect.x = MAX_MIXER_WIDTH;
- req.src_rect.w = fbi->var.xres - MAX_MIXER_WIDTH;
+ req.src_rect.x = mixer->width;
+ req.src_rect.w = fbi->var.xres - mixer->width;
} else {
req.src_rect.x = 0;
- req.src_rect.w = MIN(fbi->var.xres, MAX_MIXER_WIDTH);
+ req.src_rect.w = MIN(fbi->var.xres, mixer->width);
}
req.src_rect.y = 0;
req.src_rect.h = req.src.height;
- req.dst_rect.x = req.src_rect.x;
+ req.dst_rect.x = 0;
req.dst_rect.y = 0;
req.dst_rect.w = req.src_rect.w;
req.dst_rect.h = req.src_rect.h;
@@ -696,6 +704,7 @@
if (fbi->fix.smem_len == 0) {
pr_warn("fb memory not allocated\n");
+ mdss_mdp_overlay_kickoff(mfd->ctl);
return;
}
diff --git a/drivers/video/msm/mdss/mdss_mdp_util.c b/drivers/video/msm/mdss/mdss_mdp_util.c
index aa65018..95c92fc 100644
--- a/drivers/video/msm/mdss/mdss_mdp_util.c
+++ b/drivers/video/msm/mdss/mdss_mdp_util.c
@@ -213,7 +213,7 @@
} else {
u8 hmap[] = { 1, 2, 1, 2 };
u8 vmap[] = { 1, 1, 2, 2 };
- u8 horiz, vert, stride_align;
+ u8 horiz, vert, stride_align, height_align;
horiz = hmap[fmt->chroma_sample];
vert = vmap[fmt->chroma_sample];
@@ -221,18 +221,21 @@
switch (format) {
case MDP_Y_CR_CB_GH2V2:
stride_align = 16;
+ height_align = 1;
break;
case MDP_Y_CBCR_H2V2_VENUS:
stride_align = 32;
+ height_align = 32;
break;
default:
stride_align = 1;
+ height_align = 1;
break;
}
ps->ystride[0] = ALIGN(w, stride_align);
ps->ystride[1] = ALIGN(w / horiz, stride_align);
- ps->plane_size[0] = ps->ystride[0] * h;
+ ps->plane_size[0] = ps->ystride[0] * ALIGN(h, height_align);
ps->plane_size[1] = ps->ystride[1] * (h / vert);
if (fmt->fetch_planes == MDSS_MDP_PLANE_PSEUDO_PLANAR) {
diff --git a/drivers/video/msm/msm_fb.c b/drivers/video/msm/msm_fb.c
index 9c55fe8..1994b1b 100644
--- a/drivers/video/msm/msm_fb.c
+++ b/drivers/video/msm/msm_fb.c
@@ -185,8 +185,9 @@
if (!bl_lvl && value)
bl_lvl = 1;
-
+ down(&mfd->sem);
msm_fb_set_backlight(mfd, bl_lvl);
+ up(&mfd->sem);
}
static struct led_classdev backlight_led = {
@@ -809,7 +810,9 @@
struct mdp_bl_scale_data *data)
{
int ret = 0;
- int curr_bl = mfd->bl_level;
+ int curr_bl;
+ down(&mfd->sem);
+ curr_bl = mfd->bl_level;
bl_scale = data->scale;
bl_min_lvl = data->min_lvl;
pr_debug("%s: update scale = %d, min_lvl = %d\n", __func__, bl_scale,
@@ -817,6 +820,7 @@
/* update current backlight to use new scaling*/
msm_fb_set_backlight(mfd, curr_bl);
+ up(&mfd->sem);
return ret;
}
@@ -824,6 +828,7 @@
static void msm_fb_scale_bl(__u32 *bl_lvl)
{
__u32 temp = *bl_lvl;
+ pr_debug("%s: input = %d, scale = %d", __func__, temp, bl_scale);
if (temp >= bl_min_lvl) {
/* bl_scale is the numerator of scaling fraction (x/1024)*/
temp = ((*bl_lvl) * bl_scale) / 1024;
@@ -832,10 +837,12 @@
if (temp < bl_min_lvl)
temp = bl_min_lvl;
}
+ pr_debug("%s: output = %d", __func__, temp);
(*bl_lvl) = temp;
}
+/*must call this function from within mfd->sem*/
void msm_fb_set_backlight(struct msm_fb_data_type *mfd, __u32 bkl_lvl)
{
struct msm_fb_panel_data *pdata;
@@ -847,20 +854,17 @@
unset_bl_level = 0;
}
- msm_fb_scale_bl(&temp);
pdata = (struct msm_fb_panel_data *)mfd->pdev->dev.platform_data;
if ((pdata) && (pdata->set_backlight)) {
- down(&mfd->sem);
+ msm_fb_scale_bl(&temp);
if (bl_level_old == temp) {
- up(&mfd->sem);
return;
}
mfd->bl_level = temp;
pdata->set_backlight(mfd);
mfd->bl_level = bkl_lvl;
bl_level_old = temp;
- up(&mfd->sem);
}
}
@@ -2957,6 +2961,19 @@
return ret;
}
+static int msmfb_overlay_commit(struct fb_info *info, unsigned long *argp)
+{
+ int ret, ndx;
+
+ ret = copy_from_user(&ndx, argp, sizeof(ndx));
+ if (ret) {
+ pr_err("%s: ioctl failed\n", __func__);
+ return ret;
+ }
+
+ return mdp4_overlay_commit(info, ndx);
+}
+
static int msmfb_overlay_play(struct fb_info *info, unsigned long *argp)
{
int ret;
@@ -3376,49 +3393,36 @@
switch (cmd) {
#ifdef CONFIG_FB_MSM_OVERLAY
case MSMFB_OVERLAY_GET:
- down(&msm_fb_ioctl_ppp_sem);
ret = msmfb_overlay_get(info, argp);
- up(&msm_fb_ioctl_ppp_sem);
break;
case MSMFB_OVERLAY_SET:
- down(&msm_fb_ioctl_ppp_sem);
ret = msmfb_overlay_set(info, argp);
- up(&msm_fb_ioctl_ppp_sem);
break;
case MSMFB_OVERLAY_UNSET:
- down(&msm_fb_ioctl_ppp_sem);
ret = msmfb_overlay_unset(info, argp);
+ break;
+ case MSMFB_OVERLAY_COMMIT:
+ down(&msm_fb_ioctl_ppp_sem);
+ ret = msmfb_overlay_commit(info, argp);
up(&msm_fb_ioctl_ppp_sem);
break;
case MSMFB_OVERLAY_PLAY:
- down(&msm_fb_ioctl_ppp_sem);
ret = msmfb_overlay_play(info, argp);
- up(&msm_fb_ioctl_ppp_sem);
break;
case MSMFB_OVERLAY_PLAY_ENABLE:
- down(&msm_fb_ioctl_ppp_sem);
ret = msmfb_overlay_play_enable(info, argp);
- up(&msm_fb_ioctl_ppp_sem);
break;
case MSMFB_OVERLAY_PLAY_WAIT:
- down(&msm_fb_ioctl_ppp_sem);
ret = msmfb_overlay_play_wait(info, argp);
- up(&msm_fb_ioctl_ppp_sem);
break;
case MSMFB_OVERLAY_BLT:
- down(&msm_fb_ioctl_ppp_sem);
ret = msmfb_overlay_blt(info, argp);
- up(&msm_fb_ioctl_ppp_sem);
break;
case MSMFB_OVERLAY_3D:
- down(&msm_fb_ioctl_ppp_sem);
ret = msmfb_overlay_3d_sbys(info, argp);
- up(&msm_fb_ioctl_ppp_sem);
break;
case MSMFB_MIXER_INFO:
- down(&msm_fb_ioctl_ppp_sem);
ret = msmfb_mixer_info(info, argp);
- up(&msm_fb_ioctl_ppp_sem);
break;
case MSMFB_WRITEBACK_INIT:
ret = msmfb_overlay_ioctl_writeback_init(info);
diff --git a/drivers/video/msm/msm_fb_bl.c b/drivers/video/msm/msm_fb_bl.c
index 9afbbf1..b21adee 100644
--- a/drivers/video/msm/msm_fb_bl.c
+++ b/drivers/video/msm/msm_fb_bl.c
@@ -34,7 +34,9 @@
bl_lvl = pbd->props.brightness;
bl_lvl = mfd->fbi->bl_curve[bl_lvl];
+ down(&mfd->sem);
msm_fb_set_backlight(mfd, bl_lvl);
+ up(&mfd->sem);
return 0;
}
diff --git a/drivers/video/msm/vidc/1080p/resource_tracker/vcd_res_tracker.c b/drivers/video/msm/vidc/1080p/resource_tracker/vcd_res_tracker.c
index f68802e..3670dc81 100644
--- a/drivers/video/msm/vidc/1080p/resource_tracker/vcd_res_tracker.c
+++ b/drivers/video/msm/vidc/1080p/resource_tracker/vcd_res_tracker.c
@@ -27,8 +27,8 @@
#define PIL_FW_SIZE 0x200000
-static unsigned int vidc_clk_table[4] = {
- 48000000, 133330000, 200000000, 228570000,
+static unsigned int vidc_clk_table[5] = {
+ 48000000, 133330000, 200000000, 228570000, 266670000,
};
static unsigned int restrk_mmu_subsystem[] = {
MSM_SUBSYSTEM_VIDEO, MSM_SUBSYSTEM_VIDEO_FWARE};
@@ -629,7 +629,7 @@
vidc_freq = vidc_clk_table[2];
*pn_set_perf_lvl = RESTRK_1080P_MAX_PERF_LEVEL;
} else {
- vidc_freq = vidc_clk_table[3];
+ vidc_freq = vidc_clk_table[4];
*pn_set_perf_lvl = RESTRK_1080P_TURBO_PERF_LEVEL;
}
@@ -650,6 +650,10 @@
VCDRES_MSG_MED("%s(): Setting vidc freq to %u\n",
__func__, vidc_freq);
if (!res_trk_sel_clk_rate(vidc_freq)) {
+ if (vidc_freq == vidc_clk_table[4]) {
+ if (res_trk_sel_clk_rate(vidc_clk_table[3]))
+ goto ret;
+ }
VCDRES_MSG_ERROR("%s(): res_trk_sel_clk_rate FAILED\n",
__func__);
*pn_set_perf_lvl = 0;
@@ -657,7 +661,7 @@
}
}
#endif
- VCDRES_MSG_MED("%s() set perl level : %d", __func__, *pn_set_perf_lvl);
+ret: VCDRES_MSG_MED("%s() set perl level : %d", __func__, *pn_set_perf_lvl);
return true;
}
diff --git a/include/linux/i2c/atmel_mxt_ts.h b/include/linux/i2c/atmel_mxt_ts.h
index 5c3c728..348a231 100644
--- a/include/linux/i2c/atmel_mxt_ts.h
+++ b/include/linux/i2c/atmel_mxt_ts.h
@@ -73,6 +73,7 @@
int irq_gpio;
u32 irq_gpio_flags;
int *key_codes;
+ bool need_calibration;
u8(*read_chg) (void);
int (*init_hw) (bool);
diff --git a/include/linux/ion.h b/include/linux/ion.h
index 85bb182..85e5002 100644
--- a/include/linux/ion.h
+++ b/include/linux/ion.h
@@ -39,8 +39,6 @@
ION_HEAP_TYPE_SYSTEM,
ION_HEAP_TYPE_SYSTEM_CONTIG,
ION_HEAP_TYPE_CARVEOUT,
- ION_HEAP_TYPE_IOMMU,
- ION_HEAP_TYPE_CP,
ION_HEAP_TYPE_CUSTOM, /* must be last so device specific heaps always
are at the end of this enum */
ION_NUM_HEAPS,
@@ -49,7 +47,6 @@
#define ION_HEAP_SYSTEM_MASK (1 << ION_HEAP_TYPE_SYSTEM)
#define ION_HEAP_SYSTEM_CONTIG_MASK (1 << ION_HEAP_TYPE_SYSTEM_CONTIG)
#define ION_HEAP_CARVEOUT_MASK (1 << ION_HEAP_TYPE_CARVEOUT)
-#define ION_HEAP_CP_MASK (1 << ION_HEAP_TYPE_CP)
/**
* heap flags - the lower 16 bits are used by core ion, the upper 16
@@ -60,81 +57,6 @@
maintenance when the buffer is
mapped for dma */
-/**
- * These are the only ids that should be used for Ion heap ids.
- * The ids listed are the order in which allocation will be attempted
- * if specified. Don't swap the order of heap ids unless you know what
- * you are doing!
- * Id's are spaced by purpose to allow new Id's to be inserted in-between (for
- * possible fallbacks)
- */
-
-enum ion_heap_ids {
- INVALID_HEAP_ID = -1,
- ION_CP_MM_HEAP_ID = 8,
- ION_CP_MFC_HEAP_ID = 12,
- ION_CP_WB_HEAP_ID = 16, /* 8660 only */
- ION_CAMERA_HEAP_ID = 20, /* 8660 only */
- ION_SF_HEAP_ID = 24,
- ION_IOMMU_HEAP_ID = 25,
- ION_QSECOM_HEAP_ID = 27,
- ION_AUDIO_HEAP_ID = 28,
-
- ION_MM_FIRMWARE_HEAP_ID = 29,
- ION_SYSTEM_HEAP_ID = 30,
-
- ION_HEAP_ID_RESERVED = 31 /** Bit reserved for ION_SECURE flag */
-};
-
-enum ion_fixed_position {
- NOT_FIXED,
- FIXED_LOW,
- FIXED_MIDDLE,
- FIXED_HIGH,
-};
-
-enum cp_mem_usage {
- VIDEO_BITSTREAM = 0x1,
- VIDEO_PIXEL = 0x2,
- VIDEO_NONPIXEL = 0x3,
- MAX_USAGE = 0x4,
- UNKNOWN = 0x7FFFFFFF,
-};
-
-/**
- * Flag to use when allocating to indicate that a heap is secure.
- */
-#define ION_SECURE (1 << ION_HEAP_ID_RESERVED)
-
-/**
- * Macro should be used with ion_heap_ids defined above.
- */
-#define ION_HEAP(bit) (1 << (bit))
-
-#define ION_VMALLOC_HEAP_NAME "vmalloc"
-#define ION_AUDIO_HEAP_NAME "audio"
-#define ION_SF_HEAP_NAME "sf"
-#define ION_MM_HEAP_NAME "mm"
-#define ION_CAMERA_HEAP_NAME "camera_preview"
-#define ION_IOMMU_HEAP_NAME "iommu"
-#define ION_MFC_HEAP_NAME "mfc"
-#define ION_WB_HEAP_NAME "wb"
-#define ION_MM_FIRMWARE_HEAP_NAME "mm_fw"
-#define ION_QSECOM_HEAP_NAME "qsecom"
-#define ION_FMEM_HEAP_NAME "fmem"
-
-#define ION_SET_CACHED(__cache) (__cache | ION_FLAG_CACHED)
-#define ION_SET_UNCACHED(__cache) (__cache & ~ION_FLAG_CACHED)
-
-#define ION_IS_CACHED(__flags) ((__flags) & ION_FLAG_CACHED)
-
-
-/*
- * This flag allows clients when mapping into the IOMMU to specify to
- * defer un-mapping from the IOMMU until the buffer memory is freed.
- */
-#define ION_IOMMU_UNMAP_DELAYED 1
-
#ifdef __KERNEL__
#include <linux/err.h>
#include <mach/ion.h>
@@ -175,72 +97,6 @@
};
/**
- * struct ion_cp_heap_pdata - defines a content protection heap in the given
- * platform
- * @permission_type: Memory ID used to identify the memory to TZ
- * @align: Alignment requirement for the memory
- * @secure_base: Base address for securing the heap.
- * Note: This might be different from actual base address
- * of this heap in the case of a shared heap.
- * @secure_size: Memory size for securing the heap.
- * Note: This might be different from actual size
- * of this heap in the case of a shared heap.
- * @reusable Flag indicating whether this heap is reusable of not.
- * (see FMEM)
- * @mem_is_fmem Flag indicating whether this memory is coming from fmem
- * or not.
- * @fixed_position If nonzero, position in the fixed area.
- * @virt_addr: Virtual address used when using fmem.
- * @iommu_map_all: Indicates whether we should map whole heap into IOMMU.
- * @iommu_2x_map_domain: Indicates the domain to use for overmapping.
- * @request_region: function to be called when the number of allocations
- * goes from 0 -> 1
- * @release_region: function to be called when the number of allocations
- * goes from 1 -> 0
- * @setup_region: function to be called upon ion registration
- *
- */
-struct ion_cp_heap_pdata {
- enum ion_permission_type permission_type;
- unsigned int align;
- ion_phys_addr_t secure_base; /* Base addr used when heap is shared */
- size_t secure_size; /* Size used for securing heap when heap is shared*/
- int reusable;
- int mem_is_fmem;
- enum ion_fixed_position fixed_position;
- int iommu_map_all;
- int iommu_2x_map_domain;
- ion_virt_addr_t *virt_addr;
- int (*request_region)(void *);
- int (*release_region)(void *);
- void *(*setup_region)(void);
-};
-
-/**
- * struct ion_co_heap_pdata - defines a carveout heap in the given platform
- * @adjacent_mem_id: Id of heap that this heap must be adjacent to.
- * @align: Alignment requirement for the memory
- * @mem_is_fmem Flag indicating whether this memory is coming from fmem
- * or not.
- * @fixed_position If nonzero, position in the fixed area.
- * @request_region: function to be called when the number of allocations
- * goes from 0 -> 1
- * @release_region: function to be called when the number of allocations
- * goes from 1 -> 0
- * @setup_region: function to be called upon ion registration
- *
- */
-struct ion_co_heap_pdata {
- int adjacent_mem_id;
- unsigned int align;
- int mem_is_fmem;
- enum ion_fixed_position fixed_position;
- int (*request_region)(void *);
- int (*release_region)(void *);
- void *(*setup_region)(void);
-};
-
-/**
* struct ion_platform_data - array of platform heaps passed from board file
* @has_outer_cache: set to 1 if outer cache is used, 0 otherwise.
* @nr: number of structures in the array
@@ -426,6 +282,7 @@
* address space will be mapped to a dummy buffer.
* @iova - pointer to store the iova address
* @buffer_size - pointer to store the size of the buffer
+ * @flags - flags for options to map
* @iommu_flags - flags specific to the iommu.
*
* Maps the handle into the iova space specified via domain number. Iova
@@ -500,50 +357,6 @@
void *data);
/**
- * msm_ion_secure_heap - secure a heap. Wrapper around ion_secure_heap.
- *
- * @heap_id - heap id to secure.
- *
- * Secure a heap
- * Returns 0 on success
- */
-int msm_ion_secure_heap(int heap_id);
-
-/**
- * msm_ion_unsecure_heap - unsecure a heap. Wrapper around ion_unsecure_heap.
- *
- * @heap_id - heap id to secure.
- *
- * Un-secure a heap
- * Returns 0 on success
- */
-int msm_ion_unsecure_heap(int heap_id);
-
-/**
- * msm_ion_secure_heap_2_0 - secure a heap using 2.0 APIs
- * Wrapper around ion_secure_heap.
- *
- * @heap_id - heap id to secure.
- * @usage - usage hint to TZ
- *
- * Secure a heap
- * Returns 0 on success
- */
-int msm_ion_secure_heap_2_0(int heap_id, enum cp_mem_usage usage);
-
-/**
- * msm_ion_unsecure_heap - unsecure a heap secured with 3.0 APIs.
- * Wrapper around ion_unsecure_heap.
- *
- * @heap_id - heap id to secure.
- * @usage - usage hint to TZ
- *
- * Un-secure a heap
- * Returns 0 on success
- */
-int msm_ion_unsecure_heap_2_0(int heap_id, enum cp_mem_usage usage);
-
-/**
* msm_ion_do_cache_op - do cache operations.
*
* @client - pointer to ION client.
@@ -660,28 +473,6 @@
return -ENODEV;
}
-static inline int msm_ion_secure_heap(int heap_id)
-{
- return -ENODEV;
-
-}
-
-static inline int msm_ion_unsecure_heap(int heap_id)
-{
- return -ENODEV;
-}
-
-static inline int msm_ion_secure_heap_2_0(int heap_id, enum cp_mem_usage usage)
-{
- return -ENODEV;
-}
-
-static inline int msm_ion_unsecure_heap_2_0(int heap_id,
- enum cp_mem_usage usage)
-{
- return -ENODEV;
-}
-
static inline int msm_ion_do_cache_op(struct ion_client *client,
struct ion_handle *handle, void *vaddr,
unsigned long len, unsigned int cmd)
@@ -754,41 +545,6 @@
unsigned int cmd;
unsigned long arg;
};
-
-
-/* struct ion_flush_data - data passed to ion for flushing caches
- *
- * @handle: handle with data to flush
- * @fd: fd to flush
- * @vaddr: userspace virtual address mapped with mmap
- * @offset: offset into the handle to flush
- * @length: length of handle to flush
- *
- * Performs cache operations on the handle. If p is the start address
- * of the handle, p + offset through p + offset + length will have
- * the cache operations performed
- */
-struct ion_flush_data {
- struct ion_handle *handle;
- int fd;
- void *vaddr;
- unsigned int offset;
- unsigned int length;
-};
-
-/* struct ion_flag_data - information about flags for this buffer
- *
- * @handle: handle to get flags from
- * @flags: flags of this handle
- *
- * Takes handle as an input and outputs the flags from the handle
- * in the flag field.
- */
-struct ion_flag_data {
- struct ion_handle *handle;
- unsigned long flags;
-};
-
#define ION_IOC_MAGIC 'I'
/**
@@ -846,34 +602,4 @@
#define ION_IOC_CUSTOM _IOWR(ION_IOC_MAGIC, 6, struct ion_custom_data)
-/**
- * DOC: ION_IOC_CLEAN_CACHES - clean the caches
- *
- * Clean the caches of the handle specified.
- */
-#define ION_IOC_CLEAN_CACHES _IOWR(ION_IOC_MAGIC, 20, \
- struct ion_flush_data)
-/**
- * DOC: ION_MSM_IOC_INV_CACHES - invalidate the caches
- *
- * Invalidate the caches of the handle specified.
- */
-#define ION_IOC_INV_CACHES _IOWR(ION_IOC_MAGIC, 21, \
- struct ion_flush_data)
-/**
- * DOC: ION_MSM_IOC_CLEAN_CACHES - clean and invalidate the caches
- *
- * Clean and invalidate the caches of the handle specified.
- */
-#define ION_IOC_CLEAN_INV_CACHES _IOWR(ION_IOC_MAGIC, 22, \
- struct ion_flush_data)
-
-/**
- * DOC: ION_IOC_GET_FLAGS - get the flags of the handle
- *
- * Gets the flags of the current handle which indicate cachability,
- * secure state etc.
- */
-#define ION_IOC_GET_FLAGS _IOWR(ION_IOC_MAGIC, 23, \
- struct ion_flag_data)
#endif /* _LINUX_ION_H */
diff --git a/include/linux/mfd/pm8xxx/batterydata-lib.h b/include/linux/mfd/pm8xxx/batterydata-lib.h
new file mode 100644
index 0000000..c55e47e
--- /dev/null
+++ b/include/linux/mfd/pm8xxx/batterydata-lib.h
@@ -0,0 +1,155 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __PM8XXX_BMS_BATTERYDATA_H
+#define __PM8XXX_BMS_BATTERYDATA_H
+
+#include <linux/errno.h>
+
+#define FCC_CC_COLS 5
+#define FCC_TEMP_COLS 8
+
+#define PC_CC_ROWS 29
+#define PC_CC_COLS 13
+
+#define PC_TEMP_ROWS 29
+#define PC_TEMP_COLS 8
+
+#define MAX_SINGLE_LUT_COLS 20
+
+struct single_row_lut {
+ int x[MAX_SINGLE_LUT_COLS];
+ int y[MAX_SINGLE_LUT_COLS];
+ int cols;
+};
+
+/**
+ * struct sf_lut -
+ * @rows: number of percent charge entries should be <= PC_CC_ROWS
+ * @cols: number of charge cycle entries should be <= PC_CC_COLS
+ * @row_entries: the charge cycles/temperature at which sf data
+ * is available in the table.
+ * The charge cycles must be in increasing order from 0 to rows.
+ * @percent: the percent charge at which sf data is available in the table
+ * The percentcharge must be in decreasing order from 0 to cols.
+ * @sf: the scaling factor data
+ */
+struct sf_lut {
+ int rows;
+ int cols;
+ int row_entries[PC_CC_COLS];
+ int percent[PC_CC_ROWS];
+ int sf[PC_CC_ROWS][PC_CC_COLS];
+};
+
+/**
+ * struct pc_temp_ocv_lut -
+ * @rows: number of percent charge entries should be <= PC_TEMP_ROWS
+ * @cols: number of temperature entries should be <= PC_TEMP_COLS
+ * @temp: the temperatures at which ocv data is available in the table
+ * The temperatures must be in increasing order from 0 to rows.
+ * @percent: the percent charge at which ocv data is available in the table
+ * The percentcharge must be in decreasing order from 0 to cols.
+ * @ocv: the open circuit voltage
+ */
+struct pc_temp_ocv_lut {
+ int rows;
+ int cols;
+ int temp[PC_TEMP_COLS];
+ int percent[PC_TEMP_ROWS];
+ int ocv[PC_TEMP_ROWS][PC_TEMP_COLS];
+};
+
+enum battery_type {
+ BATT_UNKNOWN = 0,
+ BATT_PALLADIUM,
+ BATT_DESAY,
+};
+
+/**
+ * struct bms_battery_data -
+ * @fcc: full charge capacity (mAmpHour)
+ * @fcc_temp_lut: table to get fcc at a given temp
+ * @pc_temp_ocv_lut: table to get percent charge given batt temp and cycles
+ * @pc_sf_lut: table to get percent charge scaling factor given cycles
+ * and percent charge
+ * @rbatt_sf_lut: table to get battery resistance scaling factor given
+ * temperature and percent charge
+ * @default_rbatt_mohm: the default value of battery resistance to use when
+ * readings from bms are not available.
+ * @delta_rbatt_mohm: the resistance to be added towards lower soc to
+ * compensate for battery capacitance.
+ */
+
+struct bms_battery_data {
+ unsigned int fcc;
+ struct single_row_lut *fcc_temp_lut;
+ struct single_row_lut *fcc_sf_lut;
+ struct pc_temp_ocv_lut *pc_temp_ocv_lut;
+ struct sf_lut *pc_sf_lut;
+ struct sf_lut *rbatt_sf_lut;
+ int default_rbatt_mohm;
+ int delta_rbatt_mohm;
+};
+
+#if defined(CONFIG_PM8921_BMS) || \
+ defined(CONFIG_PM8921_BMS_MODULE)
+extern struct bms_battery_data palladium_1500_data;
+extern struct bms_battery_data desay_5200_data;
+
+int interpolate_fcc(struct single_row_lut *fcc_temp_lut, int batt_temp);
+int interpolate_scalingfactor(struct sf_lut *sf_lut, int row_entry, int pc);
+int interpolate_scalingfactor_fcc(struct single_row_lut *fcc_sf_lut,
+ int cycles);
+int interpolate_pc(struct pc_temp_ocv_lut *pc_temp_ocv,
+ int batt_temp_degc, int ocv);
+int interpolate_ocv(struct pc_temp_ocv_lut *pc_temp_ocv,
+ int batt_temp_degc, int pc);
+int linear_interpolate(int y0, int x0, int y1, int x1, int x);
+int is_between(int left, int right, int value);
+#else
+static inline int interpolate_fcc(struct single_row_lut *fcc_temp_lut,
+ int batt_temp)
+{
+ return -EINVAL;
+}
+static inline int interpolate_scalingfactor(struct sf_lut *sf_lut,
+ int row_entry, int pc)
+{
+ return -EINVAL;
+}
+static inline int interpolate_scalingfactor_fcc(
+ struct single_row_lut *fcc_sf_lut, int cycles)
+{
+ return -EINVAL;
+}
+static inline int interpolate_pc(struct pc_temp_ocv_lut *pc_temp_ocv,
+ int batt_temp_degc, int ocv)
+{
+ return -EINVAL;
+}
+static inline int interpolate_ocv(struct pc_temp_ocv_lut *pc_temp_ocv,
+ int batt_temp_degc, int pc)
+{
+ return -EINVAL;
+}
+static inline int linear_interpolate(int y0, int x0, int y1, int x1, int x)
+{
+ return -EINVAL;
+}
+static inline int is_between(int left, int right, int value)
+{
+ return -EINVAL;
+}
+#endif
+
+#endif
diff --git a/include/linux/mfd/pm8xxx/pm8921-bms.h b/include/linux/mfd/pm8xxx/pm8921-bms.h
index a73a284..5f2fe9f 100644
--- a/include/linux/mfd/pm8xxx/pm8921-bms.h
+++ b/include/linux/mfd/pm8xxx/pm8921-bms.h
@@ -14,87 +14,10 @@
#define __PM8XXX_BMS_H
#include <linux/errno.h>
+#include <linux/mfd/pm8xxx/batterydata-lib.h>
#define PM8921_BMS_DEV_NAME "pm8921-bms"
-#define FCC_CC_COLS 5
-#define FCC_TEMP_COLS 8
-
-#define PC_CC_ROWS 29
-#define PC_CC_COLS 13
-
-#define PC_TEMP_ROWS 29
-#define PC_TEMP_COLS 8
-
-#define MAX_SINGLE_LUT_COLS 20
-
-struct single_row_lut {
- int x[MAX_SINGLE_LUT_COLS];
- int y[MAX_SINGLE_LUT_COLS];
- int cols;
-};
-
-/**
- * struct sf_lut -
- * @rows: number of percent charge entries should be <= PC_CC_ROWS
- * @cols: number of charge cycle entries should be <= PC_CC_COLS
- * @row_entries: the charge cycles/temperature at which sf data
- * is available in the table.
- * The charge cycles must be in increasing order from 0 to rows.
- * @percent: the percent charge at which sf data is available in the table
- * The percentcharge must be in decreasing order from 0 to cols.
- * @sf: the scaling factor data
- */
-struct sf_lut {
- int rows;
- int cols;
- int row_entries[PC_CC_COLS];
- int percent[PC_CC_ROWS];
- int sf[PC_CC_ROWS][PC_CC_COLS];
-};
-
-/**
- * struct pc_temp_ocv_lut -
- * @rows: number of percent charge entries should be <= PC_TEMP_ROWS
- * @cols: number of temperature entries should be <= PC_TEMP_COLS
- * @temp: the temperatures at which ocv data is available in the table
- * The temperatures must be in increasing order from 0 to rows.
- * @percent: the percent charge at which ocv data is available in the table
- * The percentcharge must be in decreasing order from 0 to cols.
- * @ocv: the open circuit voltage
- */
-struct pc_temp_ocv_lut {
- int rows;
- int cols;
- int temp[PC_TEMP_COLS];
- int percent[PC_TEMP_ROWS];
- int ocv[PC_TEMP_ROWS][PC_TEMP_COLS];
-};
-
-/**
- * struct pm8921_bms_battery_data -
- * @fcc: full charge capacity (mAmpHour)
- * @fcc_temp_lut: table to get fcc at a given temp
- * @pc_temp_ocv_lut: table to get percent charge given batt temp and cycles
- * @pc_sf_lut: table to get percent charge scaling factor given cycles
- * and percent charge
- * @rbatt_sf_lut: table to get battery resistance scaling factor given
- * temperature and percent charge
- * @default_rbatt_mohm: the default value of battery resistance to use when
- * readings from bms are not available.
- * @delta_rbatt_mohm: the resistance to be added towards lower soc to
- * compensate for battery capacitance.
- */
-struct pm8921_bms_battery_data {
- unsigned int fcc;
- struct single_row_lut *fcc_temp_lut;
- struct single_row_lut *fcc_sf_lut;
- struct pc_temp_ocv_lut *pc_temp_ocv_lut;
- struct sf_lut *pc_sf_lut;
- struct sf_lut *rbatt_sf_lut;
- int default_rbatt_mohm;
- int delta_rbatt_mohm;
-};
struct pm8xxx_bms_core_data {
unsigned int batt_temp_channel;
@@ -104,12 +27,6 @@
unsigned int batt_id_channel;
};
-enum battery_type {
- BATT_UNKNOWN = 0,
- BATT_PALLADIUM,
- BATT_DESAY,
-};
-
/**
* struct pm8921_bms_platform_data -
* @batt_type: allows to force chose battery calibration data
@@ -137,8 +54,6 @@
};
#if defined(CONFIG_PM8921_BMS) || defined(CONFIG_PM8921_BMS_MODULE)
-extern struct pm8921_bms_battery_data palladium_1500_data;
-extern struct pm8921_bms_battery_data desay_5200_data;
/**
* pm8921_bms_get_vsense_avg - return the voltage across the sense
* resitor in microvolts
diff --git a/include/linux/mmc/card.h b/include/linux/mmc/card.h
index 3b379ba..0330dfb 100644
--- a/include/linux/mmc/card.h
+++ b/include/linux/mmc/card.h
@@ -53,6 +53,9 @@
u8 part_config;
u8 cache_ctrl;
u8 rst_n_function;
+ u8 max_packed_writes;
+ u8 max_packed_reads;
+ u8 packed_event_en;
unsigned int part_time; /* Units: ms */
unsigned int sa_timeout; /* Units: 100ns */
unsigned int generic_cmd6_time; /* Units: 10ms */
@@ -297,6 +300,11 @@
card->nr_parts++;
}
+static inline bool mmc_large_sec(struct mmc_card *card)
+{
+ return card->ext_csd.data_sector_size == 4096;
+}
+
/*
* The world is not perfect and supplies us with broken mmc/sdio devices.
* For at least some of these bugs we need a work-around.
diff --git a/include/linux/mmc/core.h b/include/linux/mmc/core.h
index 7a45622..3f26a80 100644
--- a/include/linux/mmc/core.h
+++ b/include/linux/mmc/core.h
@@ -18,6 +18,9 @@
struct mmc_command {
u32 opcode;
u32 arg;
+#define MMC_CMD23_ARG_REL_WR (1 << 31)
+#define MMC_CMD23_ARG_PACKED ((0 << 31) | (1 << 30))
+#define MMC_CMD23_ARG_TAG_REQ (1 << 29)
u32 resp[4];
unsigned int flags; /* expected response type */
#define MMC_RSP_PRESENT (1 << 0)
@@ -148,6 +151,7 @@
extern void mmc_start_bkops(struct mmc_card *card, bool from_exception);
extern int __mmc_switch(struct mmc_card *, u8, u8, u8, unsigned int, bool);
extern int mmc_switch(struct mmc_card *, u8, u8, u8, unsigned int);
+extern int mmc_send_ext_csd(struct mmc_card *card, u8 *ext_csd);
#define MMC_ERASE_ARG 0x00000000
#define MMC_SECURE_ERASE_ARG 0x80000000
diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h
index dcdcd58..714cc76 100644
--- a/include/linux/mmc/host.h
+++ b/include/linux/mmc/host.h
@@ -241,6 +241,10 @@
#define MMC_CAP2_BROKEN_VOLTAGE (1 << 7) /* Use the broken voltage */
#define MMC_CAP2_DETECT_ON_ERR (1 << 8) /* On I/O err check card removal */
#define MMC_CAP2_HC_ERASE_SZ (1 << 9) /* High-capacity erase size */
+#define MMC_CAP2_PACKED_RD (1 << 10) /* Allow packed read */
+#define MMC_CAP2_PACKED_WR (1 << 11) /* Allow packed write */
+#define MMC_CAP2_PACKED_CMD (MMC_CAP2_PACKED_RD | \
+ MMC_CAP2_PACKED_WR) /* Allow packed commands */
#define MMC_CAP2_SANITIZE (1 << 13) /* Support Sanitize */
#define MMC_CAP2_INIT_BKOPS (1 << 15) /* Need to set BKOPS_EN */
#define MMC_CAP2_POWER_OFF_VCCQ_DURING_SUSPEND (1 << 16)
diff --git a/include/linux/mmc/mmc.h b/include/linux/mmc/mmc.h
index 2cf8119..92888c3 100644
--- a/include/linux/mmc/mmc.h
+++ b/include/linux/mmc/mmc.h
@@ -276,6 +276,8 @@
#define EXT_CSD_FLUSH_CACHE 32 /* W */
#define EXT_CSD_CACHE_CTRL 33 /* R/W */
#define EXT_CSD_POWER_OFF_NOTIFICATION 34 /* R/W */
+#define EXT_CSD_PACKED_FAILURE_INDEX 35 /* RO */
+#define EXT_CSD_PACKED_CMD_STATUS 36 /* RO */
#define EXT_CSD_EXP_EVENTS_STATUS 54 /* RO, 2 bytes */
#define EXT_CSD_EXP_EVENTS_CTRL 56 /* R/W, 2 bytes */
#define EXT_CSD_DATA_SECTOR_SIZE 61 /* R */
@@ -325,6 +327,8 @@
#define EXT_CSD_CACHE_SIZE 249 /* RO, 4 bytes */
#define EXT_CSD_TAG_UNIT_SIZE 498 /* RO */
#define EXT_CSD_DATA_TAG_SUPPORT 499 /* RO */
+#define EXT_CSD_MAX_PACKED_WRITES 500 /* RO */
+#define EXT_CSD_MAX_PACKED_READS 501 /* RO */
#define EXT_CSD_BKOPS_SUPPORT 502 /* RO */
#define EXT_CSD_HPI_FEATURES 503 /* RO */
@@ -407,6 +411,13 @@
*/
#define EXT_CSD_BKOPS_LEVEL_2 0x2
+#define EXT_CSD_PACKED_EVENT_EN (1 << 3)
+
+#define EXT_CSD_PACKED_FAILURE (1 << 3)
+
+#define EXT_CSD_PACKED_GENERIC_ERROR (1 << 0)
+#define EXT_CSD_PACKED_INDEXED_ERROR (1 << 1)
+
/*
* MMC_SWITCH access modes
*/
diff --git a/include/linux/msm_ion.h b/include/linux/msm_ion.h
index e7959d1..21000f9 100644
--- a/include/linux/msm_ion.h
+++ b/include/linux/msm_ion.h
@@ -18,4 +18,294 @@
#include <linux/ion.h>
+enum msm_ion_heap_types {
+ ION_HEAP_TYPE_MSM_START = ION_HEAP_TYPE_CUSTOM + 1,
+ ION_HEAP_TYPE_IOMMU = ION_HEAP_TYPE_MSM_START,
+ ION_HEAP_TYPE_CP,
+};
+
+/**
+ * These are the only ids that should be used for Ion heap ids.
+ * The ids listed are the order in which allocation will be attempted
+ * if specified. Don't swap the order of heap ids unless you know what
+ * you are doing!
+ * Id's are spaced by purpose to allow new Id's to be inserted in-between (for
+ * possible fallbacks)
+ */
+
+enum ion_heap_ids {
+ INVALID_HEAP_ID = -1,
+ ION_CP_MM_HEAP_ID = 8,
+ ION_CP_MFC_HEAP_ID = 12,
+ ION_CP_WB_HEAP_ID = 16, /* 8660 only */
+ ION_CAMERA_HEAP_ID = 20, /* 8660 only */
+ ION_SF_HEAP_ID = 24,
+ ION_IOMMU_HEAP_ID = 25,
+ ION_QSECOM_HEAP_ID = 27,
+ ION_AUDIO_HEAP_ID = 28,
+
+ ION_MM_FIRMWARE_HEAP_ID = 29,
+ ION_SYSTEM_HEAP_ID = 30,
+
+ ION_HEAP_ID_RESERVED = 31 /** Bit reserved for ION_SECURE flag */
+};
+
+enum ion_fixed_position {
+ NOT_FIXED,
+ FIXED_LOW,
+ FIXED_MIDDLE,
+ FIXED_HIGH,
+};
+
+enum cp_mem_usage {
+ VIDEO_BITSTREAM = 0x1,
+ VIDEO_PIXEL = 0x2,
+ VIDEO_NONPIXEL = 0x3,
+ MAX_USAGE = 0x4,
+ UNKNOWN = 0x7FFFFFFF,
+};
+
+#define ION_HEAP_CP_MASK (1 << ION_HEAP_TYPE_CP)
+
+/**
+ * Flag to use when allocating to indicate that a heap is secure.
+ */
+#define ION_SECURE (1 << ION_HEAP_ID_RESERVED)
+
+/**
+ * Macro should be used with ion_heap_ids defined above.
+ */
+#define ION_HEAP(bit) (1 << (bit))
+
+#define ION_VMALLOC_HEAP_NAME "vmalloc"
+#define ION_AUDIO_HEAP_NAME "audio"
+#define ION_SF_HEAP_NAME "sf"
+#define ION_MM_HEAP_NAME "mm"
+#define ION_CAMERA_HEAP_NAME "camera_preview"
+#define ION_IOMMU_HEAP_NAME "iommu"
+#define ION_MFC_HEAP_NAME "mfc"
+#define ION_WB_HEAP_NAME "wb"
+#define ION_MM_FIRMWARE_HEAP_NAME "mm_fw"
+#define ION_QSECOM_HEAP_NAME "qsecom"
+#define ION_FMEM_HEAP_NAME "fmem"
+
+#define ION_SET_CACHED(__cache) (__cache | ION_FLAG_CACHED)
+#define ION_SET_UNCACHED(__cache) (__cache & ~ION_FLAG_CACHED)
+
+#define ION_IS_CACHED(__flags) ((__flags) & ION_FLAG_CACHED)
+
+#ifdef __KERNEL__
+
+/*
+ * This flag allows clients when mapping into the IOMMU to specify to
+ * defer un-mapping from the IOMMU until the buffer memory is freed.
+ */
+#define ION_IOMMU_UNMAP_DELAYED 1
+
+/**
+ * struct ion_cp_heap_pdata - defines a content protection heap in the given
+ * platform
+ * @permission_type: Memory ID used to identify the memory to TZ
+ * @align: Alignment requirement for the memory
+ * @secure_base: Base address for securing the heap.
+ * Note: This might be different from actual base address
+ * of this heap in the case of a shared heap.
+ * @secure_size: Memory size for securing the heap.
+ * Note: This might be different from actual size
+ * of this heap in the case of a shared heap.
+ * @reusable Flag indicating whether this heap is reusable of not.
+ * (see FMEM)
+ * @mem_is_fmem Flag indicating whether this memory is coming from fmem
+ * or not.
+ * @fixed_position If nonzero, position in the fixed area.
+ * @virt_addr: Virtual address used when using fmem.
+ * @iommu_map_all: Indicates whether we should map whole heap into IOMMU.
+ * @iommu_2x_map_domain: Indicates the domain to use for overmapping.
+ * @request_region: function to be called when the number of allocations
+ * goes from 0 -> 1
+ * @release_region: function to be called when the number of allocations
+ * goes from 1 -> 0
+ * @setup_region: function to be called upon ion registration
+ * @memory_type:Memory type used for the heap
+ *
+ */
+struct ion_cp_heap_pdata {
+ enum ion_permission_type permission_type;
+ unsigned int align;
+ ion_phys_addr_t secure_base; /* Base addr used when heap is shared */
+ size_t secure_size; /* Size used for securing heap when heap is shared*/
+ int reusable;
+ int mem_is_fmem;
+ enum ion_fixed_position fixed_position;
+ int iommu_map_all;
+ int iommu_2x_map_domain;
+ ion_virt_addr_t *virt_addr;
+ int (*request_region)(void *);
+ int (*release_region)(void *);
+ void *(*setup_region)(void);
+ enum ion_memory_types memory_type;
+};
+
+/**
+ * struct ion_co_heap_pdata - defines a carveout heap in the given platform
+ * @adjacent_mem_id: Id of heap that this heap must be adjacent to.
+ * @align: Alignment requirement for the memory
+ * @mem_is_fmem Flag indicating whether this memory is coming from fmem
+ * or not.
+ * @fixed_position If nonzero, position in the fixed area.
+ * @request_region: function to be called when the number of allocations
+ * goes from 0 -> 1
+ * @release_region: function to be called when the number of allocations
+ * goes from 1 -> 0
+ * @setup_region: function to be called upon ion registration
+ * @memory_type:Memory type used for the heap
+ *
+ */
+struct ion_co_heap_pdata {
+ int adjacent_mem_id;
+ unsigned int align;
+ int mem_is_fmem;
+ enum ion_fixed_position fixed_position;
+ int (*request_region)(void *);
+ int (*release_region)(void *);
+ void *(*setup_region)(void);
+ enum ion_memory_types memory_type;
+};
+
+#ifdef CONFIG_ION
+/**
+ * msm_ion_secure_heap - secure a heap. Wrapper around ion_secure_heap.
+ *
+ * @heap_id - heap id to secure.
+ *
+ * Secure a heap
+ * Returns 0 on success
+ */
+int msm_ion_secure_heap(int heap_id);
+
+/**
+ * msm_ion_unsecure_heap - unsecure a heap. Wrapper around ion_unsecure_heap.
+ *
+ * @heap_id - heap id to secure.
+ *
+ * Un-secure a heap
+ * Returns 0 on success
+ */
+int msm_ion_unsecure_heap(int heap_id);
+
+/**
+ * msm_ion_secure_heap_2_0 - secure a heap using 2.0 APIs
+ * Wrapper around ion_secure_heap.
+ *
+ * @heap_id - heap id to secure.
+ * @usage - usage hint to TZ
+ *
+ * Secure a heap
+ * Returns 0 on success
+ */
+int msm_ion_secure_heap_2_0(int heap_id, enum cp_mem_usage usage);
+
+/**
+ * msm_ion_unsecure_heap - unsecure a heap secured with 3.0 APIs.
+ * Wrapper around ion_unsecure_heap.
+ *
+ * @heap_id - heap id to secure.
+ * @usage - usage hint to TZ
+ *
+ * Un-secure a heap
+ * Returns 0 on success
+ */
+int msm_ion_unsecure_heap_2_0(int heap_id, enum cp_mem_usage usage);
+#else
+static inline int msm_ion_secure_heap(int heap_id)
+{
+ return -ENODEV;
+
+}
+
+static inline int msm_ion_unsecure_heap(int heap_id)
+{
+ return -ENODEV;
+}
+
+static inline int msm_ion_secure_heap_2_0(int heap_id, enum cp_mem_usage usage)
+{
+ return -ENODEV;
+}
+
+static inline int msm_ion_unsecure_heap_2_0(int heap_id,
+ enum cp_mem_usage usage)
+{
+ return -ENODEV;
+}
+#endif /* CONFIG_ION */
+
+#endif /* __KERNEL */
+
+/* struct ion_flush_data - data passed to ion for flushing caches
+ *
+ * @handle: handle with data to flush
+ * @fd: fd to flush
+ * @vaddr: userspace virtual address mapped with mmap
+ * @offset: offset into the handle to flush
+ * @length: length of handle to flush
+ *
+ * Performs cache operations on the handle. If p is the start address
+ * of the handle, p + offset through p + offset + length will have
+ * the cache operations performed
+ */
+struct ion_flush_data {
+ struct ion_handle *handle;
+ int fd;
+ void *vaddr;
+ unsigned int offset;
+ unsigned int length;
+};
+
+/* struct ion_flag_data - information about flags for this buffer
+ *
+ * @handle: handle to get flags from
+ * @flags: flags of this handle
+ *
+ * Takes handle as an input and outputs the flags from the handle
+ * in the flag field.
+ */
+struct ion_flag_data {
+ struct ion_handle *handle;
+ unsigned long flags;
+};
+
+#define ION_IOC_MSM_MAGIC 'M'
+
+/**
+ * DOC: ION_IOC_CLEAN_CACHES - clean the caches
+ *
+ * Clean the caches of the handle specified.
+ */
+#define ION_IOC_CLEAN_CACHES _IOWR(ION_IOC_MSM_MAGIC, 0, \
+ struct ion_flush_data)
+/**
+ * DOC: ION_IOC_INV_CACHES - invalidate the caches
+ *
+ * Invalidate the caches of the handle specified.
+ */
+#define ION_IOC_INV_CACHES _IOWR(ION_IOC_MSM_MAGIC, 1, \
+ struct ion_flush_data)
+/**
+ * DOC: ION_IOC_CLEAN_INV_CACHES - clean and invalidate the caches
+ *
+ * Clean and invalidate the caches of the handle specified.
+ */
+#define ION_IOC_CLEAN_INV_CACHES _IOWR(ION_IOC_MSM_MAGIC, 2, \
+ struct ion_flush_data)
+
+/**
+ * DOC: ION_IOC_GET_FLAGS - get the flags of the handle
+ *
+ * Gets the flags of the current handle which indicate cachability,
+ * secure state etc.
+ */
+#define ION_IOC_GET_FLAGS _IOWR(ION_IOC_MSM_MAGIC, 3, \
+ struct ion_flag_data)
+
#endif
diff --git a/include/linux/msm_mdp.h b/include/linux/msm_mdp.h
index 861084a..1cdc434 100644
--- a/include/linux/msm_mdp.h
+++ b/include/linux/msm_mdp.h
@@ -71,6 +71,8 @@
#define MSMFB_OVERLAY_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 160, unsigned int)
#define MSMFB_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 161, unsigned int)
#define MSMFB_METADATA_SET _IOW(MSMFB_IOCTL_MAGIC, 162, struct msmfb_metadata)
+#define MSMFB_OVERLAY_COMMIT _IOW(MSMFB_IOCTL_MAGIC, 163, unsigned int)
+
#define FB_TYPE_3D_PANEL 0x10101010
#define MDP_IMGTYPE2_START 0x10000
#define MSMFB_DRIVER_VERSION 0xF9E8D701
diff --git a/include/media/msm_camera.h b/include/media/msm_camera.h
index ed9af2c..6658b8c 100644
--- a/include/media/msm_camera.h
+++ b/include/media/msm_camera.h
@@ -34,6 +34,8 @@
#define MSM_CAM_IOCTL_MAGIC 'm'
+#define MAX_SERVER_PAYLOAD_LENGTH 8192
+
#define MSM_CAM_IOCTL_GET_SENSOR_INFO \
_IOR(MSM_CAM_IOCTL_MAGIC, 1, struct msm_camsensor_info *)
@@ -862,7 +864,10 @@
(MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+16)
#define MSM_V4L2_EXT_CAPTURE_MODE_CSTA \
(MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+17)
-#define MSM_V4L2_EXT_CAPTURE_MODE_MAX (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+18)
+#define MSM_V4L2_EXT_CAPTURE_MODE_V2X_LIVESHOT \
+ (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+18)
+#define MSM_V4L2_EXT_CAPTURE_MODE_MAX (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+19)
+
#define MSM_V4L2_PID_MOTION_ISO V4L2_CID_PRIVATE_BASE
#define MSM_V4L2_PID_EFFECT (V4L2_CID_PRIVATE_BASE+1)
diff --git a/include/media/tavarua.h b/include/media/tavarua.h
index d7b1340..1cccb2b 100644
--- a/include/media/tavarua.h
+++ b/include/media/tavarua.h
@@ -104,6 +104,7 @@
#define MARIMBA_2_1 0x02010204
#define BAHAMA_1_0 0x0302010A
#define BAHAMA_2_0 0x04020205
+#define BAHAMA_2_1 0x04020309
#define WAIT_TIMEOUT 2000
#define RADIO_INIT_TIME 15
#define TAVARUA_DELAY 10
diff --git a/include/sound/apr_audio-v2.h b/include/sound/apr_audio-v2.h
index 1da6aa2..d902881 100644
--- a/include/sound/apr_audio-v2.h
+++ b/include/sound/apr_audio-v2.h
@@ -1890,6 +1890,7 @@
struct afe_param_id_hdmi_multi_chan_audio_cfg hdmi_multi_ch;
struct afe_param_id_slimbus_cfg slim_sch;
struct afe_param_id_rt_proxy_port_cfg rtproxy;
+ struct afe_param_id_internal_bt_fm_cfg int_bt_fm;
} __packed;
struct afe_audioif_config_command {
diff --git a/include/sound/q6afe-v2.h b/include/sound/q6afe-v2.h
index 8ccc9f4..e107130 100644
--- a/include/sound/q6afe-v2.h
+++ b/include/sound/q6afe-v2.h
@@ -13,6 +13,8 @@
#define __Q6AFE_V2_H__
#include <sound/apr_audio-v2.h>
+#define IN 0x000
+#define OUT 0x001
#define MSM_AFE_MONO 0
#define MSM_AFE_MONO_RIGHT 1
#define MSM_AFE_MONO_LEFT 2
@@ -71,6 +73,40 @@
AFE_MAX_PORTS
};
+struct afe_audio_buffer {
+ dma_addr_t phys;
+ void *data;
+ uint32_t used;
+ uint32_t size;/* size of buffer */
+ uint32_t actual_size; /* actual number of bytes read by DSP */
+ struct ion_handle *handle;
+ struct ion_client *client;
+};
+
+struct afe_audio_port_data {
+ struct afe_audio_buffer *buf;
+ uint32_t max_buf_cnt;
+ uint32_t dsp_buf;
+ uint32_t cpu_buf;
+ struct list_head mem_map_handle;
+ uint32_t tmp_hdl;
+ /* read or write locks */
+ struct mutex lock;
+ spinlock_t dsp_lock;
+};
+
+struct afe_audio_client {
+ atomic_t cmd_state;
+ /* Relative or absolute TS */
+ uint32_t time_flag;
+ void *priv;
+ uint64_t time_stamp;
+ struct mutex cmd_lock;
+ /* idx:1 out port, 0: in port*/
+ struct afe_audio_port_data port[2];
+ wait_queue_head_t cmd_wait;
+};
+
int afe_open(u16 port_id, union afe_port_config *afe_config, int rate);
int afe_close(int port_id);
int afe_loopback(u16 enable, u16 rx_port, u16 tx_port);
@@ -80,6 +116,7 @@
int afe_get_port_index(u16 port_id);
int afe_start_pseudo_port(u16 port_id);
int afe_stop_pseudo_port(u16 port_id);
+uint32_t afe_req_mmap_handle(void);
int afe_cmd_memory_map(u32 dma_addr_p, u32 dma_buf_sz);
int afe_cmd_memory_map_nowait(int port_id, u32 dma_addr_p, u32 dma_buf_sz);
int afe_cmd_memory_unmap(u32 dma_addr_p);
@@ -98,6 +135,14 @@
int afe_apply_gain(u16 port_id, u16 gain);
int afe_q6_interface_prepare(void);
int afe_get_port_type(u16 port_id);
+int q6afe_audio_client_buf_alloc_contiguous(unsigned int dir,
+ struct afe_audio_client *ac,
+ unsigned int bufsz,
+ unsigned int bufcnt);
+struct afe_audio_client *q6afe_audio_client_alloc(void *priv);
+int q6afe_audio_client_buf_free_contiguous(unsigned int dir,
+ struct afe_audio_client *ac);
+void q6afe_audio_client_free(struct afe_audio_client *ac);
/* if port_id is virtual, convert to physical..
* if port_id is already physical, return physical
*/
diff --git a/sound/soc/msm/apq8064-i2s.c b/sound/soc/msm/apq8064-i2s.c
index c489573..e309370 100644
--- a/sound/soc/msm/apq8064-i2s.c
+++ b/sound/soc/msm/apq8064-i2s.c
@@ -63,9 +63,8 @@
#define JACK_DETECT_GPIO 38
-#define APQ_I2S_SLAVE_CONFIG 0
/* MCLK selection GPIOs from PMIC */
-#define PM_GPIO_MCLK_MDM 10
+#define PM_GPIO_MCLK_MDM 27
#define PM_GPIO_MCLK_APQ 41
/* SPKR I2S Configuration */
@@ -170,10 +169,8 @@
};
-#if APQ_I2S_SLAVE_CONFIG
static u32 mdm_mclk_gpio = PM8921_GPIO_PM_TO_SYS(PM_GPIO_MCLK_MDM);
static u32 apq_mclk_gpio = PM8921_GPIO_PM_TO_SYS(PM_GPIO_MCLK_APQ);
-#endif
static u32 top_spk_pamp_gpio = PM8921_GPIO_PM_TO_SYS(18);
static u32 bottom_spk_pamp_gpio = PM8921_GPIO_PM_TO_SYS(19);
static int msm_spk_control;
@@ -186,9 +183,6 @@
static struct clk *i2s_rx_bit_clk;
static struct clk *i2s_tx_bit_clk;
-#if (!APQ_I2S_SLAVE_CONFIG)
-static struct clk *mi2s_osr_clk;
-#endif
static struct clk *mi2s_bit_clk;
static int msm_i2s_rx_ch = 1;
@@ -1020,7 +1014,6 @@
struct snd_soc_dapm_context *dapm = &codec->dapm;
struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
-#if APQ_I2S_SLAVE_CONFIG
struct pm_gpio param = {
.direction = PM_GPIO_DIR_OUT,
.output_buffer = PM_GPIO_OUT_BUF_CMOS,
@@ -1030,14 +1023,13 @@
.out_strength = PM_GPIO_STRENGTH_MED,
.function = PM_GPIO_FUNC_NORMAL,
};
-#endif
+
pr_debug("%s(), dev_name(%s)\n", __func__, dev_name(cpu_dai->dev));
ret = gpio_request(GPIO_MI2S_MCLK, "MI2S_MCLK");
if (ret)
pr_err("%s: Failed to request gpio %d\n", __func__,
GPIO_MI2S_MCLK);
-#if APQ_I2S_SLAVE_CONFIG
/* APQ provides the mclk to codec */
ret = gpio_request(mdm_mclk_gpio, "MDM_MCLK_SWITCH");
if (ret) {
@@ -1052,6 +1044,7 @@
else
gpio_direction_output(mdm_mclk_gpio, 0);
+ pr_debug("%s: Config mdm_mclk_gpio\n", __func__);
ret = gpio_request(apq_mclk_gpio, "APQ_MCLK_SWITCH");
if (ret) {
pr_err("%s: Failed to request gpio %d\n", __func__,
@@ -1064,12 +1057,9 @@
apq_mclk_gpio);
else
gpio_direction_output(apq_mclk_gpio, 1);
- pr_debug("%s: Config mdm_mclk_gpio and apq_mclk_gpio\n",
- __func__);
-#else
- pr_debug("%s: Not config mdm_mclk_gpio and apq_mclk_gpio\n",
- __func__);
-#endif
+
+ pr_debug("%s: Config apq_mclk_gpio\n", __func__);
+
snd_soc_dapm_new_controls(dapm, apq8064_dapm_widgets,
ARRAY_SIZE(apq8064_dapm_widgets));
@@ -1154,12 +1144,10 @@
ret = tabla_hs_detect(codec, &mbhc_cfg);
-#if APQ_I2S_SLAVE_CONFIG
/* MDM provides the mclk to codec */
gpio_direction_output(apq_mclk_gpio, 0);
gpio_direction_output(mdm_mclk_gpio, 1);
- pr_debug("%s: Should not running here if no clock switch\n", __func__);
-#endif
+ pr_debug("%s: Clock switch to MDM\n", __func__);
/* Should we add code to put back codec clock?*/
gpio_free(GPIO_MI2S_MCLK);
pr_debug("%s: Free MCLK GPIO\n", __func__);
@@ -1184,13 +1172,6 @@
clk_put(mi2s_bit_clk);
mi2s_bit_clk = NULL;
}
-#if (!APQ_I2S_SLAVE_CONFIG)
- if (mi2s_osr_clk) {
- clk_disable_unprepare(mi2s_osr_clk);
- clk_put(mi2s_osr_clk);
- mi2s_osr_clk = NULL;
- }
-#endif
msm_mi2s_free_gpios();
}
}
@@ -1232,8 +1213,6 @@
if (atomic_inc_return(&mi2s_rsc_ref) == 1) {
pr_debug("%s: acquire mi2s resources\n", __func__);
msm_configure_mi2s_gpio();
-
-#if APQ_I2S_SLAVE_CONFIG
pr_debug("%s: APQ is MI2S slave\n", __func__);
mi2s_bit_clk = clk_get(cpu_dai->dev, "bit_clk");
if (IS_ERR(mi2s_bit_clk))
@@ -1248,38 +1227,6 @@
ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_CBM_CFM);
if (IS_ERR_VALUE(ret))
pr_err("set format for CPU dai failed\n");
-#else
- pr_debug("%s: APQ is MI2S master\n", __func__);
- mi2s_osr_clk = clk_get(cpu_dai->dev, "osr_clk");
- if (IS_ERR(mi2s_osr_clk))
- return PTR_ERR(mi2s_osr_clk);
- clk_set_rate(mi2s_osr_clk, TABLA_EXT_CLK_RATE);
- ret = clk_prepare_enable(mi2s_osr_clk);
- if (IS_ERR_VALUE(ret)) {
- pr_err("Unable to enable mi2s_osr_clk\n");
- clk_put(mi2s_osr_clk);
- return ret;
- }
- mi2s_bit_clk = clk_get(cpu_dai->dev, "bit_clk");
- if (IS_ERR(mi2s_bit_clk)) {
- pr_err("Unable to get mi2s_bit_clk\n");
- clk_disable_unprepare(mi2s_osr_clk);
- clk_put(mi2s_osr_clk);
- return PTR_ERR(mi2s_bit_clk);
- }
- clk_set_rate(mi2s_bit_clk, 8);
- ret = clk_prepare_enable(mi2s_bit_clk);
- if (IS_ERR_VALUE(ret)) {
- pr_err("Unable to enable mi2s_bit_clk\n");
- clk_disable_unprepare(mi2s_osr_clk);
- clk_put(mi2s_osr_clk);
- clk_put(mi2s_bit_clk);
- return ret;
- }
- ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_CBS_CFS);
- if (IS_ERR_VALUE(ret))
- pr_err("set format for CPU dai failed\n");
-#endif
}
return ret;
@@ -2010,57 +1957,11 @@
static int msm_aux_pcm_get_gpios(void)
{
- int ret = 0;
-
- pr_debug("%s\n", __func__);
-
- ret = gpio_request(GPIO_AUX_PCM_DOUT, "AUX PCM DOUT");
- if (ret < 0) {
- pr_err("%s: Failed to request gpio(%d): AUX PCM DOUT",
- __func__, GPIO_AUX_PCM_DOUT);
- goto fail_dout;
- }
-
- ret = gpio_request(GPIO_AUX_PCM_DIN, "AUX PCM DIN");
- if (ret < 0) {
- pr_err("%s: Failed to request gpio(%d): AUX PCM DIN",
- __func__, GPIO_AUX_PCM_DIN);
- goto fail_din;
- }
-
- ret = gpio_request(GPIO_AUX_PCM_SYNC, "AUX PCM SYNC");
- if (ret < 0) {
- pr_err("%s: Failed to request gpio(%d): AUX PCM SYNC",
- __func__, GPIO_AUX_PCM_SYNC);
- goto fail_sync;
- }
- ret = gpio_request(GPIO_AUX_PCM_CLK, "AUX PCM CLK");
- if (ret < 0) {
- pr_err("%s: Failed to request gpio(%d): AUX PCM CLK",
- __func__, GPIO_AUX_PCM_CLK);
- goto fail_clk;
- }
-
return 0;
-
-fail_clk:
- gpio_free(GPIO_AUX_PCM_SYNC);
-fail_sync:
- gpio_free(GPIO_AUX_PCM_DIN);
-fail_din:
- gpio_free(GPIO_AUX_PCM_DOUT);
-fail_dout:
-
- return ret;
}
static int msm_aux_pcm_free_gpios(void)
{
- gpio_free(GPIO_AUX_PCM_DIN);
- gpio_free(GPIO_AUX_PCM_DOUT);
- gpio_free(GPIO_AUX_PCM_SYNC);
- gpio_free(GPIO_AUX_PCM_CLK);
-
return 0;
}
static int msm_startup(struct snd_pcm_substream *substream)
@@ -2428,6 +2329,14 @@
static struct snd_soc_dai_link msm_dai[] = {
/* FrontEnd DAI Links */
{
+ /*
+ * In APQ8064 I2S platform, there is no playback support
+ * only voice call is supported so there is no even system
+ * tone or dialing tone which is by design because I2S clock
+ * is provided by MDM which matches voice call sample rate
+ * 8kHz or 16kHz while system tone is 48kHz. We disable the
+ * playback by feeding the audio to AUX PCM port.
+ */
.name = "MSM8960 Media1",
.stream_name = "MultiMedia1",
.cpu_dai_name = "MultiMedia1",
@@ -2781,7 +2690,8 @@
static void __exit msm_audio_exit(void)
{
- if (!cpu_is_apq8064() || (socinfo_get_id() == 130)) {
+ if (!(cpu_is_apq8064() || cpu_is_apq8064ab()) ||
+ (socinfo_get_id() == 130)) {
pr_err("%s: Not the right machine type\n", __func__);
return ;
}
diff --git a/sound/soc/msm/apq8064.c b/sound/soc/msm/apq8064.c
index c8cf681..b921df1 100644
--- a/sound/soc/msm/apq8064.c
+++ b/sound/soc/msm/apq8064.c
@@ -2101,7 +2101,8 @@
{
int ret;
u32 version = socinfo_get_platform_version();
- if (!cpu_is_apq8064() || (socinfo_get_id() == 130) ||
+ if (!(cpu_is_apq8064() || cpu_is_apq8064ab()) ||
+ (socinfo_get_id() == 130) ||
(machine_is_apq8064_mtp() &&
(SOCINFO_VERSION_MINOR(version) == 1))) {
pr_info("%s: Not APQ8064 in SLIMBUS mode\n", __func__);
@@ -2141,7 +2142,8 @@
static void __exit msm_audio_exit(void)
{
- if (!cpu_is_apq8064() || (socinfo_get_id() == 130)) {
+ if (!(cpu_is_apq8064() || cpu_is_apq8064ab()) ||
+ (socinfo_get_id() == 130)) {
pr_err("%s: Not the right machine type\n", __func__);
return ;
}
diff --git a/sound/soc/msm/msm8974.c b/sound/soc/msm/msm8974.c
index 92b7324..f462299 100644
--- a/sound/soc/msm/msm8974.c
+++ b/sound/soc/msm/msm8974.c
@@ -81,6 +81,7 @@
static int msm_slim_0_tx_ch = 1;
static int msm_btsco_rate = BTSCO_RATE_8KHZ;
+static int msm_btsco_ch = 1;
static struct snd_soc_jack hs_jack;
static struct snd_soc_jack button_jack;
@@ -480,6 +481,21 @@
msm_btsco_rate_get, msm_btsco_rate_put),
};
+static int msm_btsco_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
+ struct snd_pcm_hw_params *params)
+{
+ struct snd_interval *rate = hw_param_interval(params,
+ SNDRV_PCM_HW_PARAM_RATE);
+
+ struct snd_interval *channels = hw_param_interval(params,
+ SNDRV_PCM_HW_PARAM_CHANNELS);
+
+ rate->min = rate->max = msm_btsco_rate;
+ channels->min = channels->max = msm_btsco_ch;
+
+ return 0;
+}
+
static int msm_auxpcm_be_params_fixup(struct snd_soc_pcm_runtime *rtd,
struct snd_pcm_hw_params *params)
{
@@ -495,6 +511,19 @@
return 0;
}
+
+static int msm_proxy_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
+ struct snd_pcm_hw_params *params)
+{
+ struct snd_interval *rate = hw_param_interval(params,
+ SNDRV_PCM_HW_PARAM_RATE);
+
+ pr_debug("%s()\n", __func__);
+ rate->min = rate->max = 48000;
+
+ return 0;
+}
+
static int msm_aux_pcm_get_gpios(void)
{
int ret = 0;
@@ -780,19 +809,19 @@
.be_id = MSM_FRONTEND_DAI_MULTIMEDIA1
},
{
- .name = "MSM VoIP",
- .stream_name = "VoIP",
- .cpu_dai_name = "VoIP",
- .platform_name = "msm-voip-dsp",
+ .name = "MSM8974 Media2",
+ .stream_name = "MultiMedia2",
+ .cpu_dai_name = "MultiMedia2",
+ .platform_name = "msm-pcm-dsp",
.dynamic = 1,
- .trigger = {SND_SOC_DPCM_TRIGGER_POST,
- SND_SOC_DPCM_TRIGGER_POST},
.codec_dai_name = "snd-soc-dummy-dai",
.codec_name = "snd-soc-dummy",
+ .trigger = {SND_SOC_DPCM_TRIGGER_POST,
+ SND_SOC_DPCM_TRIGGER_POST},
.ignore_suspend = 1,
/* this dainlink has playback support */
.ignore_pmdown_time = 1,
- .be_id = MSM_FRONTEND_DAI_VOIP,
+ .be_id = MSM_FRONTEND_DAI_MULTIMEDIA2,
},
{
.name = "Circuit-Switch Voice",
@@ -811,6 +840,21 @@
.be_id = MSM_FRONTEND_DAI_CS_VOICE,
},
{
+ .name = "MSM VoIP",
+ .stream_name = "VoIP",
+ .cpu_dai_name = "VoIP",
+ .platform_name = "msm-voip-dsp",
+ .dynamic = 1,
+ .trigger = {SND_SOC_DPCM_TRIGGER_POST,
+ SND_SOC_DPCM_TRIGGER_POST},
+ .codec_dai_name = "snd-soc-dummy-dai",
+ .codec_name = "snd-soc-dummy",
+ .ignore_suspend = 1,
+ /* this dainlink has playback support */
+ .ignore_pmdown_time = 1,
+ .be_id = MSM_FRONTEND_DAI_VOIP,
+ },
+ {
.name = "MSM8974 LPA",
.stream_name = "LPA",
.cpu_dai_name = "MultiMedia3",
@@ -841,6 +885,41 @@
.codec_name = "snd-soc-dummy",
},
{
+ .name = "INT_FM Hostless",
+ .stream_name = "INT_FM Hostless",
+ .cpu_dai_name = "INT_FM_HOSTLESS",
+ .platform_name = "msm-pcm-hostless",
+ .dynamic = 1,
+ .trigger = {SND_SOC_DPCM_TRIGGER_POST,
+ SND_SOC_DPCM_TRIGGER_POST},
+ .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
+ .ignore_suspend = 1,
+ /* this dainlink has playback support */
+ .ignore_pmdown_time = 1,
+ .codec_dai_name = "snd-soc-dummy-dai",
+ .codec_name = "snd-soc-dummy",
+ },
+ {
+ .name = "MSM AFE-PCM RX",
+ .stream_name = "AFE-PROXY RX",
+ .cpu_dai_name = "msm-dai-q6-dev.241",
+ .codec_name = "msm-stub-codec.1",
+ .codec_dai_name = "msm-stub-rx",
+ .platform_name = "msm-pcm-afe",
+ .ignore_suspend = 1,
+ /* this dainlink has playback support */
+ .ignore_pmdown_time = 1,
+ },
+ {
+ .name = "MSM AFE-PCM TX",
+ .stream_name = "AFE-PROXY TX",
+ .cpu_dai_name = "msm-dai-q6-dev.240",
+ .codec_name = "msm-stub-codec.1",
+ .codec_dai_name = "msm-stub-tx",
+ .platform_name = "msm-pcm-afe",
+ .ignore_suspend = 1,
+ },
+ {
.name = "MSM8974 Compr",
.stream_name = "COMPR",
.cpu_dai_name = "MultiMedia4",
@@ -870,19 +949,55 @@
.codec_dai_name = "snd-soc-dummy-dai",
.codec_name = "snd-soc-dummy",
},
+ /* Backend BT/FM DAI Links */
{
- .name = "MSM8974 Media2",
- .stream_name = "MultiMedia2",
- .cpu_dai_name = "MultiMedia2",
- .platform_name = "msm-pcm-dsp",
- .dynamic = 1,
- .codec_dai_name = "snd-soc-dummy-dai",
- .codec_name = "snd-soc-dummy",
- .trigger = {SND_SOC_DPCM_TRIGGER_POST,
- SND_SOC_DPCM_TRIGGER_POST},
- .ignore_suspend = 1,
+ .name = LPASS_BE_INT_BT_SCO_RX,
+ .stream_name = "Internal BT-SCO Playback",
+ .cpu_dai_name = "msm-dai-q6-dev.12288",
+ .platform_name = "msm-pcm-routing",
+ .codec_name = "msm-stub-codec.1",
+ .codec_dai_name = "msm-stub-rx",
+ .no_pcm = 1,
+ .be_id = MSM_BACKEND_DAI_INT_BT_SCO_RX,
+ .be_hw_params_fixup = msm_btsco_be_hw_params_fixup,
+ /* this dainlink has playback support */
.ignore_pmdown_time = 1,
- .be_id = MSM_FRONTEND_DAI_MULTIMEDIA2,
+ },
+ {
+ .name = LPASS_BE_INT_BT_SCO_TX,
+ .stream_name = "Internal BT-SCO Capture",
+ .cpu_dai_name = "msm-dai-q6-dev.12289",
+ .platform_name = "msm-pcm-routing",
+ .codec_name = "msm-stub-codec.1",
+ .codec_dai_name = "msm-stub-tx",
+ .no_pcm = 1,
+ .be_id = MSM_BACKEND_DAI_INT_BT_SCO_TX,
+ .be_hw_params_fixup = msm_btsco_be_hw_params_fixup,
+ },
+ /* Backend AFE DAI Links */
+ {
+ .name = LPASS_BE_AFE_PCM_RX,
+ .stream_name = "AFE Playback",
+ .cpu_dai_name = "msm-dai-q6-dev.224",
+ .platform_name = "msm-pcm-routing",
+ .codec_name = "msm-stub-codec.1",
+ .codec_dai_name = "msm-stub-rx",
+ .no_pcm = 1,
+ .be_id = MSM_BACKEND_DAI_AFE_PCM_RX,
+ .be_hw_params_fixup = msm_proxy_be_hw_params_fixup,
+ /* this dainlink has playback support */
+ .ignore_pmdown_time = 1,
+ },
+ {
+ .name = LPASS_BE_AFE_PCM_TX,
+ .stream_name = "AFE Capture",
+ .cpu_dai_name = "msm-dai-q6-dev.225",
+ .platform_name = "msm-pcm-routing",
+ .codec_name = "msm-stub-codec.1",
+ .codec_dai_name = "msm-stub-tx",
+ .no_pcm = 1,
+ .be_id = MSM_BACKEND_DAI_AFE_PCM_TX,
+ .be_hw_params_fixup = msm_proxy_be_hw_params_fixup,
},
/* AUX PCM Backend DAI Links */
{
diff --git a/sound/soc/msm/qdsp6/q6asm.c b/sound/soc/msm/qdsp6/q6asm.c
index b086b8e..6865871 100644
--- a/sound/soc/msm/qdsp6/q6asm.c
+++ b/sound/soc/msm/qdsp6/q6asm.c
@@ -798,6 +798,25 @@
return 0;
}
+static int32_t is_no_wait_cmd_rsp(uint32_t opcode, uint32_t *cmd_type)
+{
+ if (opcode == APR_BASIC_RSP_RESULT) {
+ if (cmd_type != NULL) {
+ switch (cmd_type[0]) {
+ case ASM_SESSION_CMD_RUN:
+ case ASM_SESSION_CMD_PAUSE:
+ case ASM_DATA_CMD_EOS:
+ return 1;
+ default:
+ break;
+ }
+ } else
+ pr_err("%s: null pointer!", __func__);
+ } else if (opcode == ASM_DATA_CMDRSP_EOS)
+ return 1;
+
+ return 0;
+}
static int32_t q6asm_callback(struct apr_client_data *data, void *priv)
{
@@ -818,14 +837,16 @@
ac->session);
return -EINVAL;
}
- if (atomic_read(&ac->nowait_cmd_cnt) > 0) {
+
+ payload = data->payload;
+ if ((atomic_read(&ac->nowait_cmd_cnt) > 0) &&
+ is_no_wait_cmd_rsp(data->opcode, payload)) {
pr_debug("%s: nowait_cmd_cnt %d\n",
__func__,
atomic_read(&ac->nowait_cmd_cnt));
atomic_dec(&ac->nowait_cmd_cnt);
wakeup_flag = 0;
}
- payload = data->payload;
if (data->opcode == RESET_EVENTS) {
pr_debug("q6asm_callback: Reset event is received: %d %d apr[%p]\n",
diff --git a/sound/soc/msm/qdsp6v2/msm-dai-q6-v2.c b/sound/soc/msm/qdsp6v2/msm-dai-q6-v2.c
index 3eab972..a6cdad2 100644
--- a/sound/soc/msm/qdsp6v2/msm-dai-q6-v2.c
+++ b/sound/soc/msm/qdsp6v2/msm-dai-q6-v2.c
@@ -540,6 +540,14 @@
memset(&dai_data->port_config, 0, sizeof(dai_data->port_config));
+ pr_debug("%s: setting bt_fm parameters\n", __func__);
+
+ dai_data->port_config.int_bt_fm.bt_fm_cfg_minor_version =
+ AFE_API_VERSION_INTERNAL_BT_FM_CONFIG;
+ dai_data->port_config.int_bt_fm.num_channels = dai_data->channels;
+ dai_data->port_config.int_bt_fm.sample_rate = dai_data->rate;
+ dai_data->port_config.int_bt_fm.bit_width = 16;
+
return 0;
}
@@ -805,6 +813,36 @@
return 0;
}
+static struct snd_soc_dai_driver msm_dai_q6_afe_rx_dai = {
+ .playback = {
+ .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
+ SNDRV_PCM_RATE_16000,
+ .formats = SNDRV_PCM_FMTBIT_S16_LE,
+ .channels_min = 1,
+ .channels_max = 2,
+ .rate_min = 8000,
+ .rate_max = 48000,
+ },
+ .ops = &msm_dai_q6_ops,
+ .probe = msm_dai_q6_dai_probe,
+ .remove = msm_dai_q6_dai_remove,
+};
+
+static struct snd_soc_dai_driver msm_dai_q6_afe_tx_dai = {
+ .capture = {
+ .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
+ SNDRV_PCM_RATE_16000,
+ .formats = SNDRV_PCM_FMTBIT_S16_LE,
+ .channels_min = 1,
+ .channels_max = 4,
+ .rate_min = 8000,
+ .rate_max = 48000,
+ },
+ .ops = &msm_dai_q6_ops,
+ .probe = msm_dai_q6_dai_probe,
+ .remove = msm_dai_q6_dai_remove,
+};
+
static struct snd_soc_dai_driver msm_dai_q6_slimbus_1_rx_dai = {
.playback = {
.rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
@@ -833,6 +871,34 @@
.remove = msm_dai_q6_dai_remove,
};
+static struct snd_soc_dai_driver msm_dai_q6_bt_sco_rx_dai = {
+ .playback = {
+ .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
+ .formats = SNDRV_PCM_FMTBIT_S16_LE,
+ .channels_min = 1,
+ .channels_max = 1,
+ .rate_max = 16000,
+ .rate_min = 8000,
+ },
+ .ops = &msm_dai_q6_ops,
+ .probe = msm_dai_q6_dai_probe,
+ .remove = msm_dai_q6_dai_remove,
+};
+
+static struct snd_soc_dai_driver msm_dai_q6_bt_sco_tx_dai = {
+ .capture = {
+ .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
+ .formats = SNDRV_PCM_FMTBIT_S16_LE,
+ .channels_min = 1,
+ .channels_max = 1,
+ .rate_max = 16000,
+ .rate_min = 8000,
+ },
+ .ops = &msm_dai_q6_ops,
+ .probe = msm_dai_q6_dai_probe,
+ .remove = msm_dai_q6_dai_remove,
+};
+
static int __devinit msm_auxpcm_dev_probe(struct platform_device *pdev)
{
int id;
@@ -1084,6 +1150,22 @@
rc = snd_soc_register_dai(&pdev->dev,
&msm_dai_q6_slimbus_1_tx_dai);
break;
+ case INT_BT_SCO_RX:
+ rc = snd_soc_register_dai(&pdev->dev,
+ &msm_dai_q6_bt_sco_rx_dai);
+ break;
+ case INT_BT_SCO_TX:
+ rc = snd_soc_register_dai(&pdev->dev,
+ &msm_dai_q6_bt_sco_tx_dai);
+ break;
+ case RT_PROXY_DAI_001_RX:
+ case RT_PROXY_DAI_002_RX:
+ rc = snd_soc_register_dai(&pdev->dev, &msm_dai_q6_afe_rx_dai);
+ break;
+ case RT_PROXY_DAI_001_TX:
+ case RT_PROXY_DAI_002_TX:
+ rc = snd_soc_register_dai(&pdev->dev, &msm_dai_q6_afe_tx_dai);
+ break;
default:
rc = -ENODEV;
break;
diff --git a/sound/soc/msm/qdsp6v2/msm-pcm-afe-v2.c b/sound/soc/msm/qdsp6v2/msm-pcm-afe-v2.c
index 4593784..73a04c2 100644
--- a/sound/soc/msm/qdsp6v2/msm-pcm-afe-v2.c
+++ b/sound/soc/msm/qdsp6v2/msm-pcm-afe-v2.c
@@ -29,6 +29,8 @@
#include <sound/control.h>
#include <sound/q6adm-v2.h>
#include <asm/dma.h>
+#include <linux/memory_alloc.h>
+#include <mach/msm_subsystem_map.h>
#include "msm-pcm-afe-v2.h"
#define MIN_PERIOD_SIZE (128 * 2)
@@ -63,6 +65,11 @@
struct snd_pcm_substream *substream = prtd->substream;
struct snd_pcm_runtime *runtime = substream->runtime;
u32 mem_map_handle = 0;
+
+ mem_map_handle = afe_req_mmap_handle();
+ if (!mem_map_handle)
+ pr_err("%s: mem_map_handle is NULL\n", __func__);
+
if (prtd->start) {
pr_debug("sending frame to DSP: poll_time: %d\n",
prtd->poll_time);
@@ -89,10 +96,15 @@
struct snd_pcm_substream *substream = prtd->substream;
struct snd_pcm_runtime *runtime = substream->runtime;
u32 mem_map_handle = 0;
+
+ mem_map_handle = afe_req_mmap_handle();
+ if (!mem_map_handle)
+ pr_err("%s: mem_map_handle is NULL\n", __func__);
+
if (prtd->start) {
if (prtd->dsp_cnt == runtime->periods)
prtd->dsp_cnt = 0;
- pr_err("%s: mem_map_handle 0x%x\n", __func__, mem_map_handle);
+ pr_debug("%s: mem_map_handle 0x%x\n", __func__, mem_map_handle);
afe_rt_proxy_port_read(
(prtd->dma_addr + (prtd->dsp_cnt
* snd_pcm_lib_period_bytes(prtd->substream))), mem_map_handle,
@@ -137,9 +149,6 @@
runtime->channels * 2)));
pr_debug("prtd->poll_time: %d",
prtd->poll_time);
- hrtimer_start(&prtd->hrt,
- ns_to_ktime(0),
- HRTIMER_MODE_REL);
break;
}
case AFE_EVENT_RTPORT_STOP:
@@ -203,9 +212,6 @@
snd_pcm_lib_period_bytes(prtd->substream)
* 1000 * 1000)/(runtime->rate
* runtime->channels * 2)));
- hrtimer_start(&prtd->hrt,
- ns_to_ktime(0),
- HRTIMER_MODE_REL);
pr_debug("prtd->poll_time : %d", prtd->poll_time);
break;
}
@@ -321,13 +327,21 @@
runtime->hw = msm_afe_hardware;
prtd->substream = substream;
runtime->private_data = prtd;
- mutex_unlock(&prtd->lock);
+ prtd->audio_client = q6afe_audio_client_alloc(prtd);
+ if (!prtd->audio_client) {
+ pr_debug("%s: Could not allocate memory\n", __func__);
+ kfree(prtd);
+ mutex_unlock(&prtd->lock);
+ return -ENOMEM;
+ }
+
hrtimer_init(&prtd->hrt, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
prtd->hrt.function = afe_hrtimer_callback;
else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
prtd->hrt.function = afe_hrtimer_rec_callback;
+ mutex_unlock(&prtd->lock);
ret = snd_pcm_hw_constraint_list(runtime, 0,
SNDRV_PCM_HW_PARAM_RATE,
&constraints_sample_rates);
@@ -350,6 +364,7 @@
struct pcm_afe_info *prtd;
struct snd_soc_pcm_runtime *rtd = NULL;
struct snd_soc_dai *dai = NULL;
+ int dir = IN;
int ret = 0;
pr_debug("%s\n", __func__);
@@ -365,17 +380,19 @@
mutex_lock(&prtd->lock);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ dir = IN;
ret = afe_unregister_get_events(dai->id);
if (ret < 0)
pr_err("AFE unregister for events failed\n");
} else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
+ dir = OUT;
ret = afe_unregister_get_events(dai->id);
if (ret < 0)
pr_err("AFE unregister for events failed\n");
}
hrtimer_cancel(&prtd->hrt);
- rc = afe_cmd_memory_unmap(runtime->dma_addr);
+ rc = afe_cmd_memory_unmap(afe_req_mmap_handle());
if (rc < 0)
pr_err("AFE memory unmap failed\n");
@@ -384,15 +401,14 @@
if (dma_buf == NULL) {
pr_debug("dma_buf is NULL\n");
goto done;
- }
- if (dma_buf->area != NULL) {
- dma_free_coherent(substream->pcm->card->dev,
- runtime->hw.buffer_bytes_max, dma_buf->area,
- dma_buf->addr);
- dma_buf->area = NULL;
}
+
+ if (dma_buf->area)
+ dma_buf->area = NULL;
+ q6afe_audio_client_buf_free_contiguous(dir, prtd->audio_client);
done:
pr_debug("%s: dai->id =%x\n", __func__, dai->id);
+ q6afe_audio_client_free(prtd->audio_client);
mutex_unlock(&prtd->lock);
prtd->prepared--;
kfree(prtd);
@@ -420,14 +436,21 @@
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct pcm_afe_info *prtd = runtime->private_data;
+ int result = 0;
pr_debug("%s\n", __func__);
prtd->mmap_flag = 1;
- dma_mmap_coherent(substream->pcm->card->dev, vma,
- runtime->dma_area,
- runtime->dma_addr,
- runtime->dma_bytes);
- return 0;
+ if (runtime->dma_addr && runtime->dma_bytes) {
+ vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
+ result = remap_pfn_range(vma, vma->vm_start,
+ runtime->dma_addr >> PAGE_SHIFT,
+ runtime->dma_bytes,
+ vma->vm_page_prot);
+ } else {
+ pr_err("Physical address or size of buf is NULL");
+ return -EINVAL;
+ }
+ return result;
}
static int msm_afe_trigger(struct snd_pcm_substream *substream, int cmd)
{
@@ -441,6 +464,8 @@
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
pr_debug("%s: SNDRV_PCM_TRIGGER_START\n", __func__);
prtd->start = 1;
+ hrtimer_start(&prtd->hrt, ns_to_ktime(0),
+ HRTIMER_MODE_REL);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
@@ -460,27 +485,45 @@
struct snd_pcm_runtime *runtime = substream->runtime;
struct snd_dma_buffer *dma_buf = &substream->dma_buffer;
struct pcm_afe_info *prtd = runtime->private_data;
- int rc;
+ struct afe_audio_buffer *buf;
+ int dir, rc;
pr_debug("%s:\n", __func__);
mutex_lock(&prtd->lock);
-
- dma_buf->dev.type = SNDRV_DMA_TYPE_DEV;
- dma_buf->dev.dev = substream->pcm->card->dev;
- dma_buf->private_data = NULL;
- dma_buf->area = dma_alloc_coherent(dma_buf->dev.dev,
- runtime->hw.buffer_bytes_max,
- &dma_buf->addr, GFP_KERNEL);
-
- pr_debug("%s: dma_buf->area: 0x%p, dma_buf->addr: 0x%x", __func__,
- (unsigned int *) dma_buf->area, dma_buf->addr);
- if (!dma_buf->area) {
- pr_err("%s:MSM AFE memory allocation failed\n", __func__);
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+ dir = IN;
+ else
+ dir = OUT;
+ rc = q6afe_audio_client_buf_alloc_contiguous(dir,
+ prtd->audio_client,
+ runtime->hw.period_bytes_min,
+ runtime->hw.periods_max);
+ if (rc < 0) {
+ pr_err("Audio Start: Buffer Allocation failed rc = %d\n", rc);
mutex_unlock(&prtd->lock);
return -ENOMEM;
}
+ buf = prtd->audio_client->port[dir].buf;
+
+ if (buf == NULL || buf[0].data == NULL) {
+ mutex_unlock(&prtd->lock);
+ return -ENOMEM;
+ }
+
+ pr_debug("%s:buf = %p\n", __func__, buf);
+ dma_buf->dev.type = SNDRV_DMA_TYPE_DEV;
+ dma_buf->dev.dev = substream->pcm->card->dev;
+ dma_buf->private_data = NULL;
+ dma_buf->area = buf[0].data;
+ dma_buf->addr = buf[0].phys;
dma_buf->bytes = runtime->hw.buffer_bytes_max;
+ if (!dma_buf->area) {
+ pr_err("%s:MSM AFE physical memory allocation failed\n",
+ __func__);
+ mutex_unlock(&prtd->lock);
+ return -ENOMEM;
+ }
memset(dma_buf->area, 0, runtime->hw.buffer_bytes_max);
prtd->dma_addr = (u32) dma_buf->addr;
@@ -542,6 +585,9 @@
static __devinit int msm_afe_probe(struct platform_device *pdev)
{
+ if (pdev->dev.of_node)
+ dev_set_name(&pdev->dev, "%s", "msm-pcm-afe");
+
pr_debug("%s: dev name %s\n", __func__, dev_name(&pdev->dev));
return snd_soc_register_platform(&pdev->dev,
&msm_soc_platform);
@@ -553,11 +599,17 @@
snd_soc_unregister_platform(&pdev->dev);
return 0;
}
+static const struct of_device_id msm_pcm_afe_dt_match[] = {
+ {.compatible = "qcom,msm-pcm-afe"},
+ {}
+};
+MODULE_DEVICE_TABLE(of, msm_pcm_afe_dt_match);
static struct platform_driver msm_afe_driver = {
.driver = {
.name = "msm-pcm-afe",
.owner = THIS_MODULE,
+ .of_match_table = msm_pcm_afe_dt_match,
},
.probe = msm_afe_probe,
.remove = __devexit_p(msm_afe_remove),
diff --git a/sound/soc/msm/qdsp6v2/msm-pcm-afe-v2.h b/sound/soc/msm/qdsp6v2/msm-pcm-afe-v2.h
index 20d6377..446409f 100644
--- a/sound/soc/msm/qdsp6v2/msm-pcm-afe-v2.h
+++ b/sound/soc/msm/qdsp6v2/msm-pcm-afe-v2.h
@@ -30,6 +30,7 @@
int prepared;
struct hrtimer hrt;
int poll_time;
+ struct afe_audio_client *audio_client;
};
diff --git a/sound/soc/msm/qdsp6v2/q6afe.c b/sound/soc/msm/qdsp6v2/q6afe.c
index 0b25545..f0465a5 100644
--- a/sound/soc/msm/qdsp6v2/q6afe.c
+++ b/sound/soc/msm/qdsp6v2/q6afe.c
@@ -18,6 +18,7 @@
#include <linux/wait.h>
#include <linux/jiffies.h>
#include <linux/sched.h>
+#include <linux/msm_ion.h>
#include <mach/qdsp6v2/audio_acdb.h>
#include <sound/apr_audio-v2.h>
#include <sound/q6afe-v2.h>
@@ -37,6 +38,7 @@
uint32_t token, uint32_t *payload, void *priv);
void *tx_private_data;
void *rx_private_data;
+ uint32_t mmap_handle;
};
static struct afe_ctl this_afe;
@@ -107,6 +109,13 @@
payload[0]);
break;
}
+ } else if (data->opcode ==
+ AFE_SERVICE_CMDRSP_SHARED_MEM_MAP_REGIONS) {
+ pr_debug("%s: mmap_handle: 0x%x\n",
+ __func__, payload[0]);
+ this_afe.mmap_handle = (uint32_t)payload[0];
+ atomic_set(&this_afe.state, 0);
+ wake_up(&this_afe.wait[data->token]);
} else if (data->opcode == AFE_EVENT_RT_PROXY_PORT_STATUS) {
port_id = (uint16_t)(0x0000FFFF & payload[0]);
}
@@ -266,17 +275,21 @@
ret = -EINVAL;
return ret;
}
- index = q6audio_get_port_index(port_id);
- if (q6audio_validate_port(port_id) < 0)
- return -EINVAL;
if ((port_id == RT_PROXY_DAI_001_RX) ||
(port_id == RT_PROXY_DAI_002_TX))
- return -EINVAL;
+ return 0;
if ((port_id == RT_PROXY_DAI_002_RX) ||
(port_id == RT_PROXY_DAI_001_TX))
port_id = VIRTUAL_ID_TO_PORTID(port_id);
+ pr_debug("%s: port id: %d\n", __func__, port_id);
+ index = q6audio_get_port_index(port_id);
+ if (q6audio_validate_port(port_id) < 0) {
+ pr_err("%s: port id: %d\n", __func__, port_id);
+ return -EINVAL;
+ }
+
ret = afe_q6_interface_prepare();
if (IS_ERR_VALUE(ret))
return ret;
@@ -325,6 +338,14 @@
case SLIMBUS_4_TX:
cfg_type = AFE_PARAM_ID_SLIMBUS_CONFIG;
break;
+ case RT_PROXY_PORT_001_RX:
+ case RT_PROXY_PORT_001_TX:
+ cfg_type = AFE_PARAM_ID_RT_PROXY_CONFIG;
+ break;
+ case INT_BT_SCO_RX:
+ case INT_BT_SCO_TX:
+ cfg_type = AFE_PARAM_ID_INTERNAL_BT_FM_CONFIG;
+ break;
default:
pr_err("%s: Invalid port id 0x%x\n", __func__, port_id);
ret = -EINVAL;
@@ -904,7 +925,133 @@
return 0;
}
-/*bharath, memory map handle needs to be stored by AFE client */
+uint32_t afe_req_mmap_handle(void)
+{
+ return this_afe.mmap_handle;
+}
+
+struct afe_audio_client *q6afe_audio_client_alloc(void *priv)
+{
+ struct afe_audio_client *ac;
+ int lcnt = 0;
+
+ ac = kzalloc(sizeof(struct afe_audio_client), GFP_KERNEL);
+ if (!ac) {
+ pr_err("%s: cannot allocate audio client for afe\n", __func__);
+ return NULL;
+ }
+ ac->priv = priv;
+
+ init_waitqueue_head(&ac->cmd_wait);
+ INIT_LIST_HEAD(&ac->port[0].mem_map_handle);
+ INIT_LIST_HEAD(&ac->port[1].mem_map_handle);
+ pr_debug("%s: mem_map_handle list init'ed\n", __func__);
+ mutex_init(&ac->cmd_lock);
+ for (lcnt = 0; lcnt <= OUT; lcnt++) {
+ mutex_init(&ac->port[lcnt].lock);
+ spin_lock_init(&ac->port[lcnt].dsp_lock);
+ }
+ atomic_set(&ac->cmd_state, 0);
+
+ return ac;
+}
+
+int q6afe_audio_client_buf_alloc_contiguous(unsigned int dir,
+ struct afe_audio_client *ac,
+ unsigned int bufsz,
+ unsigned int bufcnt)
+{
+ int cnt = 0;
+ int rc = 0;
+ struct afe_audio_buffer *buf;
+ int len;
+
+ if (!(ac) || ((dir != IN) && (dir != OUT)))
+ return -EINVAL;
+
+ pr_debug("%s: bufsz[%d]bufcnt[%d]\n",
+ __func__,
+ bufsz, bufcnt);
+
+ if (ac->port[dir].buf) {
+ pr_debug("%s: buffer already allocated\n", __func__);
+ return 0;
+ }
+ mutex_lock(&ac->cmd_lock);
+ buf = kzalloc(((sizeof(struct afe_audio_buffer))*bufcnt),
+ GFP_KERNEL);
+
+ if (!buf) {
+ mutex_unlock(&ac->cmd_lock);
+ goto fail;
+ }
+
+ ac->port[dir].buf = buf;
+
+ buf[0].client = msm_ion_client_create(UINT_MAX, "audio_client");
+ if (IS_ERR_OR_NULL((void *)buf[0].client)) {
+ pr_err("%s: ION create client for AUDIO failed\n", __func__);
+ goto fail;
+ }
+ buf[0].handle = ion_alloc(buf[0].client, bufsz * bufcnt, SZ_4K,
+ (0x1 << ION_AUDIO_HEAP_ID), 0);
+ if (IS_ERR_OR_NULL((void *) buf[0].handle)) {
+ pr_err("%s: ION memory allocation for AUDIO failed\n",
+ __func__);
+ goto fail;
+ }
+
+ rc = ion_phys(buf[0].client, buf[0].handle,
+ (ion_phys_addr_t *)&buf[0].phys, (size_t *)&len);
+ if (rc) {
+ pr_err("%s: ION Get Physical for AUDIO failed, rc = %d\n",
+ __func__, rc);
+ goto fail;
+ }
+
+ buf[0].data = ion_map_kernel(buf[0].client, buf[0].handle);
+ if (IS_ERR_OR_NULL((void *) buf[0].data)) {
+ pr_err("%s: ION memory mapping for AUDIO failed\n", __func__);
+ goto fail;
+ }
+ memset((void *)buf[0].data, 0, (bufsz * bufcnt));
+ if (!buf[0].data) {
+ pr_err("%s:invalid vaddr, iomap failed\n", __func__);
+ mutex_unlock(&ac->cmd_lock);
+ goto fail;
+ }
+
+ buf[0].used = dir ^ 1;
+ buf[0].size = bufsz;
+ buf[0].actual_size = bufsz;
+ cnt = 1;
+ while (cnt < bufcnt) {
+ if (bufsz > 0) {
+ buf[cnt].data = buf[0].data + (cnt * bufsz);
+ buf[cnt].phys = buf[0].phys + (cnt * bufsz);
+ if (!buf[cnt].data) {
+ pr_err("%s Buf alloc failed\n",
+ __func__);
+ mutex_unlock(&ac->cmd_lock);
+ goto fail;
+ }
+ buf[cnt].used = dir ^ 1;
+ buf[cnt].size = bufsz;
+ buf[cnt].actual_size = bufsz;
+ pr_debug("%s data[%p]phys[%p][%p]\n", __func__,
+ (void *)buf[cnt].data,
+ (void *)buf[cnt].phys,
+ (void *)&buf[cnt].phys);
+ }
+ cnt++;
+ }
+ ac->port[dir].max_buf_cnt = cnt;
+ mutex_unlock(&ac->cmd_lock);
+ return 0;
+fail:
+ q6afe_audio_client_buf_free_contiguous(dir, ac);
+ return -EINVAL;
+}
int afe_cmd_memory_map(u32 dma_addr_p, u32 dma_buf_sz)
{
int ret = 0;
@@ -941,7 +1088,7 @@
mmap_region_cmd;
mregion->hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD,
APR_HDR_LEN(APR_HDR_SIZE), APR_PKT_VER);
- mregion->hdr.pkt_size = sizeof(mregion);
+ mregion->hdr.pkt_size = cmd_size;
mregion->hdr.src_port = 0;
mregion->hdr.dest_port = 0;
mregion->hdr.token = 0;
@@ -961,13 +1108,15 @@
mregion_pl->shm_addr_msw = 0x00;
mregion_pl->mem_size_bytes = dma_buf_sz;
+ pr_debug("%s: dma_addr_p 0x%x , size %d\n", __func__,
+ dma_addr_p, dma_buf_sz);
atomic_set(&this_afe.state, 1);
ret = apr_send_pkt(this_afe.apr, (uint32_t *) mmap_region_cmd);
if (ret < 0) {
pr_err("%s: AFE memory map cmd failed %d\n",
__func__, ret);
ret = -EINVAL;
- return ret;
+ goto fail_cmd;
}
ret = wait_event_timeout(this_afe.wait[index],
@@ -976,10 +1125,13 @@
if (!ret) {
pr_err("%s: wait_event timeout\n", __func__);
ret = -EINVAL;
- return ret;
+ goto fail_cmd;
}
-
+ pr_debug("%s: mmap handle 0x%x\n", __func__, this_afe.mmap_handle);
return 0;
+fail_cmd:
+ kfree(mmap_region_cmd);
+ return ret;
}
int afe_cmd_memory_map_nowait(int port_id, u32 dma_addr_p, u32 dma_buf_sz)
@@ -1047,6 +1199,60 @@
}
return 0;
}
+int q6afe_audio_client_buf_free_contiguous(unsigned int dir,
+ struct afe_audio_client *ac)
+{
+ struct afe_audio_port_data *port;
+ int cnt = 0;
+ mutex_lock(&ac->cmd_lock);
+ port = &ac->port[dir];
+ if (!port->buf) {
+ mutex_unlock(&ac->cmd_lock);
+ return 0;
+ }
+ cnt = port->max_buf_cnt - 1;
+
+ if (port->buf[0].data) {
+ ion_unmap_kernel(port->buf[0].client, port->buf[0].handle);
+ ion_free(port->buf[0].client, port->buf[0].handle);
+ ion_client_destroy(port->buf[0].client);
+ pr_debug("%s:data[%p]phys[%p][%p] , client[%p] handle[%p]\n",
+ __func__,
+ (void *)port->buf[0].data,
+ (void *)port->buf[0].phys,
+ (void *)&port->buf[0].phys,
+ (void *)port->buf[0].client,
+ (void *)port->buf[0].handle);
+ }
+
+ while (cnt >= 0) {
+ port->buf[cnt].data = NULL;
+ port->buf[cnt].phys = 0;
+ cnt--;
+ }
+ port->max_buf_cnt = 0;
+ kfree(port->buf);
+ port->buf = NULL;
+ mutex_unlock(&ac->cmd_lock);
+ return 0;
+}
+
+void q6afe_audio_client_free(struct afe_audio_client *ac)
+{
+ int loopcnt;
+ struct afe_audio_port_data *port;
+ if (!ac)
+ return;
+ for (loopcnt = 0; loopcnt <= OUT; loopcnt++) {
+ port = &ac->port[loopcnt];
+ if (!port->buf)
+ continue;
+ pr_debug("%s:loopcnt = %d\n", __func__, loopcnt);
+ q6afe_audio_client_buf_free_contiguous(loopcnt, ac);
+ }
+ kfree(ac);
+ return;
+}
int afe_cmd_memory_unmap(u32 mem_map_handle)
{
@@ -1143,7 +1349,7 @@
int ret = 0;
struct afe_service_cmd_register_rt_port_driver rtproxy;
- pr_debug("%s:\n", __func__);
+ pr_debug("%s: port_id: %d\n", __func__, port_id);
if (this_afe.apr == NULL) {
this_afe.apr = apr_register("ADSP", "AFE", afe_callback,
@@ -1206,9 +1412,6 @@
return ret;
}
}
- index = q6audio_get_port_index(port_id);
- if (q6audio_validate_port(port_id) < 0)
- return -EINVAL;
if ((port_id == RT_PROXY_DAI_002_RX) ||
(port_id == RT_PROXY_DAI_001_TX))
@@ -1216,6 +1419,10 @@
else
return -EINVAL;
+ index = q6audio_get_port_index(port_id);
+ if (q6audio_validate_port(port_id) < 0)
+ return -EINVAL;
+
rtproxy.hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD,
APR_HDR_LEN(APR_HDR_SIZE), APR_PKT_VER);
rtproxy.hdr.pkt_size = sizeof(rtproxy);
@@ -1318,6 +1525,7 @@
afecmd_rd.buffer_address_lsw = (uint32_t)buf_addr_p;
afecmd_rd.buffer_address_msw = 0x00;
afecmd_rd.available_bytes = bytes;
+ afecmd_rd.mem_map_handle = mem_map_handle;
ret = apr_send_pkt(this_afe.apr, (uint32_t *) &afecmd_rd);
if (ret < 0) {
@@ -1665,11 +1873,11 @@
}
pr_debug("%s: port_id=%d\n", __func__, port_id);
+ port_id = q6audio_convert_virtual_to_portid(port_id);
index = q6audio_get_port_index(port_id);
if (q6audio_validate_port(port_id) < 0)
return -EINVAL;
- port_id = q6audio_convert_virtual_to_portid(port_id);
stop.hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD,
APR_HDR_LEN(APR_HDR_SIZE), APR_PKT_VER);
@@ -1708,6 +1916,7 @@
atomic_set(&this_afe.state, 0);
atomic_set(&this_afe.status, 0);
this_afe.apr = NULL;
+ this_afe.mmap_handle = 0;
for (i = 0; i < AFE_MAX_PORTS; i++)
init_waitqueue_head(&this_afe.wait[i]);