commit c3c1e56fdb5d1154aa198670ac16e2d9c6708bee
author Linux Build Service Account <lnxbuild@localhost> Thu Nov 03 13:26:55 2011 -0700
committer QuIC Gerrit Code Review <code-review@localhost> Thu Nov 03 13:26:55 2011 -0700
tree 936e5508d3fffb9c4974c5aa94f3890310ff841a
parent 2b4bf3a674e1a750883c239be78ab33768c33c61
parent df71f2ebd92223f61802f9ab2377416384426d72

Merge "msm: clock-8960: Fix LMN values of PLLs for 8064" into msm-3.0

arch/arm/mach-msm/clock-8960.c

diff --git a/arch/arm/mach-msm/clock-8960.c b/arch/arm/mach-msm/clock-8960.c
index a0c6878..6762601 100644
--- a/arch/arm/mach-msm/clock-8960.c
+++ b/arch/arm/mach-msm/clock-8960.c
@@ -5660,10 +5660,10 @@
 		/* Check if PLL8 is active */
 		is_pll_enabled = readl_relaxed(BB_PLL8_STATUS_REG) & BIT(16);
 		if (!is_pll_enabled) {
-			/* Ref clk = 24.5MHz and program pll8 to 384MHz */
-			writel_relaxed(0xF,  BB_PLL8_L_VAL_REG);
-			writel_relaxed(0x21, BB_PLL8_M_VAL_REG);
-			writel_relaxed(0x31, BB_PLL8_N_VAL_REG);
+			/* Ref clk = 27MHz and program pll8 to 384MHz */
+			writel_relaxed(0xE, BB_PLL8_L_VAL_REG);
+			writel_relaxed(0x2, BB_PLL8_M_VAL_REG);
+			writel_relaxed(0x9, BB_PLL8_N_VAL_REG);
 
 			regval = readl_relaxed(BB_PLL8_CONFIG_REG);
 
@@ -5689,10 +5689,10 @@
 		/* Check if PLL3 is active */
 		is_pll_enabled = readl_relaxed(GPLL1_STATUS_REG) & BIT(16);
 		if (!is_pll_enabled) {
-			/* Ref clk = 24.5MHz and program pll3 to 1200MHz */
-			writel_relaxed(0x30, GPLL1_L_VAL_REG);
-			writel_relaxed(0x30, GPLL1_M_VAL_REG);
-			writel_relaxed(0x31, GPLL1_N_VAL_REG);
+			/* Ref clk = 27MHz and program pll3 to 1200MHz */
+			writel_relaxed(0x2C, GPLL1_L_VAL_REG);
+			writel_relaxed(0x4,  GPLL1_M_VAL_REG);
+			writel_relaxed(0x9,  GPLL1_N_VAL_REG);
 
 			regval = readl_relaxed(GPLL1_CONFIG_REG);
 
@@ -5708,10 +5708,10 @@
 		/* Check if PLL14 is active */
 		is_pll_enabled = readl_relaxed(BB_PLL14_STATUS_REG) & BIT(16);
 		if (!is_pll_enabled) {
-			/* Ref clk = 24.5MHz and program pll14 to 480MHz */
-			writel_relaxed(0x13, BB_PLL14_L_VAL_REG);
-			writel_relaxed(0x1D, BB_PLL14_M_VAL_REG);
-			writel_relaxed(0x31, BB_PLL14_N_VAL_REG);
+			/* Ref clk = 27MHz and program pll14 to 480MHz */
+			writel_relaxed(0x11, BB_PLL14_L_VAL_REG);
+			writel_relaxed(0x7,  BB_PLL14_M_VAL_REG);
+			writel_relaxed(0x9,  BB_PLL14_N_VAL_REG);
 
 			regval = readl_relaxed(BB_PLL14_CONFIG_REG);
 
@@ -5775,10 +5775,10 @@
 		/* Check if PLL4 is active */
 		is_pll_enabled = readl_relaxed(LCC_PLL0_STATUS_REG) & BIT(16);
 		if (!is_pll_enabled) {
-			/* Ref clk = 24.5MHz and program pll4 to 393.2160MHz */
-			writel_relaxed(0x10,   LCC_PLL0_L_VAL_REG);
-			writel_relaxed(0x130,  LCC_PLL0_M_VAL_REG);
-			writel_relaxed(0x17ED, LCC_PLL0_N_VAL_REG);
+			/* Ref clk = 27MHz and program pll4 to 393.2160MHz */
+			writel_relaxed(0xE,   LCC_PLL0_L_VAL_REG);
+			writel_relaxed(0x27A, LCC_PLL0_M_VAL_REG);
+			writel_relaxed(0x465, LCC_PLL0_N_VAL_REG);
 
 			regval = readl_relaxed(LCC_PLL0_CONFIG_REG);