Serial: pxa: work around Errata #75
Intel(R) PXA27x Processor Family Specification Update (Nov 2005)
says:
E75. UART: Baud rate may not be programmed correctly on
back-to-back writes.
Problem:
When programming the Divisor Latch registers, Low and High (DLL and
DLH), with back-to-back writes, the second register write may not
take effect. The result is an incorrect baud rate.
Workaround:
After programming the first Divisor Latch register, read and verify
it before programming the second Divisor Latch register.
This was hit when changing the baud rate from 115200 to 9600 while
receiving characters at 9600 Bd.
And fixed indention of some comments nearby.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Acked-by: Wolfram Sang <w.sang@pengutronix.de>
Acked-by: Marc Kleine-Budde <mkl@pengutronix.de>
Cc: Eric Miao <eric.y.miao@gmail.com>
Cc: Alan Cox <alan@linux.intel.com>
Cc: Mike Rapoport <mike@compulab.co.il>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
1 file changed