tree e6dd23cbcc33b69ea0ca421a07bb400d137932d9
parent 11ca3d15e79bf42765274c5846d8f78d8826b0b9
author Subhash Jadavani <subhashj@codeaurora.org> 1340692030 +0530
committer Linux Build Service Account <lnxbuild@localhost> 1341413618 -0600

msm: board: enable HS200 bus speed mode support

eMMC4.5 specification supports HS200 bus speed mode which allows the
card interface clock to run at more than 52MHz and maximum up to 200MHz.
On most of our existing chipsets we interface eMMC cards on SDC1 slot
as it give 8-bit data interface but timing closure for this slot is not
done for >100MHz clock on any of the existing chipsets (MSM8960, MSM8930
& APQ8064).

Since the timing closure is done till 100 MHz, we can enable HS200 mode
that runs at max. 100MHz. Recent performance measurements also indicate
that HS200 @96MHz (Clock plan supports max. 96MHz) gives better
performance than DDR@48MHz. So enable HS200 @96 MHz. On future targets
which get timing closed at ~200MHz, HS200 at that frequency will be
enabled.

Change-Id: I726e65ec99a9ead99ce683844e7cc15ece7a225e
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>