tree aea5d69fa11b2925336ac61c83a122611bb57808
parent c2e2a313ff8fdc25cedef5e63da712a6a0d35dfe
author Richard Cochran <richardcochran@gmail.com> 1312664583 +0000
committer David S. Miller <davem@davemloft.net> 1312782802 -0700

gianfar: fix fiper alignment after resetting the time

After resetting the time, the PPS signals on the FIPER output channels
are incorrectly offset from the clock time, as can be readily verified
by a looping back the FIPER to the external time stamp input.

Despite its name, setting the "Fiper Realignment Disable" bit seems to
fix the problem, at least on the P2020.

Also, following the example code from the Freescale BSP, it is not really
necessary to disable and re-enable the timer in order to reprogram the
FIPER. (The documentation is rather unclear on this point. It seems that
writing to the alarm register also disables the FIPER.)

Signed-off-by: Richard Cochran <richard.cochran@omicron.at>
Cc: <stable@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>