| commit | ce54afd16d874ac07378a8bb55d26f7f5b613c0e | [log] [tgz] |
|---|---|---|
| author | Bruce Allan <bruce.w.allan@intel.com> | Wed Nov 24 06:01:41 2010 +0000 |
| committer | Jeff Kirsher <jeffrey.t.kirsher@intel.com> | Fri Dec 10 22:13:27 2010 -0800 |
| tree | abad7c3150c4acbf3012168d71d611523459694a | |
| parent | d9c76f99c2a79feb413e3e751362d59c0f5323f6 [diff] |
e1000e: 82577/8/9 mis-configured OEM bits during S0->Sx The LPLU (Low Power Link Up) and Gigabit Disable bits (a.k.a. OEM bits) were being configured incorrectly when device goes to D3 state. Signed-off-by: Bruce Allan <bruce.w.allan@intel.com> Tested-by: Jeff Pieper <jeffrey.e.pieper@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>