mmc: msm_sdcc: use DATA_PEND bit for CMD53 write operation
DATA_PEND bit (in MCI_DATA_CTL register) was designed to be used
with CMD24 (WRITE_SINGLE_BLOCK) and CMD25 (WRITE_MULTIPLE_BLOCK) to
automatically start the DPSM (Data Path State Machine) after a normal
(non-error) response is received for CMD24/CMD25. To use this feature,
MCI_DATA_CTL register should be written with the enable bit and the
pending bit asserted before ENABLE bit is set in MCI_CMD register.
Now, SDCC controller on newer chipsets like 8974/9625, supports the
DATA_PEND bit for CMD53 write operations as well.
As of now SDCC driver is not using the DATA_PEND bit for CMD53 write
which means for write operation, driver first sends the write command
to card and then waits for the CMD_RESPOND_END interrupt
and then configures ADM/BAM and DATA_CTL register (with ENABLE bit set)
in interrupt context.
Instead now driver can configure the DPSM (have to set DATA_PEND bit as
well) before configuring CPSM (Command Path State Machine) to send write
command. So basically this will be the configuration sequence if
we use DATA_PEND bit:
1. Configure ADM/BAM.
2. Configure DATA_CTL with both DATA_PEND and ENABLE bits set.
3. Configure MCI_CMD register for sending the write command.
All of the above configuration will now happen at the same time in
process context.
Change-Id: I57f15ecddf0d150cdab78370eb29a622a690bd69
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
diff --git a/drivers/mmc/host/msm_sdcc.h b/drivers/mmc/host/msm_sdcc.h
index af5498e..9fa2027 100644
--- a/drivers/mmc/host/msm_sdcc.h
+++ b/drivers/mmc/host/msm_sdcc.h
@@ -446,6 +446,7 @@
#define MSMSDCC_AUTO_CMD19 (1 << 9)
#define MSMSDCC_AUTO_CMD21 (1 << 10)
#define MSMSDCC_SW_RST_CFG_BROKEN (1 << 11)
+#define MSMSDCC_DATA_PEND_FOR_CMD53 (1 << 12)
#define set_hw_caps(h, val) ((h)->hw_caps |= val)
#define is_sps_mode(h) ((h)->hw_caps & MSMSDCC_SPS_BAM_SUP)
@@ -461,6 +462,7 @@
#define is_auto_cmd21(h) ((h)->hw_caps & MSMSDCC_AUTO_CMD21)
#define is_sw_reset_save_config_broken(h) \
((h)->hw_caps & MSMSDCC_SW_RST_CFG_BROKEN)
+#define is_data_pend_for_cmd53(h) ((h)->hw_caps & MSMSDCC_DATA_PEND_FOR_CMD53)
/* Set controller capabilities based on version */
static inline void set_default_hw_caps(struct msmsdcc_host *host)
@@ -493,7 +495,8 @@
if (step >= 0x2b) /* SDCC v4 2.1.0 and greater */
host->hw_caps |= MSMSDCC_SW_RST | MSMSDCC_SW_RST_CFG |
- MSMSDCC_AUTO_CMD21;
+ MSMSDCC_AUTO_CMD21 |
+ MSMSDCC_DATA_PEND_FOR_CMD53;
if (step == 0x2b)
host->hw_caps |= MSMSDCC_SW_RST_CFG_BROKEN;