blob: 2c8f14766997bdea35016d00f82de19dd21ea3cb [file] [log] [blame]
/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/i2c.h>
#include <linux/slimbus/slimbus.h>
#include <linux/mfd/wcd9310/core.h>
#include <linux/mfd/wcd9310/pdata.h>
#include <linux/msm_ssbi.h>
#include <linux/spi/spi.h>
#include <linux/dma-mapping.h>
#include <linux/platform_data/qcom_crypto_device.h>
#include <linux/ion.h>
#include <linux/memory.h>
#include <linux/i2c/atmel_mxt_ts.h>
#include <linux/cyttsp.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/hardware/gic.h>
#include <asm/mach/mmc.h>
#include <linux/platform_data/qcom_wcnss_device.h>
#include <mach/board.h>
#include <mach/msm_iomap.h>
#include <mach/ion.h>
#include <linux/usb/msm_hsusb.h>
#include <linux/usb/android.h>
#include <mach/socinfo.h>
#include <mach/msm_spi.h>
#include "timer.h"
#include "devices.h"
#include <mach/gpio.h>
#include <mach/gpiomux.h>
#include <mach/rpm.h>
#ifdef CONFIG_ANDROID_PMEM
#include <linux/android_pmem.h>
#endif
#include <mach/msm_memtypes.h>
#include <linux/bootmem.h>
#include <asm/setup.h>
#include <mach/dma.h>
#include <mach/msm_bus_board.h>
#include <mach/cpuidle.h>
#include <mach/mdm2.h>
#include <linux/msm_tsens.h>
#include "msm_watchdog.h"
#include "board-8064.h"
#include "acpuclock.h"
#include "spm.h"
#include "mpm.h"
#include "rpm_resources.h"
#include "pm.h"
#include "pm-boot.h"
#include "devices-msm8x60.h"
#define MSM_PMEM_ADSP_SIZE 0x7800000
#define MSM_PMEM_AUDIO_SIZE 0x2B4000
#ifdef CONFIG_FB_MSM_HDMI_AS_PRIMARY
#define MSM_PMEM_SIZE 0x4000000 /* 64 Mbytes */
#else
#define MSM_PMEM_SIZE 0x2800000 /* 40 Mbytes */
#endif
#ifdef CONFIG_MSM_MULTIMEDIA_USE_ION
#define MSM_PMEM_KERNEL_EBI1_SIZE 0x280000
#define MSM_ION_SF_SIZE MSM_PMEM_SIZE
#define MSM_ION_MM_FW_SIZE 0x200000 /* (2MB) */
#define MSM_ION_MM_SIZE MSM_PMEM_ADSP_SIZE
#define MSM_ION_QSECOM_SIZE 0x100000 /* (1MB) */
#define MSM_ION_MFC_SIZE SZ_8K
#define MSM_ION_AUDIO_SIZE MSM_PMEM_AUDIO_SIZE
#define MSM_ION_HEAP_NUM 8
#else
#define MSM_PMEM_KERNEL_EBI1_SIZE 0x110C000
#define MSM_ION_HEAP_NUM 1
#endif
#ifdef CONFIG_KERNEL_PMEM_EBI_REGION
static unsigned pmem_kernel_ebi1_size = MSM_PMEM_KERNEL_EBI1_SIZE;
static int __init pmem_kernel_ebi1_size_setup(char *p)
{
pmem_kernel_ebi1_size = memparse(p, NULL);
return 0;
}
early_param("pmem_kernel_ebi1_size", pmem_kernel_ebi1_size_setup);
#endif
#ifdef CONFIG_ANDROID_PMEM
static unsigned pmem_size = MSM_PMEM_SIZE;
static int __init pmem_size_setup(char *p)
{
pmem_size = memparse(p, NULL);
return 0;
}
early_param("pmem_size", pmem_size_setup);
static unsigned pmem_adsp_size = MSM_PMEM_ADSP_SIZE;
static int __init pmem_adsp_size_setup(char *p)
{
pmem_adsp_size = memparse(p, NULL);
return 0;
}
early_param("pmem_adsp_size", pmem_adsp_size_setup);
static unsigned pmem_audio_size = MSM_PMEM_AUDIO_SIZE;
static int __init pmem_audio_size_setup(char *p)
{
pmem_audio_size = memparse(p, NULL);
return 0;
}
early_param("pmem_audio_size", pmem_audio_size_setup);
#endif
#ifdef CONFIG_ANDROID_PMEM
#ifndef CONFIG_MSM_MULTIMEDIA_USE_ION
static struct android_pmem_platform_data android_pmem_pdata = {
.name = "pmem",
.allocator_type = PMEM_ALLOCATORTYPE_ALLORNOTHING,
.cached = 1,
.memory_type = MEMTYPE_EBI1,
};
static struct platform_device android_pmem_device = {
.name = "android_pmem",
.id = 0,
.dev = {.platform_data = &android_pmem_pdata},
};
static struct android_pmem_platform_data android_pmem_adsp_pdata = {
.name = "pmem_adsp",
.allocator_type = PMEM_ALLOCATORTYPE_BITMAP,
.cached = 0,
.memory_type = MEMTYPE_EBI1,
};
static struct platform_device android_pmem_adsp_device = {
.name = "android_pmem",
.id = 2,
.dev = { .platform_data = &android_pmem_adsp_pdata },
};
#endif
static struct android_pmem_platform_data android_pmem_audio_pdata = {
.name = "pmem_audio",
.allocator_type = PMEM_ALLOCATORTYPE_BITMAP,
.cached = 0,
.memory_type = MEMTYPE_EBI1,
};
static struct platform_device android_pmem_audio_device = {
.name = "android_pmem",
.id = 4,
.dev = { .platform_data = &android_pmem_audio_pdata },
};
#endif
static struct memtype_reserve apq8064_reserve_table[] __initdata = {
[MEMTYPE_SMI] = {
},
[MEMTYPE_EBI0] = {
.flags = MEMTYPE_FLAGS_1M_ALIGN,
},
[MEMTYPE_EBI1] = {
.flags = MEMTYPE_FLAGS_1M_ALIGN,
},
};
static void __init size_pmem_devices(void)
{
#ifdef CONFIG_ANDROID_PMEM
#ifndef CONFIG_MSM_MULTIMEDIA_USE_ION
android_pmem_adsp_pdata.size = pmem_adsp_size;
android_pmem_pdata.size = pmem_size;
#endif
android_pmem_audio_pdata.size = MSM_PMEM_AUDIO_SIZE;
#endif
}
static void __init reserve_memory_for(struct android_pmem_platform_data *p)
{
apq8064_reserve_table[p->memory_type].size += p->size;
}
static void __init reserve_pmem_memory(void)
{
#ifdef CONFIG_ANDROID_PMEM
#ifndef CONFIG_MSM_MULTIMEDIA_USE_ION
reserve_memory_for(&android_pmem_adsp_pdata);
reserve_memory_for(&android_pmem_pdata);
#endif
reserve_memory_for(&android_pmem_audio_pdata);
apq8064_reserve_table[MEMTYPE_EBI1].size += pmem_kernel_ebi1_size;
#endif
}
static int apq8064_paddr_to_memtype(unsigned int paddr)
{
return MEMTYPE_EBI1;
}
#ifdef CONFIG_ION_MSM
#ifdef CONFIG_MSM_MULTIMEDIA_USE_ION
static struct ion_cp_heap_pdata cp_mm_ion_pdata = {
.permission_type = IPT_TYPE_MM_CARVEOUT,
.align = PAGE_SIZE,
};
static struct ion_cp_heap_pdata cp_mfc_ion_pdata = {
.permission_type = IPT_TYPE_MFC_SHAREDMEM,
.align = PAGE_SIZE,
};
static struct ion_co_heap_pdata co_ion_pdata = {
.adjacent_mem_id = INVALID_HEAP_ID,
.align = PAGE_SIZE,
};
static struct ion_co_heap_pdata fw_co_ion_pdata = {
.adjacent_mem_id = ION_CP_MM_HEAP_ID,
.align = SZ_128K,
};
#endif
static struct ion_platform_data ion_pdata = {
.nr = MSM_ION_HEAP_NUM,
.heaps = {
{
.id = ION_SYSTEM_HEAP_ID,
.type = ION_HEAP_TYPE_SYSTEM,
.name = ION_VMALLOC_HEAP_NAME,
},
#ifdef CONFIG_MSM_MULTIMEDIA_USE_ION
{
.id = ION_SF_HEAP_ID,
.type = ION_HEAP_TYPE_CARVEOUT,
.name = ION_SF_HEAP_NAME,
.size = MSM_ION_SF_SIZE,
.memory_type = ION_EBI_TYPE,
.extra_data = (void *) &co_ion_pdata,
},
{
.id = ION_CP_MM_HEAP_ID,
.type = ION_HEAP_TYPE_CP,
.name = ION_MM_HEAP_NAME,
.size = MSM_ION_MM_SIZE,
.memory_type = ION_EBI_TYPE,
.extra_data = (void *) &cp_mm_ion_pdata,
},
{
.id = ION_MM_FIRMWARE_HEAP_ID,
.type = ION_HEAP_TYPE_CARVEOUT,
.name = ION_MM_FIRMWARE_HEAP_NAME,
.size = MSM_ION_MM_FW_SIZE,
.memory_type = ION_EBI_TYPE,
.extra_data = (void *) &fw_co_ion_pdata,
},
{
.id = ION_CP_MFC_HEAP_ID,
.type = ION_HEAP_TYPE_CP,
.name = ION_MFC_HEAP_NAME,
.size = MSM_ION_MFC_SIZE,
.memory_type = ION_EBI_TYPE,
.extra_data = (void *) &cp_mfc_ion_pdata,
},
{
.id = ION_IOMMU_HEAP_ID,
.type = ION_HEAP_TYPE_IOMMU,
.name = ION_IOMMU_HEAP_NAME,
},
{
.id = ION_QSECOM_HEAP_ID,
.type = ION_HEAP_TYPE_CARVEOUT,
.name = ION_QSECOM_HEAP_NAME,
.size = MSM_ION_QSECOM_SIZE,
.memory_type = ION_EBI_TYPE,
.extra_data = (void *) &co_ion_pdata,
},
{
.id = ION_AUDIO_HEAP_ID,
.type = ION_HEAP_TYPE_CARVEOUT,
.name = ION_AUDIO_HEAP_NAME,
.size = MSM_ION_AUDIO_SIZE,
.memory_type = ION_EBI_TYPE,
.extra_data = (void *) &co_ion_pdata,
},
#endif
}
};
static struct platform_device ion_dev = {
.name = "ion-msm",
.id = 1,
.dev = { .platform_data = &ion_pdata },
};
#endif
static void reserve_ion_memory(void)
{
#if defined(CONFIG_ION_MSM) && defined(CONFIG_MSM_MULTIMEDIA_USE_ION)
apq8064_reserve_table[MEMTYPE_EBI1].size += MSM_ION_MM_SIZE;
apq8064_reserve_table[MEMTYPE_EBI1].size += MSM_ION_MM_FW_SIZE;
apq8064_reserve_table[MEMTYPE_EBI1].size += MSM_ION_SF_SIZE;
apq8064_reserve_table[MEMTYPE_EBI1].size += MSM_ION_MFC_SIZE;
apq8064_reserve_table[MEMTYPE_EBI1].size += MSM_ION_QSECOM_SIZE;
apq8064_reserve_table[MEMTYPE_EBI1].size += MSM_ION_AUDIO_SIZE;
#endif
}
static void __init reserve_mdp_memory(void)
{
apq8064_mdp_writeback(apq8064_reserve_table);
}
static void __init apq8064_calculate_reserve_sizes(void)
{
size_pmem_devices();
reserve_pmem_memory();
reserve_ion_memory();
reserve_mdp_memory();
}
static struct reserve_info apq8064_reserve_info __initdata = {
.memtype_reserve_table = apq8064_reserve_table,
.calculate_reserve_sizes = apq8064_calculate_reserve_sizes,
.paddr_to_memtype = apq8064_paddr_to_memtype,
};
static int apq8064_memory_bank_size(void)
{
return 1<<29;
}
static void __init locate_unstable_memory(void)
{
struct membank *mb = &meminfo.bank[meminfo.nr_banks - 1];
unsigned long bank_size;
unsigned long low, high;
bank_size = apq8064_memory_bank_size();
low = meminfo.bank[0].start;
high = mb->start + mb->size;
/* Check if 32 bit overflow occured */
if (high < mb->start)
high = ~0UL;
low &= ~(bank_size - 1);
if (high - low <= bank_size)
return;
apq8064_reserve_info.low_unstable_address = mb->start -
MIN_MEMORY_BLOCK_SIZE + mb->size;
apq8064_reserve_info.max_unstable_size = MIN_MEMORY_BLOCK_SIZE;
apq8064_reserve_info.bank_size = bank_size;
pr_info("low unstable address %lx max size %lx bank size %lx\n",
apq8064_reserve_info.low_unstable_address,
apq8064_reserve_info.max_unstable_size,
apq8064_reserve_info.bank_size);
}
static void __init apq8064_reserve(void)
{
reserve_info = &apq8064_reserve_info;
locate_unstable_memory();
msm_reserve();
}
#ifdef CONFIG_USB_EHCI_MSM_HSIC
static struct msm_hsic_host_platform_data msm_hsic_pdata = {
.strobe = 88,
.data = 89,
};
#else
static struct msm_hsic_host_platform_data msm_hsic_pdata;
#endif
#define PID_MAGIC_ID 0x71432909
#define SERIAL_NUM_MAGIC_ID 0x61945374
#define SERIAL_NUMBER_LENGTH 127
#define DLOAD_USB_BASE_ADD 0x2A03F0C8
struct magic_num_struct {
uint32_t pid;
uint32_t serial_num;
};
struct dload_struct {
uint32_t reserved1;
uint32_t reserved2;
uint32_t reserved3;
uint16_t reserved4;
uint16_t pid;
char serial_number[SERIAL_NUMBER_LENGTH];
uint16_t reserved5;
struct magic_num_struct magic_struct;
};
static int usb_diag_update_pid_and_serial_num(uint32_t pid, const char *snum)
{
struct dload_struct __iomem *dload = 0;
dload = ioremap(DLOAD_USB_BASE_ADD, sizeof(*dload));
if (!dload) {
pr_err("%s: cannot remap I/O memory region: %08x\n",
__func__, DLOAD_USB_BASE_ADD);
return -ENXIO;
}
pr_debug("%s: dload:%p pid:%x serial_num:%s\n",
__func__, dload, pid, snum);
/* update pid */
dload->magic_struct.pid = PID_MAGIC_ID;
dload->pid = pid;
/* update serial number */
dload->magic_struct.serial_num = 0;
if (!snum) {
memset(dload->serial_number, 0, SERIAL_NUMBER_LENGTH);
goto out;
}
dload->magic_struct.serial_num = SERIAL_NUM_MAGIC_ID;
strlcpy(dload->serial_number, snum, SERIAL_NUMBER_LENGTH);
out:
iounmap(dload);
return 0;
}
static struct android_usb_platform_data android_usb_pdata = {
.update_pid_and_serial_num = usb_diag_update_pid_and_serial_num,
};
static struct platform_device android_usb_device = {
.name = "android_usb",
.id = -1,
.dev = {
.platform_data = &android_usb_pdata,
},
};
static struct msm_otg_platform_data msm_otg_pdata = {
.mode = USB_OTG,
.otg_control = OTG_PMIC_CONTROL,
.phy_type = SNPS_28NM_INTEGRATED_PHY,
.pmic_id_irq = PM8921_USB_ID_IN_IRQ(PM8921_IRQ_BASE),
.power_budget = 750,
};
#define TABLA_INTERRUPT_BASE (NR_MSM_IRQS + NR_GPIO_IRQS + NR_PM8921_IRQS)
/* Micbias setting is based on 8660 CDP/MTP/FLUID requirement
* 4 micbiases are used to power various analog and digital
* microphones operating at 1800 mV. Technically, all micbiases
* can source from single cfilter since all microphones operate
* at the same voltage level. The arrangement below is to make
* sure all cfilters are exercised. LDO_H regulator ouput level
* does not need to be as high as 2.85V. It is choosen for
* microphone sensitivity purpose.
*/
static struct tabla_pdata apq8064_tabla_platform_data = {
.slimbus_slave_device = {
.name = "tabla-slave",
.e_addr = {0, 0, 0x10, 0, 0x17, 2},
},
.irq = MSM_GPIO_TO_INT(42),
.irq_base = TABLA_INTERRUPT_BASE,
.num_irqs = NR_TABLA_IRQS,
.reset_gpio = PM8921_GPIO_PM_TO_SYS(34),
.micbias = {
.ldoh_v = TABLA_LDOH_2P85_V,
.cfilt1_mv = 1800,
.cfilt2_mv = 1800,
.cfilt3_mv = 1800,
.bias1_cfilt_sel = TABLA_CFILT1_SEL,
.bias2_cfilt_sel = TABLA_CFILT2_SEL,
.bias3_cfilt_sel = TABLA_CFILT3_SEL,
.bias4_cfilt_sel = TABLA_CFILT3_SEL,
}
};
static struct slim_device apq8064_slim_tabla = {
.name = "tabla-slim",
.e_addr = {0, 1, 0x10, 0, 0x17, 2},
.dev = {
.platform_data = &apq8064_tabla_platform_data,
},
};
static struct tabla_pdata apq8064_tabla20_platform_data = {
.slimbus_slave_device = {
.name = "tabla-slave",
.e_addr = {0, 0, 0x60, 0, 0x17, 2},
},
.irq = MSM_GPIO_TO_INT(42),
.irq_base = TABLA_INTERRUPT_BASE,
.num_irqs = NR_TABLA_IRQS,
.reset_gpio = PM8921_GPIO_PM_TO_SYS(34),
.micbias = {
.ldoh_v = TABLA_LDOH_2P85_V,
.cfilt1_mv = 1800,
.cfilt2_mv = 1800,
.cfilt3_mv = 1800,
.bias1_cfilt_sel = TABLA_CFILT1_SEL,
.bias2_cfilt_sel = TABLA_CFILT2_SEL,
.bias3_cfilt_sel = TABLA_CFILT3_SEL,
.bias4_cfilt_sel = TABLA_CFILT3_SEL,
}
};
static struct slim_device apq8064_slim_tabla20 = {
.name = "tabla2x-slim",
.e_addr = {0, 1, 0x60, 0, 0x17, 2},
.dev = {
.platform_data = &apq8064_tabla20_platform_data,
},
};
/* configuration data for mxt1386e using V2.1 firmware */
static const u8 mxt1386e_config_data_v2_1[] = {
/* T6 Object */
0, 0, 0, 0, 0, 0,
/* T38 Object */
14, 0, 0, 24, 1, 12, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0,
/* T7 Object */
100, 16, 50,
/* T8 Object */
25, 0, 20, 20, 0, 0, 20, 50, 0, 0,
/* T9 Object */
131, 0, 0, 26, 42, 0, 32, 80, 2, 5,
0, 5, 5, 0, 10, 30, 10, 10, 255, 2,
85, 5, 10, 10, 10, 10, 135, 55, 70, 40,
10, 5, 0, 0, 0,
/* T18 Object */
0, 0,
/* T24 Object */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0,
/* T25 Object */
3, 0, 60, 115, 156, 99,
/* T27 Object */
0, 0, 0, 0, 0, 0, 0,
/* T40 Object */
0, 0, 0, 0, 0,
/* T42 Object */
2, 0, 255, 0, 255, 0, 0, 0, 0, 0,
/* T43 Object */
0, 0, 0, 0, 0, 0, 0, 64, 0, 8,
16,
/* T46 Object */
64, 0, 20, 20, 0, 0, 0, 0, 0,
/* T47 Object */
0, 0, 0, 0, 0, 0, 3, 64, 66, 0,
/* T48 Object */
31, 64, 64, 0, 0, 0, 0, 0, 0, 0,
48, 40, 0, 10, 10, 0, 0, 100, 10, 80,
0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
52, 0, 12, 0, 17, 0, 1, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0,
/* T56 Object */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2, 99, 33, 0, 149, 24, 193, 255, 255, 255,
255,
};
#define MXT_TS_GPIO_IRQ 6
#define MXT_TS_PWR_EN_GPIO PM8921_GPIO_PM_TO_SYS(23)
#define MXT_TS_RESET_GPIO 33
static struct mxt_config_info mxt_config_array[] = {
{
.config = mxt1386e_config_data_v2_1,
.config_length = ARRAY_SIZE(mxt1386e_config_data_v2_1),
.family_id = 0xA0,
.variant_id = 0x7,
.version = 0x21,
.build = 0xAA,
},
};
static struct mxt_platform_data mxt_platform_data = {
.config_array = mxt_config_array,
.config_array_size = ARRAY_SIZE(mxt_config_array),
.x_size = 1365,
.y_size = 767,
.irqflags = IRQF_TRIGGER_FALLING,
.i2c_pull_up = true,
.reset_gpio = MXT_TS_RESET_GPIO,
.irq_gpio = MXT_TS_GPIO_IRQ,
};
static struct i2c_board_info mxt_device_info[] __initdata = {
{
I2C_BOARD_INFO("atmel_mxt_ts", 0x5b),
.platform_data = &mxt_platform_data,
.irq = MSM_GPIO_TO_INT(MXT_TS_GPIO_IRQ),
},
};
#define CYTTSP_TS_GPIO_IRQ 6
#define CYTTSP_TS_GPIO_RESOUT 7
#define CYTTSP_TS_GPIO_SLEEP 33
static ssize_t tma340_vkeys_show(struct kobject *kobj,
struct kobj_attribute *attr, char *buf)
{
return snprintf(buf, 200,
__stringify(EV_KEY) ":" __stringify(KEY_BACK) ":73:1120:97:97"
":" __stringify(EV_KEY) ":" __stringify(KEY_MENU) ":230:1120:97:97"
":" __stringify(EV_KEY) ":" __stringify(KEY_HOME) ":389:1120:97:97"
":" __stringify(EV_KEY) ":" __stringify(KEY_SEARCH) ":544:1120:97:97"
"\n");
}
static struct kobj_attribute tma340_vkeys_attr = {
.attr = {
.mode = S_IRUGO,
},
.show = &tma340_vkeys_show,
};
static struct attribute *tma340_properties_attrs[] = {
&tma340_vkeys_attr.attr,
NULL
};
static struct attribute_group tma340_properties_attr_group = {
.attrs = tma340_properties_attrs,
};
static int cyttsp_platform_init(struct i2c_client *client)
{
int rc = 0;
static struct kobject *tma340_properties_kobj;
tma340_vkeys_attr.attr.name = "virtualkeys.cyttsp-i2c";
tma340_properties_kobj = kobject_create_and_add("board_properties",
NULL);
if (tma340_properties_kobj)
rc = sysfs_create_group(tma340_properties_kobj,
&tma340_properties_attr_group);
if (!tma340_properties_kobj || rc)
pr_err("%s: failed to create board_properties\n",
__func__);
return 0;
}
static struct cyttsp_regulator cyttsp_regulator_data[] = {
{
.name = "vdd",
.min_uV = CY_TMA300_VTG_MIN_UV,
.max_uV = CY_TMA300_VTG_MAX_UV,
.hpm_load_uA = CY_TMA300_CURR_24HZ_UA,
.lpm_load_uA = CY_TMA300_CURR_24HZ_UA,
},
{
.name = "vcc_i2c",
.min_uV = CY_I2C_VTG_MIN_UV,
.max_uV = CY_I2C_VTG_MAX_UV,
.hpm_load_uA = CY_I2C_CURR_UA,
.lpm_load_uA = CY_I2C_CURR_UA,
},
};
static struct cyttsp_platform_data cyttsp_pdata = {
.panel_maxx = 634,
.panel_maxy = 1166,
.disp_maxx = 599,
.disp_maxy = 1023,
.disp_minx = 0,
.disp_miny = 0,
.flags = 0x01,
.gen = CY_GEN3,
.use_st = CY_USE_ST,
.use_mt = CY_USE_MT,
.use_hndshk = CY_SEND_HNDSHK,
.use_trk_id = CY_USE_TRACKING_ID,
.use_sleep = CY_USE_DEEP_SLEEP_SEL,
.use_gestures = CY_USE_GESTURES,
.fw_fname = "cyttsp_8064_mtp.hex",
/* change act_intrvl to customize the Active power state
* scanning/processing refresh interval for Operating mode
*/
.act_intrvl = CY_ACT_INTRVL_DFLT,
/* change tch_tmout to customize the touch timeout for the
* Active power state for Operating mode
*/
.tch_tmout = CY_TCH_TMOUT_DFLT,
/* change lp_intrvl to customize the Low Power power state
* scanning/processing refresh interval for Operating mode
*/
.lp_intrvl = CY_LP_INTRVL_DFLT,
.sleep_gpio = CYTTSP_TS_GPIO_SLEEP,
.resout_gpio = CYTTSP_TS_GPIO_RESOUT,
.irq_gpio = CYTTSP_TS_GPIO_IRQ,
.regulator_info = cyttsp_regulator_data,
.num_regulators = ARRAY_SIZE(cyttsp_regulator_data),
.init = cyttsp_platform_init,
.correct_fw_ver = 17,
};
static struct i2c_board_info cyttsp_info[] __initdata = {
{
I2C_BOARD_INFO(CY_I2C_NAME, 0x24),
.platform_data = &cyttsp_pdata,
.irq = MSM_GPIO_TO_INT(CYTTSP_TS_GPIO_IRQ),
},
};
#define MSM_WCNSS_PHYS 0x03000000
#define MSM_WCNSS_SIZE 0x280000
static struct resource resources_wcnss_wlan[] = {
{
.start = RIVA_APPS_WLAN_RX_DATA_AVAIL_IRQ,
.end = RIVA_APPS_WLAN_RX_DATA_AVAIL_IRQ,
.name = "wcnss_wlanrx_irq",
.flags = IORESOURCE_IRQ,
},
{
.start = RIVA_APPS_WLAN_DATA_XFER_DONE_IRQ,
.end = RIVA_APPS_WLAN_DATA_XFER_DONE_IRQ,
.name = "wcnss_wlantx_irq",
.flags = IORESOURCE_IRQ,
},
{
.start = MSM_WCNSS_PHYS,
.end = MSM_WCNSS_PHYS + MSM_WCNSS_SIZE - 1,
.name = "wcnss_mmio",
.flags = IORESOURCE_MEM,
},
{
.start = 64,
.end = 68,
.name = "wcnss_gpios_5wire",
.flags = IORESOURCE_IO,
},
};
static struct qcom_wcnss_opts qcom_wcnss_pdata = {
.has_48mhz_xo = 1,
};
static struct platform_device msm_device_wcnss_wlan = {
.name = "wcnss_wlan",
.id = 0,
.num_resources = ARRAY_SIZE(resources_wcnss_wlan),
.resource = resources_wcnss_wlan,
.dev = {.platform_data = &qcom_wcnss_pdata},
};
#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE) || \
defined(CONFIG_CRYPTO_DEV_QCEDEV) || \
defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE)
#define QCE_SIZE 0x10000
#define QCE_0_BASE 0x11000000
#define QCE_HW_KEY_SUPPORT 0
#define QCE_SHA_HMAC_SUPPORT 1
#define QCE_SHARE_CE_RESOURCE 3
#define QCE_CE_SHARED 0
static struct resource qcrypto_resources[] = {
[0] = {
.start = QCE_0_BASE,
.end = QCE_0_BASE + QCE_SIZE - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.name = "crypto_channels",
.start = DMOV8064_CE_IN_CHAN,
.end = DMOV8064_CE_OUT_CHAN,
.flags = IORESOURCE_DMA,
},
[2] = {
.name = "crypto_crci_in",
.start = DMOV8064_CE_IN_CRCI,
.end = DMOV8064_CE_IN_CRCI,
.flags = IORESOURCE_DMA,
},
[3] = {
.name = "crypto_crci_out",
.start = DMOV8064_CE_OUT_CRCI,
.end = DMOV8064_CE_OUT_CRCI,
.flags = IORESOURCE_DMA,
},
};
static struct resource qcedev_resources[] = {
[0] = {
.start = QCE_0_BASE,
.end = QCE_0_BASE + QCE_SIZE - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.name = "crypto_channels",
.start = DMOV8064_CE_IN_CHAN,
.end = DMOV8064_CE_OUT_CHAN,
.flags = IORESOURCE_DMA,
},
[2] = {
.name = "crypto_crci_in",
.start = DMOV8064_CE_IN_CRCI,
.end = DMOV8064_CE_IN_CRCI,
.flags = IORESOURCE_DMA,
},
[3] = {
.name = "crypto_crci_out",
.start = DMOV8064_CE_OUT_CRCI,
.end = DMOV8064_CE_OUT_CRCI,
.flags = IORESOURCE_DMA,
},
};
#endif
#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE)
static struct msm_ce_hw_support qcrypto_ce_hw_suppport = {
.ce_shared = QCE_CE_SHARED,
.shared_ce_resource = QCE_SHARE_CE_RESOURCE,
.hw_key_support = QCE_HW_KEY_SUPPORT,
.sha_hmac = QCE_SHA_HMAC_SUPPORT,
.bus_scale_table = NULL,
};
static struct platform_device qcrypto_device = {
.name = "qcrypto",
.id = 0,
.num_resources = ARRAY_SIZE(qcrypto_resources),
.resource = qcrypto_resources,
.dev = {
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &qcrypto_ce_hw_suppport,
},
};
#endif
#if defined(CONFIG_CRYPTO_DEV_QCEDEV) || \
defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE)
static struct msm_ce_hw_support qcedev_ce_hw_suppport = {
.ce_shared = QCE_CE_SHARED,
.shared_ce_resource = QCE_SHARE_CE_RESOURCE,
.hw_key_support = QCE_HW_KEY_SUPPORT,
.sha_hmac = QCE_SHA_HMAC_SUPPORT,
.bus_scale_table = NULL,
};
static struct platform_device qcedev_device = {
.name = "qce",
.id = 0,
.num_resources = ARRAY_SIZE(qcedev_resources),
.resource = qcedev_resources,
.dev = {
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &qcedev_ce_hw_suppport,
},
};
#endif
static struct mdm_platform_data mdm_platform_data = {
.mdm_version = "3.0",
.ramdump_delay_ms = 2000,
.peripheral_platform_device = &apq8064_device_hsic_host,
};
static struct tsens_platform_data apq_tsens_pdata = {
.tsens_factor = 1000,
.hw_type = APQ_8064,
.tsens_num_sensor = 11,
.slope = {1176, 1176, 1154, 1176, 1111,
1132, 1132, 1199, 1132, 1199, 1132},
};
#define MSM_SHARED_RAM_PHYS 0x80000000
static void __init apq8064_map_io(void)
{
msm_shared_ram_phys = MSM_SHARED_RAM_PHYS;
msm_map_apq8064_io();
if (socinfo_init() < 0)
pr_err("socinfo_init() failed!\n");
}
static void __init apq8064_init_irq(void)
{
struct msm_mpm_device_data *data = NULL;
#ifdef CONFIG_MSM_MPM
data = &apq8064_mpm_dev_data;
#endif
msm_mpm_irq_extn_init(data);
gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE,
(void *)MSM_QGIC_CPU_BASE);
}
static struct platform_device msm8064_device_saw_regulator_core0 = {
.name = "saw-regulator",
.id = 0,
.dev = {
.platform_data = &msm8064_saw_regulator_pdata_8921_s5,
},
};
static struct platform_device msm8064_device_saw_regulator_core1 = {
.name = "saw-regulator",
.id = 1,
.dev = {
.platform_data = &msm8064_saw_regulator_pdata_8921_s6,
},
};
static struct platform_device msm8064_device_saw_regulator_core2 = {
.name = "saw-regulator",
.id = 2,
.dev = {
.platform_data = &msm8064_saw_regulator_pdata_8821_s0,
},
};
static struct platform_device msm8064_device_saw_regulator_core3 = {
.name = "saw-regulator",
.id = 3,
.dev = {
.platform_data = &msm8064_saw_regulator_pdata_8821_s1,
},
};
static struct msm_rpmrs_level msm_rpmrs_levels[] __initdata = {
{
MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT,
MSM_RPMRS_LIMITS(ON, ACTIVE, MAX, ACTIVE),
true,
100, 8000, 100000, 1,
},
{
MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE,
MSM_RPMRS_LIMITS(ON, ACTIVE, MAX, ACTIVE),
true,
2000, 6000, 60100000, 3000,
},
{
MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
MSM_RPMRS_LIMITS(ON, GDHS, MAX, ACTIVE),
false,
4200, 5000, 60350000, 3500,
},
{
MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
MSM_RPMRS_LIMITS(ON, HSFS_OPEN, MAX, ACTIVE),
false,
6300, 4500, 65350000, 4800,
},
{
MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
MSM_RPMRS_LIMITS(OFF, GDHS, MAX, ACTIVE),
false,
11700, 2500, 67850000, 5500,
},
{
MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
MSM_RPMRS_LIMITS(OFF, HSFS_OPEN, MAX, ACTIVE),
false,
13800, 2000, 71850000, 6800,
},
{
MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
MSM_RPMRS_LIMITS(OFF, HSFS_OPEN, ACTIVE, RET_HIGH),
false,
29700, 500, 75850000, 8800,
},
{
MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
MSM_RPMRS_LIMITS(OFF, HSFS_OPEN, RET_HIGH, RET_LOW),
false,
29700, 0, 76350000, 9800,
},
};
static struct msm_pm_boot_platform_data msm_pm_boot_pdata __initdata = {
.mode = MSM_PM_BOOT_CONFIG_TZ,
};
static struct msm_rpmrs_platform_data msm_rpmrs_data __initdata = {
.levels = &msm_rpmrs_levels[0],
.num_levels = ARRAY_SIZE(msm_rpmrs_levels),
.vdd_mem_levels = {
[MSM_RPMRS_VDD_MEM_RET_LOW] = 750000,
[MSM_RPMRS_VDD_MEM_RET_HIGH] = 750000,
[MSM_RPMRS_VDD_MEM_ACTIVE] = 1050000,
[MSM_RPMRS_VDD_MEM_MAX] = 1150000,
},
.vdd_dig_levels = {
[MSM_RPMRS_VDD_DIG_RET_LOW] = 500000,
[MSM_RPMRS_VDD_DIG_RET_HIGH] = 750000,
[MSM_RPMRS_VDD_DIG_ACTIVE] = 950000,
[MSM_RPMRS_VDD_DIG_MAX] = 1150000,
},
.vdd_mask = 0x7FFFFF,
.rpmrs_target_id = {
[MSM_RPMRS_ID_PXO_CLK] = MSM_RPM_ID_PXO_CLK,
[MSM_RPMRS_ID_L2_CACHE_CTL] = MSM_RPM_ID_LAST,
[MSM_RPMRS_ID_VDD_DIG_0] = MSM_RPM_ID_PM8921_S3_0,
[MSM_RPMRS_ID_VDD_DIG_1] = MSM_RPM_ID_PM8921_S3_1,
[MSM_RPMRS_ID_VDD_MEM_0] = MSM_RPM_ID_PM8921_L24_0,
[MSM_RPMRS_ID_VDD_MEM_1] = MSM_RPM_ID_PM8921_L24_1,
[MSM_RPMRS_ID_RPM_CTL] = MSM_RPM_ID_RPM_CTL,
},
};
static struct msm_cpuidle_state msm_cstates[] __initdata = {
{0, 0, "C0", "WFI",
MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT},
{0, 1, "C1", "STANDALONE_POWER_COLLAPSE",
MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE},
{0, 2, "C2", "POWER_COLLAPSE",
MSM_PM_SLEEP_MODE_POWER_COLLAPSE},
{1, 0, "C0", "WFI",
MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT},
{1, 1, "C1", "STANDALONE_POWER_COLLAPSE",
MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE},
{2, 0, "C0", "WFI",
MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT},
{2, 1, "C1", "STANDALONE_POWER_COLLAPSE",
MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE},
{3, 0, "C0", "WFI",
MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT},
{3, 1, "C1", "STANDALONE_POWER_COLLAPSE",
MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE},
};
static struct msm_pm_platform_data msm_pm_data[] = {
[MSM_PM_MODE(0, MSM_PM_SLEEP_MODE_POWER_COLLAPSE)] = {
.idle_supported = 1,
.suspend_supported = 1,
.idle_enabled = 0,
.suspend_enabled = 0,
},
[MSM_PM_MODE(0, MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE)] = {
.idle_supported = 1,
.suspend_supported = 1,
.idle_enabled = 0,
.suspend_enabled = 0,
},
[MSM_PM_MODE(0, MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT)] = {
.idle_supported = 1,
.suspend_supported = 1,
.idle_enabled = 1,
.suspend_enabled = 1,
},
[MSM_PM_MODE(1, MSM_PM_SLEEP_MODE_POWER_COLLAPSE)] = {
.idle_supported = 0,
.suspend_supported = 1,
.idle_enabled = 0,
.suspend_enabled = 0,
},
[MSM_PM_MODE(1, MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE)] = {
.idle_supported = 1,
.suspend_supported = 1,
.idle_enabled = 0,
.suspend_enabled = 0,
},
[MSM_PM_MODE(1, MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT)] = {
.idle_supported = 1,
.suspend_supported = 0,
.idle_enabled = 1,
.suspend_enabled = 0,
},
[MSM_PM_MODE(2, MSM_PM_SLEEP_MODE_POWER_COLLAPSE)] = {
.idle_supported = 0,
.suspend_supported = 1,
.idle_enabled = 0,
.suspend_enabled = 0,
},
[MSM_PM_MODE(2, MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE)] = {
.idle_supported = 1,
.suspend_supported = 1,
.idle_enabled = 0,
.suspend_enabled = 0,
},
[MSM_PM_MODE(2, MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT)] = {
.idle_supported = 1,
.suspend_supported = 0,
.idle_enabled = 1,
.suspend_enabled = 0,
},
[MSM_PM_MODE(3, MSM_PM_SLEEP_MODE_POWER_COLLAPSE)] = {
.idle_supported = 0,
.suspend_supported = 1,
.idle_enabled = 0,
.suspend_enabled = 0,
},
[MSM_PM_MODE(3, MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE)] = {
.idle_supported = 1,
.suspend_supported = 1,
.idle_enabled = 0,
.suspend_enabled = 0,
},
[MSM_PM_MODE(3, MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT)] = {
.idle_supported = 1,
.suspend_supported = 0,
.idle_enabled = 1,
.suspend_enabled = 0,
},
};
static uint8_t spm_wfi_cmd_sequence[] __initdata = {
0x03, 0x0f,
};
static uint8_t spm_power_collapse_without_rpm[] __initdata = {
0x00, 0x24, 0x54, 0x10,
0x09, 0x03, 0x01,
0x10, 0x54, 0x30, 0x0C,
0x24, 0x30, 0x0f,
};
static uint8_t spm_power_collapse_with_rpm[] __initdata = {
0x00, 0x24, 0x54, 0x10,
0x09, 0x07, 0x01, 0x0B,
0x10, 0x54, 0x30, 0x0C,
0x24, 0x30, 0x0f,
};
static struct msm_spm_seq_entry msm_spm_seq_list[] __initdata = {
[0] = {
.mode = MSM_SPM_MODE_CLOCK_GATING,
.notify_rpm = false,
.cmd = spm_wfi_cmd_sequence,
},
[1] = {
.mode = MSM_SPM_MODE_POWER_COLLAPSE,
.notify_rpm = false,
.cmd = spm_power_collapse_without_rpm,
},
[2] = {
.mode = MSM_SPM_MODE_POWER_COLLAPSE,
.notify_rpm = true,
.cmd = spm_power_collapse_with_rpm,
},
};
static uint8_t l2_spm_wfi_cmd_sequence[] __initdata = {
0x00, 0x20, 0x03, 0x20,
0x00, 0x0f,
};
static uint8_t l2_spm_gdhs_cmd_sequence[] __initdata = {
0x00, 0x20, 0x34, 0x64,
0x48, 0x07, 0x48, 0x20,
0x50, 0x64, 0x04, 0x34,
0x50, 0x0f,
};
static uint8_t l2_spm_power_off_cmd_sequence[] __initdata = {
0x00, 0x10, 0x34, 0x64,
0x48, 0x07, 0x48, 0x10,
0x50, 0x64, 0x04, 0x34,
0x50, 0x0F,
};
static struct msm_spm_seq_entry msm_spm_l2_seq_list[] __initdata = {
[0] = {
.mode = MSM_SPM_L2_MODE_RETENTION,
.notify_rpm = false,
.cmd = l2_spm_wfi_cmd_sequence,
},
[1] = {
.mode = MSM_SPM_L2_MODE_GDHS,
.notify_rpm = true,
.cmd = l2_spm_gdhs_cmd_sequence,
},
[2] = {
.mode = MSM_SPM_L2_MODE_POWER_COLLAPSE,
.notify_rpm = true,
.cmd = l2_spm_power_off_cmd_sequence,
},
};
static struct msm_spm_platform_data msm_spm_l2_data[] __initdata = {
[0] = {
.reg_base_addr = MSM_SAW_L2_BASE,
.reg_init_values[MSM_SPM_REG_SAW2_SPM_CTL] = 0x00,
.reg_init_values[MSM_SPM_REG_SAW2_PMIC_DLY] = 0x02020202,
.reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_0] = 0x00A000AE,
.reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_1] = 0x00A00020,
.modes = msm_spm_l2_seq_list,
.num_modes = ARRAY_SIZE(msm_spm_l2_seq_list),
},
};
static struct msm_spm_platform_data msm_spm_data[] __initdata = {
[0] = {
.reg_base_addr = MSM_SAW0_BASE,
.reg_init_values[MSM_SPM_REG_SAW2_CFG] = 0x1F,
#if defined(CONFIG_MSM_AVS_HW)
.reg_init_values[MSM_SPM_REG_SAW2_AVS_CTL] = 0x00,
.reg_init_values[MSM_SPM_REG_SAW2_AVS_HYSTERESIS] = 0x00,
#endif
.reg_init_values[MSM_SPM_REG_SAW2_SPM_CTL] = 0x01,
.reg_init_values[MSM_SPM_REG_SAW2_PMIC_DLY] = 0x02020202,
.reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_0] = 0x0060009C,
.reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_1] = 0x0000001C,
.vctl_timeout_us = 50,
.num_modes = ARRAY_SIZE(msm_spm_seq_list),
.modes = msm_spm_seq_list,
},
[1] = {
.reg_base_addr = MSM_SAW1_BASE,
.reg_init_values[MSM_SPM_REG_SAW2_CFG] = 0x1F,
#if defined(CONFIG_MSM_AVS_HW)
.reg_init_values[MSM_SPM_REG_SAW2_AVS_CTL] = 0x00,
.reg_init_values[MSM_SPM_REG_SAW2_AVS_HYSTERESIS] = 0x00,
#endif
.reg_init_values[MSM_SPM_REG_SAW2_SPM_CTL] = 0x01,
.reg_init_values[MSM_SPM_REG_SAW2_PMIC_DLY] = 0x02020202,
.reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_0] = 0x0060009C,
.reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_1] = 0x0000001C,
.vctl_timeout_us = 50,
.num_modes = ARRAY_SIZE(msm_spm_seq_list),
.modes = msm_spm_seq_list,
},
[2] = {
.reg_base_addr = MSM_SAW2_BASE,
.reg_init_values[MSM_SPM_REG_SAW2_CFG] = 0x1F,
#if defined(CONFIG_MSM_AVS_HW)
.reg_init_values[MSM_SPM_REG_SAW2_AVS_CTL] = 0x00,
.reg_init_values[MSM_SPM_REG_SAW2_AVS_HYSTERESIS] = 0x00,
#endif
.reg_init_values[MSM_SPM_REG_SAW2_SPM_CTL] = 0x01,
.reg_init_values[MSM_SPM_REG_SAW2_PMIC_DLY] = 0x02020202,
.reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_0] = 0x0060009C,
.reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_1] = 0x0000001C,
.vctl_timeout_us = 50,
.num_modes = ARRAY_SIZE(msm_spm_seq_list),
.modes = msm_spm_seq_list,
},
[3] = {
.reg_base_addr = MSM_SAW3_BASE,
.reg_init_values[MSM_SPM_REG_SAW2_CFG] = 0x1F,
#if defined(CONFIG_MSM_AVS_HW)
.reg_init_values[MSM_SPM_REG_SAW2_AVS_CTL] = 0x00,
.reg_init_values[MSM_SPM_REG_SAW2_AVS_HYSTERESIS] = 0x00,
#endif
.reg_init_values[MSM_SPM_REG_SAW2_SPM_CTL] = 0x01,
.reg_init_values[MSM_SPM_REG_SAW2_PMIC_DLY] = 0x02020202,
.reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_0] = 0x0060009C,
.reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_1] = 0x0000001C,
.vctl_timeout_us = 50,
.num_modes = ARRAY_SIZE(msm_spm_seq_list),
.modes = msm_spm_seq_list,
},
};
static void __init apq8064_init_buses(void)
{
msm_bus_rpm_set_mt_mask();
msm_bus_8064_apps_fabric_pdata.rpm_enabled = 1;
msm_bus_8064_sys_fabric_pdata.rpm_enabled = 1;
msm_bus_8064_mm_fabric_pdata.rpm_enabled = 1;
msm_bus_8064_apps_fabric.dev.platform_data =
&msm_bus_8064_apps_fabric_pdata;
msm_bus_8064_sys_fabric.dev.platform_data =
&msm_bus_8064_sys_fabric_pdata;
msm_bus_8064_mm_fabric.dev.platform_data =
&msm_bus_8064_mm_fabric_pdata;
msm_bus_8064_sys_fpb.dev.platform_data = &msm_bus_8064_sys_fpb_pdata;
msm_bus_8064_cpss_fpb.dev.platform_data = &msm_bus_8064_cpss_fpb_pdata;
}
static struct platform_device apq8064_device_ext_5v_vreg __devinitdata = {
.name = GPIO_REGULATOR_DEV_NAME,
.id = PM8921_MPP_PM_TO_SYS(7),
.dev = {
.platform_data
= &apq8064_gpio_regulator_pdata[GPIO_VREG_ID_EXT_5V],
},
};
static struct platform_device apq8064_device_ext_mpp8_vreg __devinitdata = {
.name = GPIO_REGULATOR_DEV_NAME,
.id = PM8921_MPP_PM_TO_SYS(8),
.dev = {
.platform_data
= &apq8064_gpio_regulator_pdata[GPIO_VREG_ID_EXT_MPP8],
},
};
static struct platform_device apq8064_device_ext_3p3v_vreg __devinitdata = {
.name = GPIO_REGULATOR_DEV_NAME,
.id = APQ8064_EXT_3P3V_REG_EN_GPIO,
.dev = {
.platform_data =
&apq8064_gpio_regulator_pdata[GPIO_VREG_ID_EXT_3P3V],
},
};
static struct platform_device apq8064_device_ext_ts_sw_vreg __devinitdata = {
.name = GPIO_REGULATOR_DEV_NAME,
.id = PM8921_GPIO_PM_TO_SYS(23),
.dev = {
.platform_data
= &apq8064_gpio_regulator_pdata[GPIO_VREG_ID_EXT_TS_SW],
},
};
static struct platform_device apq8064_device_rpm_regulator __devinitdata = {
.name = "rpm-regulator",
.id = -1,
.dev = {
.platform_data = &apq8064_rpm_regulator_pdata,
},
};
static struct platform_device *common_devices[] __initdata = {
&apq8064_device_dmov,
&apq8064_device_qup_i2c_gsbi3,
&apq8064_device_qup_i2c_gsbi4,
&apq8064_device_qup_spi_gsbi5,
&apq8064_device_ext_5v_vreg,
&apq8064_device_ext_mpp8_vreg,
&apq8064_device_ext_3p3v_vreg,
&apq8064_device_ext_ts_sw_vreg,
&apq8064_device_ssbi_pmic1,
&apq8064_device_ssbi_pmic2,
&msm_device_smd_apq8064,
&apq8064_device_otg,
&apq8064_device_gadget_peripheral,
&apq8064_device_hsusb_host,
&apq8064_device_hsic_host,
&android_usb_device,
&msm_device_wcnss_wlan,
#ifdef CONFIG_ANDROID_PMEM
#ifndef CONFIG_MSM_MULTIMEDIA_USE_ION
&android_pmem_device,
&android_pmem_adsp_device,
#endif
&android_pmem_audio_device,
#endif
#ifdef CONFIG_ION_MSM
&ion_dev,
#endif
&msm8064_device_watchdog,
&msm8064_device_saw_regulator_core0,
&msm8064_device_saw_regulator_core1,
&msm8064_device_saw_regulator_core2,
&msm8064_device_saw_regulator_core3,
#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE)
&qcrypto_device,
#endif
#if defined(CONFIG_CRYPTO_DEV_QCEDEV) || \
defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE)
&qcedev_device,
#endif
#ifdef CONFIG_HW_RANDOM_MSM
&apq8064_device_rng,
#endif
&apq_pcm,
&apq_pcm_routing,
&apq_cpudai0,
&apq_cpudai1,
&apq_cpudai_hdmi_rx,
&apq_cpudai_bt_rx,
&apq_cpudai_bt_tx,
&apq_cpudai_fm_rx,
&apq_cpudai_fm_tx,
&apq_cpu_fe,
&apq_stub_codec,
&apq_voice,
&apq_voip,
&apq_lpa_pcm,
&apq_pcm_hostless,
&apq_cpudai_afe_01_rx,
&apq_cpudai_afe_01_tx,
&apq_cpudai_afe_02_rx,
&apq_cpudai_afe_02_tx,
&apq_pcm_afe,
&apq_cpudai_auxpcm_rx,
&apq_cpudai_auxpcm_tx,
&apq8064_rpm_device,
&apq8064_rpm_log_device,
&apq8064_rpm_stat_device,
&msm_bus_8064_apps_fabric,
&msm_bus_8064_sys_fabric,
&msm_bus_8064_mm_fabric,
&msm_bus_8064_sys_fpb,
&msm_bus_8064_cpss_fpb,
&apq8064_msm_device_vidc,
&msm_8960_riva,
&msm_8960_q6_lpass,
&msm_gss,
};
static struct platform_device *sim_devices[] __initdata = {
&apq8064_device_uart_gsbi3,
&msm_device_sps_apq8064,
};
static struct platform_device *rumi3_devices[] __initdata = {
&apq8064_device_uart_gsbi1,
&msm_device_sps_apq8064,
#ifdef CONFIG_MSM_ROTATOR
&msm_rotator_device,
#endif
};
static struct platform_device *cdp_devices[] __initdata = {
&apq8064_device_uart_gsbi1,
&apq8064_device_uart_gsbi7,
&msm_device_sps_apq8064,
};
static struct msm_spi_platform_data apq8064_qup_spi_gsbi5_pdata = {
.max_clock_speed = 1100000,
};
#define KS8851_IRQ_GPIO 43
static struct spi_board_info spi_board_info[] __initdata = {
{
.modalias = "ks8851",
.irq = MSM_GPIO_TO_INT(KS8851_IRQ_GPIO),
.max_speed_hz = 19200000,
.bus_num = 0,
.chip_select = 2,
.mode = SPI_MODE_0,
},
};
static struct slim_boardinfo apq8064_slim_devices[] = {
{
.bus_num = 1,
.slim_slave = &apq8064_slim_tabla,
},
{
.bus_num = 1,
.slim_slave = &apq8064_slim_tabla20,
},
/* add more slimbus slaves as needed */
};
static struct msm_i2c_platform_data apq8064_i2c_qup_gsbi3_pdata = {
.clk_freq = 100000,
.src_clk_rate = 24000000,
};
static struct msm_i2c_platform_data apq8064_i2c_qup_gsbi4_pdata = {
.clk_freq = 100000,
.src_clk_rate = 24000000,
};
static void __init apq8064_i2c_init(void)
{
apq8064_device_qup_i2c_gsbi3.dev.platform_data =
&apq8064_i2c_qup_gsbi3_pdata;
apq8064_device_qup_i2c_gsbi4.dev.platform_data =
&apq8064_i2c_qup_gsbi4_pdata;
}
#if defined(CONFIG_KS8851) || defined(CONFIG_KS8851_MODULE)
static int ethernet_init(void)
{
int ret;
ret = gpio_request(KS8851_IRQ_GPIO, "ks8851_irq");
if (ret) {
pr_err("ks8851 gpio_request failed: %d\n", ret);
goto fail;
}
return 0;
fail:
return ret;
}
#else
static int ethernet_init(void)
{
return 0;
}
#endif
static void __init apq8064_clock_init(void)
{
if (machine_is_apq8064_rumi3())
msm_clock_init(&apq8064_dummy_clock_init_data);
else
msm_clock_init(&apq8064_clock_init_data);
}
#define I2C_SURF 1
#define I2C_FFA (1 << 1)
#define I2C_RUMI (1 << 2)
#define I2C_SIM (1 << 3)
#define I2C_LIQUID (1 << 4)
struct i2c_registry {
u8 machs;
int bus;
struct i2c_board_info *info;
int len;
};
static struct i2c_registry apq8064_i2c_devices[] __initdata = {
{
I2C_SURF | I2C_LIQUID,
APQ_8064_GSBI3_QUP_I2C_BUS_ID,
mxt_device_info,
ARRAY_SIZE(mxt_device_info),
},
{
I2C_FFA,
APQ_8064_GSBI3_QUP_I2C_BUS_ID,
cyttsp_info,
ARRAY_SIZE(cyttsp_info),
},
};
static void __init register_i2c_devices(void)
{
u8 mach_mask = 0;
int i;
#ifdef CONFIG_MSM_CAMERA
struct i2c_registry apq8064_camera_i2c_devices = {
I2C_SURF | I2C_FFA | I2C_LIQUID | I2C_RUMI,
APQ_8064_GSBI4_QUP_I2C_BUS_ID,
apq8064_camera_board_info.board_info,
apq8064_camera_board_info.num_i2c_board_info,
};
#endif
/* Build the matching 'supported_machs' bitmask */
if (machine_is_apq8064_cdp())
mach_mask = I2C_SURF;
else if (machine_is_apq8064_mtp())
mach_mask = I2C_FFA;
else if (machine_is_apq8064_liquid())
mach_mask = I2C_LIQUID;
else if (machine_is_apq8064_rumi3())
mach_mask = I2C_RUMI;
else if (machine_is_apq8064_sim())
mach_mask = I2C_SIM;
else
pr_err("unmatched machine ID in register_i2c_devices\n");
/* Run the array and install devices as appropriate */
for (i = 0; i < ARRAY_SIZE(apq8064_i2c_devices); ++i) {
if (apq8064_i2c_devices[i].machs & mach_mask)
i2c_register_board_info(apq8064_i2c_devices[i].bus,
apq8064_i2c_devices[i].info,
apq8064_i2c_devices[i].len);
}
#ifdef CONFIG_MSM_CAMERA
if (apq8064_camera_i2c_devices.machs & mach_mask)
i2c_register_board_info(apq8064_camera_i2c_devices.bus,
apq8064_camera_i2c_devices.info,
apq8064_camera_i2c_devices.len);
#endif
}
static void __init apq8064_common_init(void)
{
if (socinfo_init() < 0)
pr_err("socinfo_init() failed!\n");
BUG_ON(msm_rpm_init(&apq8064_rpm_data));
BUG_ON(msm_rpmrs_levels_init(&msm_rpmrs_data));
regulator_suppress_info_printing();
platform_device_register(&apq8064_device_rpm_regulator);
apq8064_clock_init();
apq8064_init_gpiomux();
apq8064_i2c_init();
register_i2c_devices();
apq8064_device_qup_spi_gsbi5.dev.platform_data =
&apq8064_qup_spi_gsbi5_pdata;
apq8064_init_pmic();
if (machine_is_apq8064_liquid())
msm_otg_pdata.mhl_enable = true;
apq8064_device_otg.dev.platform_data = &msm_otg_pdata;
apq8064_device_hsic_host.dev.platform_data = &msm_hsic_pdata;
apq8064_init_buses();
platform_add_devices(common_devices, ARRAY_SIZE(common_devices));
apq8064_pm8xxx_gpio_mpp_init();
apq8064_init_mmc();
if (machine_is_apq8064_mtp()) {
mdm_8064_device.dev.platform_data = &mdm_platform_data;
platform_device_register(&mdm_8064_device);
}
platform_device_register(&apq8064_slim_ctrl);
slim_register_board_info(apq8064_slim_devices,
ARRAY_SIZE(apq8064_slim_devices));
msm_spm_init(msm_spm_data, ARRAY_SIZE(msm_spm_data));
acpuclk_init(&acpuclk_8064_soc_data);
msm_spm_l2_init(msm_spm_l2_data);
msm_pm_set_platform_data(msm_pm_data, ARRAY_SIZE(msm_pm_data));
msm_pm_set_rpm_wakeup_irq(RPM_APCC_CPU0_WAKE_UP_IRQ);
msm_cpuidle_set_states(msm_cstates, ARRAY_SIZE(msm_cstates),
msm_pm_data);
BUG_ON(msm_pm_boot_init(&msm_pm_boot_pdata));
}
static void __init apq8064_allocate_memory_regions(void)
{
apq8064_allocate_fb_region();
}
static void __init apq8064_sim_init(void)
{
struct msm_watchdog_pdata *wdog_pdata = (struct msm_watchdog_pdata *)
&msm8064_device_watchdog.dev.platform_data;
wdog_pdata->bark_time = 15000;
msm_tsens_early_init(&apq_tsens_pdata);
apq8064_common_init();
platform_add_devices(sim_devices, ARRAY_SIZE(sim_devices));
}
static void __init apq8064_rumi3_init(void)
{
msm_tsens_early_init(&apq_tsens_pdata);
apq8064_common_init();
ethernet_init();
platform_add_devices(rumi3_devices, ARRAY_SIZE(rumi3_devices));
spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
apq8064_init_fb();
apq8064_init_gpu();
}
static void __init apq8064_cdp_init(void)
{
msm_tsens_early_init(&apq_tsens_pdata);
apq8064_common_init();
ethernet_init();
platform_add_devices(cdp_devices, ARRAY_SIZE(cdp_devices));
spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
apq8064_init_fb();
apq8064_init_gpu();
platform_add_devices(msm_footswitch_devices,
msm_num_footswitch_devices);
apq8064_init_cam();
}
MACHINE_START(APQ8064_SIM, "QCT APQ8064 SIMULATOR")
.map_io = apq8064_map_io,
.reserve = apq8064_reserve,
.init_irq = apq8064_init_irq,
.handle_irq = gic_handle_irq,
.timer = &msm_timer,
.init_machine = apq8064_sim_init,
MACHINE_END
MACHINE_START(APQ8064_RUMI3, "QCT APQ8064 RUMI3")
.map_io = apq8064_map_io,
.reserve = apq8064_reserve,
.init_irq = apq8064_init_irq,
.handle_irq = gic_handle_irq,
.timer = &msm_timer,
.init_machine = apq8064_rumi3_init,
.init_early = apq8064_allocate_memory_regions,
MACHINE_END
MACHINE_START(APQ8064_CDP, "QCT APQ8064 CDP")
.map_io = apq8064_map_io,
.reserve = apq8064_reserve,
.init_irq = apq8064_init_irq,
.handle_irq = gic_handle_irq,
.timer = &msm_timer,
.init_machine = apq8064_cdp_init,
.init_early = apq8064_allocate_memory_regions,
MACHINE_END
MACHINE_START(APQ8064_MTP, "QCT APQ8064 MTP")
.map_io = apq8064_map_io,
.reserve = apq8064_reserve,
.init_irq = apq8064_init_irq,
.handle_irq = gic_handle_irq,
.timer = &msm_timer,
.init_machine = apq8064_cdp_init,
.init_early = apq8064_allocate_memory_regions,
MACHINE_END
MACHINE_START(APQ8064_LIQUID, "QCT APQ8064 LIQUID")
.map_io = apq8064_map_io,
.reserve = apq8064_reserve,
.init_irq = apq8064_init_irq,
.handle_irq = gic_handle_irq,
.timer = &msm_timer,
.init_machine = apq8064_cdp_init,
.init_early = apq8064_allocate_memory_regions,
MACHINE_END