msm: acpuclock-8930{aa,ab}: Turn off inefficient frequencies
Given frequcies at the same voltage and the same L2 operating
point, the highest frequency is a more efficient choice. Update
the frequency tables for 8930, 8930aa, 8930ab to turn off the
inefficient frequencies.
Change-Id: I5048ecdd393836600444f45d39e5940e5fe7d106
Signed-off-by: Tianyi Gou <tgou@codeaurora.org>
diff --git a/arch/arm/mach-msm/acpuclock-8930ab.c b/arch/arm/mach-msm/acpuclock-8930ab.c
index 764ae41..96029b4 100644
--- a/arch/arm/mach-msm/acpuclock-8930ab.c
+++ b/arch/arm/mach-msm/acpuclock-8930ab.c
@@ -153,29 +153,29 @@
static struct acpu_level acpu_freq_tbl_slow[] __initdata = {
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 950000 },
- { 1, { 432000, HFPLL, 2, 0x20 }, L2(5), 975000 },
+ { 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 975000 },
{ 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 975000 },
- { 1, { 540000, HFPLL, 2, 0x28 }, L2(5), 1000000 },
+ { 0, { 540000, HFPLL, 2, 0x28 }, L2(5), 1000000 },
{ 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 1000000 },
- { 1, { 648000, HFPLL, 1, 0x18 }, L2(5), 1025000 },
+ { 0, { 648000, HFPLL, 1, 0x18 }, L2(5), 1025000 },
{ 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 1025000 },
- { 1, { 756000, HFPLL, 1, 0x1C }, L2(10), 1075000 },
+ { 0, { 756000, HFPLL, 1, 0x1C }, L2(10), 1075000 },
{ 1, { 810000, HFPLL, 1, 0x1E }, L2(10), 1075000 },
- { 1, { 864000, HFPLL, 1, 0x20 }, L2(10), 1100000 },
+ { 0, { 864000, HFPLL, 1, 0x20 }, L2(10), 1100000 },
{ 1, { 918000, HFPLL, 1, 0x22 }, L2(10), 1100000 },
- { 1, { 972000, HFPLL, 1, 0x24 }, L2(10), 1125000 },
+ { 0, { 972000, HFPLL, 1, 0x24 }, L2(10), 1125000 },
{ 1, { 1026000, HFPLL, 1, 0x26 }, L2(10), 1125000 },
- { 1, { 1080000, HFPLL, 1, 0x28 }, L2(15), 1175000 },
+ { 0, { 1080000, HFPLL, 1, 0x28 }, L2(15), 1175000 },
{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1175000 },
- { 1, { 1188000, HFPLL, 1, 0x2C }, L2(15), 1200000 },
+ { 0, { 1188000, HFPLL, 1, 0x2C }, L2(15), 1200000 },
{ 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 1200000 },
- { 1, { 1296000, HFPLL, 1, 0x30 }, L2(15), 1225000 },
+ { 0, { 1296000, HFPLL, 1, 0x30 }, L2(15), 1225000 },
{ 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1225000 },
- { 1, { 1404000, HFPLL, 1, 0x34 }, L2(15), 1237500 },
+ { 0, { 1404000, HFPLL, 1, 0x34 }, L2(15), 1237500 },
{ 1, { 1458000, HFPLL, 1, 0x36 }, L2(15), 1237500 },
- { 1, { 1512000, HFPLL, 1, 0x38 }, L2(15), 1250000 },
+ { 0, { 1512000, HFPLL, 1, 0x38 }, L2(15), 1250000 },
{ 1, { 1566000, HFPLL, 1, 0x3A }, L2(15), 1250000 },
- { 1, { 1620000, HFPLL, 1, 0x3C }, L2(15), 1262500 },
+ { 0, { 1620000, HFPLL, 1, 0x3C }, L2(15), 1262500 },
{ 1, { 1674000, HFPLL, 1, 0x3E }, L2(15), 1262500 },
{ 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1287500 },
{ 0, { 0 } }
@@ -183,29 +183,29 @@
static struct acpu_level acpu_freq_tbl_nom[] __initdata = {
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 950000 },
- { 1, { 432000, HFPLL, 2, 0x20 }, L2(5), 975000 },
+ { 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 975000 },
{ 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 975000 },
- { 1, { 540000, HFPLL, 2, 0x28 }, L2(5), 1000000 },
+ { 0, { 540000, HFPLL, 2, 0x28 }, L2(5), 1000000 },
{ 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 1000000 },
- { 1, { 648000, HFPLL, 1, 0x18 }, L2(5), 1025000 },
+ { 0, { 648000, HFPLL, 1, 0x18 }, L2(5), 1025000 },
{ 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 1025000 },
- { 1, { 756000, HFPLL, 1, 0x1C }, L2(10), 1075000 },
+ { 0, { 756000, HFPLL, 1, 0x1C }, L2(10), 1075000 },
{ 1, { 810000, HFPLL, 1, 0x1E }, L2(10), 1075000 },
- { 1, { 864000, HFPLL, 1, 0x20 }, L2(10), 1100000 },
+ { 0, { 864000, HFPLL, 1, 0x20 }, L2(10), 1100000 },
{ 1, { 918000, HFPLL, 1, 0x22 }, L2(10), 1100000 },
- { 1, { 972000, HFPLL, 1, 0x24 }, L2(10), 1125000 },
+ { 0, { 972000, HFPLL, 1, 0x24 }, L2(10), 1125000 },
{ 1, { 1026000, HFPLL, 1, 0x26 }, L2(10), 1125000 },
- { 1, { 1080000, HFPLL, 1, 0x28 }, L2(15), 1175000 },
+ { 0, { 1080000, HFPLL, 1, 0x28 }, L2(15), 1175000 },
{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1175000 },
- { 1, { 1188000, HFPLL, 1, 0x2C }, L2(15), 1200000 },
+ { 0, { 1188000, HFPLL, 1, 0x2C }, L2(15), 1200000 },
{ 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 1200000 },
- { 1, { 1296000, HFPLL, 1, 0x30 }, L2(15), 1225000 },
+ { 0, { 1296000, HFPLL, 1, 0x30 }, L2(15), 1225000 },
{ 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1225000 },
- { 1, { 1404000, HFPLL, 1, 0x34 }, L2(15), 1237500 },
+ { 0, { 1404000, HFPLL, 1, 0x34 }, L2(15), 1237500 },
{ 1, { 1458000, HFPLL, 1, 0x36 }, L2(15), 1237500 },
- { 1, { 1512000, HFPLL, 1, 0x38 }, L2(15), 1250000 },
+ { 0, { 1512000, HFPLL, 1, 0x38 }, L2(15), 1250000 },
{ 1, { 1566000, HFPLL, 1, 0x3A }, L2(15), 1250000 },
- { 1, { 1620000, HFPLL, 1, 0x3C }, L2(15), 1262500 },
+ { 0, { 1620000, HFPLL, 1, 0x3C }, L2(15), 1262500 },
{ 1, { 1674000, HFPLL, 1, 0x3E }, L2(15), 1262500 },
{ 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1287500 },
{ 0, { 0 } }
@@ -213,29 +213,29 @@
static struct acpu_level acpu_freq_tbl_fast[] __initdata = {
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 950000 },
- { 1, { 432000, HFPLL, 2, 0x20 }, L2(5), 975000 },
+ { 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 975000 },
{ 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 975000 },
- { 1, { 540000, HFPLL, 2, 0x28 }, L2(5), 1000000 },
+ { 0, { 540000, HFPLL, 2, 0x28 }, L2(5), 1000000 },
{ 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 1000000 },
- { 1, { 648000, HFPLL, 1, 0x18 }, L2(5), 1025000 },
+ { 0, { 648000, HFPLL, 1, 0x18 }, L2(5), 1025000 },
{ 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 1025000 },
- { 1, { 756000, HFPLL, 1, 0x1C }, L2(10), 1075000 },
+ { 0, { 756000, HFPLL, 1, 0x1C }, L2(10), 1075000 },
{ 1, { 810000, HFPLL, 1, 0x1E }, L2(10), 1075000 },
- { 1, { 864000, HFPLL, 1, 0x20 }, L2(10), 1100000 },
+ { 0, { 864000, HFPLL, 1, 0x20 }, L2(10), 1100000 },
{ 1, { 918000, HFPLL, 1, 0x22 }, L2(10), 1100000 },
- { 1, { 972000, HFPLL, 1, 0x24 }, L2(10), 1125000 },
+ { 0, { 972000, HFPLL, 1, 0x24 }, L2(10), 1125000 },
{ 1, { 1026000, HFPLL, 1, 0x26 }, L2(10), 1125000 },
- { 1, { 1080000, HFPLL, 1, 0x28 }, L2(15), 1175000 },
+ { 0, { 1080000, HFPLL, 1, 0x28 }, L2(15), 1175000 },
{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1175000 },
- { 1, { 1188000, HFPLL, 1, 0x2C }, L2(15), 1200000 },
+ { 0, { 1188000, HFPLL, 1, 0x2C }, L2(15), 1200000 },
{ 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 1200000 },
- { 1, { 1296000, HFPLL, 1, 0x30 }, L2(15), 1225000 },
+ { 0, { 1296000, HFPLL, 1, 0x30 }, L2(15), 1225000 },
{ 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1225000 },
- { 1, { 1404000, HFPLL, 1, 0x34 }, L2(15), 1237500 },
+ { 0, { 1404000, HFPLL, 1, 0x34 }, L2(15), 1237500 },
{ 1, { 1458000, HFPLL, 1, 0x36 }, L2(15), 1237500 },
- { 1, { 1512000, HFPLL, 1, 0x38 }, L2(15), 1250000 },
+ { 0, { 1512000, HFPLL, 1, 0x38 }, L2(15), 1250000 },
{ 1, { 1566000, HFPLL, 1, 0x3A }, L2(15), 1250000 },
- { 1, { 1620000, HFPLL, 1, 0x3C }, L2(15), 1262500 },
+ { 0, { 1620000, HFPLL, 1, 0x3C }, L2(15), 1262500 },
{ 1, { 1674000, HFPLL, 1, 0x3E }, L2(15), 1262500 },
{ 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1287500 },
{ 0, { 0 } }