msm: acpuclock-8974: Add PVS voltage table support for 8974v2 CPUs
Select the CPU voltage tables based on each part's PVS bin. This
results in lower CPU voltages being applied for some parts, which
translates to some power savings.
Change-Id: I50242488e9398c14471827d27c63598c81288c3c
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
diff --git a/arch/arm/mach-msm/acpuclock-8974.c b/arch/arm/mach-msm/acpuclock-8974.c
index efd0045..83c14a8 100644
--- a/arch/arm/mach-msm/acpuclock-8974.c
+++ b/arch/arm/mach-msm/acpuclock-8974.c
@@ -308,6 +308,168 @@
{ 0, { 0 } }
};
+static struct acpu_level acpu_freq_tbl_2g_pvs1[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 800000, 400000 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(3), 810000, 3200000 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(3), 820000, 3200000 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(6), 830000, 3200000 },
+ { 1, { 576000, HFPLL, 1, 30 }, L2(6), 840000, 3200000 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(7), 850000, 3200000 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(7), 860000, 3200000 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(10), 875000, 3200000 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(10), 885000, 3200000 },
+ { 0, { 960000, HFPLL, 1, 50 }, L2(10), 895000, 3200000 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 910000, 3200000 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(12), 920000, 3200000 },
+ { 0, { 1190400, HFPLL, 1, 62 }, L2(12), 930000, 3200000 },
+ { 0, { 1267200, HFPLL, 1, 66 }, L2(12), 945000, 3200000 },
+ { 1, { 1344000, HFPLL, 1, 70 }, L2(12), 960000, 3200000 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(16), 975000, 3200000 },
+ { 0, { 1497600, HFPLL, 1, 78 }, L2(16), 990000, 3200000 },
+ { 0, { 1574400, HFPLL, 1, 82 }, L2(16), 1005000, 3200000 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(16), 1020000, 3200000 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(16), 1030000, 3200000 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(19), 1045000, 3200000 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(19), 1060000, 3200000 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1075000, 3200000 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level acpu_freq_tbl_2g_pvs2[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 785000, 400000 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(3), 795000, 3200000 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(3), 805000, 3200000 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(6), 815000, 3200000 },
+ { 1, { 576000, HFPLL, 1, 30 }, L2(6), 825000, 3200000 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(7), 835000, 3200000 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(7), 845000, 3200000 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(10), 855000, 3200000 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(10), 865000, 3200000 },
+ { 0, { 960000, HFPLL, 1, 50 }, L2(10), 875000, 3200000 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 890000, 3200000 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(12), 900000, 3200000 },
+ { 0, { 1190400, HFPLL, 1, 62 }, L2(12), 910000, 3200000 },
+ { 0, { 1267200, HFPLL, 1, 66 }, L2(12), 925000, 3200000 },
+ { 1, { 1344000, HFPLL, 1, 70 }, L2(12), 940000, 3200000 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(16), 955000, 3200000 },
+ { 0, { 1497600, HFPLL, 1, 78 }, L2(16), 970000, 3200000 },
+ { 0, { 1574400, HFPLL, 1, 82 }, L2(16), 980000, 3200000 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(16), 995000, 3200000 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(16), 1005000, 3200000 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(19), 1020000, 3200000 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(19), 1035000, 3200000 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1050000, 3200000 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level acpu_freq_tbl_2g_pvs3[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 400000 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(3), 780000, 3200000 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(3), 790000, 3200000 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(6), 800000, 3200000 },
+ { 1, { 576000, HFPLL, 1, 30 }, L2(6), 810000, 3200000 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(7), 820000, 3200000 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(7), 830000, 3200000 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(10), 840000, 3200000 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(10), 850000, 3200000 },
+ { 0, { 960000, HFPLL, 1, 50 }, L2(10), 860000, 3200000 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 875000, 3200000 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(12), 885000, 3200000 },
+ { 0, { 1190400, HFPLL, 1, 62 }, L2(12), 895000, 3200000 },
+ { 0, { 1267200, HFPLL, 1, 66 }, L2(12), 910000, 3200000 },
+ { 1, { 1344000, HFPLL, 1, 70 }, L2(12), 925000, 3200000 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(16), 935000, 3200000 },
+ { 0, { 1497600, HFPLL, 1, 78 }, L2(16), 950000, 3200000 },
+ { 0, { 1574400, HFPLL, 1, 82 }, L2(16), 960000, 3200000 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(16), 970000, 3200000 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(16), 985000, 3200000 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(19), 995000, 3200000 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(19), 1010000, 3200000 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1025000, 3200000 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level acpu_freq_tbl_2g_pvs4[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 400000 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(3), 775000, 3200000 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(3), 780000, 3200000 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(6), 790000, 3200000 },
+ { 1, { 576000, HFPLL, 1, 30 }, L2(6), 800000, 3200000 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(7), 810000, 3200000 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(7), 820000, 3200000 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(10), 830000, 3200000 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(10), 840000, 3200000 },
+ { 0, { 960000, HFPLL, 1, 50 }, L2(10), 850000, 3200000 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 860000, 3200000 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(12), 870000, 3200000 },
+ { 0, { 1190400, HFPLL, 1, 62 }, L2(12), 880000, 3200000 },
+ { 0, { 1267200, HFPLL, 1, 66 }, L2(12), 895000, 3200000 },
+ { 1, { 1344000, HFPLL, 1, 70 }, L2(12), 910000, 3200000 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(16), 920000, 3200000 },
+ { 0, { 1497600, HFPLL, 1, 78 }, L2(16), 930000, 3200000 },
+ { 0, { 1574400, HFPLL, 1, 82 }, L2(16), 940000, 3200000 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(16), 950000, 3200000 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(16), 960000, 3200000 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(19), 975000, 3200000 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(19), 985000, 3200000 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1000000, 3200000 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level acpu_freq_tbl_2g_pvs5[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 750000, 400000 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(3), 760000, 3200000 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(3), 770000, 3200000 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(6), 780000, 3200000 },
+ { 1, { 576000, HFPLL, 1, 30 }, L2(6), 790000, 3200000 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(7), 800000, 3200000 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(7), 810000, 3200000 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(10), 820000, 3200000 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(10), 830000, 3200000 },
+ { 0, { 960000, HFPLL, 1, 50 }, L2(10), 840000, 3200000 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 850000, 3200000 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(12), 860000, 3200000 },
+ { 0, { 1190400, HFPLL, 1, 62 }, L2(12), 870000, 3200000 },
+ { 0, { 1267200, HFPLL, 1, 66 }, L2(12), 880000, 3200000 },
+ { 1, { 1344000, HFPLL, 1, 70 }, L2(12), 890000, 3200000 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(16), 900000, 3200000 },
+ { 0, { 1497600, HFPLL, 1, 78 }, L2(16), 910000, 3200000 },
+ { 0, { 1574400, HFPLL, 1, 82 }, L2(16), 920000, 3200000 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(16), 930000, 3200000 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(16), 940000, 3200000 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(19), 955000, 3200000 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(19), 965000, 3200000 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 975000, 3200000 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level acpu_freq_tbl_2g_pvs6[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 750000, 400000 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(3), 750000, 3200000 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(3), 760000, 3200000 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(6), 770000, 3200000 },
+ { 1, { 576000, HFPLL, 1, 30 }, L2(6), 780000, 3200000 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(7), 790000, 3200000 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(7), 800000, 3200000 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(10), 810000, 3200000 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(10), 820000, 3200000 },
+ { 0, { 960000, HFPLL, 1, 50 }, L2(10), 830000, 3200000 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 840000, 3200000 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(12), 850000, 3200000 },
+ { 0, { 1190400, HFPLL, 1, 62 }, L2(12), 860000, 3200000 },
+ { 0, { 1267200, HFPLL, 1, 66 }, L2(12), 870000, 3200000 },
+ { 1, { 1344000, HFPLL, 1, 70 }, L2(12), 875000, 3200000 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(16), 885000, 3200000 },
+ { 0, { 1497600, HFPLL, 1, 78 }, L2(16), 895000, 3200000 },
+ { 0, { 1574400, HFPLL, 1, 82 }, L2(16), 905000, 3200000 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(16), 915000, 3200000 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(16), 920000, 3200000 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(19), 930000, 3200000 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(19), 940000, 3200000 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 950000, 3200000 },
+ { 0, { 0 } }
+};
+
static struct acpu_level acpu_freq_tbl_2p3g_pvs0[] __initdata = {
{ 1, { 300000, PLL_0, 0, 0 }, L2(0), 800000, 400000 },
{ 0, { 345600, HFPLL, 2, 36 }, L2(3), 800000, 3200000 },
@@ -339,6 +501,192 @@
{ 0, { 0 } }
};
+static struct acpu_level acpu_freq_tbl_2p3g_pvs1[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 800000, 400000 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(3), 800000, 3200000 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(3), 800000, 3200000 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(6), 800000, 3200000 },
+ { 1, { 576000, HFPLL, 1, 30 }, L2(6), 800000, 3200000 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(7), 810000, 3200000 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(7), 820000, 3200000 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(10), 830000, 3200000 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(10), 840000, 3200000 },
+ { 0, { 960000, HFPLL, 1, 50 }, L2(10), 850000, 3200000 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 860000, 3200000 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(12), 875000, 3200000 },
+ { 0, { 1190400, HFPLL, 1, 62 }, L2(12), 885000, 3200000 },
+ { 0, { 1267200, HFPLL, 1, 66 }, L2(12), 895000, 3200000 },
+ { 1, { 1344000, HFPLL, 1, 70 }, L2(12), 910000, 3200000 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(16), 920000, 3200000 },
+ { 0, { 1497600, HFPLL, 1, 78 }, L2(16), 930000, 3200000 },
+ { 0, { 1574400, HFPLL, 1, 82 }, L2(16), 945000, 3200000 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(16), 960000, 3200000 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(16), 975000, 3200000 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(19), 990000, 3200000 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(19), 1005000, 3200000 },
+ { 0, { 1958400, HFPLL, 1, 102 }, L2(19), 1020000, 3200000 },
+ { 1, { 2035200, HFPLL, 1, 106 }, L2(19), 1030000, 3200000 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1045000, 3200000 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1060000, 3200000 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1075000, 3200000 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level acpu_freq_tbl_2p3g_pvs2[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 400000 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(3), 775000, 3200000 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(3), 775000, 3200000 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(6), 775000, 3200000 },
+ { 1, { 576000, HFPLL, 1, 30 }, L2(6), 785000, 3200000 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(7), 795000, 3200000 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(7), 805000, 3200000 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(10), 815000, 3200000 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(10), 825000, 3200000 },
+ { 0, { 960000, HFPLL, 1, 50 }, L2(10), 835000, 3200000 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 845000, 3200000 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(12), 855000, 3200000 },
+ { 0, { 1190400, HFPLL, 1, 62 }, L2(12), 865000, 3200000 },
+ { 0, { 1267200, HFPLL, 1, 66 }, L2(12), 875000, 3200000 },
+ { 1, { 1344000, HFPLL, 1, 70 }, L2(12), 890000, 3200000 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(16), 900000, 3200000 },
+ { 0, { 1497600, HFPLL, 1, 78 }, L2(16), 910000, 3200000 },
+ { 0, { 1574400, HFPLL, 1, 82 }, L2(16), 925000, 3200000 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(16), 940000, 3200000 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(16), 955000, 3200000 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(19), 970000, 3200000 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(19), 980000, 3200000 },
+ { 0, { 1958400, HFPLL, 1, 102 }, L2(19), 995000, 3200000 },
+ { 1, { 2035200, HFPLL, 1, 106 }, L2(19), 1005000, 3200000 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1020000, 3200000 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1035000, 3200000 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1050000, 3200000 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level acpu_freq_tbl_2p3g_pvs3[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 400000 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(3), 775000, 3200000 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(3), 775000, 3200000 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(6), 775000, 3200000 },
+ { 1, { 576000, HFPLL, 1, 30 }, L2(6), 775000, 3200000 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(7), 780000, 3200000 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(7), 790000, 3200000 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(10), 800000, 3200000 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(10), 810000, 3200000 },
+ { 0, { 960000, HFPLL, 1, 50 }, L2(10), 820000, 3200000 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 830000, 3200000 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(12), 840000, 3200000 },
+ { 0, { 1190400, HFPLL, 1, 62 }, L2(12), 850000, 3200000 },
+ { 0, { 1267200, HFPLL, 1, 66 }, L2(12), 860000, 3200000 },
+ { 1, { 1344000, HFPLL, 1, 70 }, L2(12), 875000, 3200000 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(16), 885000, 3200000 },
+ { 0, { 1497600, HFPLL, 1, 78 }, L2(16), 895000, 3200000 },
+ { 0, { 1574400, HFPLL, 1, 82 }, L2(16), 910000, 3200000 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(16), 925000, 3200000 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(16), 935000, 3200000 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(19), 950000, 3200000 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(19), 960000, 3200000 },
+ { 0, { 1958400, HFPLL, 1, 102 }, L2(19), 970000, 3200000 },
+ { 1, { 2035200, HFPLL, 1, 106 }, L2(19), 985000, 3200000 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 995000, 3200000 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1010000, 3200000 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1025000, 3200000 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level acpu_freq_tbl_2p3g_pvs4[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 400000 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(3), 775000, 3200000 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(3), 775000, 3200000 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(6), 775000, 3200000 },
+ { 1, { 576000, HFPLL, 1, 30 }, L2(6), 775000, 3200000 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(7), 775000, 3200000 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(7), 780000, 3200000 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(10), 790000, 3200000 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(10), 800000, 3200000 },
+ { 0, { 960000, HFPLL, 1, 50 }, L2(10), 810000, 3200000 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 820000, 3200000 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(12), 830000, 3200000 },
+ { 0, { 1190400, HFPLL, 1, 62 }, L2(12), 840000, 3200000 },
+ { 0, { 1267200, HFPLL, 1, 66 }, L2(12), 850000, 3200000 },
+ { 1, { 1344000, HFPLL, 1, 70 }, L2(12), 860000, 3200000 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(16), 870000, 3200000 },
+ { 0, { 1497600, HFPLL, 1, 78 }, L2(16), 880000, 3200000 },
+ { 0, { 1574400, HFPLL, 1, 82 }, L2(16), 895000, 3200000 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(16), 910000, 3200000 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(16), 920000, 3200000 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(19), 930000, 3200000 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(19), 940000, 3200000 },
+ { 0, { 1958400, HFPLL, 1, 102 }, L2(19), 950000, 3200000 },
+ { 1, { 2035200, HFPLL, 1, 106 }, L2(19), 960000, 3200000 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 975000, 3200000 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 985000, 3200000 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1000000, 3200000 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level acpu_freq_tbl_2p3g_pvs5[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 750000, 400000 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(3), 750000, 3200000 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(3), 750000, 3200000 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(6), 750000, 3200000 },
+ { 1, { 576000, HFPLL, 1, 30 }, L2(6), 750000, 3200000 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(7), 760000, 3200000 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(7), 770000, 3200000 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(10), 780000, 3200000 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(10), 790000, 3200000 },
+ { 0, { 960000, HFPLL, 1, 50 }, L2(10), 800000, 3200000 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 810000, 3200000 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(12), 820000, 3200000 },
+ { 0, { 1190400, HFPLL, 1, 62 }, L2(12), 830000, 3200000 },
+ { 0, { 1267200, HFPLL, 1, 66 }, L2(12), 840000, 3200000 },
+ { 1, { 1344000, HFPLL, 1, 70 }, L2(12), 850000, 3200000 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(16), 860000, 3200000 },
+ { 0, { 1497600, HFPLL, 1, 78 }, L2(16), 870000, 3200000 },
+ { 0, { 1574400, HFPLL, 1, 82 }, L2(16), 880000, 3200000 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(16), 890000, 3200000 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(16), 900000, 3200000 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(19), 910000, 3200000 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(19), 920000, 3200000 },
+ { 0, { 1958400, HFPLL, 1, 102 }, L2(19), 930000, 3200000 },
+ { 1, { 2035200, HFPLL, 1, 106 }, L2(19), 940000, 3200000 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 955000, 3200000 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 965000, 3200000 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 975000, 3200000 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level acpu_freq_tbl_2p3g_pvs6[] __initdata = {
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 750000, 400000 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(3), 750000, 3200000 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(3), 750000, 3200000 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(6), 750000, 3200000 },
+ { 1, { 576000, HFPLL, 1, 30 }, L2(6), 750000, 3200000 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(7), 750000, 3200000 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(7), 760000, 3200000 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(10), 770000, 3200000 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(10), 780000, 3200000 },
+ { 0, { 960000, HFPLL, 1, 50 }, L2(10), 790000, 3200000 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 800000, 3200000 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(12), 810000, 3200000 },
+ { 0, { 1190400, HFPLL, 1, 62 }, L2(12), 820000, 3200000 },
+ { 0, { 1267200, HFPLL, 1, 66 }, L2(12), 830000, 3200000 },
+ { 1, { 1344000, HFPLL, 1, 70 }, L2(12), 840000, 3200000 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(16), 850000, 3200000 },
+ { 0, { 1497600, HFPLL, 1, 78 }, L2(16), 860000, 3200000 },
+ { 0, { 1574400, HFPLL, 1, 82 }, L2(16), 870000, 3200000 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(16), 875000, 3200000 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(16), 885000, 3200000 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(19), 895000, 3200000 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(19), 905000, 3200000 },
+ { 0, { 1958400, HFPLL, 1, 102 }, L2(19), 915000, 3200000 },
+ { 1, { 2035200, HFPLL, 1, 106 }, L2(19), 920000, 3200000 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 930000, 3200000 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 940000, 3200000 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 950000, 3200000 },
+ { 0, { 0 } }
+};
+
static struct pvs_table pvs_v1[NUM_SPEED_BINS][NUM_PVS] __initdata = {
/* 8974v1 1.7GHz Parts */
[0][0] = { acpu_freq_tbl_v1_pvs0, sizeof(acpu_freq_tbl_v1_pvs0) },
@@ -351,23 +699,23 @@
static struct pvs_table pvs_v2[NUM_SPEED_BINS][NUM_PVS] __initdata = {
/* 8974v2 2.0GHz Parts */
[0][0] = { acpu_freq_tbl_2g_pvs0, sizeof(acpu_freq_tbl_2g_pvs0) },
- [0][1] = { acpu_freq_tbl_2g_pvs0, sizeof(acpu_freq_tbl_2g_pvs0) },
- [0][2] = { acpu_freq_tbl_2g_pvs0, sizeof(acpu_freq_tbl_2g_pvs0) },
- [0][3] = { acpu_freq_tbl_2g_pvs0, sizeof(acpu_freq_tbl_2g_pvs0) },
- [0][4] = { acpu_freq_tbl_2g_pvs0, sizeof(acpu_freq_tbl_2g_pvs0) },
- [0][5] = { acpu_freq_tbl_2g_pvs0, sizeof(acpu_freq_tbl_2g_pvs0) },
- [0][6] = { acpu_freq_tbl_2g_pvs0, sizeof(acpu_freq_tbl_2g_pvs0) },
- [0][7] = { acpu_freq_tbl_2g_pvs0, sizeof(acpu_freq_tbl_2g_pvs0) },
+ [0][1] = { acpu_freq_tbl_2g_pvs1, sizeof(acpu_freq_tbl_2g_pvs1) },
+ [0][2] = { acpu_freq_tbl_2g_pvs2, sizeof(acpu_freq_tbl_2g_pvs2) },
+ [0][3] = { acpu_freq_tbl_2g_pvs3, sizeof(acpu_freq_tbl_2g_pvs3) },
+ [0][4] = { acpu_freq_tbl_2g_pvs4, sizeof(acpu_freq_tbl_2g_pvs4) },
+ [0][5] = { acpu_freq_tbl_2g_pvs5, sizeof(acpu_freq_tbl_2g_pvs5) },
+ [0][6] = { acpu_freq_tbl_2g_pvs6, sizeof(acpu_freq_tbl_2g_pvs6) },
+ [0][7] = { acpu_freq_tbl_2g_pvs6, sizeof(acpu_freq_tbl_2g_pvs6) },
/* 8974v2 2.3GHz Parts */
[1][0] = { acpu_freq_tbl_2p3g_pvs0, sizeof(acpu_freq_tbl_2p3g_pvs0) },
- [1][1] = { acpu_freq_tbl_2p3g_pvs0, sizeof(acpu_freq_tbl_2p3g_pvs0) },
- [1][2] = { acpu_freq_tbl_2p3g_pvs0, sizeof(acpu_freq_tbl_2p3g_pvs0) },
- [1][3] = { acpu_freq_tbl_2p3g_pvs0, sizeof(acpu_freq_tbl_2p3g_pvs0) },
- [1][4] = { acpu_freq_tbl_2p3g_pvs0, sizeof(acpu_freq_tbl_2p3g_pvs0) },
- [1][5] = { acpu_freq_tbl_2p3g_pvs0, sizeof(acpu_freq_tbl_2p3g_pvs0) },
- [1][6] = { acpu_freq_tbl_2p3g_pvs0, sizeof(acpu_freq_tbl_2p3g_pvs0) },
- [1][7] = { acpu_freq_tbl_2p3g_pvs0, sizeof(acpu_freq_tbl_2p3g_pvs0) },
+ [1][1] = { acpu_freq_tbl_2p3g_pvs1, sizeof(acpu_freq_tbl_2p3g_pvs1) },
+ [1][2] = { acpu_freq_tbl_2p3g_pvs2, sizeof(acpu_freq_tbl_2p3g_pvs2) },
+ [1][3] = { acpu_freq_tbl_2p3g_pvs3, sizeof(acpu_freq_tbl_2p3g_pvs3) },
+ [1][4] = { acpu_freq_tbl_2p3g_pvs4, sizeof(acpu_freq_tbl_2p3g_pvs4) },
+ [1][5] = { acpu_freq_tbl_2p3g_pvs5, sizeof(acpu_freq_tbl_2p3g_pvs5) },
+ [1][6] = { acpu_freq_tbl_2p3g_pvs6, sizeof(acpu_freq_tbl_2p3g_pvs6) },
+ [1][7] = { acpu_freq_tbl_2p3g_pvs6, sizeof(acpu_freq_tbl_2p3g_pvs6) },
};
static struct msm_bus_scale_pdata bus_scale_data __initdata = {