Merge "Bluetooth: Handle pairing cancel req for LE device"
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 53fd3b2..23181d9 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1808,7 +1808,7 @@
config OABI_COMPAT
bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
- default y
+ default y if !SMP
help
This option preserves the old syscall interface along with the
new (ARM EABI) one. It also provides a compatibility layer to
diff --git a/arch/arm/boot/dts/msm8226.dtsi b/arch/arm/boot/dts/msm8226.dtsi
index bba15a3..36bcdd7 100644
--- a/arch/arm/boot/dts/msm8226.dtsi
+++ b/arch/arm/boot/dts/msm8226.dtsi
@@ -85,6 +85,15 @@
compatible = "qcom,android-usb";
};
+ wcd9xxx_intc: wcd9xxx-irq {
+ compatible = "qcom,wcd9xxx-irq";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&msmgpio>;
+ interrupts = <68 0>;
+ interrupt-names = "cdc-int";
+ };
+
slim@fe12f000 {
cell-index = <1>;
compatible = "qcom,slim-ngd";
@@ -93,6 +102,212 @@
reg-names = "slimbus_physical", "slimbus_bam_physical";
interrupts = <0 163 0>, <0 164 0>;
interrupt-names = "slimbus_irq", "slimbus_bam_irq";
+
+ tapan_codec {
+ compatible = "qcom,tapan-slim-pgd";
+ elemental-addr = [00 01 E0 00 17 02];
+
+ interrupt-parent = <&wcd9xxx_intc>;
+ interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
+ 17 18 19 20 21 22 23 24 25 26 27 28>;
+ qcom,cdc-reset-gpio = <&msmgpio 72 0>;
+
+ cdc-vdd-buck-supply = <&pm8026_s4>;
+ qcom,cdc-vdd-buck-voltage = <2100000 2100000>;
+ qcom,cdc-vdd-buck-current = <650000>;
+
+ cdc-vdd-h-supply = <&pm8026_l6>;
+ qcom,cdc-vdd-h-voltage = <1800000 1800000>;
+ qcom,cdc-vdd-h-current = <25000>;
+
+ cdc-vdd-px-supply = <&pm8026_l6>;
+ qcom,cdc-vdd-px-voltage = <1800000 1800000>;
+ qcom,cdc-vdd-px-current = <25000>;
+
+ cdc-vdd-a-1p2v-supply = <&pm8026_l4>;
+ qcom,cdc-vdd-a-1p2v-voltage = <1200000 1200000>;
+ qcom,cdc-vdd-a-1p2v-current = <10000>;
+
+ cdc-vdd-cx-supply = <&pm8026_l4>;
+ qcom,cdc-vdd-cx-voltage = <1200000 1200000>;
+ qcom,cdc-vdd-cx-current = <10000>;
+
+ qcom,cdc-micbias-ldoh-v = <0x3>;
+ qcom,cdc-micbias-cfilt1-mv = <1800>;
+ qcom,cdc-micbias-cfilt2-mv = <1800>;
+ qcom,cdc-micbias-cfilt3-mv = <1800>;
+
+ qcom,cdc-micbias1-cfilt-sel = <0x0>;
+ qcom,cdc-micbias2-cfilt-sel = <0x1>;
+ qcom,cdc-micbias3-cfilt-sel = <0x2>;
+
+ qcom,cdc-mclk-clk-rate = <9600000>;
+ qcom,cdc-slim-ifd = "tapan-slim-ifd";
+ qcom,cdc-slim-ifd-elemental-addr = [00 00 E0 00 17 02];
+ };
+ };
+
+ qcom,msm-adsp-loader {
+ compatible = "qcom,adsp-loader";
+ qcom,adsp-state = <0>;
+ };
+
+ sound {
+ compatible = "qcom,msm8226-audio-tapan";
+ qcom,model = "msm8226-tapan-snd-card";
+
+ qcom,audio-routing =
+ "RX_BIAS", "MCLK",
+ "LDO_H", "MCLK",
+ "AMIC1", "MIC BIAS1 Internal1",
+ "MIC BIAS1 Internal1", "Handset Mic",
+ "AMIC2", "MIC BIAS2 External",
+ "MIC BIAS2 External", "Headset Mic",
+ "AMIC3", "MIC BIAS2 External",
+ "MIC BIAS2 External", "ANCRight Headset Mic",
+ "AMIC4", "MIC BIAS2 External",
+ "MIC BIAS2 External", "ANCLeft Headset Mic",
+ "DMIC1", "MIC BIAS1 External",
+ "MIC BIAS1 External", "Digital Mic1",
+ "DMIC2", "MIC BIAS1 External",
+ "MIC BIAS1 External", "Digital Mic2",
+ "DMIC3", "MIC BIAS3 External",
+ "MIC BIAS3 External", "Digital Mic3",
+ "DMIC4", "MIC BIAS3 External",
+ "MIC BIAS3 External", "Digital Mic4",
+ "DMIC5", "MIC BIAS4 External",
+ "MIC BIAS4 External", "Digital Mic5",
+ "DMIC6", "MIC BIAS4 External",
+ "MIC BIAS4 External", "Digital Mic6";
+ qcom,tapan-mclk-clk-freq = <9600000>;
+ };
+
+ qcom,msm-pcm {
+ compatible = "qcom,msm-pcm-dsp";
+ };
+
+ qcom,msm-pcm-routing {
+ compatible = "qcom,msm-pcm-routing";
+ };
+
+ qcom,msm-pcm-lpa {
+ compatible = "qcom,msm-pcm-lpa";
+ };
+
+ qcom,msm-compr-dsp {
+ compatible = "qcom,msm-compr-dsp";
+ };
+
+ qcom,msm-voip-dsp {
+ compatible = "qcom,msm-voip-dsp";
+ };
+
+ qcom,msm-pcm-voice {
+ compatible = "qcom,msm-pcm-voice";
+ };
+
+ qcom,msm-stub-codec {
+ compatible = "qcom,msm-stub-codec";
+ };
+
+ qcom,msm-dai-fe {
+ compatible = "qcom,msm-dai-fe";
+ };
+
+ qcom,msm-pcm-afe {
+ compatible = "qcom,msm-pcm-afe";
+ };
+
+ qcom,msm-dai-q6-hdmi {
+ compatible = "qcom,msm-dai-q6-hdmi";
+ qcom,msm-dai-q6-dev-id = <8>;
+ };
+
+ qcom,msm-dai-q6 {
+ compatible = "qcom,msm-dai-q6";
+ qcom,msm-dai-q6-sb-0-rx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <16384>;
+ };
+
+ qcom,msm-dai-q6-sb-0-tx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <16385>;
+ };
+
+ qcom,msm-dai-q6-sb-1-rx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <16386>;
+ };
+
+ qcom,msm-dai-q6-sb-1-tx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <16387>;
+ };
+
+ qcom,msm-dai-q6-sb-3-rx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <16390>;
+ };
+
+ qcom,msm-dai-q6-sb-3-tx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <16391>;
+ };
+
+ qcom,msm-dai-q6-sb-4-rx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <16392>;
+ };
+
+ qcom,msm-dai-q6-sb-4-tx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <16393>;
+ };
+
+ qcom,msm-dai-q6-bt-sco-rx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <12288>;
+ };
+
+ qcom,msm-dai-q6-bt-sco-tx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <12289>;
+ };
+
+ qcom,msm-dai-q6-int-fm-rx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <12292>;
+ };
+
+ qcom,msm-dai-q6-int-fm-tx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <12293>;
+ };
+
+ qcom,msm-dai-q6-be-afe-pcm-rx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <224>;
+ };
+
+ qcom,msm-dai-q6-be-afe-pcm-tx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <225>;
+ };
+
+ qcom,msm-dai-q6-afe-proxy-rx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <241>;
+ };
+
+ qcom,msm-dai-q6-afe-proxy-tx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <240>;
+ };
+ };
+
+ qcom,msm-pcm-hostless {
+ compatible = "qcom,msm-pcm-hostless";
};
qcom,wdt@f9017000 {
diff --git a/arch/arm/configs/msm8910_defconfig b/arch/arm/configs/msm8910_defconfig
index bf163e0..4b1e3f2 100644
--- a/arch/arm/configs/msm8910_defconfig
+++ b/arch/arm/configs/msm8910_defconfig
@@ -36,6 +36,7 @@
CONFIG_ARCH_MSM=y
CONFIG_ARCH_MSM8910=y
CONFIG_ARCH_MSM8226=y
+CONFIG_SND_SOC_MSM8226=y
# CONFIG_MSM_STACKED_MEMORY is not set
CONFIG_CPU_HAS_L2_PMU=y
# CONFIG_MSM_FIQ_SUPPORT is not set
@@ -45,6 +46,7 @@
# CONFIG_MSM_HW3D is not set
CONFIG_MSM_DIRECT_SCLK_ACCESS=y
CONFIG_MSM_WATCHDOG_V2=y
+CONFIG_MSM_ADSP_LOADER=m
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_SMP=y
@@ -104,8 +106,12 @@
CONFIG_SPMI=y
CONFIG_SPMI_MSM_PMIC_ARB=y
CONFIG_MSM_QPNP_INT=y
+CONFIG_SLIMBUS=y
+CONFIG_SLIMBUS_MSM_NGD=y
CONFIG_DEBUG_GPIO=y
CONFIG_GPIO_SYSFS=y
+CONFIG_I2C=y
+CONFIG_WCD9306_CODEC=y
# CONFIG_HWMON is not set
CONFIG_REGULATOR=y
CONFIG_REGULATOR_STUB=y
@@ -130,7 +136,6 @@
CONFIG_MMC_BLOCK_MINORS=32
CONFIG_MMC_TEST=m
CONFIG_MMC_MSM=y
-CONFIG_MMC_MSM_SPS_SUPPORT=y
CONFIG_STAGING=y
CONFIG_ANDROID=y
CONFIG_ANDROID_BINDER_IPC=y
@@ -138,9 +143,10 @@
CONFIG_ANDROID_RAM_CONSOLE=y
CONFIG_ANDROID_TIMED_GPIO=y
CONFIG_ANDROID_LOW_MEMORY_KILLER=y
+CONFIG_MSM_IOMMU=y
CONFIG_SPS=y
CONFIG_SPS_SUPPORT_NDP_BAM=y
-CONFIG_MSM_IOMMU=y
+CONFIG_MMC_MSM_SPS_SUPPORT=y
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT3_FS=y
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index a32de20..5b0ac52 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -346,6 +346,7 @@
select MSM_RUN_QUEUE_STATS
select MIGHT_HAVE_CACHE_L2X0
select ARM_HAS_SG_CHAIN
+ select CPU_HAS_L2_PMU
config ARCH_MSM9625
bool "MSM9625"
@@ -403,6 +404,9 @@
select MSM_GPIOMUX
select MSM_NATIVE_RESTART
select MSM_RESTART_V2
+ select MSM_QDSP6_APRV2
+ select MSM_QDSP6V2_CODECS
+ select MSM_AUDIO_QDSP6V2 if SND_SOC
endmenu
choice
@@ -479,6 +483,7 @@
select ARCH_MSM_CORTEXMP
select MIGHT_HAVE_CACHE_L2X0
select ARM_HAS_SG_CHAIN
+ select CPU_HAS_L2_PMU
config MSM_VIC
bool
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index 9d9550e..594bb5f 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -33,8 +33,12 @@
obj-$(CONFIG_ARCH_MSM_SCORPIONMP) += perf_event_msm_l2.o
obj-$(CONFIG_ARCH_MSM_KRAIT) += msm-krait-l2-accessors.o pmu.o perf_event_msm_krait_l2.o
obj-$(CONFIG_ARCH_MSM_KRAIT) += krait-scm.o
-obj-$(CONFIG_ARCH_MSM7X27A) += pmu.o
+ifdef CONFIG_HW_PERF_EVENTS
+obj-$(CONFIG_ARCH_MSM7X27A) += pmu.o perf_event_msm_pl310.o
obj-$(CONFIG_ARCH_MSM9625) += pmu.o perf_event_msm_pl310.o
+obj-$(CONFIG_ARCH_MSM8625) += pmu.o perf_event_msm_pl310.o
+obj-$(CONFIG_ARCH_MSM9615) += pmu.o perf_event_msm_pl310.o
+endif
ifndef CONFIG_MSM_SMP
obj-$(CONFIG_ARCH_MSM_SCORPION) += msm_fault_handlers.o
diff --git a/arch/arm/mach-msm/board-8064-display.c b/arch/arm/mach-msm/board-8064-display.c
index b717973..b0dc20b 100644
--- a/arch/arm/mach-msm/board-8064-display.c
+++ b/arch/arm/mach-msm/board-8064-display.c
@@ -818,12 +818,13 @@
return 0;
/* TBD: PM8921 regulator instead of 8901 */
- if (!reg_ext_3p3v) {
+ if (!reg_ext_3p3v &&
+ (!(machine_is_mpq8064_hrd() || machine_is_mpq8064_dtv()))) {
reg_ext_3p3v = regulator_get(&hdmi_msm_device.dev,
- "hdmi_mux_vdd");
+ "hdmi_mux_vdd");
if (IS_ERR_OR_NULL(reg_ext_3p3v)) {
pr_err("could not get reg_ext_3p3v, rc = %ld\n",
- PTR_ERR(reg_ext_3p3v));
+ PTR_ERR(reg_ext_3p3v));
reg_ext_3p3v = NULL;
return -ENODEV;
}
@@ -831,7 +832,7 @@
if (!reg_8921_lvs7) {
reg_8921_lvs7 = regulator_get(&hdmi_msm_device.dev,
- "hdmi_vdda");
+ "hdmi_vdda");
if (IS_ERR(reg_8921_lvs7)) {
pr_err("could not get reg_8921_lvs7, rc = %ld\n",
PTR_ERR(reg_8921_lvs7));
@@ -841,7 +842,7 @@
}
if (!reg_8921_s4) {
reg_8921_s4 = regulator_get(&hdmi_msm_device.dev,
- "hdmi_lvl_tsl");
+ "hdmi_lvl_tsl");
if (IS_ERR(reg_8921_s4)) {
pr_err("could not get reg_8921_s4, rc = %ld\n",
PTR_ERR(reg_8921_s4));
@@ -860,17 +861,22 @@
* Configure 3P3V_BOOST_EN as GPIO, 8mA drive strength,
* pull none, out-high
*/
- rc = regulator_set_optimum_mode(reg_ext_3p3v, 290000);
- if (rc < 0) {
- pr_err("set_optimum_mode ext_3p3v failed, rc=%d\n", rc);
- return -EINVAL;
+ if (!(machine_is_mpq8064_hrd() || machine_is_mpq8064_dtv())) {
+ rc = regulator_set_optimum_mode(reg_ext_3p3v, 290000);
+ if (rc < 0) {
+ pr_err("set_optimum_mode ext_3p3v failed," \
+ "rc=%d\n", rc);
+ return -EINVAL;
+ }
+
+ rc = regulator_enable(reg_ext_3p3v);
+ if (rc) {
+ pr_err("enable reg_ext_3p3v failed, rc=%d\n",
+ rc);
+ return rc;
+ }
}
- rc = regulator_enable(reg_ext_3p3v);
- if (rc) {
- pr_err("enable reg_ext_3p3v failed, rc=%d\n", rc);
- return rc;
- }
rc = regulator_enable(reg_8921_lvs7);
if (rc) {
pr_err("'%s' regulator enable failed, rc=%d\n",
@@ -885,11 +891,15 @@
}
pr_debug("%s(on): success\n", __func__);
} else {
- rc = regulator_disable(reg_ext_3p3v);
- if (rc) {
- pr_err("disable reg_ext_3p3v failed, rc=%d\n", rc);
- return -ENODEV;
+ if (!(machine_is_mpq8064_hrd() || machine_is_mpq8064_dtv())) {
+ rc = regulator_disable(reg_ext_3p3v);
+ if (rc) {
+ pr_err("disable reg_ext_3p3v failed, rc=%d\n",
+ rc);
+ return -ENODEV;
+ }
}
+
rc = regulator_disable(reg_8921_lvs7);
if (rc) {
pr_err("disable reg_8921_l23 failed, rc=%d\n", rc);
@@ -910,7 +920,8 @@
error2:
regulator_disable(reg_8921_lvs7);
error1:
- regulator_disable(reg_ext_3p3v);
+ if (!(machine_is_mpq8064_hrd() || machine_is_mpq8064_dtv()))
+ regulator_disable(reg_ext_3p3v);
return rc;
}
diff --git a/arch/arm/mach-msm/board-8226-gpiomux.c b/arch/arm/mach-msm/board-8226-gpiomux.c
index 2b5399f..7a53b24 100644
--- a/arch/arm/mach-msm/board-8226-gpiomux.c
+++ b/arch/arm/mach-msm/board-8226-gpiomux.c
@@ -17,6 +17,57 @@
#include <mach/gpio.h>
#include <mach/gpiomux.h>
+#define KS8851_IRQ_GPIO 75
+
+#if defined(CONFIG_KS8851) || defined(CONFIG_KS8851_MODULE)
+static struct gpiomux_setting gpio_eth_config = {
+ .pull = GPIOMUX_PULL_UP,
+ .drv = GPIOMUX_DRV_2MA,
+ .func = GPIOMUX_FUNC_GPIO,
+};
+static struct gpiomux_setting gpio_spi_config = {
+ .func = GPIOMUX_FUNC_1,
+ .drv = GPIOMUX_DRV_8MA,
+ .pull = GPIOMUX_PULL_NONE,
+};
+
+static struct msm_gpiomux_config msm_eth_configs[] = {
+ {
+ .gpio = KS8851_IRQ_GPIO,
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &gpio_eth_config,
+ }
+ },
+};
+
+static struct msm_gpiomux_config msm_blsp_configs[] __initdata = {
+ {
+ .gpio = 0, /* BLSP1 QUP2 SPI_DATA_MOSI */
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &gpio_spi_config,
+ },
+ },
+ {
+ .gpio = 1, /* BLSP1 QUP2 SPI_DATA_MISO */
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &gpio_spi_config,
+ },
+ },
+ {
+ .gpio = 2, /* BLSP1 QUP2 SPI_CS_N */
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &gpio_spi_config,
+ },
+ },
+ {
+ .gpio = 3, /* BLSP1 QUP2 SPI_CLK */
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &gpio_spi_config,
+ },
+ },
+};
+#endif
+
void __init msm8226_init_gpiomux(void)
{
int rc;
@@ -26,4 +77,8 @@
pr_err("%s failed %d\n", __func__, rc);
return;
}
+#if defined(CONFIG_KS8851) || defined(CONFIG_KS8851_MODULE)
+ msm_gpiomux_install(msm_eth_configs, ARRAY_SIZE(msm_eth_configs));
+ msm_gpiomux_install(msm_blsp_configs, ARRAY_SIZE(msm_blsp_configs));
+#endif
}
diff --git a/arch/arm/mach-msm/board-8226.c b/arch/arm/mach-msm/board-8226.c
index a5cb481..2f2eb2c 100644
--- a/arch/arm/mach-msm/board-8226.c
+++ b/arch/arm/mach-msm/board-8226.c
@@ -73,6 +73,8 @@
CLK_DUMMY("iface_clk", NULL, "msm_sdcc.2", OFF),
CLK_DUMMY("core_clk", NULL, "msm_sdcc.2", OFF),
CLK_DUMMY("bus_clk", NULL, "msm_sdcc.2", OFF),
+ CLK_DUMMY("core_clk", NULL, "f9928000.spi", OFF),
+ CLK_DUMMY("iface_clk", NULL, "f9928000.spi", OFF),
};
static struct clock_init_data msm_dummy_clock_init_data __initdata = {
diff --git a/arch/arm/mach-msm/board-9615.c b/arch/arm/mach-msm/board-9615.c
index 2392f57..d6b8a97 100644
--- a/arch/arm/mach-msm/board-9615.c
+++ b/arch/arm/mach-msm/board-9615.c
@@ -254,6 +254,8 @@
ADC_DECIMATION_TYPE2, ADC_SCALE_DEFAULT},
{"pa_therm0", ADC_MPP_1_AMUX3, CHAN_PATH_SCALING1, AMUX_RSV1,
ADC_DECIMATION_TYPE2, ADC_SCALE_PA_THERM},
+ {"xo_therm", CHANNEL_MUXOFF, CHAN_PATH_SCALING1, AMUX_RSV0,
+ ADC_DECIMATION_TYPE2, ADC_SCALE_XOTHERM},
};
static struct pm8xxx_adc_properties pm8018_adc_data = {
diff --git a/arch/arm/mach-msm/clock-9625.c b/arch/arm/mach-msm/clock-9625.c
index 3b1df2e..f4c045c 100644
--- a/arch/arm/mach-msm/clock-9625.c
+++ b/arch/arm/mach-msm/clock-9625.c
@@ -2101,8 +2101,7 @@
CLK_LOOKUP("phy_clk", gcc_usb_hsic_clk.c, "f9a15000.hsic"),
CLK_LOOKUP("cal_clk", gcc_usb_hsic_io_cal_clk.c, "f9a15000.hsic"),
CLK_LOOKUP("core_clk", gcc_usb_hsic_system_clk.c, "f9a15000.hsic"),
- CLK_LOOKUP("alt_core_clk", gcc_usb_hsic_xcvr_fs_clk.c,
- "f9a15000.hsic"),
+ CLK_LOOKUP("alt_core_clk", gcc_usb_hsic_xcvr_fs_clk.c, ""),
CLK_LOOKUP("core_clk", gcc_ce1_clk.c, "fd400000.qcom,qcedev"),
CLK_LOOKUP("iface_clk", gcc_ce1_ahb_clk.c, "fd400000.qcom,qcedev"),
diff --git a/arch/arm/mach-msm/devices-msm7x27a.c b/arch/arm/mach-msm/devices-msm7x27a.c
index cf456f7..3c60fa6 100644
--- a/arch/arm/mach-msm/devices-msm7x27a.c
+++ b/arch/arm/mach-msm/devices-msm7x27a.c
@@ -1667,7 +1667,7 @@
},
{
.name = "l2_irq",
- .start = MSM8625_INT_L2CC_INTR,
+ .start = MSM8625_INT_SC_SICL2PERFMONIRPTREQ,
.flags = IORESOURCE_IRQ,
},
};
@@ -2096,7 +2096,7 @@
msm_cpr_init();
if (!cpu_is_msm8625() && !cpu_is_msm8625q())
- pl310_resources[1].start = INT_L2CC_INTR;
+ pl310_resources[1].start = SC_SICL2PERFMONIRPTREQ;
platform_device_register(&pl310_erp_device);
diff --git a/arch/arm/mach-msm/include/mach/irqs-7xxx.h b/arch/arm/mach-msm/include/mach/irqs-7xxx.h
index c90b4ee..97ca682 100644
--- a/arch/arm/mach-msm/include/mach/irqs-7xxx.h
+++ b/arch/arm/mach-msm/include/mach/irqs-7xxx.h
@@ -75,7 +75,7 @@
/* 22-31 are reserved except 7x27a*/
#if defined(CONFIG_ARCH_MSM7X27A)
#define INT_L2CC_EM (32 + 22)
-#define INT_L2CC_INTR (32 + 23)
+#define SC_SICL2PERFMONIRPTREQ (32 + 23)
#define INT_CE_IRQ (32 + 24)
#endif
diff --git a/arch/arm/mach-msm/include/mach/irqs-8625.h b/arch/arm/mach-msm/include/mach/irqs-8625.h
index a83dd2e..7083390 100644
--- a/arch/arm/mach-msm/include/mach/irqs-8625.h
+++ b/arch/arm/mach-msm/include/mach/irqs-8625.h
@@ -83,7 +83,7 @@
#define MSM8625_INT_UART2DM_IRQ (GIC_SPI_START + 32 + 20)
#define MSM8625_INT_UART2DM_RX (GIC_SPI_START + 32 + 21)
#define MSM8625_INT_L2CC_EM (GIC_SPI_START + 32 + 22)
-#define MSM8625_INT_L2CC_INTR (GIC_SPI_START + 32 + 23)
+#define MSM8625_INT_SC_SICL2PERFMONIRPTREQ (GIC_SPI_START + 32 + 23)
#define MSM8625_INT_CE_IRQ (GIC_SPI_START + 32 + 24)
#define MSM8625_INT_CPR_IRQ0 (GIC_SPI_START + 32 + 25)
#define MSM8625_INT_CPR_IRQ1 (GIC_SPI_START + 32 + 26)
diff --git a/arch/arm/mach-msm/include/mach/qdsp6v2/audio_acdb.h b/arch/arm/mach-msm/include/mach/qdsp6v2/audio_acdb.h
index 88cb94a..b830134 100644
--- a/arch/arm/mach-msm/include/mach/qdsp6v2/audio_acdb.h
+++ b/arch/arm/mach-msm/include/mach/qdsp6v2/audio_acdb.h
@@ -14,7 +14,9 @@
#define _AUDIO_ACDB_H
#include <linux/msm_audio_acdb.h>
-#if defined CONFIG_ARCH_MSM8974 || defined CONFIG_ARCH_MSM9625
+#if defined(CONFIG_ARCH_MSM8974) || defined(CONFIG_ARCH_MSM9625) \
+ || defined(CONFIG_ARCH_MSM8226)
+
#include <sound/q6adm-v2.h>
#else
#include <sound/q6adm.h>
diff --git a/arch/arm/mach-msm/include/mach/sps.h b/arch/arm/mach-msm/include/mach/sps.h
index a000c3e..d6c341a 100644
--- a/arch/arm/mach-msm/include/mach/sps.h
+++ b/arch/arm/mach-msm/include/mach/sps.h
@@ -77,6 +77,8 @@
#define SPS_BAM_OPT_IRQ_WAKEUP (1UL << 3)
/* Ignore external block pipe reset */
#define SPS_BAM_NO_EXT_P_RST (1UL << 4)
+/* Don't enable local clock gating */
+#define SPS_BAM_NO_LOCAL_CLK_GATING (1UL << 5)
/* BAM device management flags */
diff --git a/arch/arm/mach-msm/mpm-8625.c b/arch/arm/mach-msm/mpm-8625.c
index aaac476..06c0606 100644
--- a/arch/arm/mach-msm/mpm-8625.c
+++ b/arch/arm/mach-msm/mpm-8625.c
@@ -101,7 +101,7 @@
static uint16_t msm_bypassed_apps_irqs[] = {
MSM8625_INT_CPR_IRQ0,
- MSM8625_INT_L2CC_INTR,
+ MSM8625_INT_SC_SICL2PERFMONIRPTREQ,
};
/* Check IRQ falls into bypassed list are not */
diff --git a/arch/arm/mach-msm/perf_event_msm_pl310.c b/arch/arm/mach-msm/perf_event_msm_pl310.c
index 40a2f98..e2a580f 100644
--- a/arch/arm/mach-msm/perf_event_msm_pl310.c
+++ b/arch/arm/mach-msm/perf_event_msm_pl310.c
@@ -22,6 +22,9 @@
#include <asm/pmu.h>
#include <asm/hardware/cache-l2x0.h>
+#include <mach/socinfo.h>
+
+static u32 rev1;
/*
* Store dynamic PMU type after registration,
@@ -110,6 +113,30 @@
#define COUNTER_ADDR(idx) (l2x0_base + L2X0_EVENT_CNT0_VAL - 4*idx)
+static u32 l2x0_read_intr_mask(void)
+{
+ return readl_relaxed(l2x0_base + L2X0_INTR_MASK);
+}
+
+static void l2x0_write_intr_mask(u32 val)
+{
+ writel_relaxed(val, l2x0_base + L2X0_INTR_MASK);
+}
+
+static void l2x0_enable_counter_interrupt(void)
+{
+ u32 intr_mask = l2x0_read_intr_mask();
+ intr_mask |= L2X0_INTR_MASK_ECNTR;
+ l2x0_write_intr_mask(intr_mask);
+}
+
+static void l2x0_disable_counter_interrupt(void)
+{
+ u32 intr_mask = l2x0_read_intr_mask();
+ intr_mask &= ~L2X0_INTR_MASK_ECNTR;
+ l2x0_write_intr_mask(intr_mask);
+}
+
static void l2x0_clear_interrupts(u32 flags)
{
writel_relaxed(flags, l2x0_base + L2X0_INTR_CLEAR);
@@ -190,10 +217,8 @@
raw_spin_lock_irqsave(&l2x0pmu_hw_events.pmu_lock, flags);
- /*
- * TODO: Enable counter interrupt,
- * once we know it works on this chip.
- */
+ if (!rev1)
+ l2x0_enable_counter_interrupt();
val = l2x0pmu_read_ctrl();
@@ -214,10 +239,8 @@
val &= ~L2X0_EVENT_CNT_ENABLE_MASK;
l2x0pmu_write_ctrl(val);
- /*
- * TODO: Disable counter interrupt,
- * once we know it works on this chip.
- */
+ if (!rev1)
+ l2x0_disable_counter_interrupt();
raw_spin_unlock_irqrestore(&l2x0pmu_hw_events.pmu_lock, flags);
}
@@ -401,6 +424,9 @@
static int __init register_pmu_driver(void)
{
+ if (machine_is_msm9625())
+ rev1 = 1;
+
return platform_driver_register(&l2x0pmu_driver);
}
device_initcall(register_pmu_driver);
diff --git a/arch/arm/mach-msm/pmu.c b/arch/arm/mach-msm/pmu.c
index f0b83f9..cb191fc 100644
--- a/arch/arm/mach-msm/pmu.c
+++ b/arch/arm/mach-msm/pmu.c
@@ -137,6 +137,21 @@
.resource = msm8625_cpu_pmu_resource,
.num_resources = ARRAY_SIZE(msm8625_cpu_pmu_resource),
};
+
+static struct resource msm8625_l2_pmu_resource[] = {
+ {
+ .start = MSM8625_INT_SC_SICL2PERFMONIRPTREQ,
+ .end = MSM8625_INT_SC_SICL2PERFMONIRPTREQ,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device msm8625_l2_pmu_device = {
+ .name = "l2-arm-pmu",
+ .id = ARM_PMU_DEVICE_L2CC,
+ .resource = msm8625_l2_pmu_resource,
+ .num_resources = ARRAY_SIZE(msm8625_l2_pmu_resource),
+};
#endif
static struct platform_device *pmu_devices[] = {
@@ -168,6 +183,7 @@
#ifdef CONFIG_ARCH_MSM8625
if (cpu_is_msm8625()) {
pmu_devices[0] = &msm8625_cpu_pmu_device;
+ pmu_devices[1] = &msm8625_l2_pmu_device;
msm8625_cpu_pmu_device.dev.platform_data = &multicore_data;
}
#endif
diff --git a/arch/arm/mach-msm/qdsp5/audmgr.c b/arch/arm/mach-msm/qdsp5/audmgr.c
index 666323b..f2a84aa 100644
--- a/arch/arm/mach-msm/qdsp5/audmgr.c
+++ b/arch/arm/mach-msm/qdsp5/audmgr.c
@@ -3,7 +3,7 @@
* interface to "audmgr" service on the baseband cpu
*
* Copyright (C) 2008 Google, Inc.
- * Copyright (c) 2009, 2012 Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2009, 2012, 2013 Code Aurora Forum. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
@@ -46,6 +46,8 @@
struct msm_rpc_endpoint *ept;
struct task_struct *task;
uint32_t rpc_version;
+ uint32_t rx_device;
+ uint32_t tx_device;
int cad;
struct device_info_callback *device_cb[MAX_DEVICE_INFO_CALLBACK];
@@ -156,6 +158,22 @@
return;
if (am->state != STATE_ENABLED)
am->state = STATE_ENABLED;
+ if (!amg->cad)
+ break;
+
+ if (am->evt.session_info == SESSION_PLAYBACK &&
+ am->evt.dev_type.rx_device != amg->rx_device) {
+ am->evt.dev_type.rx_device = amg->rx_device;
+ am->evt.dev_type.tx_device = 0;
+ am->evt.acdb_id = am->evt.dev_type.rx_device;
+ }
+ if (am->evt.session_info == SESSION_RECORDING &&
+ am->evt.dev_type.tx_device != amg->tx_device) {
+ am->evt.dev_type.rx_device = 0;
+ am->evt.dev_type.tx_device = amg->tx_device;
+ am->evt.acdb_id = am->evt.dev_type.tx_device;
+ }
+
while ((amg->device_cb[i] != NULL) &&
(i < MAX_DEVICE_INFO_CALLBACK) &&
(amg->cad)) {
@@ -209,11 +227,13 @@
be32_to_cpu(temp->d.rx_device);
am->evt.dev_type.tx_device = 0;
am->evt.acdb_id = am->evt.dev_type.rx_device;
+ amg->rx_device = am->evt.dev_type.rx_device;
} else if (am->evt.session_info == SESSION_RECORDING) {
am->evt.dev_type.rx_device = 0;
am->evt.dev_type.tx_device =
be32_to_cpu(temp->d.tx_device);
am->evt.acdb_id = am->evt.dev_type.tx_device;
+ amg->tx_device = am->evt.dev_type.tx_device;
}
am->evt.dev_type.ear_mute =
be32_to_cpu(temp->d.ear_mute);
diff --git a/arch/arm/mach-msm/qdsp6v2/q6audio_common.h b/arch/arm/mach-msm/qdsp6v2/q6audio_common.h
index 3bc8454..5ffffd2 100644
--- a/arch/arm/mach-msm/qdsp6v2/q6audio_common.h
+++ b/arch/arm/mach-msm/qdsp6v2/q6audio_common.h
@@ -15,7 +15,9 @@
#ifndef __Q6_AUDIO_COMMON_H__
#define __Q6_AUDIO_COMMON_H__
-#if defined(CONFIG_ARCH_MSM8974) || defined(CONFIG_ARCH_MSM9625)
+#if defined(CONFIG_ARCH_MSM8974) || defined(CONFIG_ARCH_MSM9625) \
+ || defined(CONFIG_ARCH_MSM8226)
+
#include <sound/apr_audio-v2.h>
#include <sound/q6asm-v2.h>
#else
diff --git a/arch/arm/mach-msm/sdio_cmux.c b/arch/arm/mach-msm/sdio_cmux.c
index d04a0b0..48ca6b7 100644
--- a/arch/arm/mach-msm/sdio_cmux.c
+++ b/arch/arm/mach-msm/sdio_cmux.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2010-2013, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -68,6 +68,7 @@
struct list_head tx_list;
void *priv;
+ struct mutex rx_cb_lock;
void (*receive_cb)(void *, int, void *);
void (*write_done)(void *, int, void *);
void (*status_callback)(int, void *);
@@ -171,6 +172,7 @@
mutex_init(&logical_ch[id].tx_lock);
logical_ch[id].priv = NULL;
+ mutex_init(&logical_ch[id].rx_cb_lock);
logical_ch[id].receive_cb = NULL;
logical_ch[id].write_done = NULL;
return 0;
@@ -197,8 +199,10 @@
kfree(list_elem);
}
mutex_unlock(&logical_ch[id].tx_lock);
+ mutex_lock(&logical_ch[id].rx_cb_lock);
if (logical_ch[id].receive_cb)
logical_ch[id].receive_cb(NULL, 0, logical_ch[id].priv);
+ mutex_unlock(&logical_ch[id].rx_cb_lock);
if (logical_ch[id].write_done)
logical_ch[id].write_done(NULL, 0, logical_ch[id].priv);
mutex_unlock(&logical_ch[id].lc_lock);
@@ -300,9 +304,10 @@
}
logical_ch[id].is_local_open = 1;
logical_ch[id].priv = priv;
- logical_ch[id].receive_cb = receive_cb;
logical_ch[id].write_done = write_done;
logical_ch[id].status_callback = status_callback;
+ mutex_lock(&logical_ch[id].rx_cb_lock);
+ logical_ch[id].receive_cb = receive_cb;
if (logical_ch[id].receive_cb) {
mutex_lock(&temp_rx_lock);
list_for_each_entry_safe(list_elem, list_elem_tmp,
@@ -319,6 +324,7 @@
}
mutex_unlock(&temp_rx_lock);
}
+ mutex_unlock(&logical_ch[id].rx_cb_lock);
mutex_unlock(&logical_ch[id].lc_lock);
sdio_cmux_write_cmd(id, OPEN);
return 0;
@@ -338,7 +344,9 @@
ch = &logical_ch[id];
mutex_lock(&ch->lc_lock);
+ mutex_lock(&logical_ch[id].rx_cb_lock);
ch->receive_cb = NULL;
+ mutex_unlock(&logical_ch[id].rx_cb_lock);
mutex_lock(&ch->tx_lock);
ch->write_done = NULL;
mutex_unlock(&ch->tx_lock);
@@ -564,12 +572,20 @@
data = (void *)((char *)pkt + sizeof(struct sdio_cmux_hdr));
data_size = (int)(((struct sdio_cmux_hdr *)pkt)->pkt_len);
+ mutex_unlock(&logical_ch[id].lc_lock);
+ /*
+ * The lc_lock is released before the call to receive_cb
+ * to avoid a dead lock where in the receive_cb would call a
+ * function that tries to acquire a rx_lock which is already
+ * acquired by a Thread that is waiting on lc_lock.
+ */
+ mutex_lock(&logical_ch[id].rx_cb_lock);
if (logical_ch[id].receive_cb)
logical_ch[id].receive_cb(data, data_size,
logical_ch[id].priv);
else
copy_packet(pkt, size);
- mutex_unlock(&logical_ch[id].lc_lock);
+ mutex_unlock(&logical_ch[id].rx_cb_lock);
break;
case STATUS:
diff --git a/drivers/bluetooth/hci_smd.c b/drivers/bluetooth/hci_smd.c
index 6030520..9b60bda 100644
--- a/drivers/bluetooth/hci_smd.c
+++ b/drivers/bluetooth/hci_smd.c
@@ -44,6 +44,19 @@
#define RX_Q_MONITOR (500) /* 500 milli second */
#define HCI_REGISTER_SET 0
+/* SSR state machine to take care of back to back SSR requests
+ * and handling the incomming BT on/off,Airplane mode toggling and
+ * also spuriour SMD open notification while one SSr is in progress
+ */
+#define STATE_SSR_ON 0x1
+#define STATE_SSR_START 0x02
+#define STATE_SSR_CHANNEL_OPEN_PENDING 0x04
+#define STATE_SSR_PENDING_INIT 0x08
+#define STATE_SSR_COMPLETE 0x00
+#define STATE_SSR_OFF STATE_SSR_COMPLETE
+
+static int ssr_state = STATE_SSR_OFF;
+
static int hcismd_set;
static DEFINE_SEMAPHORE(hci_smd_enable);
@@ -341,25 +354,47 @@
break;
case SMD_EVENT_OPEN:
BT_INFO("opening HCI-SMD channel :%s", EVENT_CHANNEL);
- hci_smd_open(hdev);
- open_worker = kzalloc(sizeof(*open_worker), GFP_ATOMIC);
- if (!open_worker) {
- BT_ERR("Out of memory");
- break;
+ BT_DBG("SSR state is : %x", ssr_state);
+ if ((ssr_state == STATE_SSR_OFF) ||
+ (ssr_state == STATE_SSR_CHANNEL_OPEN_PENDING)) {
+
+ hci_smd_open(hdev);
+ open_worker = kzalloc(sizeof(*open_worker), GFP_ATOMIC);
+ if (!open_worker) {
+ BT_ERR("Out of memory");
+ break;
+ }
+ if (ssr_state == STATE_SSR_CHANNEL_OPEN_PENDING) {
+ ssr_state = STATE_SSR_PENDING_INIT;
+ BT_INFO("SSR state is : %x", ssr_state);
+ }
+ INIT_WORK(open_worker, hci_dev_smd_open);
+ schedule_work(open_worker);
+
}
- INIT_WORK(open_worker, hci_dev_smd_open);
- schedule_work(open_worker);
break;
case SMD_EVENT_CLOSE:
BT_INFO("Closing HCI-SMD channel :%s", EVENT_CHANNEL);
- hci_smd_close(hdev);
- reset_worker = kzalloc(sizeof(*reset_worker), GFP_ATOMIC);
- if (!reset_worker) {
- BT_ERR("Out of memory");
- break;
+ BT_DBG("SSR state is : %x", ssr_state);
+ if ((ssr_state == STATE_SSR_OFF) ||
+ (ssr_state == (STATE_SSR_PENDING_INIT))) {
+
+ hci_smd_close(hdev);
+ reset_worker = kzalloc(sizeof(*reset_worker),
+ GFP_ATOMIC);
+ if (!reset_worker) {
+ BT_ERR("Out of memory");
+ break;
+ }
+ ssr_state = STATE_SSR_ON;
+ BT_INFO("SSR state is : %x", ssr_state);
+ INIT_WORK(reset_worker, hci_dev_restart);
+ schedule_work(reset_worker);
+
+ } else if (ssr_state & STATE_SSR_ON) {
+ BT_ERR("SSR state is : %x", ssr_state);
}
- INIT_WORK(reset_worker, hci_dev_restart);
- schedule_work(reset_worker);
+
break;
default:
break;
@@ -403,19 +438,37 @@
{
struct hci_dev *hdev;
- hdev = hsmd->hdev;
- if (test_and_set_bit(HCI_REGISTER_SET, &hsmd->flags)) {
- BT_ERR("HCI device registered already");
+ if (hsmd->hdev)
+ hdev = hsmd->hdev;
+ else {
+ BT_ERR("hdev is NULL");
return 0;
- } else
- BT_INFO("HCI device registration is starting");
- if (hci_register_dev(hdev) < 0) {
- BT_ERR("Can't register HCI device");
- hci_free_dev(hdev);
- hsmd->hdev = NULL;
- clear_bit(HCI_REGISTER_SET, &hsmd->flags);
- return -ENODEV;
}
+ /* Allow the incomming SSR even the prev one at PENDING INIT STATE
+ * since clenup need to be started again from the beging and ignore
+ * or bypass the prev one
+ */
+ if ((ssr_state == STATE_SSR_OFF) ||
+ (ssr_state == STATE_SSR_PENDING_INIT)) {
+
+ if (test_and_set_bit(HCI_REGISTER_SET, &hsmd->flags)) {
+ BT_ERR("HCI device registered already");
+ return 0;
+ } else
+ BT_INFO("HCI device registration is starting");
+ if (hci_register_dev(hdev) < 0) {
+ BT_ERR("Can't register HCI device");
+ hci_free_dev(hdev);
+ hsmd->hdev = NULL;
+ clear_bit(HCI_REGISTER_SET, &hsmd->flags);
+ return -ENODEV;
+ }
+ if (ssr_state == STATE_SSR_PENDING_INIT) {
+ ssr_state = STATE_SSR_COMPLETE;
+ BT_INFO("SSR state is : %x", ssr_state);
+ }
+ } else if (ssr_state)
+ BT_ERR("Registration called in invalid context");
return 0;
}
@@ -449,7 +502,10 @@
*/
setup_timer(&hsmd->rx_q_timer, schedule_timer,
(unsigned long) hsmd->hdev);
-
+ if (ssr_state == STATE_SSR_START) {
+ ssr_state = STATE_SSR_CHANNEL_OPEN_PENDING;
+ BT_INFO("SSR state is : %x", ssr_state);
+ }
/* Open the SMD Channel and device and register the callback function */
rc = smd_named_open_on_edge(EVENT_CHANNEL, SMD_APPS_WCNSS,
&hsmd->event_channel, hdev, hci_smd_notify_event);
@@ -478,21 +534,25 @@
static void hci_smd_deregister_dev(struct hci_smd_data *hsmd)
{
tasklet_kill(&hs.rx_task);
-
+ if (ssr_state)
+ BT_DBG("SSR state is : %x", ssr_state);
+ /* Though the hci_smd driver is not registered with the hci
+ * need to close the opened channels as a part of cleaup
+ */
if (!test_and_clear_bit(HCI_REGISTER_SET, &hsmd->flags)) {
BT_ERR("HCI device un-registered already");
- return;
- } else
+ } else {
BT_INFO("HCI device un-registration going on");
- if (hsmd->hdev) {
- if (hci_unregister_dev(hsmd->hdev) < 0)
- BT_ERR("Can't unregister HCI device %s",
- hsmd->hdev->name);
- hci_free_dev(hsmd->hdev);
- hsmd->hdev = NULL;
+ if (hsmd->hdev) {
+ if (hci_unregister_dev(hsmd->hdev) < 0)
+ BT_ERR("Can't unregister HCI device %s",
+ hsmd->hdev->name);
+
+ hci_free_dev(hsmd->hdev);
+ hsmd->hdev = NULL;
+ }
}
-
smd_close(hs.event_channel);
smd_close(hs.data_channel);
@@ -513,23 +573,47 @@
{
down(&hci_smd_enable);
restart_in_progress = 1;
+ BT_DBG("SSR state is : %x", ssr_state);
+
+ if (ssr_state == STATE_SSR_ON) {
+ ssr_state = STATE_SSR_START;
+ BT_INFO("SSR state is : %x", ssr_state);
+ } else {
+ BT_ERR("restart triggered in wrong context");
+ up(&hci_smd_enable);
+ kfree(worker);
+ return;
+ }
hci_smd_deregister_dev(&hs);
hci_smd_register_smd(&hs);
up(&hci_smd_enable);
kfree(worker);
+
}
static void hci_dev_smd_open(struct work_struct *worker)
{
down(&hci_smd_enable);
+ if (ssr_state)
+ BT_DBG("SSR state is : %x", ssr_state);
+
+ if ((ssr_state != STATE_SSR_OFF) &&
+ (ssr_state != (STATE_SSR_PENDING_INIT))) {
+ up(&hci_smd_enable);
+ kfree(worker);
+ return;
+ }
+
if (restart_in_progress == 1) {
/* Allow wcnss to initialize */
restart_in_progress = 0;
msleep(10000);
}
+
hci_smd_hci_register_dev(&hs);
up(&hci_smd_enable);
kfree(worker);
+
}
static int hcismd_set_enable(const char *val, struct kernel_param *kp)
@@ -545,14 +629,23 @@
if (ret)
goto done;
+ /* Ignore the all incomming register de-register requests in case of
+ * SSR is in-progress
+ */
switch (hcismd_set) {
case 1:
- if (hs.hdev == NULL)
+ if ((hs.hdev == NULL) && (ssr_state == STATE_SSR_OFF))
hci_smd_register_smd(&hs);
+ else if (ssr_state)
+ BT_ERR("SSR is in progress,state is : %x", ssr_state);
+
break;
case 0:
- hci_smd_deregister_dev(&hs);
+ if (ssr_state == STATE_SSR_OFF)
+ hci_smd_deregister_dev(&hs);
+ else if (ssr_state)
+ BT_ERR("SSR is in progress,state is : %x", ssr_state);
break;
default:
ret = -EFAULT;
@@ -569,6 +662,7 @@
wake_lock_init(&hs.wake_lock_tx, WAKE_LOCK_SUSPEND,
"msm_smd_Tx");
restart_in_progress = 0;
+ ssr_state = STATE_SSR_OFF;
hs.hdev = NULL;
return 0;
}
diff --git a/drivers/char/diag/diag_masks.c b/drivers/char/diag/diag_masks.c
index 2a85a00..e8567db 100644
--- a/drivers/char/diag/diag_masks.c
+++ b/drivers/char/diag/diag_masks.c
@@ -26,6 +26,9 @@
#define ALL_SSID -1
#define MAX_SSID_PER_RANGE 100
+#define FEATURE_MASK_LEN_BYTES 1
+#define APPS_RESPOND_LOG_ON_DEMAND 0x04
+
struct mask_info {
int equip_id;
int num_items;
@@ -309,6 +312,7 @@
smd_info->peripheral);
diag_send_log_mask_update(smd_info->ch, ALL_EQUIP_ID);
diag_send_event_mask_update(smd_info->ch, diag_event_num_bytes);
+ diag_send_feature_mask_update(smd_info->ch, smd_info->peripheral);
smd_info->notify_context = 0;
}
@@ -461,6 +465,42 @@
mutex_unlock(&driver->diag_cntl_mutex);
}
+void diag_send_feature_mask_update(smd_channel_t *ch, int proc)
+{
+ void *buf = driver->buf_feature_mask_update;
+ int header_size = sizeof(struct diag_ctrl_feature_mask);
+ int wr_size = -ENOMEM, retry_count = 0, timer;
+ uint8_t feature_byte = 0;
+
+ mutex_lock(&driver->diag_cntl_mutex);
+ /* send feature mask update */
+ driver->feature_mask->ctrl_pkt_id = DIAG_CTRL_MSG_FEATURE;
+ driver->feature_mask->ctrl_pkt_data_len = 4 + FEATURE_MASK_LEN_BYTES;
+ driver->feature_mask->feature_mask_len = FEATURE_MASK_LEN_BYTES;
+ memcpy(buf, driver->feature_mask, header_size);
+ feature_byte |= APPS_RESPOND_LOG_ON_DEMAND;
+ memcpy(buf+header_size, &feature_byte, FEATURE_MASK_LEN_BYTES);
+
+ if (ch) {
+ while (retry_count < 3) {
+ wr_size = smd_write(ch, buf, header_size +
+ FEATURE_MASK_LEN_BYTES);
+ if (wr_size == -ENOMEM) {
+ retry_count++;
+ for (timer = 0; timer < 5; timer++)
+ udelay(2000);
+ } else
+ break;
+ }
+ if (wr_size != header_size + FEATURE_MASK_LEN_BYTES)
+ pr_err("diag: proc %d fail feature update %d, tried %d",
+ proc, wr_size, header_size + FEATURE_MASK_LEN_BYTES);
+ } else
+ pr_err("diag: ch invalid, feature update on proc %d\n", proc);
+ mutex_unlock(&driver->diag_cntl_mutex);
+
+}
+
int diag_process_apps_masks(unsigned char *buf, int len)
{
int packet_type = 1;
@@ -671,6 +711,16 @@
return 0;
}
#endif
+ } else if (*buf == 0x78) {
+ if (!(driver->smd_cntl[MODEM_DATA].ch) ||
+ (driver->log_on_demand_support)) {
+ driver->apps_rsp_buf[0] = 0x78;
+ /* Copy log code received */
+ *(uint16_t *)(driver->apps_rsp_buf+1) =
+ *(uint16_t *)buf;
+ driver->apps_rsp_buf[3] = 0x1;/* Unknown */
+ encode_rsp_and_send(3);
+ }
}
return packet_type;
@@ -727,6 +777,21 @@
goto err;
kmemleak_not_leak(driver->msg_masks);
}
+ if (driver->buf_feature_mask_update == NULL) {
+ driver->buf_feature_mask_update = kzalloc(sizeof(
+ struct diag_ctrl_feature_mask) +
+ FEATURE_MASK_LEN_BYTES, GFP_KERNEL);
+ if (driver->buf_feature_mask_update == NULL)
+ goto err;
+ kmemleak_not_leak(driver->buf_feature_mask_update);
+ }
+ if (driver->feature_mask == NULL) {
+ driver->feature_mask = kzalloc(sizeof(
+ struct diag_ctrl_feature_mask), GFP_KERNEL);
+ if (driver->feature_mask == NULL)
+ goto err;
+ kmemleak_not_leak(driver->feature_mask);
+ }
diag_create_msg_mask_table();
diag_event_num_bytes = 0;
if (driver->log_masks == NULL) {
@@ -751,6 +816,8 @@
kfree(driver->msg_masks);
kfree(driver->log_masks);
kfree(driver->event_masks);
+ kfree(driver->feature_mask);
+ kfree(driver->buf_feature_mask_update);
}
void diag_masks_exit(void)
@@ -761,4 +828,6 @@
kfree(driver->msg_masks);
kfree(driver->log_masks);
kfree(driver->event_masks);
+ kfree(driver->feature_mask);
+ kfree(driver->buf_feature_mask_update);
}
diff --git a/drivers/char/diag/diag_masks.h b/drivers/char/diag/diag_masks.h
index f144774..53f72e8 100644
--- a/drivers/char/diag/diag_masks.h
+++ b/drivers/char/diag/diag_masks.h
@@ -21,6 +21,7 @@
int ssid_last, int proc);
void diag_send_log_mask_update(smd_channel_t *, int);
void diag_mask_update_fn(struct work_struct *work);
+void diag_send_feature_mask_update(smd_channel_t *ch, int proc);
int diag_process_apps_masks(unsigned char *buf, int len);
void diag_masks_init(void);
void diag_masks_exit(void);
diff --git a/drivers/char/diag/diagchar.h b/drivers/char/diag/diagchar.h
index 8c46a5d..0b395c5 100644
--- a/drivers/char/diag/diagchar.h
+++ b/drivers/char/diag/diagchar.h
@@ -231,6 +231,7 @@
struct diag_ctrl_event_mask *event_mask;
struct diag_ctrl_log_mask *log_mask;
struct diag_ctrl_msg_mask *msg_mask;
+ struct diag_ctrl_feature_mask *feature_mask;
/* State for diag forwarding */
struct diag_smd_info smd_data[NUM_SMD_DATA_CHANNELS];
struct diag_smd_info smd_cntl[NUM_SMD_CONTROL_CHANNELS];
@@ -242,6 +243,7 @@
unsigned char *buf_msg_mask_update;
unsigned char *buf_log_mask_update;
unsigned char *buf_event_mask_update;
+ unsigned char *buf_feature_mask_update;
int read_len_legacy;
unsigned char *hdlc_buf;
unsigned hdlc_count;
@@ -259,6 +261,7 @@
uint8_t *log_masks;
int log_masks_length;
uint8_t *event_masks;
+ uint8_t log_on_demand_support;
struct diag_master_table *table;
uint8_t *pkt_buf;
int pkt_length;
diff --git a/drivers/char/diag/diagfwd_cntl.c b/drivers/char/diag/diagfwd_cntl.c
index a900d97..acac2fb 100644
--- a/drivers/char/diag/diagfwd_cntl.c
+++ b/drivers/char/diag/diagfwd_cntl.c
@@ -44,6 +44,7 @@
int total_recd)
{
int data_len = 0, type = -1, count_bytes = 0, j, flag = 0;
+ int feature_mask_len;
struct bindpkt_params_per_process *pkt_params =
kzalloc(sizeof(struct bindpkt_params_per_process), GFP_KERNEL);
struct diag_ctrl_msg *msg;
@@ -115,6 +116,11 @@
pr_err("diag: drop reg proc %d\n",
smd_info->peripheral);
kfree(temp);
+ } else if ((type == DIAG_CTRL_MSG_FEATURE) &&
+ (smd_info->peripheral == MODEM_DATA)) {
+ feature_mask_len = *(int *)(buf + 8);
+ driver->log_on_demand_support = (*(uint8_t *)
+ (buf + 12)) & 0x04;
} else if (type != DIAG_CTRL_MSG_REG) {
flag = 1;
}
@@ -209,6 +215,7 @@
reg_dirty = 0;
driver->polling_reg_flag = 0;
+ driver->log_on_demand_support = 1;
driver->diag_cntl_wq = create_singlethread_workqueue("diag_cntl_wq");
success = diag_smd_constructor(&driver->smd_cntl[MODEM_DATA],
diff --git a/drivers/char/diag/diagfwd_cntl.h b/drivers/char/diag/diagfwd_cntl.h
index aeb4ba1..8d262c4 100644
--- a/drivers/char/diag/diagfwd_cntl.h
+++ b/drivers/char/diag/diagfwd_cntl.h
@@ -77,6 +77,13 @@
/* Copy msg mask here */
} __packed;
+struct diag_ctrl_feature_mask {
+ uint32_t ctrl_pkt_id;
+ uint32_t ctrl_pkt_data_len;
+ uint32_t feature_mask_len;
+ /* Copy feature mask here */
+} __packed;
+
void diagfwd_cntl_init(void);
void diagfwd_cntl_exit(void);
void diag_read_smd_cntl_work_fn(struct work_struct *);
diff --git a/drivers/hwmon/qpnp-adc-common.c b/drivers/hwmon/qpnp-adc-common.c
index 440dc42..bde18d4 100644
--- a/drivers/hwmon/qpnp-adc-common.c
+++ b/drivers/hwmon/qpnp-adc-common.c
@@ -130,175 +130,6 @@
{790, 203}
};
-static const struct qpnp_vadc_map_pt adcmap_ntcg_104ef_104fb[] = {
- {696483, -40960},
- {649148, -39936},
- {605368, -38912},
- {564809, -37888},
- {527215, -36864},
- {492322, -35840},
- {460007, -34816},
- {429982, -33792},
- {402099, -32768},
- {376192, -31744},
- {352075, -30720},
- {329714, -29696},
- {308876, -28672},
- {289480, -27648},
- {271417, -26624},
- {254574, -25600},
- {238903, -24576},
- {224276, -23552},
- {210631, -22528},
- {197896, -21504},
- {186007, -20480},
- {174899, -19456},
- {164521, -18432},
- {154818, -17408},
- {145744, -16384},
- {137265, -15360},
- {129307, -14336},
- {121866, -13312},
- {114896, -12288},
- {108365, -11264},
- {102252, -10240},
- {96499, -9216},
- {91111, -8192},
- {86055, -7168},
- {81308, -6144},
- {76857, -5120},
- {72660, -4096},
- {68722, -3072},
- {65020, -2048},
- {61538, -1024},
- {58261, 0},
- {55177, 1024},
- {52274, 2048},
- {49538, 3072},
- {46962, 4096},
- {44531, 5120},
- {42243, 6144},
- {40083, 7168},
- {38045, 8192},
- {36122, 9216},
- {34308, 10240},
- {32592, 11264},
- {30972, 12288},
- {29442, 13312},
- {27995, 14336},
- {26624, 15360},
- {25333, 16384},
- {24109, 17408},
- {22951, 18432},
- {21854, 19456},
- {20807, 20480},
- {19831, 21504},
- {18899, 22528},
- {18016, 23552},
- {17178, 24576},
- {16384, 25600},
- {15631, 26624},
- {14916, 27648},
- {14237, 28672},
- {13593, 29696},
- {12976, 30720},
- {12400, 31744},
- {11848, 32768},
- {11324, 33792},
- {10825, 34816},
- {10354, 35840},
- {9900, 36864},
- {9471, 37888},
- {9062, 38912},
- {8674, 39936},
- {8306, 40960},
- {7951, 41984},
- {7616, 43008},
- {7296, 44032},
- {6991, 45056},
- {6701, 46080},
- {6424, 47104},
- {6160, 48128},
- {5908, 49152},
- {5667, 50176},
- {5439, 51200},
- {5219, 52224},
- {5010, 53248},
- {4810, 54272},
- {4619, 55296},
- {4440, 56320},
- {4263, 57344},
- {4097, 58368},
- {3938, 59392},
- {3785, 60416},
- {3637, 61440},
- {3501, 62464},
- {3368, 63488},
- {3240, 64512},
- {3118, 65536},
- {2998, 66560},
- {2889, 67584},
- {2782, 68608},
- {2680, 69632},
- {2581, 70656},
- {2490, 71680},
- {2397, 72704},
- {2310, 73728},
- {2227, 74752},
- {2147, 75776},
- {2064, 76800},
- {1998, 77824},
- {1927, 78848},
- {1860, 79872},
- {1795, 80896},
- {1736, 81920},
- {1673, 82944},
- {1615, 83968},
- {1560, 84992},
- {1507, 86016},
- {1456, 87040},
- {1407, 88064},
- {1360, 89088},
- {1314, 90112},
- {1271, 91136},
- {1228, 92160},
- {1189, 93184},
- {1150, 94208},
- {1112, 95232},
- {1076, 96256},
- {1042, 97280},
- {1008, 98304},
- {976, 99328},
- {945, 100352},
- {915, 101376},
- {886, 102400},
- {859, 103424},
- {832, 104448},
- {807, 105472},
- {782, 106496},
- {756, 107520},
- {735, 108544},
- {712, 109568},
- {691, 110592},
- {670, 111616},
- {650, 112640},
- {631, 113664},
- {612, 114688},
- {594, 115712},
- {577, 116736},
- {560, 117760},
- {544, 118784},
- {528, 119808},
- {513, 120832},
- {498, 121856},
- {483, 122880},
- {470, 123904},
- {457, 124928},
- {444, 125952},
- {431, 126976},
- {419, 128000}
-};
-
/* Voltage to temperature */
static const struct qpnp_vadc_map_pt adcmap_100k_104ef_104fb[] = {
{1758, -40},
@@ -553,9 +384,9 @@
xo_thm = qpnp_adc_scale_ratiometric_calib(adc_code,
adc_properties, chan_properties);
- xo_thm <<= 4;
- qpnp_adc_map_voltage_temp(adcmap_ntcg_104ef_104fb,
- ARRAY_SIZE(adcmap_ntcg_104ef_104fb),
+
+ qpnp_adc_map_voltage_temp(adcmap_100k_104ef_104fb,
+ ARRAY_SIZE(adcmap_100k_104ef_104fb),
xo_thm, &adc_chan_result->physical);
return 0;
diff --git a/drivers/hwmon/qpnp-adc-current.c b/drivers/hwmon/qpnp-adc-current.c
index 0290335..c28c61d 100644
--- a/drivers/hwmon/qpnp-adc-current.c
+++ b/drivers/hwmon/qpnp-adc-current.c
@@ -789,7 +789,7 @@
return 0;
fail:
- adc_qpnp = NULL;
+ qpnp_iadc = NULL;
return rc;
}
diff --git a/drivers/media/dvb/mpq/demux/mpq_dmx_plugin_common.c b/drivers/media/dvb/mpq/demux/mpq_dmx_plugin_common.c
index 1587068..4b67477 100644
--- a/drivers/media/dvb/mpq/demux/mpq_dmx_plugin_common.c
+++ b/drivers/media/dvb/mpq/demux/mpq_dmx_plugin_common.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -39,10 +39,14 @@
static int mpq_demux_device_num = CONFIG_DVB_MPQ_NUM_DMX_DEVICES;
module_param(mpq_demux_device_num, int, S_IRUGO);
-/* ION heap ID to be used when calling ion_alloc for video decoder buffer */
-static int video_ion_alloc_heap = ION_CP_MM_HEAP_ID;
-module_param(video_ion_alloc_heap, int, S_IRUGO | S_IWUSR);
-MODULE_PARM_DESC(video_ion_alloc_heap, "ION heap ID for allocation");
+/* ION heap IDs used for allocating video output buffer */
+static int video_secure_ion_heap = ION_CP_MM_HEAP_ID;
+module_param(video_secure_ion_heap , int, S_IRUGO | S_IWUSR);
+MODULE_PARM_DESC(video_secure_ion_heap, "ION heap for secure video buffer allocation");
+
+static int video_nonsecure_ion_heap = ION_IOMMU_HEAP_ID;
+module_param(video_nonsecure_ion_heap, int, S_IRUGO | S_IWUSR);
+MODULE_PARM_DESC(video_nonsecure_ion_heap, "ION heap for non-secure video buffer allocation");
static int generate_es_events;
module_param(generate_es_events, int, S_IRUGO | S_IWUSR);
@@ -484,7 +488,6 @@
mpq_demux->hw_notification_count = 0;
mpq_demux->hw_notification_interval = 0;
mpq_demux->hw_notification_size = 0;
- mpq_demux->decoder_drop_count = 0;
mpq_demux->hw_notification_min_size = 0xFFFFFFFF;
if (mpq_demux->demux.dmx.debugfs_demux_dir != NULL) {
@@ -547,6 +550,12 @@
S_IRUGO|S_IWUGO,
mpq_demux->demux.dmx.debugfs_demux_dir,
&mpq_demux->decoder_out_interval_max);
+
+ debugfs_create_u32(
+ "decoder_ts_errors",
+ S_IRUGO|S_IWUGO,
+ mpq_demux->demux.dmx.debugfs_demux_dir,
+ &mpq_demux->decoder_ts_errors);
}
}
EXPORT_SYMBOL(mpq_dmx_init_hw_statistics);
@@ -1033,7 +1042,9 @@
actual_buffer_size &= ~(SZ_4K - 1);
temp_handle = ion_alloc(client, actual_buffer_size, SZ_4K,
- ION_HEAP(video_ion_alloc_heap), ION_FLAG_CACHED);
+ ION_HEAP(video_secure_ion_heap) |
+ ION_HEAP(video_nonsecure_ion_heap),
+ ION_FLAG_CACHED);
if (IS_ERR_OR_NULL(temp_handle)) {
ret = PTR_ERR(temp_handle);
@@ -1425,6 +1436,12 @@
feed_data->ts_dropped_bytes = 0;
feed_data->last_pkt_index = -1;
+ mpq_demux->decoder_drop_count = 0;
+ mpq_demux->decoder_out_count = 0;
+ mpq_demux->decoder_out_interval_sum = 0;
+ mpq_demux->decoder_out_interval_max = 0;
+ mpq_demux->decoder_ts_errors = 0;
+
spin_lock(&mpq_demux->feed_lock);
feed->priv = (void *)feed_data;
spin_unlock(&mpq_demux->feed_lock);
@@ -2115,6 +2132,7 @@
/* Update error counters based on TS header */
feed_data->ts_packets_num++;
feed_data->tei_errs += ts_header->transport_error_indicator;
+ mpq_demux->decoder_ts_errors += ts_header->transport_error_indicator;
mpq_dmx_check_continuity(feed_data,
ts_header->continuity_counter,
discontinuity_indicator);
@@ -2496,6 +2514,7 @@
/* Update error counters based on TS header */
feed_data->ts_packets_num++;
feed_data->tei_errs += ts_header->transport_error_indicator;
+ mpq_demux->decoder_ts_errors += ts_header->transport_error_indicator;
mpq_dmx_check_continuity(feed_data,
ts_header->continuity_counter,
discontinuity_indicator);
@@ -2601,29 +2620,14 @@
const struct ts_packet_header *ts_header;
const struct ts_adaptation_field *adaptation_field;
- /*
- * When we play from front-end, we configure HW
- * to output the extra timestamp, if we are playing
- * from DVR, make sure the format is 192 packet.
- */
- if ((mpq_demux->source >= DMX_SOURCE_DVR0) &&
- (mpq_demux->demux.tsp_format != DMX_TSP_FORMAT_192_TAIL)) {
- MPQ_DVB_ERR_PRINT(
- "%s: invalid packet format %d for PCR extraction\n",
- __func__,
- mpq_demux->demux.tsp_format);
-
- return -EINVAL;
- }
-
ts_header = (const struct ts_packet_header *)buf;
/* Make sure this TS packet has a adaptation field */
if ((ts_header->sync_byte != 0x47) ||
(ts_header->adaptation_field_control == 0) ||
- (ts_header->adaptation_field_control == 1)) {
+ (ts_header->adaptation_field_control == 1) ||
+ ts_header->transport_error_indicator)
return 0;
- }
adaptation_field = (const struct ts_adaptation_field *)
(buf + sizeof(struct ts_packet_header));
@@ -2642,10 +2646,21 @@
(((u64)adaptation_field->program_clock_reference_ext_1) << 8) +
adaptation_field->program_clock_reference_ext_2;
- stc = buf[190] << 16;
- stc += buf[189] << 8;
- stc += buf[188];
- stc *= 256; /* convert from 105.47 KHZ to 27MHz */
+ /*
+ * When we play from front-end, we configure HW
+ * to output the extra timestamp, if we are playing
+ * from DVR, we don't have a timestamp if the packet
+ * format is not 192-tail.
+ */
+ if ((mpq_demux->source >= DMX_SOURCE_DVR0) &&
+ (mpq_demux->demux.tsp_format != DMX_TSP_FORMAT_192_TAIL)) {
+ stc = 0;
+ } else {
+ stc = buf[190] << 16;
+ stc += buf[189] << 8;
+ stc += buf[188];
+ stc *= 256; /* convert from 105.47 KHZ to 27MHz */
+ }
data.data_length = 0;
data.pcr.pcr = pcr;
diff --git a/drivers/media/dvb/mpq/demux/mpq_dmx_plugin_common.h b/drivers/media/dvb/mpq/demux/mpq_dmx_plugin_common.h
index 2cb0a92..c0d5412 100644
--- a/drivers/media/dvb/mpq/demux/mpq_dmx_plugin_common.h
+++ b/drivers/media/dvb/mpq/demux/mpq_dmx_plugin_common.h
@@ -62,6 +62,8 @@
* successive video frames output, exposed in debugfs.
* @decoder_out_interval_max: Max interval (msec) between two
* successive video frames output, exposed in debugfs.
+ * @decoder_ts_errors: Counter for number of decoder packets with TEI bit
+ * set, exposed in debugfs.
* @decoder_out_last_time: Time of last video frame output.
* @last_notification_time: Time of last HW notification.
*/
@@ -85,6 +87,7 @@
u32 decoder_out_interval_sum;
u32 decoder_out_interval_average;
u32 decoder_out_interval_max;
+ u32 decoder_ts_errors;
struct timespec decoder_out_last_time;
struct timespec last_notification_time;
};
diff --git a/drivers/media/video/msm/server/msm_cam_server.c b/drivers/media/video/msm/server/msm_cam_server.c
index af31748..78d15d9 100644
--- a/drivers/media/video/msm/server/msm_cam_server.c
+++ b/drivers/media/video/msm/server/msm_cam_server.c
@@ -1081,8 +1081,34 @@
struct v4l2_event_subscription *sub)
{
int rc = 0;
+ struct v4l2_event ev;
D("%s: fh = 0x%x\n", __func__, (u32)fh);
+
+ /* Undequeue all pending events and free associated
+ * msm_isp_event_ctrl */
+ while (v4l2_event_pending(fh)) {
+ struct msm_isp_event_ctrl *isp_event;
+ rc = v4l2_event_dequeue(fh, &ev, O_NONBLOCK);
+ if (rc) {
+ pr_err("%s: v4l2_event_dequeue failed %d",
+ __func__, rc);
+ break;
+ }
+ isp_event = (struct msm_isp_event_ctrl *)
+ (*((uint32_t *)ev.u.data));
+ if (isp_event) {
+ if (isp_event->isp_data.isp_msg.len != 0 &&
+ isp_event->isp_data.isp_msg.data != NULL) {
+ kfree(isp_event->isp_data.isp_msg.data);
+ isp_event->isp_data.isp_msg.len = 0;
+ isp_event->isp_data.isp_msg.data = NULL;
+ }
+ kfree(isp_event);
+ *((uint32_t *)ev.u.data) = 0;
+ }
+ }
+
rc = v4l2_event_unsubscribe(fh, sub);
D("%s: rc = %d\n", __func__, rc);
return rc;
@@ -1452,7 +1478,7 @@
}
}
sub.type = V4L2_EVENT_ALL;
- msm_server_v4l2_unsubscribe_event(
+ v4l2_event_unsubscribe(
&g_server_dev.server_command_queue.eventHandle, &sub);
mutex_unlock(&g_server_dev.server_lock);
}
@@ -1645,7 +1671,7 @@
static const struct v4l2_ioctl_ops msm_ioctl_ops_server = {
.vidioc_subscribe_event = msm_server_v4l2_subscribe_event,
- .vidioc_unsubscribe_event = msm_server_v4l2_unsubscribe_event,
+ .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
.vidioc_default = msm_ioctl_server,
};
@@ -3103,9 +3129,7 @@
static int msm_close_config(struct inode *node, struct file *f)
{
- struct v4l2_event ev;
struct v4l2_event_subscription sub;
- struct msm_isp_event_ctrl *isp_event;
struct msm_cam_config_dev *config_cam = f->private_data;
#ifdef CONFIG_MSM_MULTIMEDIA_USE_ION
@@ -3116,20 +3140,6 @@
msm_server_v4l2_unsubscribe_event(
&config_cam->config_stat_event_queue.eventHandle,
&sub);
- while (v4l2_event_pending(
- &config_cam->config_stat_event_queue.eventHandle)) {
- v4l2_event_dequeue(
- &config_cam->config_stat_event_queue.eventHandle,
- &ev, O_NONBLOCK);
- isp_event = (struct msm_isp_event_ctrl *)
- (*((uint32_t *)ev.u.data));
- if (isp_event) {
- if (isp_event->isp_data.isp_msg.len != 0 &&
- isp_event->isp_data.isp_msg.data != NULL)
- kfree(isp_event->isp_data.isp_msg.data);
- kfree(isp_event);
- }
- }
return 0;
}
diff --git a/drivers/media/video/msm_vidc/hfi_response_handler.c b/drivers/media/video/msm_vidc/hfi_response_handler.c
index 37605f9..50970cb 100644
--- a/drivers/media/video/msm_vidc/hfi_response_handler.c
+++ b/drivers/media/video/msm_vidc/hfi_response_handler.c
@@ -18,7 +18,7 @@
#include "vidc_hfi_io.h"
#include "msm_vidc_debug.h"
-static enum vidc_status vidc_map_hal_err_status(int hfi_err)
+static enum vidc_status hfi_map_err_status(int hfi_err)
{
enum vidc_status vidc_err;
switch (hfi_err) {
@@ -75,7 +75,7 @@
return vidc_err;
}
-void hal_process_sess_evt_seq_changed(struct hal_device *device,
+static void hfi_process_sess_evt_seq_changed(struct venus_hfi_device *device,
struct hfi_msg_event_notify_packet *pkt)
{
struct msm_vidc_cb_cmd_done cmd_done;
@@ -138,7 +138,7 @@
cmd_done.data = &event_notify;
device->callback(VIDC_EVENT_CHANGE, &cmd_done);
}
-static void hal_process_sys_watchdog_timeout(struct hal_device *device)
+static void hfi_process_sys_watchdog_timeout(struct venus_hfi_device *device)
{
struct msm_vidc_cb_cmd_done cmd_done;
device->intr_status &= ~VIDC_WRAPPER_INTR_STATUS_A2HWD_BMSK;
@@ -146,14 +146,14 @@
cmd_done.device_id = device->device_id;
device->callback(SYS_WATCHDOG_TIMEOUT, &cmd_done);
}
-static void hal_process_sys_error(struct hal_device *device)
+static void hfi_process_sys_error(struct venus_hfi_device *device)
{
struct msm_vidc_cb_cmd_done cmd_done;
memset(&cmd_done, 0, sizeof(struct msm_vidc_cb_cmd_done));
cmd_done.device_id = device->device_id;
device->callback(SYS_ERROR, &cmd_done);
}
-static void hal_process_session_error(struct hal_device *device,
+static void hfi_process_session_error(struct venus_hfi_device *device,
struct hfi_msg_event_notify_packet *pkt)
{
struct msm_vidc_cb_cmd_done cmd_done;
@@ -163,7 +163,7 @@
session_id;
device->callback(SESSION_ERROR, &cmd_done);
}
-static void hal_process_event_notify(struct hal_device *device,
+static void hfi_process_event_notify(struct venus_hfi_device *device,
struct hfi_msg_event_notify_packet *pkt)
{
dprintk(VIDC_DBG, "RECVD:EVENT_NOTIFY");
@@ -178,15 +178,15 @@
case HFI_EVENT_SYS_ERROR:
dprintk(VIDC_ERR, "HFI_EVENT_SYS_ERROR: %d\n",
pkt->event_data1);
- hal_process_sys_error(device);
+ hfi_process_sys_error(device);
break;
case HFI_EVENT_SESSION_ERROR:
dprintk(VIDC_ERR, "HFI_EVENT_SESSION_ERROR");
- hal_process_session_error(device, pkt);
+ hfi_process_session_error(device, pkt);
break;
case HFI_EVENT_SESSION_SEQUENCE_CHANGED:
dprintk(VIDC_INFO, "HFI_EVENT_SESSION_SEQUENCE_CHANGED");
- hal_process_sess_evt_seq_changed(device, pkt);
+ hfi_process_sess_evt_seq_changed(device, pkt);
break;
case HFI_EVENT_SESSION_PROPERTY_CHANGED:
dprintk(VIDC_INFO, "HFI_EVENT_SESSION_PROPERTY_CHANGED");
@@ -196,7 +196,7 @@
break;
}
}
-static void hal_process_sys_init_done(struct hal_device *device,
+static void hfi_process_sys_init_done(struct venus_hfi_device *device,
struct hfi_msg_sys_init_done_packet *pkt)
{
struct msm_vidc_cb_cmd_done cmd_done;
@@ -213,7 +213,7 @@
return;
}
- status = vidc_map_hal_err_status((u32)pkt->error_type);
+ status = hfi_map_err_status((u32)pkt->error_type);
if (!status) {
if (pkt->num_properties == 0) {
@@ -281,7 +281,7 @@
device->callback(SYS_INIT_DONE, &cmd_done);
}
-static void hal_process_sys_rel_resource_done(struct hal_device *device,
+static void hfi_process_sys_rel_resource_done(struct venus_hfi_device *device,
struct hfi_msg_sys_release_resource_done_packet *pkt)
{
struct msm_vidc_cb_cmd_done cmd_done;
@@ -296,7 +296,7 @@
pkt->size);
return;
}
- status = vidc_map_hal_err_status((u32)pkt->error_type);
+ status = hfi_map_err_status((u32)pkt->error_type);
cmd_done.device_id = device->device_id;
cmd_done.session_id = 0;
cmd_done.status = (u32) status;
@@ -305,14 +305,14 @@
device->callback(RELEASE_RESOURCE_DONE, &cmd_done);
}
-enum vidc_status vidc_hal_process_sess_init_done_prop_read(
+enum vidc_status hfi_process_sess_init_done_prop_read(
struct hfi_msg_sys_session_init_done_packet *pkt,
struct msm_vidc_cb_cmd_done *cmddone)
{
return VIDC_ERR_NONE;
}
-static void hal_process_sess_get_prop_buf_req(
+static void hfi_process_sess_get_prop_buf_req(
struct hfi_msg_session_property_info_packet *prop,
struct buffer_requirements *buffreq)
{
@@ -408,7 +408,7 @@
}
}
-static void hal_process_session_prop_info(struct hal_device *device,
+static void hfi_process_session_prop_info(struct venus_hfi_device *device,
struct hfi_msg_session_property_info_packet *pkt)
{
struct msm_vidc_cb_cmd_done cmd_done;
@@ -432,7 +432,7 @@
switch (pkt->rg_property_data[0]) {
case HFI_PROPERTY_CONFIG_BUFFER_REQUIREMENTS:
- hal_process_sess_get_prop_buf_req(pkt, &buff_req);
+ hfi_process_sess_get_prop_buf_req(pkt, &buff_req);
cmd_done.device_id = device->device_id;
cmd_done.session_id =
((struct hal_session *) pkt->session_id)->session_id;
@@ -449,7 +449,7 @@
}
}
-static void hal_process_session_init_done(struct hal_device *device,
+static void hfi_process_session_init_done(struct venus_hfi_device *device,
struct hfi_msg_sys_session_init_done_packet *pkt)
{
struct msm_vidc_cb_cmd_done cmd_done;
@@ -469,17 +469,17 @@
cmd_done.device_id = device->device_id;
cmd_done.session_id =
((struct hal_session *) pkt->session_id)->session_id;
- cmd_done.status = vidc_map_hal_err_status((u32)pkt->error_type);
+ cmd_done.status = hfi_map_err_status((u32)pkt->error_type);
cmd_done.data = &session_init_done;
if (!cmd_done.status) {
- cmd_done.status = vidc_hal_process_sess_init_done_prop_read(
+ cmd_done.status = hfi_process_sess_init_done_prop_read(
pkt, &cmd_done);
}
cmd_done.size = sizeof(struct vidc_hal_session_init_done);
device->callback(SESSION_INIT_DONE, &cmd_done);
}
-static void hal_process_session_load_res_done(struct hal_device *device,
+static void hfi_process_session_load_res_done(struct venus_hfi_device *device,
struct hfi_msg_session_load_resources_done_packet *pkt)
{
struct msm_vidc_cb_cmd_done cmd_done;
@@ -497,13 +497,13 @@
cmd_done.device_id = device->device_id;
cmd_done.session_id =
((struct hal_session *) pkt->session_id)->session_id;
- cmd_done.status = vidc_map_hal_err_status((u32)pkt->error_type);
+ cmd_done.status = hfi_map_err_status((u32)pkt->error_type);
cmd_done.data = NULL;
cmd_done.size = 0;
device->callback(SESSION_LOAD_RESOURCE_DONE, &cmd_done);
}
-static void hal_process_session_flush_done(struct hal_device *device,
+static void hfi_process_session_flush_done(struct venus_hfi_device *device,
struct hfi_msg_session_flush_done_packet *pkt)
{
struct msm_vidc_cb_cmd_done cmd_done;
@@ -520,13 +520,13 @@
cmd_done.device_id = device->device_id;
cmd_done.session_id =
((struct hal_session *) pkt->session_id)->session_id;
- cmd_done.status = vidc_map_hal_err_status((u32)pkt->error_type);
+ cmd_done.status = hfi_map_err_status((u32)pkt->error_type);
cmd_done.data = (void *) pkt->flush_type;
cmd_done.size = sizeof(u32);
device->callback(SESSION_FLUSH_DONE, &cmd_done);
}
-static void hal_process_session_etb_done(struct hal_device *device,
+static void hfi_process_session_etb_done(struct venus_hfi_device *device,
struct hfi_msg_session_empty_buffer_done_packet *pkt)
{
struct msm_vidc_cb_data_done data_done;
@@ -544,7 +544,7 @@
data_done.device_id = device->device_id;
data_done.session_id =
((struct hal_session *) pkt->session_id)->session_id;
- data_done.status = vidc_map_hal_err_status((u32) pkt->error_type);
+ data_done.status = hfi_map_err_status((u32) pkt->error_type);
data_done.size = sizeof(struct msm_vidc_cb_data_done);
data_done.clnt_data = (void *)pkt->input_tag;
data_done.input_done.offset = pkt->offset;
@@ -553,7 +553,7 @@
device->callback(SESSION_ETB_DONE, &data_done);
}
-static void hal_process_session_ftb_done(struct hal_device *device,
+static void hfi_process_session_ftb_done(struct venus_hfi_device *device,
void *msg_hdr)
{
struct msm_vidc_cb_data_done data_done;
@@ -592,7 +592,7 @@
data_done.device_id = device->device_id;
data_done.session_id = (u32) session;
- data_done.status = vidc_map_hal_err_status((u32)
+ data_done.status = hfi_map_err_status((u32)
pkt->error_type);
data_done.size = sizeof(struct msm_vidc_cb_data_done);
data_done.clnt_data = (void *) pkt->input_tag;
@@ -626,7 +626,7 @@
data_done.device_id = device->device_id;
data_done.session_id = (u32) session;
- data_done.status = vidc_map_hal_err_status((u32)
+ data_done.status = hfi_map_err_status((u32)
pkt->error_type);
data_done.size = sizeof(struct msm_vidc_cb_data_done);
data_done.clnt_data = (void *)pkt->input_tag;
@@ -660,7 +660,7 @@
device->callback(SESSION_FTB_DONE, &data_done);
}
-static void hal_process_session_start_done(struct hal_device *device,
+static void hfi_process_session_start_done(struct venus_hfi_device *device,
struct hfi_msg_session_start_done_packet *pkt)
{
struct msm_vidc_cb_cmd_done cmd_done;
@@ -678,13 +678,13 @@
cmd_done.device_id = device->device_id;
cmd_done.session_id =
((struct hal_session *) pkt->session_id)->session_id;
- cmd_done.status = vidc_map_hal_err_status((u32)pkt->error_type);
+ cmd_done.status = hfi_map_err_status((u32)pkt->error_type);
cmd_done.data = NULL;
cmd_done.size = 0;
device->callback(SESSION_START_DONE, &cmd_done);
}
-static void hal_process_session_stop_done(struct hal_device *device,
+static void hfi_process_session_stop_done(struct venus_hfi_device *device,
struct hfi_msg_session_stop_done_packet *pkt)
{
struct msm_vidc_cb_cmd_done cmd_done;
@@ -702,13 +702,13 @@
cmd_done.device_id = device->device_id;
cmd_done.session_id =
((struct hal_session *) pkt->session_id)->session_id;
- cmd_done.status = vidc_map_hal_err_status((u32)pkt->error_type);
+ cmd_done.status = hfi_map_err_status((u32)pkt->error_type);
cmd_done.data = NULL;
cmd_done.size = 0;
device->callback(SESSION_STOP_DONE, &cmd_done);
}
-static void hal_process_session_rel_res_done(struct hal_device *device,
+static void hfi_process_session_rel_res_done(struct venus_hfi_device *device,
struct hfi_msg_session_release_resources_done_packet *pkt)
{
struct msm_vidc_cb_cmd_done cmd_done;
@@ -726,13 +726,13 @@
cmd_done.device_id = device->device_id;
cmd_done.session_id =
((struct hal_session *) pkt->session_id)->session_id;
- cmd_done.status = vidc_map_hal_err_status((u32)pkt->error_type);
+ cmd_done.status = hfi_map_err_status((u32)pkt->error_type);
cmd_done.data = NULL;
cmd_done.size = 0;
device->callback(SESSION_RELEASE_RESOURCE_DONE, &cmd_done);
}
-static void hal_process_session_rel_buf_done(struct hal_device *device,
+static void hfi_process_session_rel_buf_done(struct venus_hfi_device *device,
struct hfi_msg_session_release_buffers_done_packet *pkt)
{
struct msm_vidc_cb_cmd_done cmd_done;
@@ -747,7 +747,7 @@
cmd_done.size = sizeof(struct msm_vidc_cb_cmd_done);
cmd_done.session_id =
((struct hal_session *) pkt->session_id)->session_id;
- cmd_done.status = vidc_map_hal_err_status((u32)pkt->error_type);
+ cmd_done.status = hfi_map_err_status((u32)pkt->error_type);
if (pkt->rg_buffer_info) {
cmd_done.data = (void *) &pkt->rg_buffer_info;
cmd_done.size = sizeof(struct hfi_buffer_info);
@@ -757,7 +757,7 @@
device->callback(SESSION_RELEASE_BUFFER_DONE, &cmd_done);
}
-static void hal_process_session_end_done(struct hal_device *device,
+static void hfi_process_session_end_done(struct venus_hfi_device *device,
struct hfi_msg_sys_session_end_done_packet *pkt)
{
struct msm_vidc_cb_cmd_done cmd_done;
@@ -782,13 +782,14 @@
cmd_done.device_id = device->device_id;
cmd_done.session_id =
((struct hal_session *) pkt->session_id)->session_id;
- cmd_done.status = vidc_map_hal_err_status((u32)pkt->error_type);
+ cmd_done.status = hfi_map_err_status((u32)pkt->error_type);
cmd_done.data = NULL;
cmd_done.size = 0;
device->callback(SESSION_END_DONE, &cmd_done);
}
-static void hal_process_session_get_seq_hdr_done(struct hal_device *device,
+static void hfi_process_session_get_seq_hdr_done(
+ struct venus_hfi_device *device,
struct hfi_msg_session_get_sequence_header_done_packet *pkt)
{
struct msm_vidc_cb_data_done data_done;
@@ -803,7 +804,7 @@
data_done.size = sizeof(struct msm_vidc_cb_data_done);
data_done.session_id =
((struct hal_session *) pkt->session_id)->session_id;
- data_done.status = vidc_map_hal_err_status((u32)pkt->error_type);
+ data_done.status = hfi_map_err_status((u32)pkt->error_type);
data_done.output_done.packet_buffer1 = pkt->sequence_header;
data_done.output_done.filled_len1 = pkt->header_len;
dprintk(VIDC_INFO, "seq_hdr: %p, Length: %d",
@@ -811,7 +812,7 @@
device->callback(SESSION_GET_SEQ_HDR_DONE, &data_done);
}
-static void hal_process_msg_packet(struct hal_device *device,
+static void hfi_process_msg_packet(struct venus_hfi_device *device,
struct vidc_hal_msg_pkt_hdr *msg_hdr)
{
if (!device || !msg_hdr || msg_hdr->size <
@@ -824,80 +825,80 @@
dprintk(VIDC_INFO, "Received: 0x%x in ", msg_hdr->packet);
if ((device->intr_status & VIDC_WRAPPER_INTR_CLEAR_A2HWD_BMSK)) {
dprintk(VIDC_ERR, "Received: Watchdog timeout %s", __func__);
- hal_process_sys_watchdog_timeout(device);
+ hfi_process_sys_watchdog_timeout(device);
return;
}
switch (msg_hdr->packet) {
case HFI_MSG_EVENT_NOTIFY:
- hal_process_event_notify(device,
+ hfi_process_event_notify(device,
(struct hfi_msg_event_notify_packet *) msg_hdr);
break;
case HFI_MSG_SYS_INIT_DONE:
- hal_process_sys_init_done(device,
+ hfi_process_sys_init_done(device,
(struct hfi_msg_sys_init_done_packet *)
msg_hdr);
break;
case HFI_MSG_SYS_SESSION_INIT_DONE:
- hal_process_session_init_done(device,
+ hfi_process_session_init_done(device,
(struct hfi_msg_sys_session_init_done_packet *)
msg_hdr);
break;
case HFI_MSG_SYS_SESSION_END_DONE:
- hal_process_session_end_done(device,
+ hfi_process_session_end_done(device,
(struct hfi_msg_sys_session_end_done_packet *)
msg_hdr);
break;
case HFI_MSG_SESSION_LOAD_RESOURCES_DONE:
- hal_process_session_load_res_done(device,
+ hfi_process_session_load_res_done(device,
(struct hfi_msg_session_load_resources_done_packet *)
msg_hdr);
break;
case HFI_MSG_SESSION_START_DONE:
- hal_process_session_start_done(device,
+ hfi_process_session_start_done(device,
(struct hfi_msg_session_start_done_packet *)
msg_hdr);
break;
case HFI_MSG_SESSION_STOP_DONE:
- hal_process_session_stop_done(device,
+ hfi_process_session_stop_done(device,
(struct hfi_msg_session_stop_done_packet *)
msg_hdr);
break;
case HFI_MSG_SESSION_EMPTY_BUFFER_DONE:
- hal_process_session_etb_done(device,
+ hfi_process_session_etb_done(device,
(struct hfi_msg_session_empty_buffer_done_packet *)
msg_hdr);
break;
case HFI_MSG_SESSION_FILL_BUFFER_DONE:
- hal_process_session_ftb_done(device, msg_hdr);
+ hfi_process_session_ftb_done(device, msg_hdr);
break;
case HFI_MSG_SESSION_FLUSH_DONE:
- hal_process_session_flush_done(device,
+ hfi_process_session_flush_done(device,
(struct hfi_msg_session_flush_done_packet *)
msg_hdr);
break;
case HFI_MSG_SESSION_PROPERTY_INFO:
- hal_process_session_prop_info(device,
+ hfi_process_session_prop_info(device,
(struct hfi_msg_session_property_info_packet *)
msg_hdr);
break;
case HFI_MSG_SESSION_RELEASE_RESOURCES_DONE:
- hal_process_session_rel_res_done(device,
+ hfi_process_session_rel_res_done(device,
(struct hfi_msg_session_release_resources_done_packet *)
msg_hdr);
break;
case HFI_MSG_SYS_RELEASE_RESOURCE:
- hal_process_sys_rel_resource_done(device,
+ hfi_process_sys_rel_resource_done(device,
(struct hfi_msg_sys_release_resource_done_packet *)
msg_hdr);
break;
case HFI_MSG_SESSION_GET_SEQUENCE_HEADER_DONE:
- hal_process_session_get_seq_hdr_done(device, (struct
+ hfi_process_session_get_seq_hdr_done(device, (struct
hfi_msg_session_get_sequence_header_done_packet
*) msg_hdr);
break;
case HFI_MSG_SESSION_RELEASE_BUFFERS_DONE:
- hal_process_session_rel_buf_done(device, (struct
+ hfi_process_session_rel_buf_done(device, (struct
hfi_msg_session_release_buffers_done_packet
*) msg_hdr);
break;
@@ -907,17 +908,17 @@
}
}
-void vidc_hal_response_handler(struct hal_device *device)
+void hfi_response_handler(struct venus_hfi_device *device)
{
u8 packet[VIDC_IFACEQ_MED_PKT_SIZE];
dprintk(VIDC_INFO, "#####vidc_hal_response_handler#####\n");
if (device) {
- while (!vidc_hal_iface_msgq_read(device, packet)) {
- hal_process_msg_packet(device,
+ while (!venus_hfi_iface_msgq_read(device, packet)) {
+ hfi_process_msg_packet(device,
(struct vidc_hal_msg_pkt_hdr *) packet);
}
- while (!vidc_hal_iface_dbgq_read(device, packet)) {
+ while (!venus_hfi_iface_dbgq_read(device, packet)) {
struct hfi_msg_sys_debug_packet *pkt =
(struct hfi_msg_sys_debug_packet *) packet;
dprintk(VIDC_FW, "FW-SAYS: %s", pkt->rg_msg_data);
diff --git a/drivers/media/video/msm_vidc/msm_v4l2_vidc.c b/drivers/media/video/msm_vidc/msm_v4l2_vidc.c
index 36ee792..e51896c 100644
--- a/drivers/media/video/msm_vidc/msm_v4l2_vidc.c
+++ b/drivers/media/video/msm_vidc/msm_v4l2_vidc.c
@@ -29,411 +29,9 @@
#include "msm_vidc_debug.h"
#include "vidc_hfi_api.h"
#include "msm_smem.h"
+#include "venus_hfi.h"
#define BASE_DEVICE_NUMBER 32
-#define SHARED_QSIZE 0x1000000
-
-static struct msm_bus_vectors enc_ocmem_init_vectors[] = {
- {
- .src = MSM_BUS_MASTER_VIDEO_P0_OCMEM,
- .dst = MSM_BUS_SLAVE_OCMEM,
- .ab = 0,
- .ib = 0,
- },
-};
-
-static struct msm_bus_vectors enc_ocmem_perf1_vectors[] = {
- {
- .src = MSM_BUS_MASTER_VIDEO_P0_OCMEM,
- .dst = MSM_BUS_SLAVE_OCMEM,
- .ab = 138200000,
- .ib = 1222000000,
- },
-};
-
-static struct msm_bus_vectors enc_ocmem_perf2_vectors[] = {
- {
- .src = MSM_BUS_MASTER_VIDEO_P0_OCMEM,
- .dst = MSM_BUS_SLAVE_OCMEM,
- .ab = 414700000,
- .ib = 1222000000,
- },
-};
-
-static struct msm_bus_vectors enc_ocmem_perf3_vectors[] = {
- {
- .src = MSM_BUS_MASTER_VIDEO_P0_OCMEM,
- .dst = MSM_BUS_SLAVE_OCMEM,
- .ab = 940000000,
- .ib = 2444000000U,
- },
-};
-
-static struct msm_bus_vectors enc_ocmem_perf4_vectors[] = {
- {
- .src = MSM_BUS_MASTER_VIDEO_P0_OCMEM,
- .dst = MSM_BUS_SLAVE_OCMEM,
- .ab = 1880000000,
- .ib = 2444000000U,
- },
-};
-
-static struct msm_bus_vectors enc_ocmem_perf5_vectors[] = {
- {
- .src = MSM_BUS_MASTER_VIDEO_P0_OCMEM,
- .dst = MSM_BUS_SLAVE_OCMEM,
- .ab = 3008000000U,
- .ib = 3910400000U,
- },
-};
-
-static struct msm_bus_vectors enc_ocmem_perf6_vectors[] = {
- {
- .src = MSM_BUS_MASTER_VIDEO_P0_OCMEM,
- .dst = MSM_BUS_SLAVE_OCMEM,
- .ab = 3760000000U,
- .ib = 4888000000ULL,
- },
-};
-
-static struct msm_bus_vectors dec_ocmem_init_vectors[] = {
- {
- .src = MSM_BUS_MASTER_VIDEO_P0_OCMEM,
- .dst = MSM_BUS_SLAVE_OCMEM,
- .ab = 0,
- .ib = 0,
- },
-};
-
-static struct msm_bus_vectors dec_ocmem_perf1_vectors[] = {
- {
- .src = MSM_BUS_MASTER_VIDEO_P0_OCMEM,
- .dst = MSM_BUS_SLAVE_OCMEM,
- .ab = 176900000,
- .ib = 1556640000,
- },
-};
-
-static struct msm_bus_vectors dec_ocmem_perf2_vectors[] = {
- {
- .src = MSM_BUS_MASTER_VIDEO_P0_OCMEM,
- .dst = MSM_BUS_SLAVE_OCMEM,
- .ab = 456200000,
- .ib = 1556640000,
- },
-};
-
-static struct msm_bus_vectors dec_ocmem_perf3_vectors[] = {
- {
- .src = MSM_BUS_MASTER_VIDEO_P0_OCMEM,
- .dst = MSM_BUS_SLAVE_OCMEM,
- .ab = 864800000,
- .ib = 1556640000,
- },
-};
-
-static struct msm_bus_vectors dec_ocmem_perf4_vectors[] = {
- {
- .src = MSM_BUS_MASTER_VIDEO_P0_OCMEM,
- .dst = MSM_BUS_SLAVE_OCMEM,
- .ab = 1729600000,
- .ib = 3113280000U,
- },
-};
-
-static struct msm_bus_vectors dec_ocmem_perf5_vectors[] = {
- {
- .src = MSM_BUS_MASTER_VIDEO_P0_OCMEM,
- .dst = MSM_BUS_SLAVE_OCMEM,
- .ab = 2767360000U,
- .ib = 4981248000ULL,
- },
-};
-
-static struct msm_bus_vectors dec_ocmem_perf6_vectors[] = {
- {
- .src = MSM_BUS_MASTER_VIDEO_P0_OCMEM,
- .dst = MSM_BUS_SLAVE_OCMEM,
- .ab = 3459200000U,
- .ib = 6226560000ULL,
- },
-};
-
-static struct msm_bus_paths enc_ocmem_perf_vectors[] = {
- {
- ARRAY_SIZE(enc_ocmem_init_vectors),
- enc_ocmem_init_vectors,
- },
- {
- ARRAY_SIZE(enc_ocmem_perf1_vectors),
- enc_ocmem_perf1_vectors,
- },
- {
- ARRAY_SIZE(enc_ocmem_perf2_vectors),
- enc_ocmem_perf2_vectors,
- },
- {
- ARRAY_SIZE(enc_ocmem_perf3_vectors),
- enc_ocmem_perf3_vectors,
- },
- {
- ARRAY_SIZE(enc_ocmem_perf4_vectors),
- enc_ocmem_perf4_vectors,
- },
- {
- ARRAY_SIZE(enc_ocmem_perf5_vectors),
- enc_ocmem_perf5_vectors,
- },
- {
- ARRAY_SIZE(enc_ocmem_perf6_vectors),
- enc_ocmem_perf6_vectors,
- },
-};
-
-static struct msm_bus_paths dec_ocmem_perf_vectors[] = {
- {
- ARRAY_SIZE(dec_ocmem_init_vectors),
- dec_ocmem_init_vectors,
- },
- {
- ARRAY_SIZE(dec_ocmem_perf1_vectors),
- dec_ocmem_perf1_vectors,
- },
- {
- ARRAY_SIZE(dec_ocmem_perf2_vectors),
- dec_ocmem_perf2_vectors,
- },
- {
- ARRAY_SIZE(dec_ocmem_perf3_vectors),
- dec_ocmem_perf3_vectors,
- },
- {
- ARRAY_SIZE(dec_ocmem_perf4_vectors),
- dec_ocmem_perf4_vectors,
- },
- {
- ARRAY_SIZE(dec_ocmem_perf5_vectors),
- dec_ocmem_perf5_vectors,
- },
- {
- ARRAY_SIZE(dec_ocmem_perf6_vectors),
- dec_ocmem_perf6_vectors,
- },
-};
-
-
-static struct msm_bus_scale_pdata enc_ocmem_bus_data = {
- .usecase = enc_ocmem_perf_vectors,
- .num_usecases = ARRAY_SIZE(enc_ocmem_perf_vectors),
- .name = "msm_vidc_enc_ocmem",
-};
-
-static struct msm_bus_scale_pdata dec_ocmem_bus_data = {
- .usecase = dec_ocmem_perf_vectors,
- .num_usecases = ARRAY_SIZE(dec_ocmem_perf_vectors),
- .name = "msm_vidc_dec_ocmem",
-};
-
-static struct msm_bus_vectors enc_ddr_init_vectors[] = {
- {
- .src = MSM_BUS_MASTER_VIDEO_P0,
- .dst = MSM_BUS_SLAVE_EBI_CH0,
- .ab = 0,
- .ib = 0,
- },
-};
-
-
-static struct msm_bus_vectors enc_ddr_perf1_vectors[] = {
- {
- .src = MSM_BUS_MASTER_VIDEO_P0,
- .dst = MSM_BUS_SLAVE_EBI_CH0,
- .ab = 60000000,
- .ib = 664950000,
- },
-};
-
-static struct msm_bus_vectors enc_ddr_perf2_vectors[] = {
- {
- .src = MSM_BUS_MASTER_VIDEO_P0,
- .dst = MSM_BUS_SLAVE_EBI_CH0,
- .ab = 181000000,
- .ib = 664950000,
- },
-};
-
-static struct msm_bus_vectors enc_ddr_perf3_vectors[] = {
- {
- .src = MSM_BUS_MASTER_VIDEO_P0,
- .dst = MSM_BUS_SLAVE_EBI_CH0,
- .ab = 403000000,
- .ib = 664950000,
- },
-};
-
-static struct msm_bus_vectors enc_ddr_perf4_vectors[] = {
- {
- .src = MSM_BUS_MASTER_VIDEO_P0,
- .dst = MSM_BUS_SLAVE_EBI_CH0,
- .ab = 806000000,
- .ib = 1329900000,
- },
-};
-
-static struct msm_bus_vectors enc_ddr_perf5_vectors[] = {
- {
- .src = MSM_BUS_MASTER_VIDEO_P0,
- .dst = MSM_BUS_SLAVE_EBI_CH0,
- .ab = 1289600000,
- .ib = 2127840000U,
- },
-};
-
-static struct msm_bus_vectors enc_ddr_perf6_vectors[] = {
- {
- .src = MSM_BUS_MASTER_VIDEO_P0,
- .dst = MSM_BUS_SLAVE_EBI_CH0,
- .ab = 161200000,
- .ib = 6400000000ULL,
- },
-};
-
-static struct msm_bus_vectors dec_ddr_init_vectors[] = {
- {
- .src = MSM_BUS_MASTER_VIDEO_P0,
- .dst = MSM_BUS_SLAVE_EBI_CH0,
- .ab = 0,
- .ib = 0,
- },
-};
-
-static struct msm_bus_vectors dec_ddr_perf1_vectors[] = {
- {
- .src = MSM_BUS_MASTER_VIDEO_P0,
- .dst = MSM_BUS_SLAVE_EBI_CH0,
- .ab = 110000000,
- .ib = 909000000,
- },
-};
-
-static struct msm_bus_vectors dec_ddr_perf2_vectors[] = {
- {
- .src = MSM_BUS_MASTER_VIDEO_P0,
- .dst = MSM_BUS_SLAVE_EBI_CH0,
- .ab = 268000000,
- .ib = 909000000,
- },
-};
-
-static struct msm_bus_vectors dec_ddr_perf3_vectors[] = {
- {
- .src = MSM_BUS_MASTER_VIDEO_P0,
- .dst = MSM_BUS_SLAVE_EBI_CH0,
- .ab = 505000000,
- .ib = 909000000,
- },
-};
-
-static struct msm_bus_vectors dec_ddr_perf4_vectors[] = {
- {
- .src = MSM_BUS_MASTER_VIDEO_P0,
- .dst = MSM_BUS_SLAVE_EBI_CH0,
- .ab = 1010000000,
- .ib = 1818000000,
- },
-};
-
-static struct msm_bus_vectors dec_ddr_perf5_vectors[] = {
- {
- .src = MSM_BUS_MASTER_VIDEO_P0,
- .dst = MSM_BUS_SLAVE_EBI_CH0,
- .ab = 1616000000,
- .ib = 2908800000U,
- },
-};
-
-static struct msm_bus_vectors dec_ddr_perf6_vectors[] = {
- {
- .src = MSM_BUS_MASTER_VIDEO_P0,
- .dst = MSM_BUS_SLAVE_EBI_CH0,
- .ab = 2020000000U,
- .ib = 6400000000ULL,
- },
-};
-
-static struct msm_bus_paths enc_ddr_perf_vectors[] = {
- {
- ARRAY_SIZE(enc_ddr_init_vectors),
- enc_ddr_init_vectors,
- },
- {
- ARRAY_SIZE(enc_ddr_perf1_vectors),
- enc_ddr_perf1_vectors,
- },
- {
- ARRAY_SIZE(enc_ddr_perf2_vectors),
- enc_ddr_perf2_vectors,
- },
- {
- ARRAY_SIZE(enc_ddr_perf3_vectors),
- enc_ddr_perf3_vectors,
- },
- {
- ARRAY_SIZE(enc_ddr_perf4_vectors),
- enc_ddr_perf4_vectors,
- },
- {
- ARRAY_SIZE(enc_ddr_perf5_vectors),
- enc_ddr_perf5_vectors,
- },
- {
- ARRAY_SIZE(enc_ddr_perf6_vectors),
- enc_ddr_perf6_vectors,
- },
-};
-
-static struct msm_bus_paths dec_ddr_perf_vectors[] = {
- {
- ARRAY_SIZE(dec_ddr_init_vectors),
- dec_ddr_init_vectors,
- },
- {
- ARRAY_SIZE(dec_ddr_perf1_vectors),
- dec_ddr_perf1_vectors,
- },
- {
- ARRAY_SIZE(dec_ddr_perf2_vectors),
- dec_ddr_perf2_vectors,
- },
- {
- ARRAY_SIZE(dec_ddr_perf3_vectors),
- dec_ddr_perf3_vectors,
- },
- {
- ARRAY_SIZE(dec_ddr_perf4_vectors),
- dec_ddr_perf4_vectors,
- },
- {
- ARRAY_SIZE(dec_ddr_perf5_vectors),
- dec_ddr_perf5_vectors,
- },
- {
- ARRAY_SIZE(dec_ddr_perf6_vectors),
- dec_ddr_perf6_vectors,
- },
-};
-
-static struct msm_bus_scale_pdata enc_ddr_bus_data = {
- .usecase = enc_ddr_perf_vectors,
- .num_usecases = ARRAY_SIZE(enc_ddr_perf_vectors),
- .name = "msm_vidc_enc_ddr",
-};
-
-static struct msm_bus_scale_pdata dec_ddr_bus_data = {
- .usecase = dec_ddr_perf_vectors,
- .num_usecases = ARRAY_SIZE(dec_ddr_perf_vectors),
- .name = "msm_vidc_dec_ddr",
-};
struct msm_vidc_drv *vidc_driver;
@@ -757,8 +355,16 @@
int i, rc = 0;
int smem_flags = 0;
int domain;
+ struct venus_hfi_device *device;
vidc_inst = get_vidc_inst(file, fh);
v4l2_inst = get_v4l2_inst(file, fh);
+ if (!v4l2_inst || !vidc_inst || !vidc_inst->core
+ || !vidc_inst->core->device) {
+ rc = -EINVAL;
+ goto exit;
+ }
+
+ device = vidc_inst->core->device;
if (!v4l2_inst->mem_client) {
dprintk(VIDC_ERR, "Failed to get memory client\n");
rc = -ENOMEM;
@@ -798,11 +404,9 @@
&& (!EXTRADATA_IDX(b->length)
|| (i != EXTRADATA_IDX(b->length)))) {
smem_flags |= SMEM_SECURE;
- domain =
- vidc_inst->core->resources.io_map[CP_MAP].domain;
+ domain = venus_hfi_get_domain(device, CP_MAP);
} else
- domain =
- vidc_inst->core->resources.io_map[NS_MAP].domain;
+ domain = venus_hfi_get_domain(device, NS_MAP);
if (b->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
smem_flags |= SMEM_INPUT;
@@ -1063,270 +667,24 @@
{
}
-static size_t read_u32_array(struct platform_device *pdev,
- char *name, u32 *arr, size_t size)
-{
- int len;
- size_t sz = 0;
- struct device_node *np = pdev->dev.of_node;
- if (!of_get_property(np, name, &len)) {
- dprintk(VIDC_ERR, "Failed to read %s from device tree\n",
- name);
- goto fail_read;
- }
- sz = len / sizeof(u32);
- if (sz <= 0) {
- dprintk(VIDC_ERR, "%s not specified in device tree\n",
- name);
- goto fail_read;
- }
- if (sz > size) {
- dprintk(VIDC_ERR, "Not enough memory to store %s values\n",
- name);
- goto fail_read;
- }
- if (of_property_read_u32_array(np, name, arr, sz)) {
- dprintk(VIDC_ERR,
- "error while reading %s from device tree\n",
- name);
- goto fail_read;
- }
- return sz;
-fail_read:
- sz = 0;
- return sz;
-}
-
-static int register_iommu_domains(struct platform_device *pdev,
- struct msm_vidc_core *core)
-{
- size_t len;
- struct msm_iova_partition partition[2];
- struct msm_iova_layout layout;
- int rc = 0;
- int i;
- struct msm_vidc_iommu_info *io_map = core->resources.io_map;
- strlcpy(io_map[CP_MAP].name, "vidc-cp-map",
- sizeof(io_map[CP_MAP].name));
- strlcpy(io_map[CP_MAP].ctx, "venus_cp",
- sizeof(io_map[CP_MAP].ctx));
- strlcpy(io_map[NS_MAP].name, "vidc-ns-map",
- sizeof(io_map[NS_MAP].name));
- strlcpy(io_map[NS_MAP].ctx, "venus_ns",
- sizeof(io_map[NS_MAP].ctx));
-
- for (i = 0; i < MAX_MAP; i++) {
- len = read_u32_array(pdev, io_map[i].name,
- io_map[i].addr_range,
- (sizeof(io_map[i].addr_range)/sizeof(u32)));
- if (!len) {
- dprintk(VIDC_ERR,
- "Error in reading cp address range\n");
- rc = -EINVAL;
- break;
- }
- partition[0].start = io_map[i].addr_range[0];
- if (i == NS_MAP) {
- partition[0].size =
- io_map[i].addr_range[1] - SHARED_QSIZE;
- partition[1].start =
- partition[0].start + io_map[i].addr_range[1]
- - SHARED_QSIZE;
- partition[1].size = SHARED_QSIZE;
- layout.npartitions = 2;
- layout.is_secure = 0;
- } else {
- partition[0].size = io_map[i].addr_range[1];
- layout.npartitions = 1;
- layout.is_secure = 1;
- }
- layout.partitions = &partition[0];
- layout.client_name = io_map[i].name;
- layout.domain_flags = 0;
- dprintk(VIDC_DBG, "Registering domain 1 with: %lx, %lx, %s\n",
- partition[0].start, partition[0].size,
- layout.client_name);
- dprintk(VIDC_DBG, "Registering domain 2 with: %lx, %lx, %s\n",
- partition[1].start, partition[1].size,
- layout.client_name);
- io_map[i].domain = msm_register_domain(&layout);
- if (io_map[i].domain < 0) {
- dprintk(VIDC_ERR, "Failed to register cp domain\n");
- rc = -EINVAL;
- break;
- }
- }
- /* There is no api provided as msm_unregister_domain, so
- * we are not able to unregister the previously
- * registered domains if any domain registration fails.*/
- BUG_ON(i < MAX_MAP);
- return rc;
-}
-
-static inline int msm_vidc_init_clocks(struct platform_device *pdev,
- struct msm_vidc_core *core)
-{
- struct core_clock *cl;
- int i;
- int rc = 0;
- struct core_clock *clock;
- if (!core) {
- dprintk(VIDC_ERR, "Invalid params: %p\n", core);
- return -EINVAL;
- }
- clock = core->resources.clock;
- strlcpy(clock[VCODEC_CLK].name, "core_clk",
- sizeof(clock[VCODEC_CLK].name));
- strlcpy(clock[VCODEC_AHB_CLK].name, "iface_clk",
- sizeof(clock[VCODEC_AHB_CLK].name));
- strlcpy(clock[VCODEC_AXI_CLK].name, "bus_clk",
- sizeof(clock[VCODEC_AXI_CLK].name));
- strlcpy(clock[VCODEC_OCMEM_CLK].name, "mem_clk",
- sizeof(clock[VCODEC_OCMEM_CLK].name));
-
- clock[VCODEC_CLK].count = read_u32_array(pdev,
- "load-freq-tbl", (u32 *)clock[VCODEC_CLK].load_freq_tbl,
- (sizeof(clock[VCODEC_CLK].load_freq_tbl)/sizeof(u32)));
- clock[VCODEC_CLK].count /= 2;
- dprintk(VIDC_DBG, "count = %d\n", clock[VCODEC_CLK].count);
- if (!clock[VCODEC_CLK].count) {
- dprintk(VIDC_ERR, "Failed to read clock frequency\n");
- goto fail_init_clocks;
- }
- for (i = 0; i < clock[VCODEC_CLK].count; i++) {
- dprintk(VIDC_DBG,
- "load = %d, freq = %d\n",
- clock[VCODEC_CLK].load_freq_tbl[i].load,
- clock[VCODEC_CLK].load_freq_tbl[i].freq
- );
- }
-
- for (i = 0; i < VCODEC_MAX_CLKS; i++) {
- cl = &core->resources.clock[i];
- if (!cl->clk) {
- cl->clk = devm_clk_get(&pdev->dev, cl->name);
- if (IS_ERR_OR_NULL(cl->clk)) {
- dprintk(VIDC_ERR,
- "Failed to get clock: %s\n", cl->name);
- rc = PTR_ERR(cl->clk);
- break;
- }
- }
- }
-
- if (i < VCODEC_MAX_CLKS) {
- for (--i; i >= 0; i--) {
- cl = &core->resources.clock[i];
- clk_put(cl->clk);
- }
- }
-fail_init_clocks:
- return rc;
-}
-
-static inline void msm_vidc_deinit_clocks(struct msm_vidc_core *core)
-{
- int i;
- if (!core) {
- dprintk(VIDC_ERR, "Invalid args\n");
- return;
- }
- for (i = 0; i < VCODEC_MAX_CLKS; i++)
- clk_put(core->resources.clock[i].clk);
-}
-
static int msm_vidc_initialize_core(struct platform_device *pdev,
struct msm_vidc_core *core)
{
- struct resource *res;
int i = 0;
int rc = 0;
- struct on_chip_mem *ocmem;
if (!core)
return -EINVAL;
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (!res) {
- dprintk(VIDC_ERR, "Failed to get IORESOURCE_MEM\n");
- rc = -ENODEV;
- goto core_init_failed;
- }
- core->register_base = res->start;
- core->register_size = resource_size(res);
- res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
- if (!res) {
- dprintk(VIDC_ERR, "Failed to get IORESOURCE_IRQ\n");
- rc = -ENODEV;
- goto core_init_failed;
- }
- core->irq = res->start;
+
INIT_LIST_HEAD(&core->instances);
mutex_init(&core->sync_lock);
spin_lock_init(&core->lock);
- core->base_addr = 0x0;
+
core->state = VIDC_CORE_UNINIT;
for (i = SYS_MSG_INDEX(SYS_MSG_START);
i <= SYS_MSG_INDEX(SYS_MSG_END); i++) {
init_completion(&core->completions[i]);
}
- rc = msm_vidc_init_clocks(pdev, core);
- if (rc) {
- dprintk(VIDC_ERR, "Failed to init clocks\n");
- rc = -ENODEV;
- goto core_init_failed;
- }
- core->resources.bus_info.ddr_handle[MSM_VIDC_ENCODER] =
- msm_bus_scale_register_client(&enc_ddr_bus_data);
- if (!core->resources.bus_info.ddr_handle[MSM_VIDC_ENCODER]) {
- dprintk(VIDC_ERR, "Failed to register bus scale client\n");
- goto fail_register_enc_ddr_bus;
- }
- core->resources.bus_info.ddr_handle[MSM_VIDC_DECODER] =
- msm_bus_scale_register_client(&dec_ddr_bus_data);
- if (!core->resources.bus_info.ddr_handle[MSM_VIDC_DECODER]) {
- dprintk(VIDC_ERR, "Failed to register bus scale client\n");
- goto fail_register_dec_ddr_bus;
- }
- core->resources.bus_info.ocmem_handle[MSM_VIDC_ENCODER] =
- msm_bus_scale_register_client(&enc_ocmem_bus_data);
- if (!core->resources.bus_info.ocmem_handle[MSM_VIDC_ENCODER]) {
- dprintk(VIDC_ERR, "Failed to register bus scale client\n");
- goto fail_register_enc_ocmem;
- }
- core->resources.bus_info.ocmem_handle[MSM_VIDC_DECODER] =
- msm_bus_scale_register_client(&dec_ocmem_bus_data);
- if (!core->resources.bus_info.ocmem_handle[MSM_VIDC_DECODER]) {
- dprintk(VIDC_ERR, "Failed to register bus scale client\n");
- goto fail_register_dec_ocmem;
- }
- rc = register_iommu_domains(pdev, core);
- if (rc) {
- dprintk(VIDC_ERR, "Failed to register iommu domains: %d\n", rc);
- goto fail_register_domains;
- }
- ocmem = &core->resources.ocmem;
- ocmem->vidc_ocmem_nb.notifier_call = msm_vidc_ocmem_notify_handler;
- ocmem->handle =
- ocmem_notifier_register(OCMEM_VIDEO, &ocmem->vidc_ocmem_nb);
- if (!ocmem->handle) {
- dprintk(VIDC_WARN, "Failed to register OCMEM notifier.");
- dprintk(VIDC_INFO, " Performance will be impacted\n");
- }
- return rc;
-fail_register_domains:
- msm_bus_scale_unregister_client(
- core->resources.bus_info.ocmem_handle[MSM_VIDC_DECODER]);
-fail_register_dec_ocmem:
- msm_bus_scale_unregister_client(
- core->resources.bus_info.ocmem_handle[MSM_VIDC_ENCODER]);
-fail_register_enc_ocmem:
- msm_bus_scale_unregister_client(
- core->resources.bus_info.ddr_handle[MSM_VIDC_DECODER]);
-fail_register_dec_ddr_bus:
- msm_bus_scale_unregister_client(
- core->resources.bus_info.ddr_handle[MSM_VIDC_ENCODER]);
-fail_register_enc_ddr_bus:
- msm_vidc_deinit_clocks(core);
-core_init_failed:
+
return rc;
}
@@ -1377,11 +735,11 @@
goto err_enc_register;
}
video_set_drvdata(&core->vdev[MSM_VIDC_ENCODER].vdev, core);
- core->device = vidc_hal_add_device(core->id, core->base_addr,
- core->register_base, core->register_size, core->irq,
- &handle_cmd_response);
+
+ core->device =
+ venus_hfi_get_device(core->id, pdev, &handle_cmd_response);
if (!core->device) {
- dprintk(VIDC_ERR, "Failed to create interrupt handler");
+ dprintk(VIDC_ERR, "Failed to create HFI device\n");
goto err_cores_exceeded;
}
@@ -1417,20 +775,12 @@
{
int rc = 0;
struct msm_vidc_core *core = pdev->dev.platform_data;
- int i;
- for (i = 0; i < MSM_VIDC_MAX_DEVICES; ++i) {
- msm_bus_scale_unregister_client(
- core->resources.bus_info.ddr_handle[i]);
- msm_bus_scale_unregister_client(
- core->resources.bus_info.ocmem_handle[i]);
- }
- vidc_hal_delete_device(core->device);
+
+ venus_hfi_delete_device(core->device);
video_unregister_device(&core->vdev[MSM_VIDC_ENCODER].vdev);
video_unregister_device(&core->vdev[MSM_VIDC_DECODER].vdev);
v4l2_device_unregister(&core->v4l2_dev);
- if (core->resources.ocmem.handle)
- ocmem_notifier_unregister(core->resources.ocmem.handle,
- &core->resources.ocmem.vidc_ocmem_nb);
+
kfree(core);
return rc;
}
diff --git a/drivers/media/video/msm_vidc/msm_vdec.c b/drivers/media/video/msm_vidc/msm_vdec.c
index bc94f45..525bad8 100644
--- a/drivers/media/video/msm_vidc/msm_vdec.c
+++ b/drivers/media/video/msm_vidc/msm_vdec.c
@@ -415,8 +415,8 @@
buffer_info.extradata_addr = 0;
buffer_info.extradata_size = 0;
}
- rc = vidc_hal_session_set_buffers((void *)inst->session,
- &buffer_info);
+ rc = venus_hfi_session_set_buffers(
+ (void *)inst->session, &buffer_info);
if (rc)
dprintk(VIDC_ERR,
"vidc_hal_session_set_buffers failed");
@@ -484,7 +484,7 @@
else
buffer_info.extradata_addr = 0;
buffer_info.response_required = false;
- rc = vidc_hal_session_release_buffers(
+ rc = venus_hfi_session_release_buffers(
(void *)inst->session, &buffer_info);
if (rc)
dprintk(VIDC_ERR,
@@ -851,7 +851,7 @@
new_buf_count.buffer_type = HAL_BUFFER_OUTPUT;
new_buf_count.buffer_count_actual = *num_buffers;
- rc = vidc_hal_session_set_property(inst->session,
+ rc = venus_hfi_session_set_property(inst->session,
property_id, &new_buf_count);
}
@@ -1166,7 +1166,7 @@
property_id,
msm_vdec_ctrls[control_idx].id,
control.value);
- rc = vidc_hal_session_set_property((void *)
+ rc = venus_hfi_session_set_property((void *)
inst->session, property_id,
pdata);
}
diff --git a/drivers/media/video/msm_vidc/msm_venc.c b/drivers/media/video/msm_vidc/msm_venc.c
index 0ba216c..341e06f 100644
--- a/drivers/media/video/msm_vidc/msm_venc.c
+++ b/drivers/media/video/msm_vidc/msm_venc.c
@@ -648,7 +648,7 @@
property_id = HAL_PARAM_BUFFER_COUNT_ACTUAL;
new_buf_count.buffer_type = HAL_BUFFER_INPUT;
new_buf_count.buffer_count_actual = *num_buffers;
- rc = vidc_hal_session_set_property(inst->session,
+ rc = venus_hfi_session_set_property(inst->session,
property_id, &new_buf_count);
dprintk(VIDC_DBG, "size = %d, alignment = %d, count = %d\n",
inst->buff_req.buffer[0].buffer_size,
@@ -1405,7 +1405,7 @@
dprintk(VIDC_DBG, "Control: HAL property=%d,ctrl_value=%d\n",
property_id,
ctrl->val);
- rc = vidc_hal_session_set_property((void *)inst->session,
+ rc = venus_hfi_session_set_property((void *)inst->session,
property_id, pdata);
}
@@ -1597,7 +1597,7 @@
frame_rate.frame_rate = inst->prop.fps * (0x1<<16);
frame_rate.buffer_type = HAL_BUFFER_OUTPUT;
pdata = &frame_rate;
- rc = vidc_hal_session_set_property((void *)inst->session,
+ rc = venus_hfi_session_set_property((void *)inst->session,
property_id, pdata);
if (rc) {
dprintk(VIDC_WARN,
@@ -1638,7 +1638,7 @@
frame_sz.height = inst->prop.height;
dprintk(VIDC_DBG, "width = %d, height = %d\n",
frame_sz.width, frame_sz.height);
- rc = vidc_hal_session_set_property((void *)inst->session,
+ rc = venus_hfi_session_set_property((void *)inst->session,
HAL_PARAM_FRAME_SIZE, &frame_sz);
if (rc) {
dprintk(VIDC_ERR,
@@ -1646,7 +1646,7 @@
goto exit;
}
frame_sz.buffer_type = HAL_BUFFER_OUTPUT;
- rc = vidc_hal_session_set_property((void *)inst->session,
+ rc = venus_hfi_session_set_property((void *)inst->session,
HAL_PARAM_FRAME_SIZE, &frame_sz);
if (rc) {
dprintk(VIDC_ERR,
@@ -1769,8 +1769,8 @@
b->m.planes[i].m.userptr;
buffer_info.extradata_size = 0;
buffer_info.extradata_addr = 0;
- rc = vidc_hal_session_set_buffers((void *)inst->session,
- &buffer_info);
+ rc = venus_hfi_session_set_buffers(
+ (void *)inst->session, &buffer_info);
if (rc)
dprintk(VIDC_ERR,
"vidc_hal_session_set_buffers failed");
@@ -1814,7 +1814,7 @@
buffer_info.extradata_size = 0;
buffer_info.extradata_addr = 0;
buffer_info.response_required = false;
- rc = vidc_hal_session_release_buffers(
+ rc = venus_hfi_session_release_buffers(
(void *)inst->session, &buffer_info);
if (rc)
dprintk(VIDC_ERR,
diff --git a/drivers/media/video/msm_vidc/msm_vidc.c b/drivers/media/video/msm_vidc/msm_vidc.c
index 136d4e5..b9f1508 100644
--- a/drivers/media/video/msm_vidc/msm_vidc.c
+++ b/drivers/media/video/msm_vidc/msm_vidc.c
@@ -21,6 +21,7 @@
#include "msm_vidc_common.h"
#include "msm_smem.h"
#include <linux/delay.h>
+#include "venus_hfi.h"
#define MAX_EVENTS 30
@@ -85,15 +86,11 @@
struct msm_vidc_iommu_info maps[MAX_MAP])
{
struct msm_vidc_inst *inst = instance;
- int c = 0;
- if (!inst || !maps)
+ if (!inst || !maps || !inst->core)
return -EINVAL;
- for (c = 0; c < MAX_MAP; ++c)
- maps[c] = inst->core->resources.io_map[c];
-
- return 0;
+ return venus_hfi_iommu_get_map(inst->core->device, maps);
}
int msm_vidc_querycap(void *instance, struct v4l2_capability *cap)
diff --git a/drivers/media/video/msm_vidc/msm_vidc_common.c b/drivers/media/video/msm_vidc/msm_vidc_common.c
index 042b14c..eac715f 100644
--- a/drivers/media/video/msm_vidc/msm_vidc_common.c
+++ b/drivers/media/video/msm_vidc/msm_vidc_common.c
@@ -13,17 +13,14 @@
#include <linux/sched.h>
#include <linux/slab.h>
-#include <linux/iommu.h>
#include <asm/div64.h>
-#include <mach/iommu.h>
-#include <mach/iommu_domains.h>
#include <mach/subsystem_restart.h>
-#include <mach/scm.h>
#include "msm_vidc_common.h"
#include "vidc_hfi_api.h"
#include "msm_smem.h"
#include "msm_vidc_debug.h"
+#include "venus_hfi.h"
#define HW_RESPONSE_TIMEOUT (5 * 60 * 1000)
@@ -50,42 +47,8 @@
__mbs;\
})
-#define TZBSP_MEM_PROTECT_VIDEO_VAR 0x8
-struct tzbsp_memprot {
- u32 cp_start;
- u32 cp_size;
- u32 cp_nonpixel_start;
- u32 cp_nonpixel_size;
-};
-
-struct tzbsp_resp {
- int ret;
-};
-
#define TIME_DIFF_THRESHOLD 200
-static const u32 bus_table[] = {
- 36000,
- 110400,
- 244800,
- 489000,
- 783360,
- 979200,
-};
-
-static int get_bus_vector(int load)
-{
- int num_rows = sizeof(bus_table)/(sizeof(u32));
- int i;
- for (i = 0; i < num_rows; i++) {
- if (load <= bus_table[i])
- break;
- }
- i++;
- dprintk(VIDC_DBG, "Required bus = %d\n", i);
- return i;
-}
-
static int msm_comm_get_load(struct msm_vidc_core *core,
enum session_type type)
{
@@ -109,47 +72,22 @@
return num_mbs_per_sec;
}
-static unsigned long get_clock_rate(struct core_clock *clock,
- int num_mbs_per_sec)
-{
- int num_rows = clock->count;
- struct load_freq_table *table = clock->load_freq_tbl;
- unsigned long ret = table[num_rows-1].freq;
- int i;
- for (i = 0; i < num_rows; i++) {
- if (num_mbs_per_sec > table[i].load)
- break;
- ret = table[i].freq;
- }
- dprintk(VIDC_DBG, "Required clock rate = %lu\n", ret);
- return ret;
-}
-
static int msm_comm_scale_bus(struct msm_vidc_core *core,
enum session_type type, enum mem_type mtype)
{
int load;
int rc = 0;
- u32 handle = 0;
+
if (!core || type >= MSM_VIDC_MAX_DEVICES) {
dprintk(VIDC_ERR, "Invalid args: %p, %d\n", core, type);
return -EINVAL;
}
load = msm_comm_get_load(core, type);
- if (mtype & DDR_MEM)
- handle = core->resources.bus_info.ddr_handle[type];
- if (mtype & OCMEM_MEM)
- handle = core->resources.bus_info.ocmem_handle[type];
- if (handle) {
- rc = msm_bus_scale_client_update_request(
- handle, get_bus_vector(load));
- if (rc)
- dprintk(VIDC_ERR, "Failed to scale bus: %d\n", rc);
- } else {
- dprintk(VIDC_ERR, "Failed to scale bus, mtype: %d\n",
- mtype);
- rc = -EINVAL;
- }
+
+ rc = venus_hfi_scale_bus(core->device, load, type, mtype);
+ if (rc)
+ dprintk(VIDC_ERR, "Failed to scale bus: %d\n", rc);
+
return rc;
}
@@ -159,47 +97,18 @@
int i;
for (i = 0; i < MSM_VIDC_MAX_DEVICES; i++) {
if ((mtype & DDR_MEM) &&
- msm_bus_scale_client_update_request(
- core->resources.bus_info.ddr_handle[i],
- 0)) {
+ venus_hfi_scale_bus(core->device, 0, i, DDR_MEM)) {
dprintk(VIDC_WARN,
"Failed to unvote for DDR accesses\n");
}
if ((mtype & OCMEM_MEM) &&
- msm_bus_scale_client_update_request(
- core->resources.bus_info.ocmem_handle[i],
- 0)) {
+ venus_hfi_scale_bus(core->device, 0, i, OCMEM_MEM)) {
dprintk(VIDC_WARN,
"Failed to unvote for OCMEM accesses\n");
}
}
}
-static int protect_cp_mem(struct msm_vidc_core *core)
-{
- struct tzbsp_memprot memprot;
- unsigned int resp = 0;
- int rc = 0;
- struct msm_vidc_iommu_info *io_map = core->resources.io_map;
- if (!io_map) {
- dprintk(VIDC_ERR, "invalid params: %p\n", io_map);
- return -EINVAL;
- }
- memprot.cp_start = 0x0;
- memprot.cp_size = io_map[CP_MAP].addr_range[0] +
- io_map[CP_MAP].addr_range[1];
- memprot.cp_nonpixel_start = 0;
- memprot.cp_nonpixel_size = 0;
-
- rc = scm_call(SCM_SVC_CP, TZBSP_MEM_PROTECT_VIDEO_VAR, &memprot,
- sizeof(memprot), &resp, sizeof(resp));
- if (rc)
- dprintk(VIDC_ERR,
- "Failed to protect memory , rc is :%d, response : %d\n",
- rc, resp);
- return rc;
-}
-
struct msm_vidc_core *get_vidc_core(int core_id)
{
struct msm_vidc_core *core;
@@ -222,62 +131,6 @@
return NULL;
}
-static int msm_comm_iommu_attach(struct msm_vidc_core *core)
-{
- int rc;
- struct iommu_domain *domain;
- int i;
- struct msm_vidc_iommu_info *io_map;
- struct device *dev;
- for (i = 0; i < MAX_MAP; i++) {
- io_map = &core->resources.io_map[i];
- dev = msm_iommu_get_ctx(io_map->ctx);
- domain = msm_get_iommu_domain(io_map->domain);
- if (IS_ERR_OR_NULL(domain)) {
- dprintk(VIDC_ERR,
- "Failed to get domain: %s\n", io_map->name);
- rc = PTR_ERR(domain);
- break;
- }
- rc = iommu_attach_device(domain, dev);
- if (rc) {
- dprintk(VIDC_ERR,
- "IOMMU attach failed: %s\n", io_map->name);
- break;
- }
- }
- if (i < MAX_MAP) {
- i--;
- for (; i >= 0; i--) {
- io_map = &core->resources.io_map[i];
- dev = msm_iommu_get_ctx(io_map->ctx);
- domain = msm_get_iommu_domain(io_map->domain);
- if (dev && domain)
- iommu_detach_device(domain, dev);
- }
- }
- return rc;
-}
-
-static void msm_comm_iommu_detach(struct msm_vidc_core *core)
-{
- struct device *dev;
- struct iommu_domain *domain;
- struct msm_vidc_iommu_info *io_map;
- int i;
- if (!core) {
- dprintk(VIDC_ERR, "Invalid paramter: %p\n", core);
- return;
- }
- for (i = 0; i < MAX_MAP; i++) {
- io_map = &core->resources.io_map[i];
- dev = msm_iommu_get_ctx(io_map->ctx);
- domain = msm_get_iommu_domain(io_map->domain);
- if (dev && domain)
- iommu_detach_device(domain, dev);
- }
-}
-
const struct msm_vidc_format *msm_comm_get_pixel_fmt_index(
const struct msm_vidc_format fmt[], int size, int index, int fmt_type)
{
@@ -1029,60 +882,18 @@
}
num_mbs_per_sec = msm_comm_get_load(core, MSM_VIDC_ENCODER);
num_mbs_per_sec += msm_comm_get_load(core, MSM_VIDC_DECODER);
+
dprintk(VIDC_INFO, "num_mbs_per_sec = %d\n", num_mbs_per_sec);
- rc = clk_set_rate(core->resources.clock[VCODEC_CLK].clk,
- get_clock_rate(&core->resources.clock[VCODEC_CLK],
- num_mbs_per_sec));
+ rc = venus_hfi_scale_clocks(core->device, num_mbs_per_sec);
if (rc)
dprintk(VIDC_ERR, "Failed to set clock rate: %d\n", rc);
return rc;
}
-static inline int msm_comm_enable_clks(struct msm_vidc_core *core)
-{
- int i;
- struct core_clock *cl;
- int rc = 0;
- if (!core) {
- dprintk(VIDC_ERR, "Invalid params: %p\n", core);
- return -EINVAL;
- }
- for (i = 0; i < VCODEC_MAX_CLKS; i++) {
- cl = &core->resources.clock[i];
- rc = clk_prepare_enable(cl->clk);
- if (rc) {
- dprintk(VIDC_ERR, "Failed to enable clocks\n");
- goto fail_clk_enable;
- } else {
- dprintk(VIDC_DBG, "Clock: %s enabled\n", cl->name);
- }
- }
- return rc;
-fail_clk_enable:
- for (; i >= 0; i--) {
- cl = &core->resources.clock[i];
- clk_disable_unprepare(cl->clk);
- }
- return rc;
-}
-
-static inline void msm_comm_disable_clks(struct msm_vidc_core *core)
-{
- int i;
- struct core_clock *cl;
- if (!core) {
- dprintk(VIDC_ERR, "Invalid params: %p\n", core);
- return;
- }
- for (i = 0; i < VCODEC_MAX_CLKS; i++) {
- cl = &core->resources.clock[i];
- clk_disable_unprepare(cl->clk);
- }
-}
-
void msm_comm_scale_clocks_and_bus(struct msm_vidc_inst *inst)
{
struct msm_vidc_core *core = inst->core;
+
if (!inst) {
dprintk(VIDC_WARN, "Invalid params\n");
return;
@@ -1095,7 +906,7 @@
dprintk(VIDC_WARN,
"Failed to scale DDR bus. Performance might be impacted\n");
}
- if (core->resources.ocmem.buf) {
+ if (venus_hfi_is_ocmem_present(core->device)) {
if (msm_comm_scale_bus(core, inst->session_type,
OCMEM_MEM))
dprintk(VIDC_WARN,
@@ -1103,64 +914,6 @@
}
}
-static int msm_comm_load_fw(struct msm_vidc_core *core)
-{
- int rc = 0;
- if (!core) {
- dprintk(VIDC_ERR, "Invalid paramter: %p\n", core);
- return -EINVAL;
- }
- if (!core->resources.fw.cookie)
- core->resources.fw.cookie = subsystem_get("venus");
-
- if (IS_ERR_OR_NULL(core->resources.fw.cookie)) {
- dprintk(VIDC_ERR, "Failed to download firmware\n");
- rc = -ENOMEM;
- goto fail_load_fw;
- }
- /*Clocks can be enabled only after pil_get since
- * gdsc is turned-on in pil_get*/
- rc = msm_comm_enable_clks(core);
- if (rc) {
- dprintk(VIDC_ERR, "Failed to enable clocks: %d\n", rc);
- goto fail_enable_clks;
- }
-
- rc = protect_cp_mem(core);
- if (rc) {
- dprintk(VIDC_ERR, "Failed to protect memory\n");
- goto fail_iommu_attach;
- }
-
- rc = msm_comm_iommu_attach(core);
- if (rc) {
- dprintk(VIDC_ERR, "Failed to attach iommu");
- goto fail_iommu_attach;
- }
- return rc;
-fail_iommu_attach:
- msm_comm_disable_clks(core);
-fail_enable_clks:
- subsystem_put(core->resources.fw.cookie);
- core->resources.fw.cookie = NULL;
-fail_load_fw:
- return rc;
-}
-
-static void msm_comm_unload_fw(struct msm_vidc_core *core)
-{
- if (!core) {
- dprintk(VIDC_ERR, "Invalid paramter: %p\n", core);
- return;
- }
- if (core->resources.fw.cookie) {
- msm_comm_iommu_detach(core);
- msm_comm_disable_clks(core);
- subsystem_put(core->resources.fw.cookie);
- core->resources.fw.cookie = NULL;
- }
-}
-
static inline unsigned long get_ocmem_requirement(u32 height, u32 width)
{
int num_mbs = 0;
@@ -1170,48 +923,19 @@
return 512 * 1024;
}
-static int msm_comm_set_ocmem(struct msm_vidc_core *core,
- struct ocmem_buf *ocmem)
-{
- struct vidc_resource_hdr rhdr;
- int rc = 0;
- if (!core || !ocmem) {
- dprintk(VIDC_ERR, "Invalid params, core:%p, ocmem: %p\n",
- core, ocmem);
- return -EINVAL;
- }
- rhdr.resource_id = VIDC_RESOURCE_OCMEM;
- rhdr.resource_handle = (u32) &core->resources.ocmem;
- rhdr.size = ocmem->len;
- rc = vidc_hal_core_set_resource(core->device, &rhdr, ocmem);
- if (rc) {
- dprintk(VIDC_ERR, "Failed to set OCMEM on driver\n");
- goto ocmem_set_failed;
- }
- dprintk(VIDC_DBG, "OCMEM set, addr = %lx, size: %ld\n",
- ocmem->addr, ocmem->len);
-ocmem_set_failed:
- return rc;
-}
-
static int msm_comm_unset_ocmem(struct msm_vidc_core *core)
{
- struct vidc_resource_hdr rhdr;
int rc = 0;
- if (!core || !core->resources.ocmem.buf) {
- dprintk(VIDC_ERR, "Invalid params, core:%p\n", core);
- return -EINVAL;
- }
if (core->state == VIDC_CORE_INVALID) {
dprintk(VIDC_ERR,
"Core is in bad state. Cannot unset ocmem\n");
return -EIO;
}
- rhdr.resource_id = VIDC_RESOURCE_OCMEM;
- rhdr.resource_handle = (u32) &core->resources.ocmem;
+
init_completion(
&core->completions[SYS_MSG_INDEX(RELEASE_RESOURCE_DONE)]);
- rc = vidc_hal_core_release_resource(core->device, &rhdr);
+
+ rc = venus_hfi_unset_ocmem(core->device);
if (rc) {
dprintk(VIDC_ERR, "Failed to set OCMEM on driver\n");
goto release_ocmem_failed;
@@ -1222,67 +946,18 @@
if (!rc) {
dprintk(VIDC_ERR, "Wait interrupted or timeout: %d\n", rc);
rc = -EIO;
- goto release_ocmem_failed;
}
release_ocmem_failed:
return rc;
}
-static int msm_comm_alloc_ocmem(struct msm_vidc_core *core,
- unsigned long size)
-{
- int rc = 0;
- struct ocmem_buf *ocmem_buffer;
- mutex_lock(&core->sync_lock);
- if (!core || !size) {
- dprintk(VIDC_ERR,
- "Invalid param, core: %p, size: %lu\n", core, size);
- return -EINVAL;
- }
- ocmem_buffer = core->resources.ocmem.buf;
- if (!ocmem_buffer ||
- ocmem_buffer->len < size) {
- ocmem_buffer = ocmem_allocate_nb(OCMEM_VIDEO, size);
- if (IS_ERR_OR_NULL(ocmem_buffer)) {
- dprintk(VIDC_ERR,
- "ocmem_allocate_nb failed: %d\n",
- (u32) ocmem_buffer);
- rc = -ENOMEM;
- }
- core->resources.ocmem.buf = ocmem_buffer;
- rc = msm_comm_set_ocmem(core, ocmem_buffer);
- if (rc) {
- dprintk(VIDC_ERR, "Failed to set ocmem: %d\n", rc);
- goto ocmem_set_failed;
- }
- } else
- dprintk(VIDC_DBG,
- "OCMEM is enough. reqd: %lu, available: %lu\n",
- size, ocmem_buffer->len);
-
-ocmem_set_failed:
- mutex_unlock(&core->sync_lock);
- return rc;
-}
-
-static int msm_comm_free_ocmem(struct msm_vidc_core *core)
-{
- int rc = 0;
- if (core->resources.ocmem.buf) {
- rc = ocmem_free(OCMEM_VIDEO, core->resources.ocmem.buf);
- if (rc)
- dprintk(VIDC_ERR, "Failed to free ocmem\n");
- }
- core->resources.ocmem.buf = NULL;
- return rc;
-}
-
int msm_vidc_ocmem_notify_handler(struct notifier_block *this,
unsigned long event, void *data)
{
struct ocmem_buf *buff = data;
struct msm_vidc_core *core;
- struct msm_vidc_resources *resources;
+ struct venus_hfi_device *device;
+ struct venus_resources *resources;
struct on_chip_mem *ocmem;
int rc = NOTIFY_DONE;
if (event == OCMEM_ALLOC_GROW) {
@@ -1293,10 +968,12 @@
goto bad_notfier;
}
resources = container_of(ocmem,
- struct msm_vidc_resources, ocmem);
- core = container_of(resources,
- struct msm_vidc_core, resources);
- if (msm_comm_set_ocmem(core, buff)) {
+ struct venus_resources, ocmem);
+ device = container_of(resources,
+ struct venus_hfi_device, resources);
+ core = container_of((void *)device,
+ struct msm_vidc_core, device);
+ if (venus_hfi_set_ocmem(core->device, buff)) {
dprintk(VIDC_ERR, "Failed to set ocmem: %d\n", rc);
goto ocmem_set_failed;
}
@@ -1345,6 +1022,12 @@
int rc = 0;
struct msm_vidc_core *core = inst->core;
unsigned long flags;
+ struct venus_hfi_device *device;
+
+ if (!core || !core->device)
+ return -EINVAL;
+ device = core->device;
+
mutex_lock(&core->sync_lock);
if (core->state >= VIDC_CORE_INIT) {
dprintk(VIDC_INFO, "Video core: %d is already in state: %d\n",
@@ -1358,7 +1041,7 @@
goto fail_scale_bus;
}
- rc = msm_comm_load_fw(core);
+ rc = venus_hfi_load_fw(core->device);
if (rc) {
dprintk(VIDC_ERR, "Failed to load video firmware\n");
goto fail_load_fw;
@@ -1370,8 +1053,7 @@
}
init_completion(&core->completions[SYS_MSG_INDEX(SYS_INIT_DONE)]);
- rc = vidc_hal_core_init(core->device,
- core->resources.io_map[NS_MAP].domain);
+ rc = venus_hfi_core_init(core->device);
if (rc) {
dprintk(VIDC_ERR, "Failed to init core, id = %d\n", core->id);
goto fail_core_init;
@@ -1384,7 +1066,7 @@
mutex_unlock(&core->sync_lock);
return rc;
fail_core_init:
- msm_comm_unload_fw(core);
+ venus_hfi_unload_fw(core->device);
fail_load_fw:
msm_comm_unvote_buses(core, DDR_MEM);
fail_scale_bus:
@@ -1406,9 +1088,9 @@
msm_comm_scale_clocks_and_bus(inst);
if (list_empty(&core->instances)) {
msm_comm_unset_ocmem(core);
- msm_comm_free_ocmem(core);
+ venus_hfi_free_ocmem(core->device);
dprintk(VIDC_DBG, "Calling vidc_hal_core_release\n");
- rc = vidc_hal_core_release(core->device);
+ rc = venus_hfi_core_release(core->device);
if (rc) {
dprintk(VIDC_ERR, "Failed to release core, id = %d\n",
core->id);
@@ -1417,7 +1099,7 @@
spin_lock_irqsave(&core->lock, flags);
core->state = VIDC_CORE_UNINIT;
spin_unlock_irqrestore(&core->lock, flags);
- msm_comm_unload_fw(core);
+ venus_hfi_unload_fw(core->device);
msm_comm_unvote_buses(core, DDR_MEM|OCMEM_MEM);
}
core_already_uninited:
@@ -1515,7 +1197,7 @@
}
init_completion(
&inst->completions[SESSION_MSG_INDEX(SESSION_INIT_DONE)]);
- inst->session = vidc_hal_session_init(inst->core->device, (u32) inst,
+ inst->session = venus_hfi_session_init(inst->core->device, (u32) inst,
get_hal_domain(inst->session_type),
get_hal_codec_type(fourcc));
if (!inst->session) {
@@ -1544,7 +1226,9 @@
ocmem_sz = get_ocmem_requirement(inst->prop.height, inst->prop.width);
rc = msm_comm_scale_bus(inst->core, inst->session_type, OCMEM_MEM);
if (!rc) {
- rc = msm_comm_alloc_ocmem(inst->core, ocmem_sz);
+ mutex_lock(&inst->core->sync_lock);
+ rc = venus_hfi_alloc_ocmem(inst->core->device, ocmem_sz);
+ mutex_unlock(&inst->core->sync_lock);
if (rc) {
dprintk(VIDC_WARN,
"Failed to allocate OCMEM. Performance will be impacted\n");
@@ -1554,7 +1238,7 @@
dprintk(VIDC_WARN,
"Failed to vote for OCMEM BW. Performance will be impacted\n");
}
- rc = vidc_hal_session_load_res((void *) inst->session);
+ rc = venus_hfi_session_load_res((void *) inst->session);
if (rc) {
dprintk(VIDC_ERR,
"Failed to send load resources\n");
@@ -1576,7 +1260,7 @@
}
init_completion(
&inst->completions[SESSION_MSG_INDEX(SESSION_START_DONE)]);
- rc = vidc_hal_session_start((void *) inst->session);
+ rc = venus_hfi_session_start((void *) inst->session);
if (rc) {
dprintk(VIDC_ERR,
"Failed to send start\n");
@@ -1599,7 +1283,7 @@
dprintk(VIDC_DBG, "Send Stop to hal\n");
init_completion(
&inst->completions[SESSION_MSG_INDEX(SESSION_STOP_DONE)]);
- rc = vidc_hal_session_stop((void *) inst->session);
+ rc = venus_hfi_session_stop((void *) inst->session);
if (rc) {
dprintk(VIDC_ERR, "Failed to send stop\n");
goto exit;
@@ -1622,7 +1306,7 @@
"Send release res to hal\n");
init_completion(
&inst->completions[SESSION_MSG_INDEX(SESSION_RELEASE_RESOURCE_DONE)]);
- rc = vidc_hal_session_release_res((void *) inst->session);
+ rc = venus_hfi_session_release_res((void *) inst->session);
if (rc) {
dprintk(VIDC_ERR,
"Failed to send release resources\n");
@@ -1646,7 +1330,7 @@
"Send session close to hal\n");
init_completion(
&inst->completions[SESSION_MSG_INDEX(SESSION_END_DONE)]);
- rc = vidc_hal_session_end((void *) inst->session);
+ rc = venus_hfi_session_end((void *) inst->session);
if (rc) {
dprintk(VIDC_ERR,
"Failed to send close\n");
@@ -1850,7 +1534,7 @@
dprintk(VIDC_DBG,
"Sending etb to hal: Alloc: %d :filled: %d\n",
frame_data.alloc_len, frame_data.filled_len);
- rc = vidc_hal_session_etb((void *) inst->session,
+ rc = venus_hfi_session_etb((void *) inst->session,
&frame_data);
if (!rc)
msm_vidc_debugfs_update(inst,
@@ -1880,7 +1564,7 @@
seq_hdr.seq_hdr = (u8 *) vb->v4l2_planes[0].
m.userptr;
seq_hdr.seq_hdr_len = vb->v4l2_planes[0].length;
- rc = vidc_hal_session_get_seq_hdr((void *)
+ rc = venus_hfi_session_get_seq_hdr((void *)
inst->session, &seq_hdr);
if (!rc) {
inst->vb2_seq_hdr = vb;
@@ -1888,7 +1572,7 @@
inst->vb2_seq_hdr);
}
} else {
- rc = vidc_hal_session_ftb((void *)
+ rc = venus_hfi_session_ftb((void *)
inst->session, &frame_data);
if (!rc)
msm_vidc_debugfs_update(inst,
@@ -1920,7 +1604,7 @@
}
init_completion(
&inst->completions[SESSION_MSG_INDEX(SESSION_PROPERTY_INFO)]);
- rc = vidc_hal_session_get_buf_req((void *) inst->session);
+ rc = venus_hfi_session_get_buf_req((void *) inst->session);
if (rc) {
dprintk(VIDC_ERR, "Failed to get property\n");
goto exit;
@@ -1975,7 +1659,7 @@
init_completion(
&inst->completions[SESSION_MSG_INDEX
(SESSION_RELEASE_BUFFER_DONE)]);
- rc = vidc_hal_session_release_buffers(
+ rc = venus_hfi_session_release_buffers(
(void *) inst->session,
&buffer_info);
if (rc)
@@ -2035,7 +1719,7 @@
init_completion(
&inst->completions[SESSION_MSG_INDEX
(SESSION_RELEASE_BUFFER_DONE)]);
- rc = vidc_hal_session_release_buffers(
+ rc = venus_hfi_session_release_buffers(
(void *) inst->session,
&buffer_info);
if (rc)
@@ -2073,7 +1757,7 @@
rc = -EAGAIN;
goto exit;
}
- rc = vidc_hal_session_set_property((void *)inst->session,
+ rc = venus_hfi_session_set_property((void *)inst->session,
ptype, pdata);
if (rc)
dprintk(VIDC_ERR, "Failed to set hal property for framesize\n");
@@ -2091,9 +1775,16 @@
unsigned long flags;
int domain;
unsigned long smem_flags = 0;
- struct hal_buffer_requirements *scratch_buf =
- &inst->buff_req.buffer[HAL_BUFFER_INTERNAL_SCRATCH];
+ struct hal_buffer_requirements *scratch_buf;
int i;
+ struct venus_hfi_device *device;
+
+ if (!inst || !inst->core || !inst->core->device)
+ return -EINVAL;
+
+ device = inst->core->device;
+ scratch_buf =
+ &inst->buff_req.buffer[HAL_BUFFER_INTERNAL_SCRATCH];
dprintk(VIDC_DBG,
"scratch: num = %d, size = %d\n",
scratch_buf->buffer_count_actual,
@@ -2101,10 +1792,10 @@
if (msm_comm_release_scratch_buffers(inst))
dprintk(VIDC_WARN, "Failed to release scratch buffers\n");
if (inst->mode == VIDC_SECURE) {
- domain = inst->core->resources.io_map[CP_MAP].domain;
+ domain = venus_hfi_get_domain(device, CP_MAP);
smem_flags |= SMEM_SECURE;
} else
- domain = inst->core->resources.io_map[NS_MAP].domain;
+ domain = venus_hfi_get_domain(device, NS_MAP);
if (scratch_buf->buffer_size) {
for (i = 0; i < scratch_buf->buffer_count_actual;
@@ -2131,7 +1822,7 @@
buffer_info.align_device_addr = handle->device_addr;
dprintk(VIDC_DBG, "Scratch buffer address: %x",
buffer_info.align_device_addr);
- rc = vidc_hal_session_set_buffers(
+ rc = venus_hfi_session_set_buffers(
(void *) inst->session, &buffer_info);
if (rc) {
dprintk(VIDC_ERR,
@@ -2161,9 +1852,17 @@
unsigned long flags;
unsigned long smem_flags = 0;
int domain;
- struct hal_buffer_requirements *persist_buf =
- &inst->buff_req.buffer[HAL_BUFFER_INTERNAL_PERSIST];
+ struct hal_buffer_requirements *persist_buf;
int i;
+ struct venus_hfi_device *device;
+
+ if (!inst || !inst->core || !inst->core->device)
+ return -EINVAL;
+
+ device = inst->core->device;
+
+ persist_buf =
+ &inst->buff_req.buffer[HAL_BUFFER_INTERNAL_PERSIST];
dprintk(VIDC_DBG,
"persist: num = %d, size = %d\n",
persist_buf->buffer_count_actual,
@@ -2175,10 +1874,10 @@
}
if (inst->mode == VIDC_SECURE) {
- domain = inst->core->resources.io_map[CP_MAP].domain;
+ domain = venus_hfi_get_domain(device, CP_MAP);
flags |= SMEM_SECURE;
} else
- domain = inst->core->resources.io_map[NS_MAP].domain;
+ domain = venus_hfi_get_domain(device, NS_MAP);
if (persist_buf->buffer_size) {
for (i = 0; i < persist_buf->buffer_count_actual; i++) {
@@ -2204,7 +1903,7 @@
buffer_info.align_device_addr = handle->device_addr;
dprintk(VIDC_DBG, "Persist buffer address: %x",
buffer_info.align_device_addr);
- rc = vidc_hal_session_set_buffers(
+ rc = venus_hfi_session_set_buffers(
(void *) inst->session, &buffer_info);
if (rc) {
dprintk(VIDC_ERR,
@@ -2315,7 +2014,7 @@
dprintk(VIDC_WARN,
"FLUSH BUG: Pending q not empty! It should be empty\n");
}
- rc = vidc_hal_session_flush(inst->session,
+ rc = venus_hfi_session_flush(inst->session,
HAL_FLUSH_OUTPUT);
} else {
if (!list_empty(&inst->pendingq)) {
@@ -2336,7 +2035,7 @@
kfree(temp);
}
}
- rc = vidc_hal_session_flush(inst->session,
+ rc = venus_hfi_session_flush(inst->session,
HAL_FLUSH_ALL);
}
mutex_unlock(&inst->sync_lock);
diff --git a/drivers/media/video/msm_vidc/msm_vidc_debug.c b/drivers/media/video/msm_vidc/msm_vidc_debug.c
index 133bfb5..bdf146e 100644
--- a/drivers/media/video/msm_vidc/msm_vidc_debug.c
+++ b/drivers/media/video/msm_vidc/msm_vidc_debug.c
@@ -12,10 +12,11 @@
*/
#include "msm_vidc_debug.h"
+#include "venus_hfi.h"
#define MAX_DBG_BUF_SIZE 4096
-int msm_vidc_debug;
-int msm_fw_debug;
+int msm_vidc_debug = 0x3;
+int msm_fw_debug = 0x18;
struct debug_buffer {
char ptr[MAX_DBG_BUF_SIZE];
@@ -52,20 +53,22 @@
size_t count, loff_t *ppos)
{
struct msm_vidc_core *core = file->private_data;
+ struct venus_hfi_device *device;
int i = 0;
- if (!core) {
+ if (!core || !core->device) {
dprintk(VIDC_ERR, "Invalid params, core: %p\n", core);
return 0;
}
+ device = core->device;
INIT_DBG_BUF(dbg_buf);
write_str(&dbg_buf, "===============================\n");
write_str(&dbg_buf, "CORE %d: 0x%p\n", core->id, core);
write_str(&dbg_buf, "===============================\n");
write_str(&dbg_buf, "state: %d\n", core->state);
- write_str(&dbg_buf, "base addr: 0x%x\n", core->base_addr);
- write_str(&dbg_buf, "register_base: 0x%x\n", core->register_base);
- write_str(&dbg_buf, "register_size: %u\n", core->register_size);
- write_str(&dbg_buf, "irq: %u\n", core->irq);
+ write_str(&dbg_buf, "base addr: 0x%x\n", device->base_addr);
+ write_str(&dbg_buf, "register_base: 0x%x\n", device->register_base);
+ write_str(&dbg_buf, "register_size: %u\n", device->register_size);
+ write_str(&dbg_buf, "irq: %u\n", device->irq);
for (i = SYS_MSG_START; i < SYS_MSG_END; i++) {
write_str(&dbg_buf, "completions[%d]: %s\n", i,
completion_done(&core->completions[SYS_MSG_INDEX(i)]) ?
@@ -89,8 +92,7 @@
dprintk(VIDC_ERR, "Invalid params, core: %p\n", core);
goto failed_create_dir;
}
- msm_vidc_debug = 0;
- msm_fw_debug = 0;
+
snprintf(debugfs_name, MAX_DEBUGFS_NAME, "core%d", core->id);
dir = debugfs_create_dir(debugfs_name, parent);
if (!dir) {
@@ -106,13 +108,11 @@
dprintk(VIDC_ERR, "debugfs_create_file: fail\n");
goto failed_create_dir;
}
- msm_vidc_debug = 0x3;
if (!debugfs_create_u32("fw_level", S_IRUGO | S_IWUSR,
parent, &msm_fw_debug)) {
dprintk(VIDC_ERR, "debugfs_create_file: fail\n");
goto failed_create_dir;
}
- msm_fw_debug = 0x18;
failed_create_dir:
return dir;
}
diff --git a/drivers/media/video/msm_vidc/msm_vidc_internal.h b/drivers/media/video/msm_vidc/msm_vidc_internal.h
index d8a3304..14cef1e 100644
--- a/drivers/media/video/msm_vidc/msm_vidc_internal.h
+++ b/drivers/media/video/msm_vidc/msm_vidc_internal.h
@@ -18,7 +18,6 @@
#include <linux/spinlock.h>
#include <linux/types.h>
#include <linux/completion.h>
-#include <linux/clk.h>
#include <linux/wait.h>
#include <mach/msm_bus.h>
#include <mach/msm_bus_board.h>
@@ -117,54 +116,6 @@
struct video_device vdev;
};
-struct msm_vidc_fw {
- void *cookie;
-};
-
-enum vidc_clocks {
- VCODEC_CLK,
- VCODEC_AHB_CLK,
- VCODEC_AXI_CLK,
- VCODEC_OCMEM_CLK,
- VCODEC_MAX_CLKS
-};
-
-struct load_freq_table {
- u32 load;
- u32 freq;
-};
-
-enum mem_type {
- DDR_MEM = 0x1,
- OCMEM_MEM = 0x2,
-};
-
-struct core_clock {
- char name[MAX_NAME_LENGTH];
- struct clk *clk;
- u32 count;
- struct load_freq_table load_freq_tbl[8];
-};
-
-struct vidc_bus_info {
- u32 ddr_handle[MSM_VIDC_MAX_DEVICES];
- u32 ocmem_handle[MSM_VIDC_MAX_DEVICES];
-};
-
-struct on_chip_mem {
- struct ocmem_buf *buf;
- struct notifier_block vidc_ocmem_nb;
- void *handle;
-};
-
-struct msm_vidc_resources {
- struct msm_vidc_fw fw;
- struct msm_vidc_iommu_info io_map[MAX_MAP];
- struct core_clock clock[VCODEC_MAX_CLKS];
- struct vidc_bus_info bus_info;
- struct on_chip_mem ocmem;
-};
-
struct session_prop {
u32 width;
u32 height;
@@ -224,12 +175,7 @@
spinlock_t lock;
struct list_head instances;
struct dentry *debugfs_root;
- u32 base_addr;
- u32 register_base;
- u32 register_size;
- u32 irq;
enum vidc_core_state state;
- struct msm_vidc_resources resources;
struct completion completions[SYS_MSG_END - SYS_MSG_START + 1];
};
diff --git a/drivers/media/video/msm_vidc/venus_hfi.c b/drivers/media/video/msm_vidc/venus_hfi.c
index 4a5f340..8f0902f 100644
--- a/drivers/media/video/msm_vidc/venus_hfi.c
+++ b/drivers/media/video/msm_vidc/venus_hfi.c
@@ -16,8 +16,13 @@
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/delay.h>
+#include <linux/of.h>
+#include <linux/iommu.h>
+#include <mach/iommu.h>
+#include <mach/iommu_domains.h>
#include <mach/ocmem.h>
-
+#include <mach/scm.h>
+#include <mach/subsystem_restart.h>
#include <asm/memory.h>
#include "hfi_packetization.h"
#include "venus_hfi.h"
@@ -27,12 +32,428 @@
#define FIRMWARE_SIZE 0X00A00000
#define REG_ADDR_OFFSET_BITMASK 0x000FFFFF
-/*Workaround for virtio */
-#define HFI_VIRTIO_FW_BIAS 0x0
+/*Workaround for simulator */
+#define HFI_SIM_FW_BIAS 0x0
+
+#define SHARED_QSIZE 0x1000000
struct hal_device_data hal_ctxt;
-static void hal_virtio_modify_cmd_packet(u8 *packet)
+static struct msm_bus_vectors enc_ocmem_init_vectors[] = {
+ {
+ .src = MSM_BUS_MASTER_VIDEO_P0_OCMEM,
+ .dst = MSM_BUS_SLAVE_OCMEM,
+ .ab = 0,
+ .ib = 0,
+ },
+};
+
+static struct msm_bus_vectors enc_ocmem_perf1_vectors[] = {
+ {
+ .src = MSM_BUS_MASTER_VIDEO_P0_OCMEM,
+ .dst = MSM_BUS_SLAVE_OCMEM,
+ .ab = 138200000,
+ .ib = 1222000000,
+ },
+};
+
+static struct msm_bus_vectors enc_ocmem_perf2_vectors[] = {
+ {
+ .src = MSM_BUS_MASTER_VIDEO_P0_OCMEM,
+ .dst = MSM_BUS_SLAVE_OCMEM,
+ .ab = 414700000,
+ .ib = 1222000000,
+ },
+};
+
+static struct msm_bus_vectors enc_ocmem_perf3_vectors[] = {
+ {
+ .src = MSM_BUS_MASTER_VIDEO_P0_OCMEM,
+ .dst = MSM_BUS_SLAVE_OCMEM,
+ .ab = 940000000,
+ .ib = 2444000000U,
+ },
+};
+
+static struct msm_bus_vectors enc_ocmem_perf4_vectors[] = {
+ {
+ .src = MSM_BUS_MASTER_VIDEO_P0_OCMEM,
+ .dst = MSM_BUS_SLAVE_OCMEM,
+ .ab = 1880000000,
+ .ib = 2444000000U,
+ },
+};
+
+static struct msm_bus_vectors enc_ocmem_perf5_vectors[] = {
+ {
+ .src = MSM_BUS_MASTER_VIDEO_P0_OCMEM,
+ .dst = MSM_BUS_SLAVE_OCMEM,
+ .ab = 3008000000U,
+ .ib = 3910400000U,
+ },
+};
+
+static struct msm_bus_vectors enc_ocmem_perf6_vectors[] = {
+ {
+ .src = MSM_BUS_MASTER_VIDEO_P0_OCMEM,
+ .dst = MSM_BUS_SLAVE_OCMEM,
+ .ab = 3760000000U,
+ .ib = 4888000000ULL,
+ },
+};
+
+static struct msm_bus_vectors dec_ocmem_init_vectors[] = {
+ {
+ .src = MSM_BUS_MASTER_VIDEO_P0_OCMEM,
+ .dst = MSM_BUS_SLAVE_OCMEM,
+ .ab = 0,
+ .ib = 0,
+ },
+};
+
+static struct msm_bus_vectors dec_ocmem_perf1_vectors[] = {
+ {
+ .src = MSM_BUS_MASTER_VIDEO_P0_OCMEM,
+ .dst = MSM_BUS_SLAVE_OCMEM,
+ .ab = 176900000,
+ .ib = 1556640000,
+ },
+};
+
+static struct msm_bus_vectors dec_ocmem_perf2_vectors[] = {
+ {
+ .src = MSM_BUS_MASTER_VIDEO_P0_OCMEM,
+ .dst = MSM_BUS_SLAVE_OCMEM,
+ .ab = 456200000,
+ .ib = 1556640000,
+ },
+};
+
+static struct msm_bus_vectors dec_ocmem_perf3_vectors[] = {
+ {
+ .src = MSM_BUS_MASTER_VIDEO_P0_OCMEM,
+ .dst = MSM_BUS_SLAVE_OCMEM,
+ .ab = 864800000,
+ .ib = 1556640000,
+ },
+};
+
+static struct msm_bus_vectors dec_ocmem_perf4_vectors[] = {
+ {
+ .src = MSM_BUS_MASTER_VIDEO_P0_OCMEM,
+ .dst = MSM_BUS_SLAVE_OCMEM,
+ .ab = 1729600000,
+ .ib = 3113280000U,
+ },
+};
+
+static struct msm_bus_vectors dec_ocmem_perf5_vectors[] = {
+ {
+ .src = MSM_BUS_MASTER_VIDEO_P0_OCMEM,
+ .dst = MSM_BUS_SLAVE_OCMEM,
+ .ab = 2767360000U,
+ .ib = 4981248000ULL,
+ },
+};
+
+static struct msm_bus_vectors dec_ocmem_perf6_vectors[] = {
+ {
+ .src = MSM_BUS_MASTER_VIDEO_P0_OCMEM,
+ .dst = MSM_BUS_SLAVE_OCMEM,
+ .ab = 3459200000U,
+ .ib = 6226560000ULL,
+ },
+};
+
+static struct msm_bus_paths enc_ocmem_perf_vectors[] = {
+ {
+ ARRAY_SIZE(enc_ocmem_init_vectors),
+ enc_ocmem_init_vectors,
+ },
+ {
+ ARRAY_SIZE(enc_ocmem_perf1_vectors),
+ enc_ocmem_perf1_vectors,
+ },
+ {
+ ARRAY_SIZE(enc_ocmem_perf2_vectors),
+ enc_ocmem_perf2_vectors,
+ },
+ {
+ ARRAY_SIZE(enc_ocmem_perf3_vectors),
+ enc_ocmem_perf3_vectors,
+ },
+ {
+ ARRAY_SIZE(enc_ocmem_perf4_vectors),
+ enc_ocmem_perf4_vectors,
+ },
+ {
+ ARRAY_SIZE(enc_ocmem_perf5_vectors),
+ enc_ocmem_perf5_vectors,
+ },
+ {
+ ARRAY_SIZE(enc_ocmem_perf6_vectors),
+ enc_ocmem_perf6_vectors,
+ },
+};
+
+static struct msm_bus_paths dec_ocmem_perf_vectors[] = {
+ {
+ ARRAY_SIZE(dec_ocmem_init_vectors),
+ dec_ocmem_init_vectors,
+ },
+ {
+ ARRAY_SIZE(dec_ocmem_perf1_vectors),
+ dec_ocmem_perf1_vectors,
+ },
+ {
+ ARRAY_SIZE(dec_ocmem_perf2_vectors),
+ dec_ocmem_perf2_vectors,
+ },
+ {
+ ARRAY_SIZE(dec_ocmem_perf3_vectors),
+ dec_ocmem_perf3_vectors,
+ },
+ {
+ ARRAY_SIZE(dec_ocmem_perf4_vectors),
+ dec_ocmem_perf4_vectors,
+ },
+ {
+ ARRAY_SIZE(dec_ocmem_perf5_vectors),
+ dec_ocmem_perf5_vectors,
+ },
+ {
+ ARRAY_SIZE(dec_ocmem_perf6_vectors),
+ dec_ocmem_perf6_vectors,
+ },
+};
+
+
+static struct msm_bus_scale_pdata enc_ocmem_bus_data = {
+ .usecase = enc_ocmem_perf_vectors,
+ .num_usecases = ARRAY_SIZE(enc_ocmem_perf_vectors),
+ .name = "msm_vidc_enc_ocmem",
+};
+
+static struct msm_bus_scale_pdata dec_ocmem_bus_data = {
+ .usecase = dec_ocmem_perf_vectors,
+ .num_usecases = ARRAY_SIZE(dec_ocmem_perf_vectors),
+ .name = "msm_vidc_dec_ocmem",
+};
+
+static struct msm_bus_vectors enc_ddr_init_vectors[] = {
+ {
+ .src = MSM_BUS_MASTER_VIDEO_P0,
+ .dst = MSM_BUS_SLAVE_EBI_CH0,
+ .ab = 0,
+ .ib = 0,
+ },
+};
+
+
+static struct msm_bus_vectors enc_ddr_perf1_vectors[] = {
+ {
+ .src = MSM_BUS_MASTER_VIDEO_P0,
+ .dst = MSM_BUS_SLAVE_EBI_CH0,
+ .ab = 60000000,
+ .ib = 664950000,
+ },
+};
+
+static struct msm_bus_vectors enc_ddr_perf2_vectors[] = {
+ {
+ .src = MSM_BUS_MASTER_VIDEO_P0,
+ .dst = MSM_BUS_SLAVE_EBI_CH0,
+ .ab = 181000000,
+ .ib = 664950000,
+ },
+};
+
+static struct msm_bus_vectors enc_ddr_perf3_vectors[] = {
+ {
+ .src = MSM_BUS_MASTER_VIDEO_P0,
+ .dst = MSM_BUS_SLAVE_EBI_CH0,
+ .ab = 403000000,
+ .ib = 664950000,
+ },
+};
+
+static struct msm_bus_vectors enc_ddr_perf4_vectors[] = {
+ {
+ .src = MSM_BUS_MASTER_VIDEO_P0,
+ .dst = MSM_BUS_SLAVE_EBI_CH0,
+ .ab = 806000000,
+ .ib = 1329900000,
+ },
+};
+
+static struct msm_bus_vectors enc_ddr_perf5_vectors[] = {
+ {
+ .src = MSM_BUS_MASTER_VIDEO_P0,
+ .dst = MSM_BUS_SLAVE_EBI_CH0,
+ .ab = 1289600000,
+ .ib = 2127840000U,
+ },
+};
+
+static struct msm_bus_vectors enc_ddr_perf6_vectors[] = {
+ {
+ .src = MSM_BUS_MASTER_VIDEO_P0,
+ .dst = MSM_BUS_SLAVE_EBI_CH0,
+ .ab = 161200000,
+ .ib = 6400000000ULL,
+ },
+};
+
+static struct msm_bus_vectors dec_ddr_init_vectors[] = {
+ {
+ .src = MSM_BUS_MASTER_VIDEO_P0,
+ .dst = MSM_BUS_SLAVE_EBI_CH0,
+ .ab = 0,
+ .ib = 0,
+ },
+};
+
+static struct msm_bus_vectors dec_ddr_perf1_vectors[] = {
+ {
+ .src = MSM_BUS_MASTER_VIDEO_P0,
+ .dst = MSM_BUS_SLAVE_EBI_CH0,
+ .ab = 110000000,
+ .ib = 909000000,
+ },
+};
+
+static struct msm_bus_vectors dec_ddr_perf2_vectors[] = {
+ {
+ .src = MSM_BUS_MASTER_VIDEO_P0,
+ .dst = MSM_BUS_SLAVE_EBI_CH0,
+ .ab = 268000000,
+ .ib = 909000000,
+ },
+};
+
+static struct msm_bus_vectors dec_ddr_perf3_vectors[] = {
+ {
+ .src = MSM_BUS_MASTER_VIDEO_P0,
+ .dst = MSM_BUS_SLAVE_EBI_CH0,
+ .ab = 505000000,
+ .ib = 909000000,
+ },
+};
+
+static struct msm_bus_vectors dec_ddr_perf4_vectors[] = {
+ {
+ .src = MSM_BUS_MASTER_VIDEO_P0,
+ .dst = MSM_BUS_SLAVE_EBI_CH0,
+ .ab = 1010000000,
+ .ib = 1818000000,
+ },
+};
+
+static struct msm_bus_vectors dec_ddr_perf5_vectors[] = {
+ {
+ .src = MSM_BUS_MASTER_VIDEO_P0,
+ .dst = MSM_BUS_SLAVE_EBI_CH0,
+ .ab = 1616000000,
+ .ib = 2908800000U,
+ },
+};
+
+static struct msm_bus_vectors dec_ddr_perf6_vectors[] = {
+ {
+ .src = MSM_BUS_MASTER_VIDEO_P0,
+ .dst = MSM_BUS_SLAVE_EBI_CH0,
+ .ab = 2020000000U,
+ .ib = 6400000000ULL,
+ },
+};
+
+static struct msm_bus_paths enc_ddr_perf_vectors[] = {
+ {
+ ARRAY_SIZE(enc_ddr_init_vectors),
+ enc_ddr_init_vectors,
+ },
+ {
+ ARRAY_SIZE(enc_ddr_perf1_vectors),
+ enc_ddr_perf1_vectors,
+ },
+ {
+ ARRAY_SIZE(enc_ddr_perf2_vectors),
+ enc_ddr_perf2_vectors,
+ },
+ {
+ ARRAY_SIZE(enc_ddr_perf3_vectors),
+ enc_ddr_perf3_vectors,
+ },
+ {
+ ARRAY_SIZE(enc_ddr_perf4_vectors),
+ enc_ddr_perf4_vectors,
+ },
+ {
+ ARRAY_SIZE(enc_ddr_perf5_vectors),
+ enc_ddr_perf5_vectors,
+ },
+ {
+ ARRAY_SIZE(enc_ddr_perf6_vectors),
+ enc_ddr_perf6_vectors,
+ },
+};
+
+static struct msm_bus_paths dec_ddr_perf_vectors[] = {
+ {
+ ARRAY_SIZE(dec_ddr_init_vectors),
+ dec_ddr_init_vectors,
+ },
+ {
+ ARRAY_SIZE(dec_ddr_perf1_vectors),
+ dec_ddr_perf1_vectors,
+ },
+ {
+ ARRAY_SIZE(dec_ddr_perf2_vectors),
+ dec_ddr_perf2_vectors,
+ },
+ {
+ ARRAY_SIZE(dec_ddr_perf3_vectors),
+ dec_ddr_perf3_vectors,
+ },
+ {
+ ARRAY_SIZE(dec_ddr_perf4_vectors),
+ dec_ddr_perf4_vectors,
+ },
+ {
+ ARRAY_SIZE(dec_ddr_perf5_vectors),
+ dec_ddr_perf5_vectors,
+ },
+ {
+ ARRAY_SIZE(dec_ddr_perf6_vectors),
+ dec_ddr_perf6_vectors,
+ },
+};
+
+static struct msm_bus_scale_pdata enc_ddr_bus_data = {
+ .usecase = enc_ddr_perf_vectors,
+ .num_usecases = ARRAY_SIZE(enc_ddr_perf_vectors),
+ .name = "msm_vidc_enc_ddr",
+};
+
+static struct msm_bus_scale_pdata dec_ddr_bus_data = {
+ .usecase = dec_ddr_perf_vectors,
+ .num_usecases = ARRAY_SIZE(dec_ddr_perf_vectors),
+ .name = "msm_vidc_dec_ddr",
+};
+
+#define TZBSP_MEM_PROTECT_VIDEO_VAR 0x8
+struct tzbsp_memprot {
+ u32 cp_start;
+ u32 cp_size;
+ u32 cp_nonpixel_start;
+ u32 cp_nonpixel_size;
+};
+
+struct tzbsp_resp {
+ int ret;
+};
+
+static void venus_hfi_sim_modify_cmd_packet(u8 *packet)
{
struct hfi_cmd_sys_session_init_packet *sys_init;
struct hal_session *sess;
@@ -52,21 +473,21 @@
*pkt = (struct
hfi_cmd_session_empty_buffer_compressed_packet
*) packet;
- pkt->packet_buffer -= HFI_VIRTIO_FW_BIAS;
+ pkt->packet_buffer -= HFI_SIM_FW_BIAS;
} else {
struct
hfi_cmd_session_empty_buffer_uncompressed_plane0_packet
*pkt = (struct
hfi_cmd_session_empty_buffer_uncompressed_plane0_packet
*) packet;
- pkt->packet_buffer -= HFI_VIRTIO_FW_BIAS;
+ pkt->packet_buffer -= HFI_SIM_FW_BIAS;
}
break;
case HFI_CMD_SESSION_FILL_BUFFER:
{
struct hfi_cmd_session_fill_buffer_packet *pkt =
(struct hfi_cmd_session_fill_buffer_packet *)packet;
- pkt->packet_buffer -= HFI_VIRTIO_FW_BIAS;
+ pkt->packet_buffer -= HFI_SIM_FW_BIAS;
break;
}
case HFI_CMD_SESSION_SET_BUFFERS:
@@ -77,11 +498,11 @@
(pkt->buffer_type == HFI_BUFFER_OUTPUT2)) {
struct hfi_buffer_info *buff;
buff = (struct hfi_buffer_info *) pkt->rg_buffer_info;
- buff->buffer_addr -= HFI_VIRTIO_FW_BIAS;
- buff->extra_data_addr -= HFI_VIRTIO_FW_BIAS;
+ buff->buffer_addr -= HFI_SIM_FW_BIAS;
+ buff->extra_data_addr -= HFI_SIM_FW_BIAS;
} else {
for (i = 0; i < pkt->num_buffers; i++)
- pkt->rg_buffer_info[i] -= HFI_VIRTIO_FW_BIAS;
+ pkt->rg_buffer_info[i] -= HFI_SIM_FW_BIAS;
}
break;
}
@@ -93,11 +514,11 @@
(pkt->buffer_type == HFI_BUFFER_OUTPUT2)) {
struct hfi_buffer_info *buff;
buff = (struct hfi_buffer_info *) pkt->rg_buffer_info;
- buff->buffer_addr -= HFI_VIRTIO_FW_BIAS;
- buff->extra_data_addr -= HFI_VIRTIO_FW_BIAS;
+ buff->buffer_addr -= HFI_SIM_FW_BIAS;
+ buff->extra_data_addr -= HFI_SIM_FW_BIAS;
} else {
for (i = 0; i < pkt->num_buffers; i++)
- pkt->rg_buffer_info[i] -= HFI_VIRTIO_FW_BIAS;
+ pkt->rg_buffer_info[i] -= HFI_SIM_FW_BIAS;
}
break;
}
@@ -106,7 +527,7 @@
struct hfi_cmd_session_parse_sequence_header_packet *pkt =
(struct hfi_cmd_session_parse_sequence_header_packet *)
packet;
- pkt->packet_buffer -= HFI_VIRTIO_FW_BIAS;
+ pkt->packet_buffer -= HFI_SIM_FW_BIAS;
break;
}
case HFI_CMD_SESSION_GET_SEQUENCE_HEADER:
@@ -114,7 +535,7 @@
struct hfi_cmd_session_get_sequence_header_packet *pkt =
(struct hfi_cmd_session_get_sequence_header_packet *)
packet;
- pkt->packet_buffer -= HFI_VIRTIO_FW_BIAS;
+ pkt->packet_buffer -= HFI_SIM_FW_BIAS;
break;
}
default:
@@ -122,7 +543,7 @@
}
}
-static int write_queue(void *info, u8 *packet, u32 *rx_req_is_set)
+static int venus_hfi_write_queue(void *info, u8 *packet, u32 *rx_req_is_set)
{
struct hfi_queue_header *queue;
u32 packet_size_in_words, new_write_idx;
@@ -136,7 +557,7 @@
}
qinfo = (struct vidc_iface_q_info *) info;
- hal_virtio_modify_cmd_packet(packet);
+ venus_hfi_sim_modify_cmd_packet(packet);
queue = (struct hfi_queue_header *) qinfo->q_hdr;
@@ -188,7 +609,7 @@
return 0;
}
-static void hal_virtio_modify_msg_packet(u8 *packet)
+static void venus_hfi_hal_sim_modify_msg_packet(u8 *packet)
{
struct hfi_msg_sys_session_init_done_packet *sys_idle;
struct hal_session *sess;
@@ -209,21 +630,21 @@
*pkt_uc = (struct
hfi_msg_session_fbd_uncompressed_plane0_packet
*) packet;
- pkt_uc->packet_buffer += HFI_VIRTIO_FW_BIAS;
+ pkt_uc->packet_buffer += HFI_SIM_FW_BIAS;
} else {
struct
hfi_msg_session_fill_buffer_done_compressed_packet
*pkt = (struct
hfi_msg_session_fill_buffer_done_compressed_packet
*) packet;
- pkt->packet_buffer += HFI_VIRTIO_FW_BIAS;
+ pkt->packet_buffer += HFI_SIM_FW_BIAS;
}
break;
case HFI_MSG_SESSION_EMPTY_BUFFER_DONE:
{
struct hfi_msg_session_empty_buffer_done_packet *pkt =
(struct hfi_msg_session_empty_buffer_done_packet *)packet;
- pkt->packet_buffer += HFI_VIRTIO_FW_BIAS;
+ pkt->packet_buffer += HFI_SIM_FW_BIAS;
break;
}
case HFI_MSG_SESSION_GET_SEQUENCE_HEADER_DONE:
@@ -233,7 +654,7 @@
*pkt =
(struct hfi_msg_session_get_sequence_header_done_packet *)
packet;
- pkt->sequence_header += HFI_VIRTIO_FW_BIAS;
+ pkt->sequence_header += HFI_SIM_FW_BIAS;
break;
}
default:
@@ -241,7 +662,7 @@
}
}
-static int read_queue(void *info, u8 *packet, u32 *pb_tx_req_is_set)
+static int venus_hfi_read_queue(void *info, u8 *packet, u32 *pb_tx_req_is_set)
{
struct hfi_queue_header *queue;
u32 packet_size_in_words, new_read_idx;
@@ -299,13 +720,13 @@
queue->qhdr_rx_req = 1;
*pb_tx_req_is_set = (1 == queue->qhdr_tx_req) ? 1 : 0;
- hal_virtio_modify_msg_packet(packet);
+ venus_hfi_hal_sim_modify_msg_packet(packet);
dprintk(VIDC_DBG, "Out : ");
return 0;
}
-static int vidc_hal_alloc(void *mem, void *clnt, u32 size, u32 align, u32 flags,
- int domain)
+static int venus_hfi_alloc(void *mem, void *clnt, u32 size, u32 align,
+ u32 flags, int domain)
{
struct vidc_mem_addr *vmem;
struct msm_smem *alloc;
@@ -330,7 +751,7 @@
dprintk(VIDC_ERR, "NOTE: Failed to clean caches\n");
goto fail_clean_cache;
}
- dprintk(VIDC_DBG, "vidc_hal_alloc:ptr=%p,size=%d",
+ dprintk(VIDC_DBG, "venus_hfi_alloc:ptr=%p,size=%d",
alloc->kvaddr, size);
vmem->mem_size = alloc->size;
vmem->mem_data = alloc;
@@ -343,12 +764,13 @@
return rc;
}
-static void vidc_hal_free(struct smem_client *clnt, struct msm_smem *mem)
+static void venus_hfi_free(struct smem_client *clnt, struct msm_smem *mem)
{
msm_smem_free(clnt, mem);
}
-static void write_register(u8 *base_addr, u32 reg, u32 value, u8 *vaddr)
+static void venus_hfi_write_register(u8 *base_addr, u32 reg,
+ u32 value, u8 *vaddr)
{
u32 hwiosymaddr = reg;
@@ -360,14 +782,14 @@
(struct hfi_queue_table_header *)vaddr;
qhdr = VIDC_IFACEQ_GET_QHDR_START_ADDR(qtbl_hdr, 0);
- qhdr->qhdr_start_addr -= HFI_VIRTIO_FW_BIAS;
+ qhdr->qhdr_start_addr -= HFI_SIM_FW_BIAS;
qhdr = VIDC_IFACEQ_GET_QHDR_START_ADDR(qtbl_hdr, 1);
- qhdr->qhdr_start_addr -= HFI_VIRTIO_FW_BIAS;
+ qhdr->qhdr_start_addr -= HFI_SIM_FW_BIAS;
qhdr = VIDC_IFACEQ_GET_QHDR_START_ADDR(qtbl_hdr, 2);
- qhdr->qhdr_start_addr -= HFI_VIRTIO_FW_BIAS;
- value -= HFI_VIRTIO_FW_BIAS;
+ qhdr->qhdr_start_addr -= HFI_SIM_FW_BIAS;
+ value -= HFI_SIM_FW_BIAS;
}
hwiosymaddr = ((u32)base_addr + (hwiosymaddr));
@@ -377,14 +799,15 @@
wmb();
}
-static int read_register(u8 *base_addr, u32 reg)
+static int venus_hfi_read_register(u8 *base_addr, u32 reg)
{
int rc = readl_relaxed((u32)base_addr + reg);
rmb();
return rc;
}
-static int vidc_hal_iface_cmdq_write(struct hal_device *device, void *pkt)
+static int venus_hfi_iface_cmdq_write(struct venus_hfi_device *device,
+ void *pkt)
{
u32 rx_req_is_set = 0;
struct vidc_iface_q_info *q_info;
@@ -402,21 +825,22 @@
goto err_q_write;
}
- if (!write_queue(q_info, (u8 *)pkt, &rx_req_is_set)) {
+ if (!venus_hfi_write_queue(q_info, (u8 *)pkt, &rx_req_is_set)) {
if (rx_req_is_set)
- write_register(device->hal_data->register_base_addr,
+ venus_hfi_write_register(
+ device->hal_data->register_base_addr,
VIDC_CPU_IC_SOFTINT,
1 << VIDC_CPU_IC_SOFTINT_H2A_SHFT, 0);
result = 0;
} else {
- dprintk(VIDC_ERR, "vidc_hal_iface_cmdq_write:queue_full");
+ dprintk(VIDC_ERR, "venus_hfi_iface_cmdq_write:queue_full");
}
err_q_write:
spin_unlock(&device->write_lock);
return result;
}
-int vidc_hal_iface_msgq_read(struct hal_device *device, void *pkt)
+int venus_hfi_iface_msgq_read(struct venus_hfi_device *device, void *pkt)
{
u32 tx_req_is_set = 0;
int rc = 0;
@@ -435,14 +859,15 @@
}
q_info = &device->iface_queues[VIDC_IFACEQ_MSGQ_IDX];
- if (!read_queue(q_info, (u8 *)pkt, &tx_req_is_set)) {
+ if (!venus_hfi_read_queue(q_info, (u8 *)pkt, &tx_req_is_set)) {
if (tx_req_is_set)
- write_register(device->hal_data->register_base_addr,
+ venus_hfi_write_register(
+ device->hal_data->register_base_addr,
VIDC_CPU_IC_SOFTINT,
1 << VIDC_CPU_IC_SOFTINT_H2A_SHFT, 0);
rc = 0;
} else {
- dprintk(VIDC_INFO, "vidc_hal_iface_msgq_read:queue_empty");
+ dprintk(VIDC_INFO, "venus_hfi_iface_msgq_read:queue_empty");
rc = -ENODATA;
}
read_error:
@@ -450,7 +875,7 @@
return rc;
}
-int vidc_hal_iface_dbgq_read(struct hal_device *device, void *pkt)
+int venus_hfi_iface_dbgq_read(struct venus_hfi_device *device, void *pkt)
{
u32 tx_req_is_set = 0;
int rc = 0;
@@ -468,14 +893,15 @@
goto dbg_error;
}
q_info = &device->iface_queues[VIDC_IFACEQ_DBGQ_IDX];
- if (!read_queue(q_info, (u8 *)pkt, &tx_req_is_set)) {
+ if (!venus_hfi_read_queue(q_info, (u8 *)pkt, &tx_req_is_set)) {
if (tx_req_is_set)
- write_register(device->hal_data->register_base_addr,
- VIDC_CPU_IC_SOFTINT,
- 1 << VIDC_CPU_IC_SOFTINT_H2A_SHFT, 0);
+ venus_hfi_write_register(
+ device->hal_data->register_base_addr,
+ VIDC_CPU_IC_SOFTINT,
+ 1 << VIDC_CPU_IC_SOFTINT_H2A_SHFT, 0);
rc = 0;
} else {
- dprintk(VIDC_INFO, "vidc_hal_iface_dbgq_read:queue_empty");
+ dprintk(VIDC_INFO, "venus_hfi_iface_dbgq_read:queue_empty");
rc = -ENODATA;
}
dbg_error:
@@ -483,7 +909,7 @@
return rc;
}
-static void vidc_hal_set_queue_hdr_defaults(struct hfi_queue_header *q_hdr)
+static void venus_hfi_set_queue_hdr_defaults(struct hfi_queue_header *q_hdr)
{
q_hdr->qhdr_status = 0x1;
q_hdr->qhdr_type = VIDC_IFACEQ_DFLT_QHDR;
@@ -499,11 +925,11 @@
q_hdr->qhdr_write_idx = 0x0;
}
-static void vidc_hal_interface_queues_release(struct hal_device *device)
+static void venus_hfi_interface_queues_release(struct venus_hfi_device *device)
{
int i;
- vidc_hal_free(device->hal_client, device->mem_addr.mem_data);
+ venus_hfi_free(device->hal_client, device->mem_addr.mem_data);
for (i = 0; i < VIDC_IFACEQ_NUMQ; i++) {
device->iface_queues[i].q_hdr = NULL;
@@ -527,7 +953,8 @@
device->hal_client = NULL;
}
-static int vidc_hal_interface_queues_init(struct hal_device *dev, int domain)
+static int venus_hfi_interface_queues_init(struct venus_hfi_device *dev,
+ int domain)
{
struct hfi_queue_table_header *q_tbl_hdr;
struct hfi_queue_header *q_hdr;
@@ -540,7 +967,7 @@
int size_1m = 1024 * 1024;
int uc_size = (UC_SIZE + size_1m - 1) & (~(size_1m - 1));
mem_addr = &dev->mem_addr;
- rc = vidc_hal_alloc((void *) mem_addr,
+ rc = venus_hfi_alloc((void *) mem_addr,
dev->hal_client, uc_size, 1,
0, domain);
if (rc) {
@@ -564,7 +991,7 @@
offset += iface_q->q_array.mem_size;
iface_q->q_hdr = VIDC_IFACEQ_GET_QHDR_START_ADDR(
dev->iface_q_table.align_virtual_addr, i);
- vidc_hal_set_queue_hdr_defaults(iface_q->q_hdr);
+ venus_hfi_set_queue_hdr_defaults(iface_q->q_hdr);
}
dev->qdss.align_device_addr = mem_addr->align_device_addr + offset;
@@ -608,43 +1035,43 @@
iface_q->q_array.align_device_addr;
q_hdr->qhdr_type |= HFI_Q_ID_CTRL_TO_HOST_DEBUG_Q;
- write_register(dev->hal_data->register_base_addr,
+ venus_hfi_write_register(dev->hal_data->register_base_addr,
VIDC_UC_REGION_ADDR,
(u32) mem_addr->align_device_addr, 0);
- write_register(dev->hal_data->register_base_addr,
+ venus_hfi_write_register(dev->hal_data->register_base_addr,
VIDC_UC_REGION_SIZE, mem_addr->mem_size, 0);
- write_register(dev->hal_data->register_base_addr,
+ venus_hfi_write_register(dev->hal_data->register_base_addr,
VIDC_CPU_CS_SCIACMDARG2,
(u32) dev->iface_q_table.align_device_addr,
dev->iface_q_table.align_virtual_addr);
- write_register(dev->hal_data->register_base_addr,
+ venus_hfi_write_register(dev->hal_data->register_base_addr,
VIDC_CPU_CS_SCIACMDARG1, 0x01,
dev->iface_q_table.align_virtual_addr);
- write_register(dev->hal_data->register_base_addr,
+ venus_hfi_write_register(dev->hal_data->register_base_addr,
VIDC_MMAP_ADDR,
(u32) dev->qdss.align_device_addr, 0);
vsfr = (struct hfi_sfr_struct *) dev->sfr.align_virtual_addr;
vsfr->bufSize = SFR_SIZE;
- write_register(dev->hal_data->register_base_addr,
+ venus_hfi_write_register(dev->hal_data->register_base_addr,
VIDC_SFR_ADDR, (u32)dev->sfr.align_device_addr , 0);
return 0;
}
-static int vidc_hal_core_start_cpu(struct hal_device *device)
+static int venus_hfi_core_start_cpu(struct venus_hfi_device *device)
{
u32 ctrl_status = 0, count = 0, rc = 0;
int max_tries = 100;
- write_register(device->hal_data->register_base_addr,
+ venus_hfi_write_register(device->hal_data->register_base_addr,
VIDC_WRAPPER_INTR_MASK, 0x8, 0);
- write_register(device->hal_data->register_base_addr,
+ venus_hfi_write_register(device->hal_data->register_base_addr,
VIDC_CPU_CS_SCIACMDARG3, 1, 0);
while (!ctrl_status && count < max_tries) {
- ctrl_status = read_register(
- device->hal_data->register_base_addr,
- VIDC_CPU_CS_SCIACMDARG0);
+ ctrl_status = venus_hfi_read_register(
+ device->hal_data->register_base_addr,
+ VIDC_CPU_CS_SCIACMDARG0);
if ((ctrl_status & 0xFE) == 0x4) {
dprintk(VIDC_ERR, "invalid setting for UC_REGION\n");
break;
@@ -657,50 +1084,50 @@
return rc;
}
-static void set_vbif_registers(struct hal_device *device)
+static void venus_hfi_set_vbif_registers(struct venus_hfi_device *device)
{
/*Disable Dynamic clock gating for Venus VBIF*/
- write_register(device->hal_data->register_base_addr,
+ venus_hfi_write_register(device->hal_data->register_base_addr,
VIDC_VENUS_VBIF_CLK_ON, 1, 0);
- write_register(device->hal_data->register_base_addr,
+ venus_hfi_write_register(device->hal_data->register_base_addr,
VIDC_VBIF_OUT_AXI_AOOO_EN, 0x00001FFF, 0);
- write_register(device->hal_data->register_base_addr,
+ venus_hfi_write_register(device->hal_data->register_base_addr,
VIDC_VBIF_OUT_AXI_AOOO, 0x1FFF1FFF, 0);
- write_register(device->hal_data->register_base_addr,
+ venus_hfi_write_register(device->hal_data->register_base_addr,
VIDC_VBIF_IN_RD_LIM_CONF0, 0x10101001, 0);
- write_register(device->hal_data->register_base_addr,
+ venus_hfi_write_register(device->hal_data->register_base_addr,
VIDC_VBIF_IN_RD_LIM_CONF1, 0x10101010, 0);
- write_register(device->hal_data->register_base_addr,
+ venus_hfi_write_register(device->hal_data->register_base_addr,
VIDC_VBIF_IN_RD_LIM_CONF2, 0x10101010, 0);
- write_register(device->hal_data->register_base_addr,
+ venus_hfi_write_register(device->hal_data->register_base_addr,
VIDC_VBIF_IN_RD_LIM_CONF3, 0x00000010, 0);
- write_register(device->hal_data->register_base_addr,
+ venus_hfi_write_register(device->hal_data->register_base_addr,
VIDC_VBIF_IN_WR_LIM_CONF0, 0x1010100f, 0);
- write_register(device->hal_data->register_base_addr,
+ venus_hfi_write_register(device->hal_data->register_base_addr,
VIDC_VBIF_IN_WR_LIM_CONF1, 0x10101010, 0);
- write_register(device->hal_data->register_base_addr,
+ venus_hfi_write_register(device->hal_data->register_base_addr,
VIDC_VBIF_IN_WR_LIM_CONF2, 0x10101010, 0);
- write_register(device->hal_data->register_base_addr,
+ venus_hfi_write_register(device->hal_data->register_base_addr,
VIDC_VBIF_IN_WR_LIM_CONF3, 0x00000010, 0);
- write_register(device->hal_data->register_base_addr,
+ venus_hfi_write_register(device->hal_data->register_base_addr,
VIDC_VBIF_OUT_RD_LIM_CONF0, 0x00001010, 0);
- write_register(device->hal_data->register_base_addr,
+ venus_hfi_write_register(device->hal_data->register_base_addr,
VIDC_VBIF_OUT_WR_LIM_CONF0, 0x00001010, 0);
- write_register(device->hal_data->register_base_addr,
+ venus_hfi_write_register(device->hal_data->register_base_addr,
VIDC_VBIF_ARB_CTL, 0x00000030, 0);
- write_register(device->hal_data->register_base_addr,
+ venus_hfi_write_register(device->hal_data->register_base_addr,
VIDC_VENUS_VBIF_DDR_OUT_MAX_BURST, 0x00000707, 0);
- write_register(device->hal_data->register_base_addr,
+ venus_hfi_write_register(device->hal_data->register_base_addr,
VIDC_VENUS_VBIF_OCMEM_OUT_MAX_BURST, 0x00000707, 0);
- write_register(device->hal_data->register_base_addr,
+ venus_hfi_write_register(device->hal_data->register_base_addr,
VIDC_VENUS_VBIF_ROUND_ROBIN_QOS_ARB, 0x00000001, 0);
- write_register(device->hal_data->register_base_addr,
+ venus_hfi_write_register(device->hal_data->register_base_addr,
VIDC_VENUS0_WRAPPER_VBIF_REQ_PRIORITY, 0x5555556, 0);
- write_register(device->hal_data->register_base_addr,
+ venus_hfi_write_register(device->hal_data->register_base_addr,
VIDC_VENUS0_WRAPPER_VBIF_PRIORITY_LEVEL, 0, 0);
}
-static int vidc_hal_sys_set_debug(struct hal_device *device, int debug)
+static int venus_hfi_sys_set_debug(struct venus_hfi_device *device, int debug)
{
struct hfi_debug_config *hfi;
u8 packet[VIDC_IFACEQ_VAR_SMALL_PKT_SIZE];
@@ -714,16 +1141,16 @@
hfi = (struct hfi_debug_config *) &pkt->rg_property_data[1];
hfi->debug_config = debug;
hfi->debug_mode = HFI_DEBUG_MODE_QUEUE;
- if (vidc_hal_iface_cmdq_write(device, pkt))
+ if (venus_hfi_iface_cmdq_write(device, pkt))
return -ENOTEMPTY;
return 0;
}
-int vidc_hal_core_init(void *device, int domain)
+int venus_hfi_core_init(void *device)
{
struct hfi_cmd_sys_init_packet pkt;
int rc = 0;
- struct hal_device *dev;
+ struct venus_hfi_device *dev;
if (device) {
dev = device;
@@ -731,12 +1158,13 @@
dprintk(VIDC_ERR, "Invalid device");
return -ENODEV;
}
+
dev->intr_status = 0;
enable_irq(dev->hal_data->irq);
INIT_LIST_HEAD(&dev->sess_head);
spin_lock_init(&dev->read_lock);
spin_lock_init(&dev->write_lock);
- set_vbif_registers(dev);
+ venus_hfi_set_vbif_registers(dev);
if (!dev->hal_client) {
dev->hal_client = msm_smem_new_client(SMEM_ION);
@@ -750,7 +1178,8 @@
dev->hal_data->device_base_addr,
(u32) dev->hal_data->register_base_addr);
- rc = vidc_hal_interface_queues_init(dev, domain);
+ rc = venus_hfi_interface_queues_init(dev,
+ dev->resources.io_map[NS_MAP].domain);
if (rc) {
dprintk(VIDC_ERR, "failed to init queues");
rc = -ENOMEM;
@@ -761,9 +1190,9 @@
rc = -EEXIST;
goto err_core_init;
}
- write_register(dev->hal_data->register_base_addr,
+ venus_hfi_write_register(dev->hal_data->register_base_addr,
VIDC_CTRL_INIT, 0x1, 0);
- rc = vidc_hal_core_start_cpu(dev);
+ rc = venus_hfi_core_start_cpu(dev);
if (rc) {
dprintk(VIDC_ERR, "Failed to start core");
rc = -ENODEV;
@@ -775,7 +1204,7 @@
dprintk(VIDC_ERR, "Failed to create sys init pkt");
goto err_core_init;
}
- if (vidc_hal_iface_cmdq_write(dev, &pkt)) {
+ if (venus_hfi_iface_cmdq_write(dev, &pkt)) {
rc = -ENOTEMPTY;
goto err_core_init;
}
@@ -785,9 +1214,9 @@
return rc;
}
-int vidc_hal_core_release(void *device)
+int venus_hfi_core_release(void *device)
{
- struct hal_device *dev;
+ struct venus_hfi_device *dev;
if (device) {
dev = device;
} else {
@@ -795,20 +1224,20 @@
return -ENODEV;
}
if (dev->hal_client) {
- write_register(dev->hal_data->register_base_addr,
+ venus_hfi_write_register(dev->hal_data->register_base_addr,
VIDC_CPU_CS_SCIACMDARG3, 0, 0);
disable_irq_nosync(dev->hal_data->irq);
- vidc_hal_interface_queues_release(dev);
+ venus_hfi_interface_queues_release(dev);
}
dprintk(VIDC_INFO, "HAL exited\n");
return 0;
}
-int vidc_hal_core_pc_prep(void *device)
+int venus_hfi_core_pc_prep(void *device)
{
struct hfi_cmd_sys_pc_prep_packet pkt;
int rc = 0;
- struct hal_device *dev;
+ struct venus_hfi_device *dev;
if (device) {
dev = device;
@@ -823,23 +1252,23 @@
goto err_create_pkt;
}
- if (vidc_hal_iface_cmdq_write(dev, &pkt))
+ if (venus_hfi_iface_cmdq_write(dev, &pkt))
rc = -ENOTEMPTY;
err_create_pkt:
return rc;
}
-static void vidc_hal_core_clear_interrupt(struct hal_device *device)
+static void venus_hfi_core_clear_interrupt(struct venus_hfi_device *device)
{
u32 intr_status = 0;
if (!device->callback)
return;
- intr_status = read_register(
- device->hal_data->register_base_addr,
- VIDC_WRAPPER_INTR_STATUS);
+ intr_status = venus_hfi_read_register(
+ device->hal_data->register_base_addr,
+ VIDC_WRAPPER_INTR_STATUS);
if ((intr_status & VIDC_WRAPPER_INTR_STATUS_A2H_BMSK) ||
(intr_status & VIDC_WRAPPER_INTR_STATUS_A2HWD_BMSK)) {
@@ -852,20 +1281,20 @@
"times: %d interrupt_status: %d",
(u32) device, ++device->spur_count, intr_status);
}
- write_register(device->hal_data->register_base_addr,
+ venus_hfi_write_register(device->hal_data->register_base_addr,
VIDC_CPU_CS_A2HSOFTINTCLR, 1, 0);
- write_register(device->hal_data->register_base_addr,
+ venus_hfi_write_register(device->hal_data->register_base_addr,
VIDC_WRAPPER_INTR_CLEAR, intr_status, 0);
dprintk(VIDC_DBG, "Cleared WRAPPER/A2H interrupt");
}
-int vidc_hal_core_set_resource(void *device,
+int venus_hfi_core_set_resource(void *device,
struct vidc_resource_hdr *resource_hdr, void *resource_value)
{
struct hfi_cmd_sys_set_resource_packet *pkt;
u8 packet[VIDC_IFACEQ_VAR_SMALL_PKT_SIZE];
int rc = 0;
- struct hal_device *dev;
+ struct venus_hfi_device *dev;
if (!device || !resource_hdr || !resource_value) {
dprintk(VIDC_ERR, "set_res: Invalid Params");
@@ -877,24 +1306,24 @@
pkt = (struct hfi_cmd_sys_set_resource_packet *) packet;
rc = create_pkt_set_cmd_sys_resource(pkt, resource_hdr,
- resource_value);
+ resource_value);
if (rc) {
dprintk(VIDC_ERR, "set_res: failed to create packet");
goto err_create_pkt;
}
- if (vidc_hal_iface_cmdq_write(dev, pkt))
+ if (venus_hfi_iface_cmdq_write(dev, pkt))
rc = -ENOTEMPTY;
err_create_pkt:
return rc;
}
-int vidc_hal_core_release_resource(void *device,
+int venus_hfi_core_release_resource(void *device,
struct vidc_resource_hdr *resource_hdr)
{
struct hfi_cmd_sys_release_resource_packet pkt;
int rc = 0;
- struct hal_device *dev;
+ struct venus_hfi_device *dev;
if (!device || !resource_hdr) {
dprintk(VIDC_ERR, "Inv-Params in rel_res");
@@ -909,18 +1338,18 @@
goto err_create_pkt;
}
- if (vidc_hal_iface_cmdq_write(dev, &pkt))
+ if (venus_hfi_iface_cmdq_write(dev, &pkt))
rc = -ENOTEMPTY;
err_create_pkt:
return rc;
}
-int vidc_hal_core_ping(void *device)
+int venus_hfi_core_ping(void *device)
{
struct hfi_cmd_sys_ping_packet pkt;
int rc = 0;
- struct hal_device *dev;
+ struct venus_hfi_device *dev;
if (device) {
dev = device;
@@ -935,14 +1364,14 @@
goto err_create_pkt;
}
- if (vidc_hal_iface_cmdq_write(dev, &pkt))
+ if (venus_hfi_iface_cmdq_write(dev, &pkt))
rc = -ENOTEMPTY;
err_create_pkt:
return rc;
}
-int vidc_hal_session_set_property(void *sess,
+int venus_hfi_session_set_property(void *sess,
enum hal_property ptype, void *pdata)
{
u8 packet[VIDC_IFACEQ_VAR_LARGE_PKT_SIZE];
@@ -966,13 +1395,13 @@
return -EINVAL;
}
- if (vidc_hal_iface_cmdq_write(session->device, pkt))
+ if (venus_hfi_iface_cmdq_write(session->device, pkt))
return -ENOTEMPTY;
return rc;
}
-int vidc_hal_session_get_property(void *sess,
+int venus_hfi_session_get_property(void *sess,
enum hal_property ptype, void *pdata)
{
struct hal_session *session;
@@ -1095,12 +1524,12 @@
return 0;
}
-void *vidc_hal_session_init(void *device, u32 session_id,
+void *venus_hfi_session_init(void *device, u32 session_id,
enum hal_domain session_type, enum hal_video_codec codec_type)
{
struct hfi_cmd_sys_session_init_packet pkt;
struct hal_session *new_session;
- struct hal_device *dev;
+ struct venus_hfi_device *dev;
if (device) {
dev = device;
@@ -1125,9 +1554,9 @@
goto err_session_init_fail;
}
- if (vidc_hal_iface_cmdq_write(dev, &pkt))
+ if (venus_hfi_iface_cmdq_write(dev, &pkt))
goto err_session_init_fail;
- if (vidc_hal_sys_set_debug(dev, msm_fw_debug))
+ if (venus_hfi_sys_set_debug(dev, msm_fw_debug))
dprintk(VIDC_ERR, "Setting fw_debug msg ON failed");
return (void *) new_session;
@@ -1136,7 +1565,7 @@
return NULL;
}
-static int vidc_hal_send_session_cmd(void *session_id,
+static int venus_hfi_send_session_cmd(void *session_id,
int pkt_type)
{
struct vidc_hal_session_cmd_pkt pkt;
@@ -1156,26 +1585,26 @@
goto err_create_pkt;
}
- if (vidc_hal_iface_cmdq_write(session->device, &pkt))
+ if (venus_hfi_iface_cmdq_write(session->device, &pkt))
rc = -ENOTEMPTY;
err_create_pkt:
return rc;
}
-int vidc_hal_session_end(void *session)
+int venus_hfi_session_end(void *session)
{
- return vidc_hal_send_session_cmd(session,
+ return venus_hfi_send_session_cmd(session,
HFI_CMD_SYS_SESSION_END);
}
-int vidc_hal_session_abort(void *session)
+int venus_hfi_session_abort(void *session)
{
- return vidc_hal_send_session_cmd(session,
+ return venus_hfi_send_session_cmd(session,
HFI_CMD_SYS_SESSION_ABORT);
}
-int vidc_hal_session_set_buffers(void *sess,
+int venus_hfi_session_set_buffers(void *sess,
struct vidc_buffer_addr_info *buffer_info)
{
struct hfi_cmd_session_set_buffers_packet *pkt;
@@ -1203,13 +1632,13 @@
}
dprintk(VIDC_INFO, "set buffers: 0x%x", buffer_info->buffer_type);
- if (vidc_hal_iface_cmdq_write(session->device, pkt))
+ if (venus_hfi_iface_cmdq_write(session->device, pkt))
rc = -ENOTEMPTY;
err_create_pkt:
return rc;
}
-int vidc_hal_session_release_buffers(void *sess,
+int venus_hfi_session_release_buffers(void *sess,
struct vidc_buffer_addr_info *buffer_info)
{
struct hfi_cmd_session_release_buffer_packet *pkt;
@@ -1237,49 +1666,49 @@
}
dprintk(VIDC_INFO, "Release buffers: 0x%x", buffer_info->buffer_type);
- if (vidc_hal_iface_cmdq_write(session->device, pkt))
+ if (venus_hfi_iface_cmdq_write(session->device, pkt))
rc = -ENOTEMPTY;
err_create_pkt:
return rc;
}
-int vidc_hal_session_load_res(void *sess)
+int venus_hfi_session_load_res(void *sess)
{
- return vidc_hal_send_session_cmd(sess,
+ return venus_hfi_send_session_cmd(sess,
HFI_CMD_SESSION_LOAD_RESOURCES);
}
-int vidc_hal_session_release_res(void *sess)
+int venus_hfi_session_release_res(void *sess)
{
- return vidc_hal_send_session_cmd(sess,
+ return venus_hfi_send_session_cmd(sess,
HFI_CMD_SESSION_RELEASE_RESOURCES);
}
-int vidc_hal_session_start(void *sess)
+int venus_hfi_session_start(void *sess)
{
- return vidc_hal_send_session_cmd(sess,
+ return venus_hfi_send_session_cmd(sess,
HFI_CMD_SESSION_START);
}
-int vidc_hal_session_stop(void *sess)
+int venus_hfi_session_stop(void *sess)
{
- return vidc_hal_send_session_cmd(sess,
+ return venus_hfi_send_session_cmd(sess,
HFI_CMD_SESSION_STOP);
}
-int vidc_hal_session_suspend(void *sess)
+int venus_hfi_session_suspend(void *sess)
{
- return vidc_hal_send_session_cmd(sess,
+ return venus_hfi_send_session_cmd(sess,
HFI_CMD_SESSION_SUSPEND);
}
-int vidc_hal_session_resume(void *sess)
+int venus_hfi_session_resume(void *sess)
{
- return vidc_hal_send_session_cmd(sess,
+ return venus_hfi_send_session_cmd(sess,
HFI_CMD_SESSION_RESUME);
}
-int vidc_hal_session_etb(void *sess, struct vidc_frame_data *input_frame)
+int venus_hfi_session_etb(void *sess, struct vidc_frame_data *input_frame)
{
int rc = 0;
struct hal_session *session;
@@ -1302,7 +1731,7 @@
goto err_create_pkt;
}
dprintk(VIDC_DBG, "Q DECODER INPUT BUFFER");
- if (vidc_hal_iface_cmdq_write(session->device, &pkt))
+ if (venus_hfi_iface_cmdq_write(session->device, &pkt))
rc = -ENOTEMPTY;
} else {
struct hfi_cmd_session_empty_buffer_uncompressed_plane0_packet
@@ -1316,14 +1745,14 @@
goto err_create_pkt;
}
dprintk(VIDC_DBG, "Q ENCODER INPUT BUFFER");
- if (vidc_hal_iface_cmdq_write(session->device, &pkt))
+ if (venus_hfi_iface_cmdq_write(session->device, &pkt))
rc = -ENOTEMPTY;
}
err_create_pkt:
return rc;
}
-int vidc_hal_session_ftb(void *sess,
+int venus_hfi_session_ftb(void *sess,
struct vidc_frame_data *output_frame)
{
struct hfi_cmd_session_fill_buffer_packet pkt;
@@ -1343,13 +1772,13 @@
goto err_create_pkt;
}
- if (vidc_hal_iface_cmdq_write(session->device, &pkt))
+ if (venus_hfi_iface_cmdq_write(session->device, &pkt))
rc = -ENOTEMPTY;
err_create_pkt:
return rc;
}
-int vidc_hal_session_parse_seq_hdr(void *sess,
+int venus_hfi_session_parse_seq_hdr(void *sess,
struct vidc_seq_hdr *seq_hdr)
{
struct hfi_cmd_session_parse_sequence_header_packet *pkt;
@@ -1374,13 +1803,13 @@
goto err_create_pkt;
}
- if (vidc_hal_iface_cmdq_write(session->device, pkt))
+ if (venus_hfi_iface_cmdq_write(session->device, pkt))
rc = -ENOTEMPTY;
err_create_pkt:
return rc;
}
-int vidc_hal_session_get_seq_hdr(void *sess,
+int venus_hfi_session_get_seq_hdr(void *sess,
struct vidc_seq_hdr *seq_hdr)
{
struct hfi_cmd_session_get_sequence_header_packet *pkt;
@@ -1402,13 +1831,13 @@
goto err_create_pkt;
}
- if (vidc_hal_iface_cmdq_write(session->device, pkt))
+ if (venus_hfi_iface_cmdq_write(session->device, pkt))
rc = -ENOTEMPTY;
err_create_pkt:
return rc;
}
-int vidc_hal_session_get_buf_req(void *sess)
+int venus_hfi_session_get_buf_req(void *sess)
{
struct hfi_cmd_session_get_property_packet pkt;
int rc = 0;
@@ -1427,13 +1856,13 @@
goto err_create_pkt;
}
- if (vidc_hal_iface_cmdq_write(session->device, &pkt))
+ if (venus_hfi_iface_cmdq_write(session->device, &pkt))
rc = -ENOTEMPTY;
err_create_pkt:
return rc;
}
-int vidc_hal_session_flush(void *sess, enum hal_flush flush_mode)
+int venus_hfi_session_flush(void *sess, enum hal_flush flush_mode)
{
struct hfi_cmd_session_flush_packet pkt;
int rc = 0;
@@ -1452,22 +1881,23 @@
goto err_create_pkt;
}
- if (vidc_hal_iface_cmdq_write(session->device, &pkt))
+ if (venus_hfi_iface_cmdq_write(session->device, &pkt))
rc = -ENOTEMPTY;
err_create_pkt:
return rc;
}
-static int vidc_hal_check_core_registered(
+static int venus_hfi_check_core_registered(
struct hal_device_data core, u32 fw_addr,
u32 reg_addr, u32 reg_size, u32 irq)
{
- struct hal_device *device;
+ struct venus_hfi_device *device;
struct list_head *curr, *next;
if (core.dev_count) {
list_for_each_safe(curr, next, &core.dev_head) {
- device = list_entry(curr, struct hal_device, list);
+ device = list_entry(curr,
+ struct venus_hfi_device, list);
if (device && device->hal_data->irq == irq &&
(CONTAINS(device->hal_data->
device_base_addr,
@@ -1507,10 +1937,10 @@
return -EINVAL;
}
-static void vidc_hal_core_work_handler(struct work_struct *work)
+static void venus_hfi_core_work_handler(struct work_struct *work)
{
- struct hal_device *device = list_first_entry(
- &hal_ctxt.dev_head, struct hal_device, list);
+ struct venus_hfi_device *device = list_first_entry(
+ &hal_ctxt.dev_head, struct venus_hfi_device, list);
dprintk(VIDC_INFO, " GOT INTERRUPT () ");
if (!device->callback) {
@@ -1518,75 +1948,825 @@
device);
return;
}
- vidc_hal_core_clear_interrupt(device);
- vidc_hal_response_handler(device);
+ venus_hfi_core_clear_interrupt(device);
+ hfi_response_handler(device);
enable_irq(device->hal_data->irq);
}
-static DECLARE_WORK(vidc_hal_work, vidc_hal_core_work_handler);
+static DECLARE_WORK(venus_hfi_work, venus_hfi_core_work_handler);
-static irqreturn_t vidc_hal_isr(int irq, void *dev)
+static irqreturn_t venus_hfi_isr(int irq, void *dev)
{
- struct hal_device *device = dev;
+ struct venus_hfi_device *device = dev;
dprintk(VIDC_INFO, "vidc_hal_isr() %d ", irq);
disable_irq_nosync(irq);
- queue_work(device->vidc_workq, &vidc_hal_work);
+ queue_work(device->vidc_workq, &venus_hfi_work);
dprintk(VIDC_INFO, "vidc_hal_isr() %d ", irq);
return IRQ_HANDLED;
}
-void *vidc_hal_add_device(u32 device_id, u32 fw_base_addr, u32 reg_base,
- u32 reg_size, u32 irq,
- void (*callback) (enum command_response cmd, void *data))
+static int venus_hfi_init_regs_and_interrupts(
+ struct venus_hfi_device *device, struct platform_device *pdev)
{
- struct hal_device *hdevice = NULL;
struct hal_data *hal = NULL;
int rc = 0;
+ struct resource *res;
- if (device_id || !reg_base || !reg_size ||
- !irq || !callback) {
+ device->base_addr = 0x0;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ dprintk(VIDC_ERR, "Failed to get IORESOURCE_MEM\n");
+ rc = -ENODEV;
+ goto err_core_init;
+ }
+ device->register_base = res->start;
+ device->register_size = resource_size(res);
+
+ res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+ if (!res) {
+ dprintk(VIDC_ERR, "Failed to get IORESOURCE_IRQ\n");
+ rc = -ENODEV;
+ goto err_core_init;
+ }
+ device->irq = res->start;
+
+ rc = venus_hfi_check_core_registered(hal_ctxt, device->base_addr,
+ device->register_base, device->register_size,
+ device->irq);
+ if (!rc) {
+ dprintk(VIDC_ERR, "Core present/Already added");
+ rc = -EEXIST;
+ goto err_core_init;
+ }
+
+ dprintk(VIDC_DBG, "HAL_DATA will be assigned now");
+ hal = (struct hal_data *)
+ kzalloc(sizeof(struct hal_data), GFP_KERNEL);
+ if (!hal) {
+ dprintk(VIDC_ERR, "Failed to alloc");
+ rc = -ENOMEM;
+ goto err_core_init;
+ }
+ hal->irq = device->irq;
+ hal->device_base_addr = device->base_addr;
+ hal->register_base_addr =
+ ioremap_nocache(device->register_base, device->register_size);
+ if (!hal->register_base_addr) {
+ dprintk(VIDC_ERR,
+ "could not map reg addr %d of size %d",
+ device->register_base, device->register_size);
+ goto error_irq_fail;
+ }
+
+ device->hal_data = hal;
+ rc = request_irq(device->irq, venus_hfi_isr, IRQF_TRIGGER_HIGH,
+ "msm_vidc", device);
+ if (unlikely(rc)) {
+ dprintk(VIDC_ERR, "() :request_irq failed\n");
+ goto error_irq_fail;
+ }
+ disable_irq_nosync(device->irq);
+ return rc;
+
+error_irq_fail:
+ kfree(hal);
+err_core_init:
+ return rc;
+
+}
+
+static size_t read_u32_array(struct platform_device *pdev,
+ char *name, u32 *arr, size_t size)
+{
+ int len;
+ size_t sz = 0;
+ struct device_node *np = pdev->dev.of_node;
+ if (!of_get_property(np, name, &len)) {
+ dprintk(VIDC_ERR, "Failed to read %s from device tree\n",
+ name);
+ goto fail_read;
+ }
+ sz = len / sizeof(u32);
+ if (sz <= 0) {
+ dprintk(VIDC_ERR, "%s not specified in device tree\n",
+ name);
+ goto fail_read;
+ }
+ if (sz > size) {
+ dprintk(VIDC_ERR, "Not enough memory to store %s values\n",
+ name);
+ goto fail_read;
+ }
+ if (of_property_read_u32_array(np, name, arr, sz)) {
+ dprintk(VIDC_ERR,
+ "error while reading %s from device tree\n",
+ name);
+ goto fail_read;
+ }
+ return sz;
+fail_read:
+ sz = 0;
+ return sz;
+}
+
+static inline int venus_hfi_init_clocks(struct platform_device *pdev,
+ struct venus_hfi_device *device)
+{
+ struct venus_core_clock *cl;
+ int i;
+ int rc = 0;
+ struct venus_core_clock *clock;
+ if (!device) {
+ dprintk(VIDC_ERR, "Invalid params: %p\n", device);
+ return -EINVAL;
+ }
+ clock = device->resources.clock;
+ strlcpy(clock[VCODEC_CLK].name, "core_clk",
+ sizeof(clock[VCODEC_CLK].name));
+ strlcpy(clock[VCODEC_AHB_CLK].name, "iface_clk",
+ sizeof(clock[VCODEC_AHB_CLK].name));
+ strlcpy(clock[VCODEC_AXI_CLK].name, "bus_clk",
+ sizeof(clock[VCODEC_AXI_CLK].name));
+ strlcpy(clock[VCODEC_OCMEM_CLK].name, "mem_clk",
+ sizeof(clock[VCODEC_OCMEM_CLK].name));
+
+ clock[VCODEC_CLK].count = read_u32_array(pdev,
+ "load-freq-tbl", (u32 *)clock[VCODEC_CLK].load_freq_tbl,
+ (sizeof(clock[VCODEC_CLK].load_freq_tbl)/sizeof(u32)));
+ clock[VCODEC_CLK].count /= 2;
+ dprintk(VIDC_DBG, "count = %d\n", clock[VCODEC_CLK].count);
+ if (!clock[VCODEC_CLK].count) {
+ dprintk(VIDC_ERR, "Failed to read clock frequency\n");
+ goto fail_init_clocks;
+ }
+ for (i = 0; i < clock[VCODEC_CLK].count; i++) {
+ dprintk(VIDC_DBG,
+ "load = %d, freq = %d\n",
+ clock[VCODEC_CLK].load_freq_tbl[i].load,
+ clock[VCODEC_CLK].load_freq_tbl[i].freq
+ );
+ }
+
+ for (i = 0; i < VCODEC_MAX_CLKS; i++) {
+ cl = &device->resources.clock[i];
+ if (!cl->clk) {
+ cl->clk = devm_clk_get(&pdev->dev, cl->name);
+ if (IS_ERR_OR_NULL(cl->clk)) {
+ dprintk(VIDC_ERR,
+ "Failed to get clock: %s\n", cl->name);
+ rc = PTR_ERR(cl->clk);
+ break;
+ }
+ }
+ }
+
+ if (i < VCODEC_MAX_CLKS) {
+ for (--i; i >= 0; i--) {
+ cl = &device->resources.clock[i];
+ clk_put(cl->clk);
+ }
+ }
+fail_init_clocks:
+ return rc;
+}
+
+static inline void venus_hfi_deinit_clocks(struct venus_hfi_device *device)
+{
+ int i;
+ if (!device) {
+ dprintk(VIDC_ERR, "Invalid args\n");
+ return;
+ }
+ for (i = 0; i < VCODEC_MAX_CLKS; i++)
+ clk_put(device->resources.clock[i].clk);
+}
+
+static unsigned long venus_hfi_get_clock_rate(struct venus_core_clock *clock,
+ int num_mbs_per_sec)
+{
+ int num_rows = clock->count;
+ struct load_freq_table *table = clock->load_freq_tbl;
+ unsigned long ret = table[num_rows-1].freq;
+ int i;
+ for (i = 0; i < num_rows; i++) {
+ if (num_mbs_per_sec > table[i].load)
+ break;
+ ret = table[i].freq;
+ }
+ dprintk(VIDC_DBG, "Required clock rate = %lu\n", ret);
+ return ret;
+}
+
+int venus_hfi_scale_clocks(struct venus_hfi_device *device, int load)
+{
+ int rc = 0;
+ if (!device) {
+ dprintk(VIDC_ERR, "Invalid args: %p\n", device);
+ return -EINVAL;
+ }
+
+ rc = clk_set_rate(device->resources.clock[VCODEC_CLK].clk,
+ venus_hfi_get_clock_rate(&device->resources.clock[VCODEC_CLK],
+ load));
+ if (rc)
+ dprintk(VIDC_ERR, "Failed to set clock rate: %d\n", rc);
+ return rc;
+}
+
+static inline int venus_hfi_enable_clks(struct venus_hfi_device *device)
+{
+ int i;
+ struct venus_core_clock *cl;
+ int rc = 0;
+ if (!device) {
+ dprintk(VIDC_ERR, "Invalid params: %p\n", device);
+ return -EINVAL;
+ }
+ for (i = 0; i < VCODEC_MAX_CLKS; i++) {
+ cl = &device->resources.clock[i];
+ rc = clk_prepare_enable(cl->clk);
+ if (rc) {
+ dprintk(VIDC_ERR, "Failed to enable clocks\n");
+ goto fail_clk_enable;
+ } else {
+ dprintk(VIDC_DBG, "Clock: %s enabled\n", cl->name);
+ }
+ }
+ return rc;
+fail_clk_enable:
+ for (; i >= 0; i--) {
+ cl = &device->resources.clock[i];
+ clk_disable_unprepare(cl->clk);
+ }
+ return rc;
+}
+
+static inline void venus_hfi_disable_clks(struct venus_hfi_device *device)
+{
+ int i;
+ struct venus_core_clock *cl;
+ if (!device) {
+ dprintk(VIDC_ERR, "Invalid params: %p\n", device);
+ return;
+ }
+ for (i = 0; i < VCODEC_MAX_CLKS; i++) {
+ cl = &device->resources.clock[i];
+ clk_disable_unprepare(cl->clk);
+ }
+}
+
+static int venus_hfi_register_iommu_domains(struct venus_hfi_device *device,
+ struct platform_device *pdev)
+{
+ size_t len;
+ struct msm_iova_partition partition[2];
+ struct msm_iova_layout layout;
+ int rc = 0;
+ int i;
+ struct msm_vidc_iommu_info *io_map;
+
+ if (!device)
+ return -EINVAL;
+
+ io_map = device->resources.io_map;
+
+ strlcpy(io_map[CP_MAP].name, "vidc-cp-map",
+ sizeof(io_map[CP_MAP].name));
+ strlcpy(io_map[CP_MAP].ctx, "venus_cp",
+ sizeof(io_map[CP_MAP].ctx));
+ strlcpy(io_map[NS_MAP].name, "vidc-ns-map",
+ sizeof(io_map[NS_MAP].name));
+ strlcpy(io_map[NS_MAP].ctx, "venus_ns",
+ sizeof(io_map[NS_MAP].ctx));
+
+ for (i = 0; i < MAX_MAP; i++) {
+ len = read_u32_array(pdev, io_map[i].name,
+ io_map[i].addr_range,
+ (sizeof(io_map[i].addr_range)/sizeof(u32)));
+ if (!len) {
+ dprintk(VIDC_ERR,
+ "Error in reading cp address range\n");
+ rc = -EINVAL;
+ break;
+ }
+ partition[0].start = io_map[i].addr_range[0];
+ if (i == NS_MAP) {
+ partition[0].size =
+ io_map[i].addr_range[1] - SHARED_QSIZE;
+ partition[1].start =
+ partition[0].start + io_map[i].addr_range[1]
+ - SHARED_QSIZE;
+ partition[1].size = SHARED_QSIZE;
+ layout.npartitions = 2;
+ layout.is_secure = 0;
+ } else {
+ partition[0].size = io_map[i].addr_range[1];
+ layout.npartitions = 1;
+ layout.is_secure = 1;
+ }
+ layout.partitions = &partition[0];
+ layout.client_name = io_map[i].name;
+ layout.domain_flags = 0;
+ dprintk(VIDC_DBG, "Registering domain 1 with: %lx, %lx, %s\n",
+ partition[0].start, partition[0].size,
+ layout.client_name);
+ dprintk(VIDC_DBG, "Registering domain 2 with: %lx, %lx, %s\n",
+ partition[1].start, partition[1].size,
+ layout.client_name);
+ io_map[i].domain = msm_register_domain(&layout);
+ if (io_map[i].domain < 0) {
+ dprintk(VIDC_ERR, "Failed to register cp domain\n");
+ rc = -EINVAL;
+ break;
+ }
+ }
+ /* There is no api provided as msm_unregister_domain, so
+ * we are not able to unregister the previously
+ * registered domains if any domain registration fails.*/
+ BUG_ON(i < MAX_MAP);
+ return rc;
+}
+
+static void venus_hfi_deinit_bus(struct venus_hfi_device *device)
+{
+ struct venus_bus_info *bus_info;
+ int i = 0;
+
+ if (!device)
+ return;
+
+ bus_info = &device->resources.bus_info;
+
+ for (i = 0; i < MSM_VIDC_MAX_DEVICES; i++) {
+ if (bus_info->ddr_handle[i]) {
+ msm_bus_scale_unregister_client(
+ bus_info->ddr_handle[i]);
+ bus_info->ddr_handle[i] = 0;
+ }
+
+ if (bus_info->ocmem_handle[i]) {
+ msm_bus_scale_unregister_client(
+ bus_info->ocmem_handle[i]);
+ bus_info->ocmem_handle[i] = 0;
+ }
+ }
+}
+
+static int venus_hfi_init_bus(struct venus_hfi_device *device)
+{
+ struct venus_bus_info *bus_info;
+ int rc = 0;
+ if (!device)
+ return -EINVAL;
+
+ bus_info = &device->resources.bus_info;
+
+ bus_info->ddr_handle[MSM_VIDC_ENCODER] =
+ msm_bus_scale_register_client(&enc_ddr_bus_data);
+ if (!bus_info->ddr_handle[MSM_VIDC_ENCODER]) {
+ dprintk(VIDC_ERR, "Failed to register bus scale client\n");
+ goto err_init_bus;
+ }
+ bus_info->ddr_handle[MSM_VIDC_DECODER] =
+ msm_bus_scale_register_client(&dec_ddr_bus_data);
+ if (!bus_info->ddr_handle[MSM_VIDC_DECODER]) {
+ dprintk(VIDC_ERR, "Failed to register bus scale client\n");
+ goto err_init_bus;
+ }
+ bus_info->ocmem_handle[MSM_VIDC_ENCODER] =
+ msm_bus_scale_register_client(&enc_ocmem_bus_data);
+ if (!bus_info->ocmem_handle[MSM_VIDC_ENCODER]) {
+ dprintk(VIDC_ERR, "Failed to register bus scale client\n");
+ goto err_init_bus;
+ }
+ bus_info->ocmem_handle[MSM_VIDC_DECODER] =
+ msm_bus_scale_register_client(&dec_ocmem_bus_data);
+ if (!bus_info->ocmem_handle[MSM_VIDC_DECODER]) {
+ dprintk(VIDC_ERR, "Failed to register bus scale client\n");
+ goto err_init_bus;
+ }
+ return rc;
+err_init_bus:
+ venus_hfi_deinit_bus(device);
+ return -EINVAL;
+}
+
+
+static const u32 venus_hfi_bus_table[] = {
+ 36000,
+ 110400,
+ 244800,
+ 489000,
+ 783360,
+ 979200,
+};
+
+static int venus_hfi_get_bus_vector(int load)
+{
+ int num_rows = sizeof(venus_hfi_bus_table)/(sizeof(u32));
+ int i;
+ for (i = 0; i < num_rows; i++) {
+ if (load <= venus_hfi_bus_table[i])
+ break;
+ }
+ i++;
+ dprintk(VIDC_DBG, "Required bus = %d\n", i);
+ return i;
+}
+
+int venus_hfi_scale_bus(struct venus_hfi_device *device, int load,
+ enum session_type type, enum mem_type mtype)
+{
+ int rc = 0;
+ u32 handle = 0;
+
+ if (mtype & DDR_MEM)
+ handle = device->resources.bus_info.ddr_handle[type];
+ if (mtype & OCMEM_MEM)
+ handle = device->resources.bus_info.ocmem_handle[type];
+
+ if (handle) {
+ rc = msm_bus_scale_client_update_request(
+ handle, venus_hfi_get_bus_vector(load));
+ if (rc)
+ dprintk(VIDC_ERR, "Failed to scale bus: %d\n", rc);
+ } else {
+ dprintk(VIDC_ERR, "Failed to scale bus, mtype: %d\n",
+ mtype);
+ rc = -EINVAL;
+ }
+
+ return rc;
+}
+
+static void venus_hfi_ocmem_init(struct venus_hfi_device *device)
+{
+ struct on_chip_mem *ocmem;
+
+ ocmem = &device->resources.ocmem;
+ ocmem->vidc_ocmem_nb.notifier_call = msm_vidc_ocmem_notify_handler;
+ ocmem->handle =
+ ocmem_notifier_register(OCMEM_VIDEO, &ocmem->vidc_ocmem_nb);
+ if (!ocmem->handle) {
+ dprintk(VIDC_WARN, "Failed to register OCMEM notifier.");
+ dprintk(VIDC_INFO, " Performance will be impacted\n");
+ }
+}
+
+int venus_hfi_set_ocmem(struct venus_hfi_device *device,
+ struct ocmem_buf *ocmem)
+{
+ struct vidc_resource_hdr rhdr;
+ int rc = 0;
+ if (!device || !ocmem) {
+ dprintk(VIDC_ERR, "Invalid params, core:%p, ocmem: %p\n",
+ device, ocmem);
+ return -EINVAL;
+ }
+ rhdr.resource_id = VIDC_RESOURCE_OCMEM;
+ rhdr.resource_handle = (u32) &device->resources.ocmem;
+ rhdr.size = ocmem->len;
+ rc = venus_hfi_core_set_resource(device, &rhdr, ocmem);
+ if (rc) {
+ dprintk(VIDC_ERR, "Failed to set OCMEM on driver\n");
+ goto ocmem_set_failed;
+ }
+ dprintk(VIDC_DBG, "OCMEM set, addr = %lx, size: %ld\n",
+ ocmem->addr, ocmem->len);
+ocmem_set_failed:
+ return rc;
+}
+
+int venus_hfi_unset_ocmem(struct venus_hfi_device *device)
+{
+ struct vidc_resource_hdr rhdr;
+ int rc = 0;
+ if (!device || !device->resources.ocmem.buf) {
+ dprintk(VIDC_ERR, "Invalid params, device:%p\n", device);
+ return -EINVAL;
+ }
+ rhdr.resource_id = VIDC_RESOURCE_OCMEM;
+ rhdr.resource_handle = (u32) &device->resources.ocmem;
+ rc = venus_hfi_core_release_resource(device, &rhdr);
+ if (rc)
+ dprintk(VIDC_ERR, "Failed to set OCMEM on driver\n");
+
+ return rc;
+}
+
+int venus_hfi_alloc_ocmem(struct venus_hfi_device *device,
+ unsigned long size)
+{
+ int rc = 0;
+ struct ocmem_buf *ocmem_buffer;
+
+ if (!device || !size) {
+ dprintk(VIDC_ERR,
+ "Invalid param, core: %p, size: %lu\n", device, size);
+ return -EINVAL;
+ }
+ ocmem_buffer = device->resources.ocmem.buf;
+ if (!ocmem_buffer ||
+ ocmem_buffer->len < size) {
+ ocmem_buffer = ocmem_allocate_nb(OCMEM_VIDEO, size);
+ if (IS_ERR_OR_NULL(ocmem_buffer)) {
+ dprintk(VIDC_ERR,
+ "ocmem_allocate_nb failed: %d\n",
+ (u32) ocmem_buffer);
+ rc = -ENOMEM;
+ }
+ device->resources.ocmem.buf = ocmem_buffer;
+ rc = venus_hfi_set_ocmem(device, ocmem_buffer);
+ if (rc) {
+ dprintk(VIDC_ERR, "Failed to set ocmem: %d\n", rc);
+ goto ocmem_set_failed;
+ }
+ } else
+ dprintk(VIDC_DBG,
+ "OCMEM is enough. reqd: %lu, available: %lu\n",
+ size, ocmem_buffer->len);
+
+ocmem_set_failed:
+ return rc;
+}
+
+int venus_hfi_free_ocmem(struct venus_hfi_device *device)
+{
+ int rc = 0;
+
+ if (device->resources.ocmem.buf) {
+ rc = ocmem_free(OCMEM_VIDEO, device->resources.ocmem.buf);
+ if (rc)
+ dprintk(VIDC_ERR, "Failed to free ocmem\n");
+ }
+ device->resources.ocmem.buf = NULL;
+ return rc;
+}
+
+int venus_hfi_is_ocmem_present(struct venus_hfi_device *device)
+{
+ return device->resources.ocmem.buf ? 1 : 0;
+}
+
+static void venus_hfi_deinit_ocmem(struct venus_hfi_device *device)
+{
+ if (device->resources.ocmem.handle)
+ ocmem_notifier_unregister(device->resources.ocmem.handle,
+ &device->resources.ocmem.vidc_ocmem_nb);
+}
+
+static int venus_hfi_init_resources(struct venus_hfi_device *device,
+ struct platform_device *pdev)
+{
+ int rc = 0;
+
+ rc = venus_hfi_init_clocks(pdev, device);
+ if (rc) {
+ dprintk(VIDC_ERR, "Failed to init clocks\n");
+ rc = -ENODEV;
+ goto err_init_clocks;
+ }
+
+ rc = venus_hfi_init_bus(device);
+ if (rc) {
+ dprintk(VIDC_ERR, "Failed to init bus: %d\n", rc);
+ goto err_init_bus;
+ }
+
+ rc = venus_hfi_register_iommu_domains(device, pdev);
+ if (rc) {
+ dprintk(VIDC_ERR, "Failed to register iommu domains: %d\n", rc);
+ goto err_register_iommu_domain;
+ }
+
+ venus_hfi_ocmem_init(device);
+ return rc;
+
+err_register_iommu_domain:
+ venus_hfi_deinit_bus(device);
+err_init_bus:
+ venus_hfi_deinit_clocks(device);
+err_init_clocks:
+ return rc;
+}
+
+static void venus_hfi_deinit_resources(struct venus_hfi_device *device)
+{
+ venus_hfi_deinit_ocmem(device);
+ venus_hfi_deinit_bus(device);
+ venus_hfi_deinit_clocks(device);
+}
+
+static int venus_hfi_iommu_attach(struct venus_hfi_device *device)
+{
+ int rc;
+ struct iommu_domain *domain;
+ int i;
+ struct msm_vidc_iommu_info *io_map;
+ struct device *dev;
+
+ if (!device)
+ return -EINVAL;
+
+ for (i = 0; i < MAX_MAP; i++) {
+ io_map = &device->resources.io_map[i];
+ dev = msm_iommu_get_ctx(io_map->ctx);
+ domain = msm_get_iommu_domain(io_map->domain);
+ if (IS_ERR_OR_NULL(domain)) {
+ dprintk(VIDC_ERR,
+ "Failed to get domain: %s\n", io_map->name);
+ rc = PTR_ERR(domain);
+ break;
+ }
+ rc = iommu_attach_device(domain, dev);
+ if (rc) {
+ dprintk(VIDC_ERR,
+ "IOMMU attach failed: %s\n", io_map->name);
+ break;
+ }
+ }
+ if (i < MAX_MAP) {
+ i--;
+ for (; i >= 0; i--) {
+ io_map = &device->resources.io_map[i];
+ dev = msm_iommu_get_ctx(io_map->ctx);
+ domain = msm_get_iommu_domain(io_map->domain);
+ if (dev && domain)
+ iommu_detach_device(domain, dev);
+ }
+ }
+ return rc;
+}
+
+static void venus_hfi_iommu_detach(struct venus_hfi_device *device)
+{
+ struct device *dev;
+ struct iommu_domain *domain;
+ struct msm_vidc_iommu_info *io_map;
+ int i;
+
+ if (!device) {
+ dprintk(VIDC_ERR, "Invalid paramter: %p\n", device);
+ return;
+ }
+
+ for (i = 0; i < MAX_MAP; i++) {
+ io_map = &device->resources.io_map[i];
+ dev = msm_iommu_get_ctx(io_map->ctx);
+ domain = msm_get_iommu_domain(io_map->domain);
+ if (dev && domain)
+ iommu_detach_device(domain, dev);
+ }
+}
+
+int venus_hfi_get_domain(struct venus_hfi_device *device,
+ enum msm_vidc_io_maps iomap)
+{
+ if (!device || iomap < CP_MAP || iomap >= MAX_MAP) {
+ dprintk(VIDC_ERR, "%s: Invalid parameter: %p iomap: %d\n",
+ __func__, device, iomap);
+ return -EINVAL;
+ }
+ return device->resources.io_map[iomap].domain;
+}
+
+int venus_hfi_iommu_get_map(struct venus_hfi_device *device,
+ struct msm_vidc_iommu_info maps[MAX_MAP])
+{
+ int i = 0;
+
+ if (!device || !maps) {
+ dprintk(VIDC_ERR, "%s: Invalid param device: %p maps: %p\n",
+ __func__, device, maps);
+ return -EINVAL;
+ }
+
+ for (i = 0; i < MAX_MAP; i++)
+ maps[i] = device->resources.io_map[i];
+
+ return 0;
+}
+
+static int protect_cp_mem(struct venus_hfi_device *device)
+{
+ struct tzbsp_memprot memprot;
+ unsigned int resp = 0;
+ int rc = 0;
+ struct msm_vidc_iommu_info *io_map;
+
+ if (!device)
+ return -EINVAL;
+
+ io_map = device->resources.io_map;
+ if (!io_map) {
+ dprintk(VIDC_ERR, "invalid params: %p\n", io_map);
+ return -EINVAL;
+ }
+ memprot.cp_start = 0x0;
+ memprot.cp_size = io_map[CP_MAP].addr_range[0] +
+ io_map[CP_MAP].addr_range[1];
+ memprot.cp_nonpixel_start = 0;
+ memprot.cp_nonpixel_size = 0;
+
+ rc = scm_call(SCM_SVC_CP, TZBSP_MEM_PROTECT_VIDEO_VAR, &memprot,
+ sizeof(memprot), &resp, sizeof(resp));
+ if (rc)
+ dprintk(VIDC_ERR,
+ "Failed to protect memory , rc is :%d, response : %d\n",
+ rc, resp);
+ return rc;
+}
+
+int venus_hfi_load_fw(struct venus_hfi_device *device)
+{
+ int rc = 0;
+
+ if (!device) {
+ dprintk(VIDC_ERR, "Invalid paramter: %p\n", device);
+ return -EINVAL;
+ }
+
+ if (!device->resources.fw.cookie)
+ device->resources.fw.cookie = subsystem_get("venus");
+
+ if (IS_ERR_OR_NULL(device->resources.fw.cookie)) {
+ dprintk(VIDC_ERR, "Failed to download firmware\n");
+ rc = -ENOMEM;
+ goto fail_load_fw;
+ }
+ /*Clocks can be enabled only after pil_get since
+ * gdsc is turned-on in pil_get*/
+ rc = venus_hfi_enable_clks(device);
+ if (rc) {
+ dprintk(VIDC_ERR, "Failed to enable clocks: %d\n", rc);
+ goto fail_enable_clks;
+ }
+
+ rc = protect_cp_mem(device);
+ if (rc) {
+ dprintk(VIDC_ERR, "Failed to protect memory\n");
+ goto fail_iommu_attach;
+ }
+
+ rc = venus_hfi_iommu_attach(device);
+ if (rc) {
+ dprintk(VIDC_ERR, "Failed to attach iommu");
+ goto fail_iommu_attach;
+ }
+ return rc;
+fail_iommu_attach:
+ venus_hfi_disable_clks(device);
+fail_enable_clks:
+ subsystem_put(device->resources.fw.cookie);
+ device->resources.fw.cookie = NULL;
+fail_load_fw:
+ return rc;
+}
+
+void venus_hfi_unload_fw(struct venus_hfi_device *device)
+{
+ if (!device) {
+ dprintk(VIDC_ERR, "Invalid paramter: %p\n", device);
+ return;
+ }
+ if (device->resources.fw.cookie) {
+ venus_hfi_iommu_detach(device);
+ venus_hfi_disable_clks(device);
+ subsystem_put(device->resources.fw.cookie);
+ device->resources.fw.cookie = NULL;
+ }
+}
+
+static void *venus_hfi_add_device(u32 device_id, struct platform_device *pdev,
+ void (*callback) (enum command_response cmd, void *data))
+{
+ struct venus_hfi_device *hdevice = NULL;
+ int rc = 0;
+
+ if (device_id || !pdev || !callback) {
dprintk(VIDC_ERR, "Invalid Paramters");
return NULL;
- } else {
- dprintk(VIDC_INFO, "entered , device_id: %d", device_id);
}
- if (vidc_hal_check_core_registered(hal_ctxt, fw_base_addr,
- reg_base, reg_size, irq)) {
- dprintk(VIDC_DBG, "HAL_DATA will be assigned now");
- hal = (struct hal_data *)
- kzalloc(sizeof(struct hal_data), GFP_KERNEL);
- if (!hal) {
- dprintk(VIDC_ERR, "Failed to alloc");
- return NULL;
- }
- hal->irq = irq;
- hal->device_base_addr = fw_base_addr;
- hal->register_base_addr =
- ioremap_nocache(reg_base, reg_size);
- if (!hal->register_base_addr) {
- dprintk(VIDC_ERR,
- "could not map reg addr %d of size %d",
- reg_base, reg_size);
- goto err_map;
- }
- INIT_LIST_HEAD(&hal_ctxt.dev_head);
- } else {
- dprintk(VIDC_ERR, "Core present/Already added");
- return NULL;
- }
+ dprintk(VIDC_INFO, "entered , device_id: %d", device_id);
- hdevice = (struct hal_device *)
- kzalloc(sizeof(struct hal_device), GFP_KERNEL);
+ hdevice = (struct venus_hfi_device *)
+ kzalloc(sizeof(struct venus_hfi_device), GFP_KERNEL);
if (!hdevice) {
dprintk(VIDC_ERR, "failed to allocate new device");
- goto err_map;
+ goto err_alloc;
}
+ rc = venus_hfi_init_regs_and_interrupts(hdevice, pdev);
+ if (rc)
+ goto err_init_regs;
+
+ INIT_LIST_HEAD(&hal_ctxt.dev_head);
INIT_LIST_HEAD(&hdevice->list);
list_add_tail(&hdevice->list, &hal_ctxt.dev_head);
hal_ctxt.dev_count++;
hdevice->device_id = device_id;
- hdevice->hal_data = hal;
+
hdevice->callback = callback;
hdevice->vidc_workq = create_singlethread_workqueue(
@@ -1596,30 +2776,53 @@
goto error_createq;
}
- rc = request_irq(irq, vidc_hal_isr, IRQF_TRIGGER_HIGH,
- "msm_vidc", hdevice);
- if (unlikely(rc)) {
- dprintk(VIDC_ERR, "() :request_irq failed\n");
- goto error_irq_fail;
- }
- disable_irq_nosync(irq);
return (void *) hdevice;
-error_irq_fail:
- destroy_workqueue(hdevice->vidc_workq);
error_createq:
hal_ctxt.dev_count--;
list_del(&hal_ctxt.dev_head);
-err_map:
- kfree(hal);
+err_init_regs:
+ kfree(hdevice);
+err_alloc:
return NULL;
}
-void vidc_hal_delete_device(void *device)
+void *venus_hfi_get_device(u32 device_id,
+ struct platform_device *pdev,
+ void (*callback) (enum command_response cmd, void *data))
{
- struct hal_device *close, *dev;
+ struct venus_hfi_device *device;
+ int rc = 0;
+
+ if (!pdev || !callback) {
+ dprintk(VIDC_ERR, "Invalid params: %p %p\n", pdev, callback);
+ return NULL;
+ }
+
+ device = venus_hfi_add_device(device_id, pdev, &handle_cmd_response);
+ if (!device) {
+ dprintk(VIDC_ERR, "Failed to create HFI device\n");
+ return NULL;
+ }
+
+ rc = venus_hfi_init_resources(device, pdev);
+ if (rc) {
+ dprintk(VIDC_ERR, "Failed to init resources: %d\n", rc);
+ goto err_fail_init_res;
+ }
+ return device;
+
+err_fail_init_res:
+ venus_hfi_delete_device(device);
+ return NULL;
+}
+
+void venus_hfi_delete_device(void *device)
+{
+ struct venus_hfi_device *close, *dev;
if (device) {
- dev = (struct hal_device *) device;
+ venus_hfi_deinit_resources(device);
+ dev = (struct venus_hfi_device *) device;
list_for_each_entry(close, &hal_ctxt.dev_head, list) {
if (close->hal_data->irq == dev->hal_data->irq) {
hal_ctxt.dev_count--;
diff --git a/drivers/media/video/msm_vidc/venus_hfi.h b/drivers/media/video/msm_vidc/venus_hfi.h
index 6b904fd..93b9ae3 100644
--- a/drivers/media/video/msm_vidc/venus_hfi.h
+++ b/drivers/media/video/msm_vidc/venus_hfi.h
@@ -14,8 +14,12 @@
#ifndef __H_VENUS_HFI_H__
#define __H_VENUS_HFI_H__
-#include <linux/spinlock.h>
+#include <linux/clk.h>
#include <linux/mutex.h>
+#include <linux/platform_device.h>
+#include <linux/spinlock.h>
+#include <mach/ocmem.h>
+#include <media/msm_vidc.h>
#include "vidc_hfi_api.h"
#include "msm_smem.h"
#include "vidc_hfi_helper.h"
@@ -45,6 +49,8 @@
#define VIDC_IFACE_MAX_PARALLEL_CLNTS 16
#define VIDC_IFACEQ_DFLT_QHDR 0x01010000
+#define VIDC_MAX_NAME_LENGTH 64
+
struct hfi_queue_table_header {
u32 qtbl_version;
u32 qtbl_size;
@@ -907,7 +913,55 @@
u8 *register_base_addr;
};
-struct hal_device {
+enum vidc_clocks {
+ VCODEC_CLK,
+ VCODEC_AHB_CLK,
+ VCODEC_AXI_CLK,
+ VCODEC_OCMEM_CLK,
+ VCODEC_MAX_CLKS
+};
+
+enum mem_type {
+ DDR_MEM = 0x1,
+ OCMEM_MEM = 0x2,
+};
+
+struct load_freq_table {
+ u32 load;
+ u32 freq;
+};
+
+struct msm_vidc_fw {
+ void *cookie;
+};
+
+struct venus_core_clock {
+ char name[VIDC_MAX_NAME_LENGTH];
+ struct clk *clk;
+ u32 count;
+ struct load_freq_table load_freq_tbl[8];
+};
+
+struct venus_bus_info {
+ u32 ddr_handle[MSM_VIDC_MAX_DEVICES];
+ u32 ocmem_handle[MSM_VIDC_MAX_DEVICES];
+};
+
+struct on_chip_mem {
+ struct ocmem_buf *buf;
+ struct notifier_block vidc_ocmem_nb;
+ void *handle;
+};
+
+struct venus_resources {
+ struct msm_vidc_fw fw;
+ struct msm_vidc_iommu_info io_map[MAX_MAP];
+ struct venus_core_clock clock[VCODEC_MAX_CLKS];
+ struct venus_bus_info bus_info;
+ struct on_chip_mem ocmem;
+};
+
+struct venus_hfi_device {
struct list_head list;
struct list_head sess_head;
u32 intr_status;
@@ -925,13 +979,18 @@
struct workqueue_struct *vidc_workq;
int spur_count;
int reg_count;
+ u32 base_addr;
+ u32 register_base;
+ u32 register_size;
+ u32 irq;
+ struct venus_resources resources;
};
struct hal_session {
struct list_head list;
u32 session_id;
u32 is_decoder;
- struct hal_device *device;
+ struct venus_hfi_device *device;
};
struct hal_device_data {
@@ -941,10 +1000,35 @@
extern struct hal_device_data hal_ctxt;
-int vidc_hal_iface_msgq_read(struct hal_device *device, void *pkt);
-int vidc_hal_iface_dbgq_read(struct hal_device *device, void *pkt);
+int venus_hfi_iface_msgq_read(struct venus_hfi_device *device, void *pkt);
+int venus_hfi_iface_dbgq_read(struct venus_hfi_device *device, void *pkt);
/* Interrupt Processing:*/
-void vidc_hal_response_handler(struct hal_device *device);
+void hfi_response_handler(struct venus_hfi_device *device);
+
+void venus_hfi_delete_device(void *device);
+
+int venus_hfi_scale_clocks(struct venus_hfi_device *device, int load);
+
+void *venus_hfi_get_device(u32 device_id,
+ struct platform_device *pdev,
+ void (*callback) (enum command_response cmd, void *data));
+
+int venus_hfi_scale_bus(struct venus_hfi_device *device, int load,
+ enum session_type type, enum mem_type mtype);
+int venus_hfi_set_ocmem(struct venus_hfi_device *device,
+ struct ocmem_buf *ocmem);
+int venus_hfi_unset_ocmem(struct venus_hfi_device *device);
+int venus_hfi_alloc_ocmem(struct venus_hfi_device *device,
+ unsigned long size);
+int venus_hfi_free_ocmem(struct venus_hfi_device *device);
+int venus_hfi_is_ocmem_present(struct venus_hfi_device *device);
+
+int venus_hfi_get_domain(struct venus_hfi_device *device,
+ enum msm_vidc_io_maps iomap);
+int venus_hfi_iommu_get_map(struct venus_hfi_device *device,
+ struct msm_vidc_iommu_info maps[MAX_MAP]);
+int venus_hfi_load_fw(struct venus_hfi_device *device);
+void venus_hfi_unload_fw(struct venus_hfi_device *device);
#endif
diff --git a/drivers/media/video/msm_vidc/vidc_hfi_api.h b/drivers/media/video/msm_vidc/vidc_hfi_api.h
index 02f474c..79fee90 100644
--- a/drivers/media/video/msm_vidc/vidc_hfi_api.h
+++ b/drivers/media/video/msm_vidc/vidc_hfi_api.h
@@ -980,47 +980,43 @@
};
/* VIDC_HAL CORE API's */
-int vidc_hal_core_init(void *device, int domain);
-int vidc_hal_core_release(void *device);
-int vidc_hal_core_pc_prep(void *device);
-int vidc_hal_core_set_resource(void *device,
+int venus_hfi_core_init(void *device);
+int venus_hfi_core_release(void *device);
+int venus_hfi_core_pc_prep(void *device);
+int venus_hfi_core_set_resource(void *device,
struct vidc_resource_hdr *resource_hdr, void *resource_value);
-int vidc_hal_core_release_resource(void *device,
+int venus_hfi_core_release_resource(void *device,
struct vidc_resource_hdr *resource_hdr);
-int vidc_hal_core_ping(void *device);
+int venus_hfi_core_ping(void *device);
/* VIDC_HAL SESSION API's */
-void *vidc_hal_session_init(void *device, u32 session_id,
+void *venus_hfi_session_init(void *device, u32 session_id,
enum hal_domain session_type, enum hal_video_codec codec_type);
-int vidc_hal_session_end(void *session);
-int vidc_hal_session_abort(void *session);
-int vidc_hal_session_set_buffers(void *sess,
+int venus_hfi_session_end(void *session);
+int venus_hfi_session_abort(void *session);
+int venus_hfi_session_set_buffers(void *sess,
struct vidc_buffer_addr_info *buffer_info);
-int vidc_hal_session_release_buffers(void *sess,
+int venus_hfi_session_release_buffers(void *sess,
struct vidc_buffer_addr_info *buffer_info);
-int vidc_hal_session_load_res(void *sess);
-int vidc_hal_session_release_res(void *sess);
-int vidc_hal_session_start(void *sess);
-int vidc_hal_session_stop(void *sess);
-int vidc_hal_session_suspend(void *sess);
-int vidc_hal_session_resume(void *sess);
-int vidc_hal_session_etb(void *sess,
+int venus_hfi_session_load_res(void *sess);
+int venus_hfi_session_release_res(void *sess);
+int venus_hfi_session_start(void *sess);
+int venus_hfi_session_stop(void *sess);
+int venus_hfi_session_suspend(void *sess);
+int venus_hfi_session_resume(void *sess);
+int venus_hfi_session_etb(void *sess,
struct vidc_frame_data *input_frame);
-int vidc_hal_session_ftb(void *sess,
+int venus_hfi_session_ftb(void *sess,
struct vidc_frame_data *output_frame);
-int vidc_hal_session_parse_seq_hdr(void *sess,
+int venus_hfi_session_parse_seq_hdr(void *sess,
struct vidc_seq_hdr *seq_hdr);
-int vidc_hal_session_get_seq_hdr(void *sess,
+int venus_hfi_session_get_seq_hdr(void *sess,
struct vidc_seq_hdr *seq_hdr);
-int vidc_hal_session_get_buf_req(void *sess);
-int vidc_hal_session_flush(void *sess, enum hal_flush flush_mode);
-int vidc_hal_session_set_property(void *sess, enum hal_property ptype,
+int venus_hfi_session_get_buf_req(void *sess);
+int venus_hfi_session_flush(void *sess, enum hal_flush flush_mode);
+int venus_hfi_session_set_property(void *sess, enum hal_property ptype,
void *pdata);
-int vidc_hal_session_get_property(void *sess, enum hal_property ptype,
+int venus_hfi_session_get_property(void *sess, enum hal_property ptype,
void *pdata);
-void *vidc_hal_add_device(u32 device_id, u32 base_addr,
- u32 reg_base, u32 reg_size, u32 irq,
- void (*callback) (enum command_response cmd, void *data));
-void vidc_hal_delete_device(void *device);
#endif /*__VIDC_HFI_API_H__ */
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 464f19f..ff0fc74 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -1054,6 +1054,16 @@
The WCD9320 codec support either I2C/I2S or Slimbus for
control and data exchnage with master processor.
+config WCD9306_CODEC
+ tristate "WCD9306 Codec"
+ select SLIMBUS
+ select MFD_CORE
+ help
+ Enables the WCD9xxx codec core driver. The core driver provides
+ read/write capability to registers which are part of the
+ WCD9306 core and gives the ability to use the WCD9306 codec.
+ The WCD9306 codec supports either I2C/I2S or Slimbus for
+ control and data exchnage with master processor.
config MFD_RC5T583
bool "Ricoh RC5T583 Power Management system device"
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 07552c8..ce65e3f 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -81,6 +81,7 @@
obj-$(CONFIG_WCD9310_CODEC) += wcd9xxx-core.o wcd9xxx-irq.o wcd9xxx-slimslave.o
obj-$(CONFIG_WCD9304_CODEC) += wcd9xxx-core.o wcd9xxx-irq.o wcd9xxx-slimslave.o
obj-$(CONFIG_WCD9320_CODEC) += wcd9xxx-core.o wcd9xxx-irq.o wcd9xxx-slimslave.o
+obj-$(CONFIG_WCD9306_CODEC) += wcd9xxx-core.o wcd9xxx-irq.o wcd9xxx-slimslave.o
ifeq ($(CONFIG_SA1100_ASSABET),y)
diff --git a/drivers/mfd/wcd9xxx-core.c b/drivers/mfd/wcd9xxx-core.c
index d43b399..bc129da 100644
--- a/drivers/mfd/wcd9xxx-core.c
+++ b/drivers/mfd/wcd9xxx-core.c
@@ -46,6 +46,11 @@
#define WCD9XXX_I2C_DIGITAL_1 2
#define WCD9XXX_I2C_DIGITAL_2 3
+/* Number of return values needs to be checked for each
+ * registration of Slimbus of I2C bus for each codec
+ */
+#define NUM_WCD9XXX_REG_RET 8
+
struct wcd9xxx_i2c {
struct i2c_client *client;
struct i2c_msg xfer_msg[2];
@@ -58,6 +63,11 @@
"cdc-vdd-a-1p2v", "cdc-vddcx-1", "cdc-vddcx-2",
};
+static char *tapan_supplies[] = {
+ "cdc-vdd-buck", "cdc-vdd-h", "cdc-vdd-px",
+ "cdc-vdd-a-1p2v", "cdc-vdd-cx"
+};
+
static int wcd9xxx_dt_parse_vreg_info(struct device *dev,
struct wcd9xxx_regulator *vreg, const char *vreg_name);
static int wcd9xxx_dt_parse_micbias_info(struct device *dev,
@@ -275,6 +285,12 @@
},
};
+static struct mfd_cell tapan_devs[] = {
+ {
+ .name = "tapan_codec",
+ },
+};
+
static struct wcd9xx_codec_type {
u8 byte[4];
struct mfd_cell *dev;
@@ -287,6 +303,8 @@
TABLA_NUM_IRQS},
{{0x0, 0x0, 0x2, 0x1}, taiko_devs, ARRAY_SIZE(taiko_devs),
TAIKO_NUM_IRQS},
+ {{0x0, 0x0, 0x3, 0x1}, tapan_devs, ARRAY_SIZE(tapan_devs),
+ TAPAN_NUM_IRQS},
{{0x0, 0x0, 0x0, 0x1}, sitar_devs, ARRAY_SIZE(sitar_devs),
SITAR_NUM_IRQS},
{{0x1, 0x0, 0x1, 0x1}, sitar_devs, ARRAY_SIZE(sitar_devs),
@@ -987,92 +1005,54 @@
return 0;
}
+static int wcd9xxx_read_of_property_u32(struct device *dev,
+ const char *name, u32 *val)
+{
+ int ret = 0;
+ ret = of_property_read_u32(dev->of_node, name, val);
+ if (ret)
+ dev_err(dev, "Looking up %s property in node %s failed",
+ name, dev->of_node->full_name);
+ return ret;
+}
+
static int wcd9xxx_dt_parse_micbias_info(struct device *dev,
struct wcd9xxx_micbias_setting *micbias)
{
- int ret = 0;
- char prop_name[CODEC_DT_MAX_PROP_SIZE];
u32 prop_val;
- snprintf(prop_name, CODEC_DT_MAX_PROP_SIZE,
- "qcom,cdc-micbias-ldoh-v");
- ret = of_property_read_u32(dev->of_node, prop_name, &prop_val);
- if (ret) {
- dev_err(dev, "Looking up %s property in node %s failed",
- prop_name, dev->of_node->full_name);
- return -ENODEV;
- }
- micbias->ldoh_v = (u8)prop_val;
+ if (!(wcd9xxx_read_of_property_u32(dev, "qcom,cdc-micbias-ldoh-v",
+ &prop_val)))
+ micbias->ldoh_v = (u8)prop_val;
- snprintf(prop_name, CODEC_DT_MAX_PROP_SIZE,
- "qcom,cdc-micbias-cfilt1-mv");
- ret = of_property_read_u32(dev->of_node, prop_name,
- &micbias->cfilt1_mv);
- if (ret) {
- dev_err(dev, "Looking up %s property in node %s failed",
- prop_name, dev->of_node->full_name);
- return -ENODEV;
- }
+ wcd9xxx_read_of_property_u32(dev, "qcom,cdc-micbias-cfilt1-mv",
+ &micbias->cfilt1_mv);
- snprintf(prop_name, CODEC_DT_MAX_PROP_SIZE,
- "qcom,cdc-micbias-cfilt2-mv");
- ret = of_property_read_u32(dev->of_node, prop_name,
- &micbias->cfilt2_mv);
- if (ret) {
- dev_err(dev, "Looking up %s property in node %s failed",
- prop_name, dev->of_node->full_name);
- return -ENODEV;
- }
+ wcd9xxx_read_of_property_u32(dev, "qcom,cdc-micbias-cfilt2-mv",
+ &micbias->cfilt2_mv);
- snprintf(prop_name, CODEC_DT_MAX_PROP_SIZE,
- "qcom,cdc-micbias-cfilt3-mv");
- ret = of_property_read_u32(dev->of_node, prop_name,
- &micbias->cfilt3_mv);
- if (ret) {
- dev_err(dev, "Looking up %s property in node %s failed",
- prop_name, dev->of_node->full_name);
- return -ENODEV;
- }
+ wcd9xxx_read_of_property_u32(dev, "qcom,cdc-micbias-cfilt3-mv",
+ &micbias->cfilt3_mv);
- snprintf(prop_name, CODEC_DT_MAX_PROP_SIZE,
- "qcom,cdc-micbias1-cfilt-sel");
- ret = of_property_read_u32(dev->of_node, prop_name, &prop_val);
- if (ret) {
- dev_err(dev, "Looking up %s property in node %s failed",
- prop_name, dev->of_node->full_name);
- return -ENODEV;
- }
- micbias->bias1_cfilt_sel = (u8)prop_val;
+ /* Read micbias values for codec. Does not matter even if a few
+ * micbias values are not defined in the Device Tree. Codec will
+ * anyway not use those values
+ */
+ if (!(wcd9xxx_read_of_property_u32(dev, "qcom,cdc-micbias1-cfilt-sel",
+ &prop_val)))
+ micbias->bias1_cfilt_sel = (u8)prop_val;
- snprintf(prop_name, CODEC_DT_MAX_PROP_SIZE,
- "qcom,cdc-micbias2-cfilt-sel");
- ret = of_property_read_u32(dev->of_node, prop_name, &prop_val);
- if (ret) {
- dev_err(dev, "Looking up %s property in node %s failed",
- prop_name, dev->of_node->full_name);
- return -ENODEV;
- }
- micbias->bias2_cfilt_sel = (u8)prop_val;
+ if (!(wcd9xxx_read_of_property_u32(dev, "qcom,cdc-micbias2-cfilt-sel",
+ &prop_val)))
+ micbias->bias2_cfilt_sel = (u8)prop_val;
- snprintf(prop_name, CODEC_DT_MAX_PROP_SIZE,
- "qcom,cdc-micbias3-cfilt-sel");
- ret = of_property_read_u32(dev->of_node, prop_name, &prop_val);
- if (ret) {
- dev_err(dev, "Looking up %s property in node %s failed",
- prop_name, dev->of_node->full_name);
- return -ENODEV;
- }
- micbias->bias3_cfilt_sel = (u8)prop_val;
+ if (!(wcd9xxx_read_of_property_u32(dev, "qcom,cdc-micbias3-cfilt-sel",
+ &prop_val)))
+ micbias->bias3_cfilt_sel = (u8)prop_val;
- snprintf(prop_name, CODEC_DT_MAX_PROP_SIZE,
- "qcom,cdc-micbias4-cfilt-sel");
- ret = of_property_read_u32(dev->of_node, prop_name, &prop_val);
- if (ret) {
- dev_err(dev, "Looking up %s property in node %s failed",
- prop_name, dev->of_node->full_name);
- return -ENODEV;
- }
- micbias->bias4_cfilt_sel = (u8)prop_val;
+ if (!(wcd9xxx_read_of_property_u32(dev, "qcom,cdc-micbias4-cfilt-sel",
+ &prop_val)))
+ micbias->bias4_cfilt_sel = (u8)prop_val;
/* micbias external cap */
micbias->bias1_cap_mode =
@@ -1153,6 +1133,9 @@
(!strcmp(dev_name(dev), WCD9XXX_I2C_GSBI_SLAVE_ID))) {
codec_supplies = taiko_supplies;
num_of_supplies = ARRAY_SIZE(taiko_supplies);
+ } else if (!strcmp(dev_name(dev), "tapan-slim-pgd")) {
+ codec_supplies = tapan_supplies;
+ num_of_supplies = ARRAY_SIZE(tapan_supplies);
} else {
dev_err(dev, "%s unsupported device %s\n",
__func__, dev_name(dev));
@@ -1552,6 +1535,23 @@
.suspend = wcd9xxx_slim_suspend,
};
+static const struct slim_device_id tapan_slimtest_id[] = {
+ {"tapan-slim-pgd", 0},
+ {}
+};
+
+static struct slim_driver tapan_slim_driver = {
+ .driver = {
+ .name = "tapan-slim",
+ .owner = THIS_MODULE,
+ },
+ .probe = wcd9xxx_slim_probe,
+ .remove = wcd9xxx_slim_remove,
+ .id_table = tapan_slimtest_id,
+ .resume = wcd9xxx_slim_resume,
+ .suspend = wcd9xxx_slim_suspend,
+};
+
static struct i2c_device_id wcd9xxx_id_table[] = {
{"wcd9xxx-i2c", WCD9XXX_I2C_TOP_LEVEL},
{"wcd9xxx-i2c", WCD9XXX_I2C_ANALOG},
@@ -1596,39 +1596,48 @@
static int __init wcd9xxx_init(void)
{
- int ret1, ret2, ret3, ret4, ret5, ret6, ret7;
+ int ret[NUM_WCD9XXX_REG_RET];
+ int i = 0;
wcd9xxx_intf = WCD9XXX_INTERFACE_TYPE_PROBING;
- ret1 = slim_driver_register(&tabla_slim_driver);
- if (ret1 != 0)
- pr_err("Failed to register tabla SB driver: %d\n", ret1);
+ ret[0] = slim_driver_register(&tabla_slim_driver);
+ if (ret[0])
+ pr_err("Failed to register tabla SB driver: %d\n", ret[0]);
- ret2 = slim_driver_register(&tabla2x_slim_driver);
- if (ret2 != 0)
- pr_err("Failed to register tabla2x SB driver: %d\n", ret2);
+ ret[1] = slim_driver_register(&tabla2x_slim_driver);
+ if (ret[1])
+ pr_err("Failed to register tabla2x SB driver: %d\n", ret[1]);
- ret3 = i2c_add_driver(&tabla_i2c_driver);
- if (ret3 != 0)
- pr_err("failed to add the tabla2x I2C driver\n");
+ ret[2] = i2c_add_driver(&tabla_i2c_driver);
+ if (ret[2])
+ pr_err("failed to add the tabla2x I2C driver: %d\n", ret[2]);
- ret4 = slim_driver_register(&sitar_slim_driver);
- if (ret4 != 0)
- pr_err("Failed to register sitar SB driver: %d\n", ret4);
+ ret[3] = slim_driver_register(&sitar_slim_driver);
+ if (ret[3])
+ pr_err("Failed to register sitar SB driver: %d\n", ret[3]);
- ret5 = slim_driver_register(&sitar1p1_slim_driver);
- if (ret5 != 0)
- pr_err("Failed to register sitar SB driver: %d\n", ret5);
+ ret[4] = slim_driver_register(&sitar1p1_slim_driver);
+ if (ret[4])
+ pr_err("Failed to register sitar SB driver: %d\n", ret[4]);
- ret6 = slim_driver_register(&taiko_slim_driver);
- if (ret6 != 0)
- pr_err("Failed to register taiko SB driver: %d\n", ret6);
+ ret[5] = slim_driver_register(&taiko_slim_driver);
+ if (ret[5])
+ pr_err("Failed to register taiko SB driver: %d\n", ret[5]);
- ret7 = i2c_add_driver(&wcd9xxx_i2c_driver);
- if (ret7 != 0)
- pr_err("failed to add the wcd9xxx I2C driver\n");
+ ret[6] = i2c_add_driver(&wcd9xxx_i2c_driver);
+ if (ret[6])
+ pr_err("failed to add the wcd9xxx I2C driver: %d\n", ret[6]);
- return (ret1 && ret2 && ret3 && ret4 && ret5 && ret6 && ret7) ? -1 : 0;
+ ret[7] = slim_driver_register(&tapan_slim_driver);
+ if (ret[7])
+ pr_err("Failed to register tapan SB driver: %d\n", ret[7]);
+
+ for (i = 0; i < NUM_WCD9XXX_REG_RET; i++) {
+ if (ret[i])
+ return ret[i];
+ }
+ return 0;
}
module_init(wcd9xxx_init);
diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c
index 864dfa7..f598e63 100644
--- a/drivers/mmc/core/core.c
+++ b/drivers/mmc/core/core.c
@@ -51,7 +51,7 @@
* Background operations can take a long time, depending on the housekeeping
* operations the card has to perform.
*/
-#define MMC_BKOPS_MAX_TIMEOUT (4 * 60 * 1000) /* max time to wait in ms */
+#define MMC_BKOPS_MAX_TIMEOUT (30 * 1000) /* max time to wait in ms */
static struct workqueue_struct *workqueue;
@@ -443,7 +443,8 @@
}
err = __mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
- EXT_CSD_BKOPS_START, 1, timeout, use_busy_signal);
+ EXT_CSD_BKOPS_START, 1, timeout,
+ use_busy_signal, use_busy_signal);
if (err) {
pr_warn("%s: %s: Error %d when starting bkops\n",
mmc_hostname(card->host), __func__, err);
@@ -679,6 +680,24 @@
wait_for_completion_io(&mrq->completion);
cmd = mrq->cmd;
+
+ /*
+ * If host has timed out waiting for the blocking BKOPs
+ * to complete, card might be still in programming state
+ * so let's try to bring the card out of programming state.
+ */
+ if (cmd->bkops_busy && cmd->error == -ETIMEDOUT) {
+ if (!mmc_interrupt_hpi(host->card)) {
+ pr_warning("%s: %s: Interrupted blocking bkops\n",
+ mmc_hostname(host), __func__);
+ cmd->error = 0;
+ break;
+ } else {
+ pr_err("%s: %s: Failed to interrupt blocking bkops\n",
+ mmc_hostname(host), __func__);
+ }
+ }
+
if (!cmd->error || !cmd->retries ||
mmc_card_removed(host->card))
break;
diff --git a/drivers/mmc/core/mmc_ops.c b/drivers/mmc/core/mmc_ops.c
index 4f46ed1..f8c9720 100644
--- a/drivers/mmc/core/mmc_ops.c
+++ b/drivers/mmc/core/mmc_ops.c
@@ -376,11 +376,13 @@
* @timeout_ms: timeout (ms) for operation performed by register write,
* timeout of zero implies maximum possible timeout
* @use_busy_signal: use the busy signal as response type
+ * @bkops_busy: set this to indicate that we are starting blocking bkops
*
* Modifies the EXT_CSD register for selected card.
*/
int __mmc_switch(struct mmc_card *card, u8 set, u8 index, u8 value,
- unsigned int timeout_ms, bool use_busy_signal)
+ unsigned int timeout_ms, bool use_busy_signal,
+ bool bkops_busy)
{
int err;
struct mmc_command cmd = {0};
@@ -402,6 +404,7 @@
cmd.cmd_timeout_ms = timeout_ms;
+ cmd.bkops_busy = bkops_busy;
err = mmc_wait_for_cmd(card->host, &cmd, MMC_CMD_RETRIES);
if (err)
@@ -440,7 +443,7 @@
int mmc_switch(struct mmc_card *card, u8 set, u8 index, u8 value,
unsigned int timeout_ms)
{
- return __mmc_switch(card, set, index, value, timeout_ms, true);
+ return __mmc_switch(card, set, index, value, timeout_ms, true, false);
}
EXPORT_SYMBOL_GPL(mmc_switch);
diff --git a/drivers/mmc/host/msm_sdcc.c b/drivers/mmc/host/msm_sdcc.c
index e8f3d38..f1ba8ad 100644
--- a/drivers/mmc/host/msm_sdcc.c
+++ b/drivers/mmc/host/msm_sdcc.c
@@ -163,6 +163,10 @@
static int msmsdcc_dt_get_array(struct device *dev, const char *prop_name,
u32 **out_array, int *len, int size);
static int msmsdcc_execute_tuning(struct mmc_host *mmc, u32 opcode);
+static bool msmsdcc_is_wait_for_auto_prog_done(struct msmsdcc_host *host,
+ struct mmc_request *mrq);
+static bool msmsdcc_is_wait_for_prog_done(struct msmsdcc_host *host,
+ struct mmc_request *mrq);
static inline unsigned short msmsdcc_get_nr_sg(struct msmsdcc_host *host)
{
@@ -440,18 +444,23 @@
{
struct mmc_request *mrq = host->curr.mrq;
- if (!mrq || !mrq->cmd || (!mrq->data && !host->pending_dpsm_reset))
- goto out;
+ if (!mrq || !mrq->cmd || !mrq->data)
+ goto out;
/*
- * For CMD24, if auto prog done is not supported defer
- * dpsm reset until prog done is received. Otherwise,
- * we poll here unnecessarily as TXACTIVE will not be
- * deasserted until DAT0 goes high.
+ * If we have not waited for the prog done for write transfer then
+ * perform the DPSM reset without polling for TXACTIVE.
+ * Otherwise, we poll here unnecessarily as TXACTIVE will not be
+ * deasserted until DAT0 (Busy line) goes high.
*/
- if ((mrq->cmd->opcode == MMC_WRITE_BLOCK) && !is_auto_prog_done(host)) {
- host->pending_dpsm_reset = true;
- goto out;
+ if (mrq->data->flags & MMC_DATA_WRITE) {
+ if (!msmsdcc_is_wait_for_prog_done(host, mrq)) {
+ if (is_wait_for_tx_rx_active(host) &&
+ !is_auto_prog_done(host))
+ pr_warning("%s: %s: AUTO_PROG_DONE capability is must\n",
+ mmc_hostname(host->mmc), __func__);
+ goto no_polling;
+ }
}
/* Make sure h/w (TX/RX) is inactive before resetting DPSM */
@@ -473,15 +482,14 @@
& MCI_TXACTIVE ? "TX" : "RX");
msmsdcc_dump_sdcc_state(host);
msmsdcc_reset_and_restore(host);
- host->pending_dpsm_reset = false;
goto out;
}
}
}
+no_polling:
writel_relaxed(0, host->base + MMCIDATACTRL);
msmsdcc_sync_reg_wr(host); /* Allow the DPSM to be reset */
- host->pending_dpsm_reset = false;
out:
return;
}
@@ -1240,13 +1248,10 @@
MCI_DLL_CONFIG) & ~MCI_CDR_EN),
host->base + MCI_DLL_CONFIG);
- if (((cmd->flags & MMC_RSP_R1B) == MMC_RSP_R1B) ||
- (cmd->opcode == MMC_SEND_STATUS &&
- !(cmd->flags & MMC_CMD_ADTC))) {
+ if ((cmd->flags & MMC_RSP_R1B) == MMC_RSP_R1B) {
*c |= MCI_CPSM_PROGENA;
host->prog_enable = 1;
}
-
if (cmd == cmd->mrq->stop)
*c |= MCI_CSPM_MCIABORT;
@@ -2139,6 +2144,43 @@
}
}
+/*
+ * This function returns true if AUTO_PROG_DONE feature of host is
+ * applicable for current request, returns "false" otherwise.
+ *
+ * NOTE: Caller should call this function only for data write operations.
+ */
+static bool msmsdcc_is_wait_for_auto_prog_done(struct msmsdcc_host *host,
+ struct mmc_request *mrq)
+{
+ /*
+ * Auto-prog done will be enabled for following cases:
+ * mrq->sbc | mrq->stop
+ * _____________|________________
+ * True | Don't care
+ * False | False (CMD24, ACMD25 use case)
+ */
+ if (is_auto_prog_done(host) && (mrq->sbc || !mrq->stop))
+ return true;
+
+ return false;
+}
+
+/*
+ * This function returns true if controller can wait for prog done
+ * for current request, returns "false" otherwise.
+ *
+ * NOTE: Caller should call this function only for data write operations.
+ */
+static bool msmsdcc_is_wait_for_prog_done(struct msmsdcc_host *host,
+ struct mmc_request *mrq)
+{
+ if (msmsdcc_is_wait_for_auto_prog_done(host, mrq) || mrq->stop)
+ return true;
+
+ return false;
+}
+
static void
msmsdcc_request(struct mmc_host *mmc, struct mmc_request *mrq)
{
@@ -2235,16 +2277,8 @@
}
if (mrq->data && (mrq->data->flags & MMC_DATA_WRITE)) {
- if (is_auto_prog_done(host)) {
- /*
- * Auto-prog done will be enabled for following cases:
- * mrq->sbc | mrq->stop
- * _____________|________________
- * True | Don't care
- * False | False (CMD24, ACMD25 use case)
- */
- if (mrq->sbc || !mrq->stop)
- host->curr.wait_for_auto_prog_done = true;
+ if (msmsdcc_is_wait_for_auto_prog_done(host, mrq)) {
+ host->curr.wait_for_auto_prog_done = true;
} else {
if ((mrq->cmd->opcode == SD_IO_RW_EXTENDED) ||
(mrq->cmd->opcode == 54))
@@ -5200,9 +5234,11 @@
mrq = host->curr.mrq;
if (mrq && mrq->cmd) {
- pr_info("%s: CMD%d: Request timeout\n", mmc_hostname(host->mmc),
- mrq->cmd->opcode);
- msmsdcc_dump_sdcc_state(host);
+ if (!mrq->cmd->bkops_busy) {
+ pr_info("%s: CMD%d: Request timeout\n",
+ mmc_hostname(host->mmc), mrq->cmd->opcode);
+ msmsdcc_dump_sdcc_state(host);
+ }
if (!mrq->cmd->error)
mrq->cmd->error = -ETIMEDOUT;
@@ -6170,6 +6206,11 @@
mmc_add_host(mmc);
+ mmc->clk_scaling.up_threshold = 35;
+ mmc->clk_scaling.down_threshold = 5;
+ mmc->clk_scaling.polling_delay_ms = 100;
+ mmc->caps2 |= MMC_CAP2_CLK_SCALE;
+
#ifdef CONFIG_HAS_EARLYSUSPEND
host->early_suspend.suspend = msmsdcc_early_suspend;
host->early_suspend.resume = msmsdcc_late_resume;
diff --git a/drivers/mmc/host/msm_sdcc.h b/drivers/mmc/host/msm_sdcc.h
index 7469c8e..8ae5b86 100644
--- a/drivers/mmc/host/msm_sdcc.h
+++ b/drivers/mmc/host/msm_sdcc.h
@@ -422,7 +422,6 @@
struct mutex clk_mutex;
bool pending_resume;
unsigned int idle_tout; /* Timeout in msecs */
- bool pending_dpsm_reset;
bool enforce_pio_mode;
bool print_pm_stats;
struct msmsdcc_msm_bus_vote msm_bus_vote;
diff --git a/drivers/platform/msm/ipa/ipa.c b/drivers/platform/msm/ipa/ipa.c
index 288de52..d673e5a 100644
--- a/drivers/platform/msm/ipa/ipa.c
+++ b/drivers/platform/msm/ipa/ipa.c
@@ -929,23 +929,30 @@
static void ipa_set_aggregation_params(void)
{
struct ipa_ep_cfg_aggr agg_params;
+ struct ipa_ep_cfg_hdr hdr_params;
u32 producer_hdl = 0;
u32 consumer_hdl = 0;
rmnet_bridge_get_client_handles(&producer_hdl, &consumer_hdl);
+ /* configure aggregation on producer */
+ memset(&agg_params, 0, sizeof(struct ipa_ep_cfg_aggr));
+ agg_params.aggr_en = IPA_ENABLE_AGGR;
agg_params.aggr = ipa_ctx->aggregation_type;
agg_params.aggr_byte_limit = ipa_ctx->aggregation_byte_limit;
agg_params.aggr_time_limit = ipa_ctx->aggregation_time_limit;
-
- /* configure aggregation on producer */
- agg_params.aggr_en = IPA_ENABLE_AGGR;
ipa_cfg_ep_aggr(producer_hdl, &agg_params);
- /* configure deaggregation on consumer */
- agg_params.aggr_en = IPA_ENABLE_DEAGGR;
- ipa_cfg_ep_aggr(consumer_hdl, &agg_params);
+ /* configure header on producer */
+ memset(&hdr_params, 0, sizeof(struct ipa_ep_cfg_hdr));
+ hdr_params.hdr_len = 1;
+ ipa_cfg_ep_hdr(producer_hdl, &hdr_params);
+ /* configure deaggregation on consumer */
+ memset(&agg_params, 0, sizeof(struct ipa_ep_cfg_aggr));
+ agg_params.aggr_en = IPA_ENABLE_DEAGGR;
+ agg_params.aggr = ipa_ctx->aggregation_type;
+ ipa_cfg_ep_aggr(consumer_hdl, &agg_params);
}
/*
@@ -1340,6 +1347,22 @@
result = -ENODEV;
goto fail_init_hw;
}
+
+ /* setup chicken bits */
+ result = ipa_set_single_ndp_per_mbim(true);
+ if (result) {
+ IPAERR(":failed to set single ndp per mbim.\n");
+ result = -EFAULT;
+ goto fail_init_hw;
+ }
+
+ result = ipa_set_hw_timer_fix_for_mbim_aggr(true);
+ if (result) {
+ IPAERR(":failed to set HW timer fix for MBIM aggregation.\n");
+ result = -EFAULT;
+ goto fail_init_hw;
+ }
+
/* read how much SRAM is available for SW use */
ipa_ctx->smem_sz = ipa_read_reg(ipa_ctx->mmio,
IPA_SHARED_MEM_SIZE_OFST);
diff --git a/drivers/platform/msm/ipa/ipa_i.h b/drivers/platform/msm/ipa/ipa_i.h
index 3be2369..4172371 100644
--- a/drivers/platform/msm/ipa/ipa_i.h
+++ b/drivers/platform/msm/ipa/ipa_i.h
@@ -654,6 +654,8 @@
int ipa_generate_hdr_hw_tbl(struct ipa_mem_buffer *mem);
int ipa_generate_rt_hw_tbl(enum ipa_ip_type ip, struct ipa_mem_buffer *mem);
int ipa_generate_flt_hw_tbl(enum ipa_ip_type ip, struct ipa_mem_buffer *mem);
+int ipa_set_single_ndp_per_mbim(bool);
+int ipa_set_hw_timer_fix_for_mbim_aggr(bool);
void ipa_debugfs_init(void);
void ipa_debugfs_remove(void);
diff --git a/drivers/platform/msm/ipa/ipa_reg.h b/drivers/platform/msm/ipa/ipa_reg.h
index 61913b6..ca67e35 100644
--- a/drivers/platform/msm/ipa/ipa_reg.h
+++ b/drivers/platform/msm/ipa/ipa_reg.h
@@ -213,6 +213,8 @@
#define IPA_AGGREGATION_QCNCM_SIG_BMSK 0xff000000
#define IPA_AGGREGATION_SINGLE_NDP_MSK 0x1
#define IPA_AGGREGATION_SINGLE_NDP_BMSK 0xfffffffe
+#define IPA_AGGREGATION_HW_TIMER_FIX_MBIM_AGGR_SHFT 2
+#define IPA_AGGREGATION_HW_TIMER_FIX_MBIM_AGGR_BMSK 0x4
#define IPA_SRAM_DIRECT_ACCESS_n_OFST(n) (0x00004000 + 0x4 * (n))
#define IPA_SRAM_DIRECT_ACCESS_n_RMSK 0xffffffff
diff --git a/drivers/platform/msm/ipa/ipa_utils.c b/drivers/platform/msm/ipa/ipa_utils.c
index d5d5566..7cdde4a 100644
--- a/drivers/platform/msm/ipa/ipa_utils.c
+++ b/drivers/platform/msm/ipa/ipa_utils.c
@@ -1323,6 +1323,24 @@
EXPORT_SYMBOL(ipa_set_single_ndp_per_mbim);
/**
+ * ipa_set_hw_timer_fix_for_mbim_aggr() - Enable/disable HW timer fix
+ * for MBIM aggregation.
+ * @enable: [in] true for enable HW fix; false otherwise
+ *
+ * Returns: 0 on success
+ */
+int ipa_set_hw_timer_fix_for_mbim_aggr(bool enable)
+{
+ u32 reg_val;
+ reg_val = ipa_read_reg(ipa_ctx->mmio, IPA_AGGREGATION_SPARE_REG_1_OFST);
+ ipa_write_reg(ipa_ctx->mmio, IPA_AGGREGATION_SPARE_REG_1_OFST,
+ (enable << IPA_AGGREGATION_HW_TIMER_FIX_MBIM_AGGR_SHFT) |
+ (reg_val & ~IPA_AGGREGATION_HW_TIMER_FIX_MBIM_AGGR_BMSK));
+ return 0;
+}
+EXPORT_SYMBOL(ipa_set_hw_timer_fix_for_mbim_aggr);
+
+/**
* ipa_straddle_boundary() - Checks whether a memory buffer straddles a boundary
* @start: start address of the memory buffer
* @end: end address of the memory buffer
diff --git a/drivers/platform/msm/sps/bam.c b/drivers/platform/msm/sps/bam.c
index bcb4cdb..97c3f3d 100644
--- a/drivers/platform/msm/sps/bam.c
+++ b/drivers/platform/msm/sps/bam.c
@@ -644,7 +644,7 @@
int bam_init(void *base, u32 ee,
u16 summing_threshold,
u32 irq_mask, u32 *version,
- u32 *num_pipes, u32 p_rst)
+ u32 *num_pipes, u32 options)
{
u32 cfg_bits;
u32 ver = 0;
@@ -667,7 +667,7 @@
"use default 4.\n", (u32) base);
}
- if (p_rst)
+ if (options & SPS_BAM_NO_EXT_P_RST)
cfg_bits = 0xffffffff & ~(3 << 11);
else
cfg_bits = 0xffffffff & ~(1 << 11);
@@ -681,7 +681,10 @@
#ifdef CONFIG_SPS_SUPPORT_NDP_BAM
bam_write_reg_field(base, CTRL, CACHE_MISS_ERR_RESP_EN, 0);
- bam_write_reg_field(base, CTRL, LOCAL_CLK_GATING, 1);
+ if (options & SPS_BAM_NO_LOCAL_CLK_GATING)
+ bam_write_reg_field(base, CTRL, LOCAL_CLK_GATING, 0);
+ else
+ bam_write_reg_field(base, CTRL, LOCAL_CLK_GATING, 1);
#endif
bam_write_reg(base, DESC_CNT_TRSHLD, summing_threshold);
diff --git a/drivers/platform/msm/sps/bam.h b/drivers/platform/msm/sps/bam.h
index c183fcd..86808d9 100644
--- a/drivers/platform/msm/sps/bam.h
+++ b/drivers/platform/msm/sps/bam.h
@@ -102,7 +102,7 @@
*
* @num_pipes - return number of pipes
*
- * @p_rst - ignore external block pipe reset
+ * @options - BAM configuration options
*
* @return 0 on success, negative value on error
*
@@ -111,7 +111,7 @@
u32 ee,
u16 summing_threshold,
u32 irq_mask, u32 *version,
- u32 *num_pipes, u32 p_rst);
+ u32 *num_pipes, u32 options);
/**
* Initialize BAM device security execution environment
diff --git a/drivers/platform/msm/sps/sps_bam.c b/drivers/platform/msm/sps/sps_bam.c
index af421ac..a1ff7cb 100644
--- a/drivers/platform/msm/sps/sps_bam.c
+++ b/drivers/platform/msm/sps/sps_bam.c
@@ -255,7 +255,7 @@
(u16) dev->props.summing_threshold,
irq_mask,
&dev->version, &num_pipes,
- dev->props.options & SPS_BAM_NO_EXT_P_RST);
+ dev->props.options);
else
/* No, so just verify that it is enabled */
rc = bam_check(dev->base, &dev->version, &num_pipes);
diff --git a/drivers/power/pm8921-bms.c b/drivers/power/pm8921-bms.c
index 070fb62..f6591c3d 100644
--- a/drivers/power/pm8921-bms.c
+++ b/drivers/power/pm8921-bms.c
@@ -134,6 +134,7 @@
int rconn_mohm;
struct mutex last_ocv_uv_mutex;
int last_ocv_uv;
+ int last_ocv_temp_decidegc;
int pon_ocv_uv;
int last_cc_uah;
unsigned long tm_sec;
@@ -730,7 +731,8 @@
#define CC_RAW_5MAH 0x00110000
#define MIN_OCV_UV 2000000
static int read_soc_params_raw(struct pm8921_bms_chip *chip,
- struct pm8921_soc_params *raw)
+ struct pm8921_soc_params *raw,
+ int batt_temp_decidegc)
{
int usb_chg;
int est_ocv_uv;
@@ -783,12 +785,14 @@
raw->cc = 0;
}
}
+ chip->last_ocv_temp_decidegc = batt_temp_decidegc;
pr_debug("PON_OCV_UV = %d\n", chip->last_ocv_uv);
} else if (chip->prev_last_good_ocv_raw != raw->last_good_ocv_raw) {
chip->prev_last_good_ocv_raw = raw->last_good_ocv_raw;
convert_vbatt_raw_to_uv(chip, usb_chg,
raw->last_good_ocv_raw, &raw->last_good_ocv_uv);
chip->last_ocv_uv = raw->last_good_ocv_uv;
+ chip->last_ocv_temp_decidegc = batt_temp_decidegc;
/* forget the old cc value upon ocv */
chip->last_cc_uah = 0;
} else {
@@ -806,6 +810,7 @@
*/
raw->last_good_ocv_uv = chip->max_voltage_uv;
chip->last_ocv_uv = chip->max_voltage_uv;
+ chip->last_ocv_temp_decidegc = batt_temp_decidegc;
}
pr_debug("0p625 = %duV\n", chip->xoadc_v0625);
pr_debug("1p25 = %duV\n", chip->xoadc_v125);
@@ -908,18 +913,19 @@
}
static int calculate_pc(struct pm8921_bms_chip *chip, int ocv_uv,
- int batt_temp, int chargecycles)
+ int batt_temp_decidegc, int chargecycles)
{
int pc, scalefactor;
pc = interpolate_pc(chip->pc_temp_ocv_lut,
- batt_temp / 10, ocv_uv / 1000);
+ batt_temp_decidegc / 10, ocv_uv / 1000);
pr_debug("pc = %u for ocv = %dmicroVolts batt_temp = %d\n",
- pc, ocv_uv, batt_temp);
+ pc, ocv_uv, batt_temp_decidegc);
scalefactor = interpolate_scalingfactor(chip->pc_sf_lut,
chargecycles, pc);
- pr_debug("scalefactor = %u batt_temp = %d\n", scalefactor, batt_temp);
+ pr_debug("scalefactor = %u batt_temp = %d\n",
+ scalefactor, batt_temp_decidegc);
/* Multiply the initial FCC value by the scale factor. */
pc = (pc * scalefactor) / 100;
@@ -1216,10 +1222,11 @@
int fcc_uah, int batt_temp,
int chargecycles)
{
- int ocv, pc;
+ int ocv, pc, batt_temp_decidegc;
ocv = raw->last_good_ocv_uv;
- pc = calculate_pc(chip, ocv, batt_temp, chargecycles);
+ batt_temp_decidegc = chip->last_ocv_temp_decidegc;
+ pc = calculate_pc(chip, ocv, batt_temp_decidegc, chargecycles);
pr_debug("ocv = %d pc = %d\n", ocv, pc);
return (fcc_uah * pc) / 100;
}
@@ -1562,16 +1569,18 @@
last_soc_est = soc_est;
pc = calculate_pc(chip, chip->last_ocv_uv,
- batt_temp, last_chargecycles);
+ chip->last_ocv_temp_decidegc, last_chargecycles);
if (pc > 0) {
pc_new = calculate_pc(chip, chip->last_ocv_uv - (++m * 1000),
- batt_temp, last_chargecycles);
+ chip->last_ocv_temp_decidegc,
+ last_chargecycles);
while (pc_new == pc) {
/* start taking 10mV steps */
m = m + 10;
pc_new = calculate_pc(chip,
chip->last_ocv_uv - (m * 1000),
- batt_temp, last_chargecycles);
+ chip->last_ocv_temp_decidegc,
+ last_chargecycles);
}
} else {
/*
@@ -1604,7 +1613,7 @@
/* calculate the soc based on this new ocv */
pc_new = calculate_pc(chip, chip->last_ocv_uv,
- batt_temp, last_chargecycles);
+ chip->last_ocv_temp_decidegc, last_chargecycles);
rc_new_uah = (fcc_uah * pc_new) / 100;
soc_new = (rc_new_uah - cc_uah - uuc_uah)*100 / (fcc_uah - uuc_uah);
soc_new = bound_soc(soc_new);
@@ -2041,7 +2050,7 @@
get_batt_temp(chip, &batt_temp);
mutex_lock(&chip->last_ocv_uv_mutex);
- read_soc_params_raw(chip, &raw);
+ read_soc_params_raw(chip, &raw, batt_temp);
soc = calculate_state_of_charge(chip, &raw,
batt_temp, last_chargecycles);
@@ -2253,7 +2262,7 @@
mutex_lock(&the_chip->last_ocv_uv_mutex);
- read_soc_params_raw(the_chip, &raw);
+ read_soc_params_raw(the_chip, &raw, batt_temp);
calculate_soc_params(the_chip, &raw, batt_temp, last_chargecycles,
&fcc_uah,
@@ -2292,9 +2301,12 @@
void pm8921_bms_charging_began(void)
{
struct pm8921_soc_params raw;
+ int batt_temp;
+
+ get_batt_temp(the_chip, &batt_temp);
mutex_lock(&the_chip->last_ocv_uv_mutex);
- read_soc_params_raw(the_chip, &raw);
+ read_soc_params_raw(the_chip, &raw, batt_temp);
mutex_unlock(&the_chip->last_ocv_uv_mutex);
the_chip->start_percent = report_state_of_charge(the_chip);
@@ -2327,7 +2339,7 @@
mutex_lock(&the_chip->last_ocv_uv_mutex);
- read_soc_params_raw(the_chip, &raw);
+ read_soc_params_raw(the_chip, &raw, batt_temp);
calculate_cc_uah(the_chip, raw.cc, &bms_end_cc_uah);
@@ -2720,7 +2732,7 @@
int ibat_ua, vbat_uv;
struct pm8921_soc_params raw;
- read_soc_params_raw(the_chip, &raw);
+ read_soc_params_raw(the_chip, &raw, 300);
*val = 0;
@@ -2786,7 +2798,7 @@
struct pm8921_soc_params raw;
mutex_lock(&the_chip->bms_output_lock);
- read_soc_params_raw(the_chip, &raw);
+ read_soc_params_raw(the_chip, &raw, 300);
mutex_unlock(&the_chip->bms_output_lock);
*val = 0;
diff --git a/drivers/power/pm8921-charger.c b/drivers/power/pm8921-charger.c
index 1ca0728..c86ba9e 100644
--- a/drivers/power/pm8921-charger.c
+++ b/drivers/power/pm8921-charger.c
@@ -293,6 +293,7 @@
int btc_override_hot_decidegc;
int btc_delay_ms;
bool btc_panic_if_cant_stop_chg;
+ int stop_chg_upon_expiry;
};
/* user space parameter to limit usb current */
@@ -2733,9 +2734,11 @@
struct pm8921_chg_chip *chip = data;
int ret;
- ret = pm_chg_failed_clear(chip, 1);
- if (ret)
- pr_err("Failed to write CHG_FAILED_CLEAR bit\n");
+ if (!chip->stop_chg_upon_expiry) {
+ ret = pm_chg_failed_clear(chip, 1);
+ if (ret)
+ pr_err("Failed to write CHG_FAILED_CLEAR bit\n");
+ }
pr_err("batt_present = %d, batt_temp_ok = %d, state_changed_to=%d\n",
get_prop_batt_present(chip),
@@ -3237,7 +3240,6 @@
struct pm8921_chg_chip *chip = container_of(dwork,
struct pm8921_chg_chip, update_heartbeat_work);
- pm_chg_failed_clear(chip, 1);
power_supply_changed(&chip->batt_psy);
if (chip->recent_reported_soc <= 20)
schedule_delayed_work(&chip->update_heartbeat_work,
@@ -3670,8 +3672,6 @@
int ichg_meas_ua, ichg_meas_ma;
int vbat_batt_terminal_uv;
- pm_chg_failed_clear(chip, 1);
-
pm8921_bms_get_simultaneous_battery_voltage_and_current(
&ichg_meas_ua, &vbat_meas_uv);
vbat_meas_mv = vbat_meas_uv / 1000;
@@ -4736,6 +4736,8 @@
if (chip->btc_override)
pm8921_chg_btc_override_init(chip);
+ chip->stop_chg_upon_expiry = pdata->stop_chg_upon_expiry;
+
chip->usb_psy.name = "usb",
chip->usb_psy.type = POWER_SUPPLY_TYPE_USB,
chip->usb_psy.supplied_to = pm_power_supplied_to,
diff --git a/drivers/thermal/qpnp-adc-tm.c b/drivers/thermal/qpnp-adc-tm.c
index 20481ac..4818941 100644
--- a/drivers/thermal/qpnp-adc-tm.c
+++ b/drivers/thermal/qpnp-adc-tm.c
@@ -1488,7 +1488,7 @@
return 0;
fail:
- adc_qpnp = NULL;
+ qpnp_adc_tm = NULL;
return rc;
}
diff --git a/drivers/video/msm/mdp.h b/drivers/video/msm/mdp.h
index 7396013..20b20bc 100644
--- a/drivers/video/msm/mdp.h
+++ b/drivers/video/msm/mdp.h
@@ -73,6 +73,7 @@
#define MDPOP_SHARPENING BIT(11) /* enable sharpening */
#define MDPOP_BLUR BIT(12) /* enable blur */
#define MDPOP_FG_PM_ALPHA BIT(13)
+#define MDPOP_LAYER_IS_FG BIT(14)
#define MDP_ALLOC(x) kmalloc(x, GFP_KERNEL)
struct mdp_buf_type {
diff --git a/drivers/video/msm/mdp_ppp.c b/drivers/video/msm/mdp_ppp.c
index 8631d6d..c8367c3 100644
--- a/drivers/video/msm/mdp_ppp.c
+++ b/drivers/video/msm/mdp_ppp.c
@@ -1401,6 +1401,9 @@
iBuf.mdpImg.mdpOp = MDPOP_NOP;
+ if (req->flags & MDP_IS_FG)
+ iBuf.mdpImg.mdpOp |= MDPOP_LAYER_IS_FG;
+
/* blending check */
if (req->transp_mask != MDP_TRANSP_NOP) {
iBuf.mdpImg.mdpOp |= MDPOP_TRANSP;
diff --git a/drivers/video/msm/mdp_ppp_v20.c b/drivers/video/msm/mdp_ppp_v20.c
index 418528e..5da6b4f5 100644
--- a/drivers/video/msm/mdp_ppp_v20.c
+++ b/drivers/video/msm/mdp_ppp_v20.c
@@ -2467,7 +2467,8 @@
bg_alpha = PPP_BLEND_BG_USE_ALPHA_SEL |
PPP_BLEND_BG_ALPHA_REVERSE;
- if (perPixelAlpha) {
+ if ((perPixelAlpha) && !(iBuf->mdpImg.mdpOp &
+ MDPOP_LAYER_IS_FG)) {
bg_alpha |= PPP_BLEND_BG_SRCPIXEL_ALPHA;
} else {
bg_alpha |= PPP_BLEND_BG_CONSTANT_ALPHA;
@@ -2478,7 +2479,12 @@
if (iBuf->mdpImg.mdpOp & MDPOP_TRANSP)
*pppop_reg_ptr |= PPP_BLEND_CALPHA_TRNASP;
} else if (perPixelAlpha) {
- *pppop_reg_ptr |= PPP_OP_ROT_ON |
+ if (iBuf->mdpImg.mdpOp & MDPOP_LAYER_IS_FG)
+ *pppop_reg_ptr |= PPP_OP_ROT_ON |
+ PPP_OP_BLEND_ON |
+ PPP_OP_BLEND_CONSTANT_ALPHA;
+ else
+ *pppop_reg_ptr |= PPP_OP_ROT_ON |
PPP_OP_BLEND_ON |
PPP_OP_BLEND_SRCPIXEL_ALPHA;
outpdw(MDP_BASE + 0x70010, 0);
diff --git a/drivers/video/msm/mdss/mdss_mdp_pp.c b/drivers/video/msm/mdss/mdss_mdp_pp.c
index c90ae82..1482935 100644
--- a/drivers/video/msm/mdss/mdss_mdp_pp.c
+++ b/drivers/video/msm/mdss/mdss_mdp_pp.c
@@ -420,19 +420,19 @@
pp_sts = &mdss_pp_res->pp_dspp_sts[dspp_num];
if (flags & PP_FLAGS_DIRTY_PA) {
pa_config = &mdss_pp_res->pa_disp_cfg[disp_num];
- if (pa_config->flags & MDP_PP_OPS_WRITE) {
+ if (pa_config->pa_data.flags & MDP_PP_OPS_WRITE) {
offset = base + MDSS_MDP_REG_DSPP_PA_BASE;
- MDSS_MDP_REG_WRITE(offset, pa_config->hue_adj);
+ MDSS_MDP_REG_WRITE(offset, pa_config->pa_data.hue_adj);
offset += 4;
- MDSS_MDP_REG_WRITE(offset, pa_config->sat_adj);
+ MDSS_MDP_REG_WRITE(offset, pa_config->pa_data.sat_adj);
offset += 4;
- MDSS_MDP_REG_WRITE(offset, pa_config->val_adj);
+ MDSS_MDP_REG_WRITE(offset, pa_config->pa_data.val_adj);
offset += 4;
- MDSS_MDP_REG_WRITE(offset, pa_config->cont_adj);
+ MDSS_MDP_REG_WRITE(offset, pa_config->pa_data.cont_adj);
}
- if (pa_config->flags & MDP_PP_OPS_DISABLE)
+ if (pa_config->pa_data.flags & MDP_PP_OPS_DISABLE)
pp_sts->pa_sts &= ~PP_STS_ENABLE;
- else if (pa_config->flags & MDP_PP_OPS_ENABLE)
+ else if (pa_config->pa_data.flags & MDP_PP_OPS_ENABLE)
pp_sts->pa_sts |= PP_STS_ENABLE;
}
if (pp_sts->pa_sts & PP_STS_ENABLE)
@@ -636,7 +636,7 @@
mutex_lock(&mdss_pp_mutex);
disp_num = config->block - MDP_LOGICAL_BLOCK_DISP_0;
- if (config->flags & MDP_PP_OPS_READ) {
+ if (config->pa_data.flags & MDP_PP_OPS_READ) {
ret = pp_get_dspp_num(disp_num, &dspp_num);
if (ret) {
pr_err("%s, no dspp connects to disp %d",
@@ -646,13 +646,13 @@
mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_ON, false);
pa_offset = MDSS_MDP_REG_DSPP_OFFSET(dspp_num) +
MDSS_MDP_REG_DSPP_PA_BASE;
- config->hue_adj = MDSS_MDP_REG_READ(pa_offset);
+ config->pa_data.hue_adj = MDSS_MDP_REG_READ(pa_offset);
pa_offset += 4;
- config->sat_adj = MDSS_MDP_REG_READ(pa_offset);
+ config->pa_data.sat_adj = MDSS_MDP_REG_READ(pa_offset);
pa_offset += 4;
- config->val_adj = MDSS_MDP_REG_READ(pa_offset);
+ config->pa_data.val_adj = MDSS_MDP_REG_READ(pa_offset);
pa_offset += 4;
- config->cont_adj = MDSS_MDP_REG_READ(pa_offset);
+ config->pa_data.cont_adj = MDSS_MDP_REG_READ(pa_offset);
*copyback = 1;
mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_OFF, false);
} else {
diff --git a/drivers/video/msm/msm_fb.c b/drivers/video/msm/msm_fb.c
index 9fe5d8f..e4e93eb 100644
--- a/drivers/video/msm/msm_fb.c
+++ b/drivers/video/msm/msm_fb.c
@@ -726,36 +726,11 @@
},
};
-#if defined(CONFIG_HAS_EARLYSUSPEND) && defined(CONFIG_FB_MSM_MDP303)
-static void memset32_io(u32 __iomem *_ptr, u32 val, size_t count)
-{
- count >>= 2;
- while (count--)
- writel(val, _ptr++);
-}
-#endif
-
#ifdef CONFIG_HAS_EARLYSUSPEND
static void msmfb_early_suspend(struct early_suspend *h)
{
struct msm_fb_data_type *mfd = container_of(h, struct msm_fb_data_type,
early_suspend);
-#if defined(CONFIG_FB_MSM_MDP303)
- /*
- * For MDP with overlay, set framebuffer with black pixels
- * to show black screen on HDMI.
- */
- struct fb_info *fbi = mfd->fbi;
- switch (mfd->fbi->var.bits_per_pixel) {
- case 32:
- memset32_io((void *)fbi->screen_base, 0xFF000000,
- fbi->fix.smem_len);
- break;
- default:
- memset32_io((void *)fbi->screen_base, 0x00, fbi->fix.smem_len);
- break;
- }
-#endif
msm_fb_suspend_sub(mfd);
}
@@ -3144,6 +3119,7 @@
#endif
DEFINE_SEMAPHORE(msm_fb_ioctl_ppp_sem);
+DEFINE_SEMAPHORE(msm_fb_ioctl_vsync_sem);
DEFINE_MUTEX(msm_fb_ioctl_lut_sem);
/* Set color conversion matrix from user space */
@@ -3384,12 +3360,12 @@
#endif
case MSMFB_VSYNC_CTRL:
case MSMFB_OVERLAY_VSYNC_CTRL:
- down(&msm_fb_ioctl_ppp_sem);
+ down(&msm_fb_ioctl_vsync_sem);
if (mdp_rev >= MDP_REV_40)
ret = msmfb_overlay_vsync_ctrl(info, argp);
else
ret = msmfb_vsync_ctrl(info, argp);
- up(&msm_fb_ioctl_ppp_sem);
+ up(&msm_fb_ioctl_vsync_sem);
break;
case MSMFB_BLIT:
down(&msm_fb_ioctl_ppp_sem);
diff --git a/drivers/video/msm/vidc/1080p/ddl/vcd_ddl.c b/drivers/video/msm/vidc/1080p/ddl/vcd_ddl.c
index f8c26ff..91cf3ae 100644
--- a/drivers/video/msm/vidc/1080p/ddl/vcd_ddl.c
+++ b/drivers/video/msm/vidc/1080p/ddl/vcd_ddl.c
@@ -88,7 +88,7 @@
ddl_context->dram_base_a.align_virtual_addr;
}
if (!status) {
- ddl_context->metadata_shared_input.mem_type = DDL_FW_MEM;
+ ddl_context->metadata_shared_input.mem_type = DDL_CMD_MEM;
ptr = ddl_pmem_alloc(&ddl_context->metadata_shared_input,
DDL_METADATA_TOTAL_INPUTBUFSIZE,
DDL_LINEAR_BUFFER_ALIGN_BYTES);
diff --git a/drivers/video/msm/vidc/1080p/ddl/vcd_ddl.h b/drivers/video/msm/vidc/1080p/ddl/vcd_ddl.h
index 0404e82..248ad57 100644
--- a/drivers/video/msm/vidc/1080p/ddl/vcd_ddl.h
+++ b/drivers/video/msm/vidc/1080p/ddl/vcd_ddl.h
@@ -205,6 +205,7 @@
struct ddl_buf_addr h264_nb_ip;
struct ddl_buf_addr context;
struct ddl_buf_addr extnuserdata;
+ struct ddl_buf_addr meta_hdr[DDL_MAX_BUFFER_COUNT];
};
struct ddl_enc_buffer_size{
u32 sz_cur_y;
diff --git a/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_helper.c b/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_helper.c
index 15b37a1b..729fb2e 100644
--- a/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_helper.c
+++ b/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_helper.c
@@ -781,7 +781,7 @@
}
}
if (buf_size.sz_extnuserdata > 0) {
- dec_bufs->extnuserdata.mem_type = DDL_FW_MEM;
+ dec_bufs->extnuserdata.mem_type = DDL_CMD_MEM;
ptr = ddl_pmem_alloc(&dec_bufs->extnuserdata,
buf_size.sz_extnuserdata, DDL_KILO_BYTE(2));
if (!ptr)
diff --git a/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_metadata.c b/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_metadata.c
index 1aee3d9..803af02 100644
--- a/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_metadata.c
+++ b/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_metadata.c
@@ -165,7 +165,8 @@
if (ddl->decoding) {
flag |= (VCD_METADATA_CONCEALMB | VCD_METADATA_PASSTHROUGH |
- VCD_METADATA_QPARRAY);
+ VCD_METADATA_QPARRAY |
+ VCD_METADATA_SEPARATE_BUF);
if (codec == VCD_CODEC_H264)
flag |= (VCD_METADATA_SEI | VCD_METADATA_VUI);
else if (codec == VCD_CODEC_VC1 ||
@@ -260,6 +261,9 @@
DDL_METADATA_ALIGNSIZE(suffix);
decoder->suffix = suffix;
output_buf_req->sz += suffix;
+ output_buf_req->meta_buffer_size = suffix;
+ output_buf_req->meta_buffer_size =
+ (output_buf_req->meta_buffer_size + 8191) & (~8191);
decoder->meta_data_offset = 0;
DDL_MSG_LOW("metadata output buf size : %d", suffix);
}
@@ -481,13 +485,14 @@
void ddl_vidc_decode_set_metadata_output(struct ddl_decoder_data *decoder)
{
struct ddl_context *ddl_context;
- u32 loopc, yuv_size;
+ u32 loopc, yuv_size, dpb;
u32 *buffer;
-
+ struct ddl_dec_buffers *dec_buffers = &decoder->hw_bufs;
if (!decoder->meta_data_enable_flag) {
decoder->meta_data_offset = 0;
return;
}
+ dpb = decoder->dp_buf.no_of_dec_pic_buf;
ddl_context = ddl_get_context();
yuv_size = ddl_get_yuv_buffer_size(&decoder->client_frame_size,
&decoder->buf_format, !decoder->progressive_only,
@@ -495,15 +500,22 @@
decoder->meta_data_offset = DDL_ALIGN_SIZE(yuv_size,
DDL_LINEAR_BUF_ALIGN_GUARD_BYTES, DDL_LINEAR_BUF_ALIGN_MASK);
buffer = (u32 *) decoder->meta_data_input.align_virtual_addr;
- *buffer++ = decoder->suffix;
DDL_MSG_LOW("Metadata offset & size : %d/%d",
decoder->meta_data_offset, decoder->suffix);
- for (loopc = 0; loopc < decoder->dp_buf.no_of_dec_pic_buf;
- ++loopc) {
- *buffer++ = (u32)(decoder->meta_data_offset + (u8 *)
+ if (!(decoder->meta_data_enable_flag & VCD_METADATA_SEPARATE_BUF)) {
+ *buffer++ = decoder->suffix;
+ for (loopc = 0; loopc < dpb; ++loopc) {
+ *buffer++ = (u32)(decoder->meta_data_offset + (u8 *)
DDL_OFFSET(ddl_context->dram_base_a.
align_physical_addr, decoder->dp_buf.
dec_pic_buffers[loopc].vcd_frm.physical));
+ }
+ } else {
+ *buffer++ = decoder->actual_output_buf_req.meta_buffer_size;
+ for (loopc = 0; loopc < dpb; ++loopc) {
+ *buffer++ = DDL_ADDR_OFFSET(ddl_context->dram_base_a,
+ dec_buffers->meta_hdr[loopc]);
+ }
}
}
@@ -627,7 +639,8 @@
DDL_MSG_LOW("data_len/metadata_offset : %d/%d",
output_frame->data_len, decoder->meta_data_offset);
output_frame->flags |= VCD_FRAME_FLAG_EXTRADATA;
- if (output_frame->data_len != decoder->meta_data_offset) {
+ if (!(decoder->meta_data_enable_flag & VCD_METADATA_SEPARATE_BUF)
+ && (output_frame->data_len != decoder->meta_data_offset)) {
qfiller = (u32 *)((u32)((output_frame->data_len +
output_frame->offset +
(u8 *) output_frame->virtual) + 3) & ~3);
diff --git a/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_properties.c b/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_properties.c
index 94ec12e..95f4bf0 100644
--- a/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_properties.c
+++ b/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_properties.c
@@ -341,6 +341,61 @@
}
}
break;
+ case VCD_I_SET_EXT_METABUFFER:
+ {
+ int index, buffer_size;
+ u8 *phys_addr;
+ u8 *virt_addr;
+ struct vcd_property_meta_buffer *meta_buffer =
+ (struct vcd_property_meta_buffer *) property_value;
+ DDL_MSG_LOW("Entered VCD_I_SET_EXT_METABUFFER Virt: %p,"\
+ "Phys %p, fd: %d size: %d count: %d",
+ meta_buffer->kernel_virtual_addr,
+ meta_buffer->physical_addr,
+ meta_buffer->pmem_fd,
+ meta_buffer->size, meta_buffer->count);
+ if ((property_hdr->sz == sizeof(struct
+ vcd_property_meta_buffer)) &&
+ (DDLCLIENT_STATE_IS(ddl,
+ DDL_CLIENT_WAIT_FOR_INITCODEC) ||
+ DDLCLIENT_STATE_IS(ddl, DDL_CLIENT_WAIT_FOR_DPB) ||
+ DDLCLIENT_STATE_IS(ddl, DDL_CLIENT_OPEN))) {
+ phys_addr = meta_buffer->dev_addr;
+ virt_addr = meta_buffer->kernel_virtual_addr;
+ buffer_size = meta_buffer->size/meta_buffer->count;
+
+ for (index = 0; index < meta_buffer->count; index++) {
+ ddl->codec_data.decoder.hw_bufs.
+ meta_hdr[index].align_physical_addr
+ = phys_addr;
+ ddl->codec_data.decoder.hw_bufs.
+ meta_hdr[index].align_virtual_addr
+ = virt_addr;
+ ddl->codec_data.decoder.hw_bufs.
+ meta_hdr[index].buffer_size
+ = buffer_size;
+ ddl->codec_data.decoder.hw_bufs.
+ meta_hdr[index].physical_base_addr
+ = phys_addr;
+ ddl->codec_data.decoder.hw_bufs.
+ meta_hdr[index].virtual_base_addr
+ = virt_addr;
+
+ DDL_MSG_LOW("Meta Buffer: "\
+ "Assigned %d buffer for "
+ "virt: %p, phys %p for "
+ "meta_buffers "
+ "of size: %d\n",
+ index, virt_addr,
+ phys_addr, buffer_size);
+
+ phys_addr += buffer_size;
+ virt_addr += buffer_size;
+ }
+ vcd_status = VCD_S_SUCCESS;
+ }
+ }
+ break;
case VCD_I_H264_MV_BUFFER:
{
int index, buffer_size;
@@ -401,6 +456,13 @@
vcd_status = VCD_S_SUCCESS;
}
break;
+ case VCD_I_FREE_EXT_METABUFFER:
+ {
+ memset(&decoder->hw_bufs.meta_hdr, 0, sizeof(struct
+ ddl_buf_addr) * DDL_MAX_BUFFER_COUNT);
+ vcd_status = VCD_S_SUCCESS;
+ }
+ break;
case VCD_I_OUTPUT_ORDER:
{
if (sizeof(u32) == property_hdr->sz &&
diff --git a/drivers/video/msm/vidc/common/dec/vdec.c b/drivers/video/msm/vidc/common/dec/vdec.c
index 59e19b7..48f127a 100644
--- a/drivers/video/msm/vidc/common/dec/vdec.c
+++ b/drivers/video/msm/vidc/common/dec/vdec.c
@@ -271,6 +271,38 @@
&phy_addr, &pmem_fd, &file,
&buffer_index) ||
(vcd_frame_data->flags & VCD_FRAME_FLAG_EOS)) {
+
+ if (res_trk_check_for_sec_session() &&
+ event == VCD_EVT_RESP_OUTPUT_DONE) {
+ DBG("Buffer Index = %d", buffer_index);
+ if (buffer_index != -1) {
+ if (client_ctx->meta_addr_table[buffer_index].
+ kernel_vir_addr_iommu &&
+ client_ctx->
+ meta_addr_table[buffer_index].
+ kernel_vir_addr) {
+
+ memcpy(client_ctx->
+ meta_addr_table[buffer_index].
+ kernel_vir_addr_iommu,
+ client_ctx->
+ meta_addr_table[buffer_index].
+ kernel_vir_addr,
+ client_ctx->meta_buf_size);
+ DBG("Copying Meta Buffer from "\
+ "secure memory"
+ "kernel_virt_iommu = %p "
+ "kernel_virt = %p",
+ client_ctx->
+ meta_addr_table[buffer_index].
+ kernel_vir_addr_iommu,
+ client_ctx->
+ meta_addr_table[buffer_index].
+ kernel_vir_addr);
+ }
+ }
+ }
+
/* Buffer address in user space */
vdec_msg->vdec_msg_info.msgdata.output_frame.bufferaddr =
(u8 *) user_vaddr;
@@ -838,7 +870,263 @@
return false;
return true;
}
+static u32 vid_dec_set_meta_buffers(struct video_client_ctx *client_ctx,
+ struct vdec_meta_buffers *meta_buffers)
+{
+ struct vcd_property_hdr vcd_property_hdr;
+ struct vcd_property_meta_buffer *vcd_meta_buffer = NULL;
+ struct msm_mapped_buffer *mapped_buffer = NULL;
+ struct msm_mapped_buffer *mapped_buffer_iommu = NULL;
+ u32 vcd_status = VCD_ERR_FAIL;
+ u32 len = 0, flags = 0, len_iommu = 0, flags_iommu = 0, buf_size = 0;
+ struct file *file, *file_iommu;
+ int rc = 0;
+ unsigned long ionflag = 0, ionflag_iommu = 0;
+ unsigned long buffer_size = 0, buffer_size_iommu = 0;
+ unsigned long iova = 0, iova_iommu = 0;
+ int index = -1, num_buffers = 0;
+ u8 *ker_vir_addr = NULL, *ker_vir_addr_iommu = NULL;
+ if (!client_ctx || !meta_buffers)
+ return false;
+
+ vcd_property_hdr.prop_id = VCD_I_SET_EXT_METABUFFER;
+ vcd_property_hdr.sz = sizeof(struct vcd_property_meta_buffer);
+ vcd_meta_buffer = &client_ctx->vcd_meta_buffer;
+
+ memset(&client_ctx->vcd_meta_buffer, 0,
+ sizeof(struct vcd_property_meta_buffer));
+ vcd_meta_buffer->size = meta_buffers->size;
+ vcd_meta_buffer->count = meta_buffers->count;
+ vcd_meta_buffer->pmem_fd = meta_buffers->pmem_fd;
+ vcd_meta_buffer->offset = meta_buffers->offset;
+ vcd_meta_buffer->pmem_fd_iommu = meta_buffers->pmem_fd_iommu;
+
+ if (!vcd_get_ion_status()) {
+ if (get_pmem_file(vcd_meta_buffer->pmem_fd,
+ (unsigned long *) (&(vcd_meta_buffer->
+ physical_addr)),
+ (unsigned long *) (&vcd_meta_buffer->
+ kernel_virtual_addr),
+ (unsigned long *) (&len), &file)) {
+ ERR("%s(): get_pmem_file failed\n", __func__);
+ return false;
+ }
+ put_pmem_file(file);
+ flags = MSM_SUBSYSTEM_MAP_IOVA;
+ mapped_buffer = msm_subsystem_map_buffer(
+ (unsigned long)vcd_meta_buffer->physical_addr,
+ len, flags, vidc_mmu_subsystem,
+ sizeof(vidc_mmu_subsystem)/
+ sizeof(unsigned int));
+ if (IS_ERR(mapped_buffer)) {
+ pr_err("buffer map failed");
+ return false;
+ }
+ vcd_meta_buffer->client_data = (void *) mapped_buffer;
+ vcd_meta_buffer->dev_addr =
+ (u8 *)mapped_buffer->iova[0];
+
+ if (get_pmem_file(vcd_meta_buffer->pmem_fd_iommu,
+ (unsigned long *) (&(vcd_meta_buffer->
+ physical_addr_iommu)),
+ (unsigned long *) (&vcd_meta_buffer->
+ kernel_virt_addr_iommu),
+ (unsigned long *) (&len_iommu), &file_iommu)) {
+ ERR("%s(): get_pmem_file failed\n", __func__);
+ return false;
+ }
+ put_pmem_file(file_iommu);
+ flags_iommu = MSM_SUBSYSTEM_MAP_IOVA;
+ mapped_buffer_iommu = msm_subsystem_map_buffer(
+ (unsigned long)vcd_meta_buffer->physical_addr_iommu,
+ len_iommu, flags_iommu, vidc_mmu_subsystem,
+ sizeof(vidc_mmu_subsystem)/
+ sizeof(unsigned int));
+ if (IS_ERR(mapped_buffer_iommu)) {
+ pr_err("buffer map failed");
+ return false;
+ }
+ vcd_meta_buffer->client_data_iommu =
+ (void *) mapped_buffer_iommu;
+ vcd_meta_buffer->dev_addr_iommu =
+ (u8 *)mapped_buffer_iommu->iova[0];
+ } else {
+ client_ctx->meta_buffer_ion_handle = ion_import_dma_buf(
+ client_ctx->user_ion_client,
+ vcd_meta_buffer->pmem_fd);
+ if (IS_ERR_OR_NULL(client_ctx->meta_buffer_ion_handle)) {
+ ERR("%s(): get_ION_handle failed\n", __func__);
+ goto import_ion_error;
+ }
+ rc = ion_handle_get_flags(client_ctx->user_ion_client,
+ client_ctx->meta_buffer_ion_handle,
+ &ionflag);
+ if (rc) {
+ ERR("%s():get_ION_flags fail\n",
+ __func__);
+ goto import_ion_error;
+ }
+ vcd_meta_buffer->kernel_virtual_addr =
+ (u8 *) ion_map_kernel(
+ client_ctx->user_ion_client,
+ client_ctx->meta_buffer_ion_handle);
+ if (!vcd_meta_buffer->kernel_virtual_addr) {
+ ERR("%s(): get_ION_kernel virtual addr failed\n",
+ __func__);
+ goto import_ion_error;
+ }
+ if (res_trk_check_for_sec_session() ||
+ (res_trk_get_core_type() == (u32)VCD_CORE_720P)) {
+ rc = ion_phys(client_ctx->user_ion_client,
+ client_ctx->meta_buffer_ion_handle,
+ (unsigned long *) (&(vcd_meta_buffer->
+ physical_addr)), &len);
+ if (rc) {
+ ERR("%s():get_ION_kernel physical addr fail\n",
+ __func__);
+ goto ion_map_error;
+ }
+ vcd_meta_buffer->client_data = NULL;
+ vcd_meta_buffer->dev_addr = (u8 *)
+ vcd_meta_buffer->physical_addr;
+ } else {
+ rc = ion_map_iommu(client_ctx->user_ion_client,
+ client_ctx->meta_buffer_ion_handle,
+ VIDEO_DOMAIN, VIDEO_MAIN_POOL,
+ SZ_4K, 0, (unsigned long *)&iova,
+ (unsigned long *)&buffer_size,
+ 0, 0);
+ if (rc || !iova) {
+ ERR("%s():get_ION_kernel physical addr fail,"\
+ " rc = %d iova = 0x%lx\n",
+ __func__, rc, iova);
+ goto ion_map_error;
+ }
+ vcd_meta_buffer->physical_addr = (u8 *) iova;
+ vcd_meta_buffer->client_data = NULL;
+ vcd_meta_buffer->dev_addr = (u8 *) iova;
+ }
+
+ client_ctx->meta_buffer_iommu_ion_handle = ion_import_dma_buf(
+ client_ctx->user_ion_client,
+ vcd_meta_buffer->pmem_fd_iommu);
+ if (IS_ERR_OR_NULL(client_ctx->meta_buffer_iommu_ion_handle)) {
+ ERR("%s(): get_ION_handle failed\n", __func__);
+ goto import_ion_error;
+ }
+ rc = ion_handle_get_flags(client_ctx->user_ion_client,
+ client_ctx->
+ meta_buffer_iommu_ion_handle,
+ &ionflag_iommu);
+ if (rc) {
+ ERR("%s():get_ION_flags fail\n",
+ __func__);
+ goto import_ion_error;
+ }
+ vcd_meta_buffer->kernel_virt_addr_iommu =
+ (u8 *) ion_map_kernel(
+ client_ctx->user_ion_client,
+ client_ctx->meta_buffer_iommu_ion_handle);
+ if (!vcd_meta_buffer->kernel_virt_addr_iommu) {
+ ERR("%s(): get_ION_kernel virtual addr failed\n",
+ __func__);
+ goto import_ion_error;
+ }
+ if (res_trk_get_core_type() == (u32)VCD_CORE_720P) {
+ rc = ion_phys(client_ctx->user_ion_client,
+ client_ctx->meta_buffer_iommu_ion_handle,
+ (unsigned long *) (&(vcd_meta_buffer->
+ physical_addr_iommu)), &len_iommu);
+ if (rc) {
+ ERR("%s():get_ION_kernel physical addr fail\n",
+ __func__);
+ goto ion_map_error_iommu;
+ }
+ vcd_meta_buffer->client_data_iommu = NULL;
+ vcd_meta_buffer->dev_addr_iommu = (u8 *)
+ vcd_meta_buffer->physical_addr_iommu;
+ } else {
+ rc = ion_map_iommu(client_ctx->user_ion_client,
+ client_ctx->meta_buffer_iommu_ion_handle,
+ VIDEO_DOMAIN, VIDEO_MAIN_POOL,
+ SZ_4K, 0, (unsigned long *)&iova_iommu,
+ (unsigned long *)&buffer_size_iommu,
+ 0, 0);
+ if (rc || !iova_iommu) {
+ ERR("%s():get_ION_kernel physical addr fail, "\
+ "rc = %d iova = 0x%lx\n",
+ __func__, rc, iova);
+ goto ion_map_error_iommu;
+ }
+ vcd_meta_buffer->physical_addr_iommu =
+ (u8 *) iova_iommu;
+ vcd_meta_buffer->client_data_iommu = NULL;
+ vcd_meta_buffer->dev_addr_iommu = (u8 *) iova_iommu;
+ }
+ }
+
+ /*fill the meta addr table*/
+ num_buffers = vcd_meta_buffer->count;
+ buf_size = vcd_meta_buffer->size/num_buffers;
+ ker_vir_addr = vcd_meta_buffer->kernel_virtual_addr;
+ ker_vir_addr_iommu = vcd_meta_buffer->kernel_virt_addr_iommu;
+ client_ctx->meta_buf_size = buf_size;
+ for (index = 0; index < num_buffers; index++) {
+ client_ctx->meta_addr_table[index].kernel_vir_addr =
+ ker_vir_addr;
+ client_ctx->meta_addr_table[index].kernel_vir_addr_iommu =
+ ker_vir_addr_iommu;
+ DBG("[%d] kernel_virtual = %p kernel_vir_iommu = %p",
+ index, ker_vir_addr, ker_vir_addr_iommu);
+ ker_vir_addr += buf_size;
+ ker_vir_addr_iommu += buf_size;
+ }
+
+ DBG("Meta Buffer: Virt: %p, Phys %p, fd: %d",
+ vcd_meta_buffer->kernel_virtual_addr,
+ vcd_meta_buffer->physical_addr,
+ vcd_meta_buffer->pmem_fd);
+ DBG("IOMMU Meta Buffer: Virt: %p, Phys %p, fd: %d",
+ vcd_meta_buffer->kernel_virt_addr_iommu,
+ vcd_meta_buffer->physical_addr_iommu,
+ vcd_meta_buffer->pmem_fd_iommu);
+ DBG("Meta_buffer: Dev addr %p", vcd_meta_buffer->dev_addr);
+ DBG("IOMMU Meta_buffer: Dev addr %p",
+ vcd_meta_buffer->dev_addr_iommu);
+ vcd_status = vcd_set_property(client_ctx->vcd_handle,
+ &vcd_property_hdr,
+ vcd_meta_buffer);
+
+ if (vcd_status)
+ return false;
+ else
+ return true;
+ion_map_error_iommu:
+ if (vcd_meta_buffer->kernel_virt_addr_iommu) {
+ ion_unmap_kernel(client_ctx->user_ion_client,
+ client_ctx->meta_buffer_iommu_ion_handle);
+ vcd_meta_buffer->kernel_virt_addr_iommu = NULL;
+ }
+ if (!IS_ERR_OR_NULL(client_ctx->meta_buffer_iommu_ion_handle)) {
+ ion_free(client_ctx->user_ion_client,
+ client_ctx->meta_buffer_iommu_ion_handle);
+ client_ctx->meta_buffer_iommu_ion_handle = NULL;
+ }
+ion_map_error:
+ if (vcd_meta_buffer->kernel_virtual_addr) {
+ ion_unmap_kernel(client_ctx->user_ion_client,
+ client_ctx->meta_buffer_ion_handle);
+ vcd_meta_buffer->kernel_virtual_addr = NULL;
+ }
+ if (!IS_ERR_OR_NULL(client_ctx->meta_buffer_ion_handle)) {
+ ion_free(client_ctx->user_ion_client,
+ client_ctx->meta_buffer_ion_handle);
+ client_ctx->meta_buffer_ion_handle = NULL;
+ }
+import_ion_error:
+ return false;
+}
static u32 vid_dec_set_h264_mv_buffers(struct video_client_ctx *client_ctx,
struct vdec_h264_mv *mv_data)
{
@@ -1018,6 +1306,65 @@
return true;
}
+static u32 vid_dec_free_meta_buffers(struct video_client_ctx *client_ctx)
+{
+ struct vcd_property_hdr vcd_property_hdr;
+ struct vcd_property_buffer_size meta_buffer_size;
+ u32 vcd_status = VCD_ERR_FAIL;
+
+ if (!client_ctx)
+ return false;
+ if (client_ctx->vcd_meta_buffer.client_data)
+ msm_subsystem_unmap_buffer((struct msm_mapped_buffer *)
+ client_ctx->vcd_meta_buffer.client_data);
+
+ if (client_ctx->vcd_meta_buffer.client_data_iommu)
+ msm_subsystem_unmap_buffer((struct msm_mapped_buffer *)
+ client_ctx->vcd_meta_buffer.client_data_iommu);
+
+ vcd_property_hdr.prop_id = VCD_I_FREE_EXT_METABUFFER;
+ vcd_property_hdr.sz = sizeof(struct vcd_property_buffer_size);
+
+ vcd_status = vcd_set_property(client_ctx->vcd_handle,
+ &vcd_property_hdr, &meta_buffer_size);
+
+ if (!IS_ERR_OR_NULL(client_ctx->meta_buffer_ion_handle)) {
+ ion_unmap_kernel(client_ctx->user_ion_client,
+ client_ctx->meta_buffer_ion_handle);
+ if (!res_trk_check_for_sec_session() &&
+ (res_trk_get_core_type() != (u32)VCD_CORE_720P)) {
+ ion_unmap_iommu(client_ctx->user_ion_client,
+ client_ctx->meta_buffer_ion_handle,
+ VIDEO_DOMAIN,
+ VIDEO_MAIN_POOL);
+ }
+ ion_free(client_ctx->user_ion_client,
+ client_ctx->meta_buffer_ion_handle);
+ client_ctx->meta_buffer_ion_handle = NULL;
+ }
+
+ if (!IS_ERR_OR_NULL(client_ctx->meta_buffer_iommu_ion_handle)) {
+ ion_unmap_kernel(client_ctx->user_ion_client,
+ client_ctx->meta_buffer_iommu_ion_handle);
+ if (res_trk_check_for_sec_session() &&
+ (res_trk_get_core_type() != (u32)VCD_CORE_720P)) {
+ ion_unmap_iommu(client_ctx->user_ion_client,
+ client_ctx->meta_buffer_iommu_ion_handle,
+ VIDEO_DOMAIN,
+ VIDEO_MAIN_POOL);
+ }
+ ion_free(client_ctx->user_ion_client,
+ client_ctx->meta_buffer_iommu_ion_handle);
+ client_ctx->meta_buffer_iommu_ion_handle = NULL;
+ }
+
+ if (vcd_status)
+ return false;
+ else
+ return true;
+}
+
+
static u32 vid_dec_free_h264_mv_buffers(struct video_client_ctx *client_ctx)
{
struct vcd_property_hdr vcd_property_hdr;
@@ -1085,6 +1432,7 @@
vdec_buf_req->buffer_size = vcd_buf_req.sz;
vdec_buf_req->alignment = vcd_buf_req.align;
vdec_buf_req->buf_poolid = vcd_buf_req.buf_pool_id;
+ vdec_buf_req->meta_buffer_size = vcd_buf_req.meta_buffer_size;
return true;
}
@@ -1977,6 +2325,29 @@
return -EIO;
break;
}
+ case VDEC_IOCTL_SET_META_BUFFERS:
+ {
+ struct vdec_meta_buffers meta_buffers;
+ DBG("VDEC_IOCTL_SET_META_BUFFERS\n");
+ if (copy_from_user(&vdec_msg, arg, sizeof(vdec_msg)))
+ return -EFAULT;
+ if (copy_from_user(&meta_buffers, vdec_msg.in,
+ sizeof(meta_buffers)))
+ return -EFAULT;
+ result = vid_dec_set_meta_buffers(client_ctx, &meta_buffers);
+
+ if (!result)
+ return -EIO;
+ break;
+ }
+ case VDEC_IOCTL_FREE_META_BUFFERS:
+ {
+ DBG("VDEC_IOCTL_FREE_META_BUFFERS\n");
+ result = vid_dec_free_meta_buffers(client_ctx);
+ if (!result)
+ return -EIO;
+ break;
+ }
case VDEC_IOCTL_SET_H264_MV_BUFFER:
{
struct vdec_h264_mv mv_data;
diff --git a/include/linux/mfd/pm8xxx/pm8921-charger.h b/include/linux/mfd/pm8xxx/pm8921-charger.h
index 44f8538..ab52309 100644
--- a/include/linux/mfd/pm8xxx/pm8921-charger.h
+++ b/include/linux/mfd/pm8xxx/pm8921-charger.h
@@ -138,6 +138,10 @@
* driver couldn't stop charging when battery
* temperature is out of bounds. Used only if
* btc_override = 1
+ * stop_chg_upon_expiry: flag to indicate that the charger driver should
+ * stop charging the battery when the safety timer
+ * expires. If not set the charger driver will
+ * restart charging upon expiry.
*/
struct pm8921_charger_platform_data {
struct pm8xxx_charger_core_data charger_cdata;
@@ -183,6 +187,7 @@
int btc_override_hot_degc;
int btc_delay_ms;
int btc_panic_if_cant_stop_chg;
+ int stop_chg_upon_expiry;
};
enum pm8921_charger_source {
diff --git a/include/linux/mfd/wcd9xxx/core.h b/include/linux/mfd/wcd9xxx/core.h
index 2874a3b..4b2ad66 100644
--- a/include/linux/mfd/wcd9xxx/core.h
+++ b/include/linux/mfd/wcd9xxx/core.h
@@ -83,6 +83,7 @@
TABLA_NUM_IRQS = WCD9XXX_NUM_IRQS,
SITAR_NUM_IRQS = WCD9XXX_NUM_IRQS,
TAIKO_NUM_IRQS = WCD9XXX_NUM_IRQS,
+ TAPAN_NUM_IRQS = WCD9XXX_NUM_IRQS,
};
@@ -212,7 +213,8 @@
void wcd9xxx_disable_irq_sync(struct wcd9xxx *wcd9xxx, int irq);
#if defined(CONFIG_WCD9310_CODEC) || \
defined(CONFIG_WCD9304_CODEC) || \
- defined(CONFIG_WCD9320_CODEC)
+ defined(CONFIG_WCD9320_CODEC) || \
+ defined(CONFIG_WCD9306_CODEC)
int __init wcd9xxx_irq_of_init(struct device_node *node,
struct device_node *parent);
#else
@@ -221,5 +223,5 @@
{
return 0;
}
-#endif
+#endif /* CONFIG_OF */
#endif
diff --git a/include/linux/mfd/wcd9xxx/wcd9306_registers.h b/include/linux/mfd/wcd9xxx/wcd9306_registers.h
new file mode 100644
index 0000000..1254fac
--- /dev/null
+++ b/include/linux/mfd/wcd9xxx/wcd9306_registers.h
@@ -0,0 +1,1015 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef WCD9306_REGISTERS_H
+#define WCD9306_REGISTERS_H
+
+#include <linux/mfd/wcd9xxx/wcd9xxx_registers.h>
+
+#define TAPAN_A_CHIP_CTL WCD9XXX_A_CHIP_CTL
+#define TAPAN_A_CHIP_CTL__POR WCD9XXX_A_CHIP_CTL__POR
+#define TAPAN_A_CHIP_STATUS WCD9XXX_A_CHIP_STATUS
+#define TAPAN_A_CHIP_STATUS__POR WCD9XXX_A_CHIP_STATUS__POR
+#define TAPAN_A_CHIP_ID_BYTE_0 WCD9XXX_A_CHIP_ID_BYTE_0
+#define TAPAN_A_CHIP_ID_BYTE_0__POR WCD9XXX_A_CHIP_ID_BYTE_0__POR
+#define TAPAN_A_CHIP_ID_BYTE_1 WCD9XXX_A_CHIP_ID_BYTE_1
+#define TAPAN_A_CHIP_ID_BYTE_1__POR WCD9XXX_A_CHIP_ID_BYTE_1__POR
+#define TAPAN_A_CHIP_ID_BYTE_2 WCD9XXX_A_CHIP_ID_BYTE_2
+#define TAPAN_A_CHIP_ID_BYTE_2__POR WCD9XXX_A_CHIP_ID_BYTE_2__POR
+#define TAPAN_A_CHIP_ID_BYTE_3 WCD9XXX_A_CHIP_ID_BYTE_3
+#define TAPAN_A_CHIP_ID_BYTE_3__POR WCD9XXX_A_CHIP_ID_BYTE_3__POR
+#define TAPAN_A_CHIP_VERSION WCD9XXX_A_CHIP_VERSION
+#define TAPAN_A_CHIP_VERSION__POR WCD9XXX_A_CHIP_VERSION__POR
+#define TAPAN_A_CHIP_DEBUG_CTL (0x009)
+#define TAPAN_A_CHIP_DEBUG_CTL__POR (0x00)
+#define TAPAN_A_SLAVE_ID_1 (0x00C)
+#define TAPAN_A_SLAVE_ID_1__POR (0x77)
+#define TAPAN_A_SLAVE_ID_2 (0x00D)
+#define TAPAN_A_SLAVE_ID_2__POR (0x66)
+#define TAPAN_A_SLAVE_ID_3 (0x00E)
+#define TAPAN_A_SLAVE_ID_3__POR (0x55)
+#define TAPAN_A_PIN_CTL_OE0 (0x010)
+#define TAPAN_A_PIN_CTL_OE0__POR (0x00)
+#define TAPAN_A_PIN_CTL_DATA0 (0x012)
+#define TAPAN_A_PIN_CTL_DATA0__POR (0x00)
+#define TAPAN_A_HDRIVE_GENERIC (0x018)
+#define TAPAN_A_HDRIVE_GENERIC__POR (0x00)
+#define TAPAN_A_HDRIVE_OVERRIDE (0x019)
+#define TAPAN_A_HDRIVE_OVERRIDE__POR (0x08)
+#define TAPAN_A_ANA_CSR_WAIT_STATE (0x020)
+#define TAPAN_A_ANA_CSR_WAIT_STATE__POR (0x44)
+#define TAPAN_A_PROCESS_MONITOR_CTL0 (0x040)
+#define TAPAN_A_PROCESS_MONITOR_CTL0__POR (0x80)
+#define TAPAN_A_PROCESS_MONITOR_CTL1 (0x041)
+#define TAPAN_A_PROCESS_MONITOR_CTL1__POR (0x00)
+#define TAPAN_A_PROCESS_MONITOR_CTL2 (0x042)
+#define TAPAN_A_PROCESS_MONITOR_CTL2__POR (0x00)
+#define TAPAN_A_PROCESS_MONITOR_CTL3 (0x043)
+#define TAPAN_A_PROCESS_MONITOR_CTL3__POR (0x01)
+#define TAPAN_A_QFUSE_CTL (0x048)
+#define TAPAN_A_QFUSE_CTL__POR (0x00)
+#define TAPAN_A_QFUSE_STATUS (0x049)
+#define TAPAN_A_QFUSE_STATUS__POR (0x00)
+#define TAPAN_A_QFUSE_DATA_OUT0 (0x04A)
+#define TAPAN_A_QFUSE_DATA_OUT0__POR (0x00)
+#define TAPAN_A_QFUSE_DATA_OUT1 (0x04B)
+#define TAPAN_A_QFUSE_DATA_OUT1__POR (0x00)
+#define TAPAN_A_QFUSE_DATA_OUT2 (0x04C)
+#define TAPAN_A_QFUSE_DATA_OUT2__POR (0x00)
+#define TAPAN_A_QFUSE_DATA_OUT3 (0x04D)
+#define TAPAN_A_QFUSE_DATA_OUT3__POR (0x00)
+#define TAPAN_A_QFUSE_DATA_OUT4 (0x04E)
+#define TAPAN_A_QFUSE_DATA_OUT4__POR (0x00)
+#define TAPAN_A_QFUSE_DATA_OUT5 (0x04F)
+#define TAPAN_A_QFUSE_DATA_OUT5__POR (0x00)
+#define TAPAN_A_QFUSE_DATA_OUT6 (0x050)
+#define TAPAN_A_QFUSE_DATA_OUT6__POR (0x00)
+#define TAPAN_A_QFUSE_DATA_OUT7 (0x051)
+#define TAPAN_A_QFUSE_DATA_OUT7__POR (0x00)
+#define TAPAN_A_CDC_CTL (0x080)
+#define TAPAN_A_CDC_CTL__POR (0x00)
+#define TAPAN_A_LEAKAGE_CTL (0x088)
+#define TAPAN_A_LEAKAGE_CTL__POR (0x04)
+#define TAPAN_A_INTR_MODE (0x090)
+#define TAPAN_A_INTR_MODE__POR (0x00)
+#define TAPAN_A_INTR_MASK0 (0x094)
+#define TAPAN_A_INTR_MASK0__POR (0xFF)
+#define TAPAN_A_INTR_MASK1 (0x095)
+#define TAPAN_A_INTR_MASK1__POR (0xFF)
+#define TAPAN_A_INTR_MASK2 (0x096)
+#define TAPAN_A_INTR_MASK2__POR (0x3F)
+#define TAPAN_A_INTR_MASK3 (0x097)
+#define TAPAN_A_INTR_MASK3__POR (0x3F)
+#define TAPAN_A_INTR_STATUS0 (0x098)
+#define TAPAN_A_INTR_STATUS0__POR (0x00)
+#define TAPAN_A_INTR_STATUS1 (0x099)
+#define TAPAN_A_INTR_STATUS1__POR (0x00)
+#define TAPAN_A_INTR_STATUS2 (0x09A)
+#define TAPAN_A_INTR_STATUS2__POR (0x00)
+#define TAPAN_A_INTR_STATUS3 (0x09B)
+#define TAPAN_A_INTR_STATUS3__POR (0x00)
+#define TAPAN_A_INTR_CLEAR0 (0x09C)
+#define TAPAN_A_INTR_CLEAR0__POR (0x00)
+#define TAPAN_A_INTR_CLEAR1 (0x09D)
+#define TAPAN_A_INTR_CLEAR1__POR (0x00)
+#define TAPAN_A_INTR_CLEAR2 (0x09E)
+#define TAPAN_A_INTR_CLEAR2__POR (0x00)
+#define TAPAN_A_INTR_CLEAR3 (0x09F)
+#define TAPAN_A_INTR_CLEAR3__POR (0x00)
+#define TAPAN_A_INTR_LEVEL0 (0x0A0)
+#define TAPAN_A_INTR_LEVEL0__POR (0x01)
+#define TAPAN_A_INTR_LEVEL1 (0x0A1)
+#define TAPAN_A_INTR_LEVEL1__POR (0x00)
+#define TAPAN_A_INTR_LEVEL2 (0x0A2)
+#define TAPAN_A_INTR_LEVEL2__POR (0x00)
+#define TAPAN_A_INTR_LEVEL3 (0x0A3)
+#define TAPAN_A_INTR_LEVEL3__POR (0x00)
+#define TAPAN_A_INTR_TEST0 (0x0A4)
+#define TAPAN_A_INTR_TEST0__POR (0x00)
+#define TAPAN_A_INTR_TEST1 (0x0A5)
+#define TAPAN_A_INTR_TEST1__POR (0x00)
+#define TAPAN_A_INTR_TEST2 (0x0A6)
+#define TAPAN_A_INTR_TEST2__POR (0x00)
+#define TAPAN_A_INTR_TEST3 (0x0A7)
+#define TAPAN_A_INTR_TEST3__POR (0x00)
+#define TAPAN_A_INTR_SET0 (0x0A8)
+#define TAPAN_A_INTR_SET0__POR (0x00)
+#define TAPAN_A_INTR_SET1 (0x0A9)
+#define TAPAN_A_INTR_SET1__POR (0x00)
+#define TAPAN_A_INTR_SET2 (0x0AA)
+#define TAPAN_A_INTR_SET2__POR (0x00)
+#define TAPAN_A_INTR_SET3 (0x0AB)
+#define TAPAN_A_INTR_SET3__POR (0x00)
+#define TAPAN_A_INTR_DESTN0 (0x0AC)
+#define TAPAN_A_INTR_DESTN0__POR (0x00)
+#define TAPAN_A_INTR_DESTN1 (0x0AD)
+#define TAPAN_A_INTR_DESTN1__POR (0x00)
+#define TAPAN_A_INTR_DESTN2 (0x0AE)
+#define TAPAN_A_INTR_DESTN2__POR (0x00)
+#define TAPAN_A_INTR_DESTN3 (0x0AF)
+#define TAPAN_A_INTR_DESTN3__POR (0x00)
+#define TAPAN_A_CDC_DMIC_DATA0_MODE (0x0C0)
+#define TAPAN_A_CDC_DMIC_DATA0_MODE__POR (0x00)
+#define TAPAN_A_CDC_DMIC_CLK0_MODE (0x0C1)
+#define TAPAN_A_CDC_DMIC_CLK0_MODE__POR (0x00)
+#define TAPAN_A_CDC_DMIC_DATA1_MODE (0x0C2)
+#define TAPAN_A_CDC_DMIC_DATA1_MODE__POR (0x00)
+#define TAPAN_A_CDC_DMIC_CLK1_MODE (0x0C3)
+#define TAPAN_A_CDC_DMIC_CLK1_MODE__POR (0x00)
+#define TAPAN_A_CDC_INTR_MODE (0x0C4)
+#define TAPAN_A_CDC_INTR_MODE__POR (0x00)
+#define TAPAN_A_BIAS_REF_CTL (0x100)
+#define TAPAN_A_BIAS_REF_CTL__POR (0x1C)
+#define TAPAN_A_BIAS_CENTRAL_BG_CTL (0x101)
+#define TAPAN_A_BIAS_CENTRAL_BG_CTL__POR (0x50)
+#define TAPAN_A_BIAS_PRECHRG_CTL (0x102)
+#define TAPAN_A_BIAS_PRECHRG_CTL__POR (0x07)
+#define TAPAN_A_BIAS_CURR_CTL_1 (0x103)
+#define TAPAN_A_BIAS_CURR_CTL_1__POR (0x52)
+#define TAPAN_A_BIAS_CURR_CTL_2 (0x104)
+#define TAPAN_A_BIAS_CURR_CTL_2__POR (0x00)
+#define TAPAN_A_BIAS_OSC_BG_CTL (0x105)
+#define TAPAN_A_BIAS_OSC_BG_CTL__POR (0x16)
+#define TAPAN_A_CLK_BUFF_EN1 (0x108)
+#define TAPAN_A_CLK_BUFF_EN1__POR (0x04)
+#define TAPAN_A_CLK_BUFF_EN2 (0x109)
+#define TAPAN_A_CLK_BUFF_EN2__POR (0x02)
+#define TAPAN_A_LDO_H_MODE_1 (0x110)
+#define TAPAN_A_LDO_H_MODE_1__POR (0x65)
+#define TAPAN_A_LDO_H_MODE_2 (0x111)
+#define TAPAN_A_LDO_H_MODE_2__POR (0xA8)
+#define TAPAN_A_LDO_H_LOOP_CTL (0x112)
+#define TAPAN_A_LDO_H_LOOP_CTL__POR (0x6B)
+#define TAPAN_A_LDO_H_COMP_1 (0x113)
+#define TAPAN_A_LDO_H_COMP_1__POR (0x84)
+#define TAPAN_A_LDO_H_COMP_2 (0x114)
+#define TAPAN_A_LDO_H_COMP_2__POR (0xE0)
+#define TAPAN_A_LDO_H_BIAS_1 (0x115)
+#define TAPAN_A_LDO_H_BIAS_1__POR (0x6D)
+#define TAPAN_A_LDO_H_BIAS_2 (0x116)
+#define TAPAN_A_LDO_H_BIAS_2__POR (0xA5)
+#define TAPAN_A_LDO_H_BIAS_3 (0x117)
+#define TAPAN_A_LDO_H_BIAS_3__POR (0x60)
+#define TAPAN_A_MICB_CFILT_1_CTL (0x128)
+#define TAPAN_A_MICB_CFILT_1_CTL__POR (0x40)
+#define TAPAN_A_MICB_CFILT_1_VAL (0x129)
+#define TAPAN_A_MICB_CFILT_1_VAL__POR (0x80)
+#define TAPAN_A_MICB_CFILT_1_PRECHRG (0x12A)
+#define TAPAN_A_MICB_CFILT_1_PRECHRG__POR (0x00)
+#define TAPAN_A_MICB_1_CTL (0x12B)
+#define TAPAN_A_MICB_1_CTL__POR (0x02)
+#define TAPAN_A_MICB_1_INT_RBIAS (0x12C)
+#define TAPAN_A_MICB_1_INT_RBIAS__POR (0x24)
+#define TAPAN_A_MICB_1_MBHC (0x12D)
+#define TAPAN_A_MICB_1_MBHC__POR (0x01)
+#define TAPAN_A_MICB_CFILT_2_CTL (0x12E)
+#define TAPAN_A_MICB_CFILT_2_CTL__POR (0x40)
+#define TAPAN_A_MICB_CFILT_2_VAL (0x12F)
+#define TAPAN_A_MICB_CFILT_2_VAL__POR (0x80)
+#define TAPAN_A_MICB_CFILT_2_PRECHRG (0x130)
+#define TAPAN_A_MICB_CFILT_2_PRECHRG__POR (0x00)
+#define TAPAN_A_MICB_2_CTL (0x131)
+#define TAPAN_A_MICB_2_CTL__POR (0x12)
+#define TAPAN_A_MICB_2_INT_RBIAS (0x132)
+#define TAPAN_A_MICB_2_INT_RBIAS__POR (0x24)
+#define TAPAN_A_MICB_2_MBHC (0x133)
+#define TAPAN_A_MICB_2_MBHC__POR (0x02)
+#define TAPAN_A_MICB_CFILT_3_CTL (0x134)
+#define TAPAN_A_MICB_CFILT_3_CTL__POR (0x40)
+#define TAPAN_A_MICB_CFILT_3_VAL (0x135)
+#define TAPAN_A_MICB_CFILT_3_VAL__POR (0x80)
+#define TAPAN_A_MICB_CFILT_3_PRECHRG (0x136)
+#define TAPAN_A_MICB_CFILT_3_PRECHRG__POR (0x00)
+#define TAPAN_A_MICB_3_CTL (0x137)
+#define TAPAN_A_MICB_3_CTL__POR (0x02)
+#define TAPAN_A_MICB_3_INT_RBIAS (0x138)
+#define TAPAN_A_MICB_3_INT_RBIAS__POR (0x24)
+#define TAPAN_A_MICB_3_MBHC (0x139)
+#define TAPAN_A_MICB_3_MBHC__POR (0x00)
+#define TAPAN_A_MBHC_INSERT_DETECT (0x14A)
+#define TAPAN_A_MBHC_INSERT_DETECT__POR (0x00)
+#define TAPAN_A_MBHC_INSERT_DET_STATUS (0x14B)
+#define TAPAN_A_MBHC_INSERT_DET_STATUS__POR (0x00)
+#define TAPAN_A_TX_COM_BIAS (0x14C)
+#define TAPAN_A_TX_COM_BIAS__POR (0xF0)
+#define TAPAN_A_MBHC_SCALING_MUX_1 (0x14E)
+#define TAPAN_A_MBHC_SCALING_MUX_1__POR (0x00)
+#define TAPAN_A_MBHC_SCALING_MUX_2 (0x14F)
+#define TAPAN_A_MBHC_SCALING_MUX_2__POR (0x80)
+#define TAPAN_A_RESERVED_MAD_ANA_CTRL (0x150)
+#define TAPAN_A_RESERVED_MAD_ANA_CTRL__POR (0xF1)
+#define TAPAN_A_TX_SUP_SWITCH_CTRL_1 (0x151)
+#define TAPAN_A_TX_SUP_SWITCH_CTRL_1__POR (0x00)
+#define TAPAN_A_TX_SUP_SWITCH_CTRL_2 (0x152)
+#define TAPAN_A_TX_SUP_SWITCH_CTRL_2__POR (0x80)
+#define TAPAN_A_TX_1_EN (0x153)
+#define TAPAN_A_TX_1_EN__POR (0x02)
+#define TAPAN_A_TX_2_EN (0x154)
+#define TAPAN_A_TX_2_EN__POR (0x02)
+#define TAPAN_A_TX_1_2_ADC_CH1 (0x155)
+#define TAPAN_A_TX_1_2_ADC_CH1__POR (0x44)
+#define TAPAN_A_TX_1_2_ADC_CH2 (0x156)
+#define TAPAN_A_TX_1_2_ADC_CH2__POR (0x44)
+#define TAPAN_A_TX_1_2_ATEST_REFCTRL (0x157)
+#define TAPAN_A_TX_1_2_ATEST_REFCTRL__POR (0x00)
+#define TAPAN_A_TX_1_2_TEST_CTL (0x158)
+#define TAPAN_A_TX_1_2_TEST_CTL__POR (0x38)
+#define TAPAN_A_TX_1_2_TEST_BLOCK_EN (0x159)
+#define TAPAN_A_TX_1_2_TEST_BLOCK_EN__POR (0xFC)
+#define TAPAN_A_TX_1_2_TXFE_CLKDIV (0x15A)
+#define TAPAN_A_TX_1_2_TXFE_CLKDIV__POR (0x55)
+#define TAPAN_A_TX_1_2_SAR_ERR_CH1 (0x15B)
+#define TAPAN_A_TX_1_2_SAR_ERR_CH1__POR (0x00)
+#define TAPAN_A_TX_1_2_SAR_ERR_CH2 (0x15C)
+#define TAPAN_A_TX_1_2_SAR_ERR_CH2__POR (0x00)
+#define TAPAN_A_TX_3_EN (0x15D)
+#define TAPAN_A_TX_3_EN__POR (0x00)
+#define TAPAN_A_TX_1_2_TEST_EN (0x15E)
+#define TAPAN_A_TX_1_2_TEST_EN__POR (0xCC)
+#define TAPAN_A_TX_4_5_TXFE_SC_CTL (0x15F)
+#define TAPAN_A_TX_4_5_TXFE_SC_CTL__POR (0x00)
+#define TAPAN_A_TX_4_5_TEST_EN (0x160)
+#define TAPAN_A_TX_4_5_TEST_EN__POR (0xCC)
+#define TAPAN_A_TX_4_EN (0x167)
+#define TAPAN_A_TX_4_EN__POR (0x02)
+#define TAPAN_A_TX_5_EN (0x168)
+#define TAPAN_A_TX_5_EN__POR (0x02)
+#define TAPAN_A_TX_4_5_ADC_CH4 (0x169)
+#define TAPAN_A_TX_4_5_ADC_CH4__POR (0x44)
+#define TAPAN_A_TX_4_5_ADC_CH5 (0x16A)
+#define TAPAN_A_TX_4_5_ADC_CH5__POR (0x44)
+#define TAPAN_A_TX_4_5_ATEST_REFCTRL (0x16B)
+#define TAPAN_A_TX_4_5_ATEST_REFCTRL__POR (0x00)
+#define TAPAN_A_TX_4_5_TEST_CTL (0x16C)
+#define TAPAN_A_TX_4_5_TEST_CTL__POR (0x38)
+#define TAPAN_A_TX_4_5_TEST_BLOCK_EN (0x16D)
+#define TAPAN_A_TX_4_5_TEST_BLOCK_EN__POR (0xFC)
+#define TAPAN_A_TX_4_5_TXFE_CKDIV (0x16E)
+#define TAPAN_A_TX_4_5_TXFE_CKDIV__POR (0x55)
+#define TAPAN_A_TX_4_5_SAR_ERR_CH4 (0x16F)
+#define TAPAN_A_TX_4_5_SAR_ERR_CH4__POR (0x00)
+#define TAPAN_A_TX_4_5_SAR_ERR_CH5 (0x170)
+#define TAPAN_A_TX_4_5_SAR_ERR_CH5__POR (0x00)
+#define TAPAN_A_TX_7_MBHC_EN (0x171)
+#define TAPAN_A_TX_7_MBHC_EN__POR (0x0C)
+#define TAPAN_A_TX_7_MBHC_ATEST_REFCTRL (0x172)
+#define TAPAN_A_TX_7_MBHC_ATEST_REFCTRL__POR (0x00)
+#define TAPAN_A_TX_7_MBHC_ADC (0x173)
+#define TAPAN_A_TX_7_MBHC_ADC__POR (0x44)
+#define TAPAN_A_TX_7_MBHC_TEST_CTL (0x174)
+#define TAPAN_A_TX_7_MBHC_TEST_CTL__POR (0x38)
+#define TAPAN_A_TX_7_MBHC_SAR_ERR (0x175)
+#define TAPAN_A_TX_7_MBHC_SAR_ERR__POR (0x00)
+#define TAPAN_A_TX_7_TXFE_CLKDIV (0x176)
+#define TAPAN_A_TX_7_TXFE_CLKDIV__POR (0x0B)
+#define TAPAN_A_BUCK_MODE_1 (0x181)
+#define TAPAN_A_BUCK_MODE_1__POR (0x21)
+#define TAPAN_A_BUCK_MODE_2 (0x182)
+#define TAPAN_A_BUCK_MODE_2__POR (0xFF)
+#define TAPAN_A_BUCK_MODE_3 (0x183)
+#define TAPAN_A_BUCK_MODE_3__POR (0xCE)
+#define TAPAN_A_BUCK_MODE_4 (0x184)
+#define TAPAN_A_BUCK_MODE_4__POR (0x3A)
+#define TAPAN_A_BUCK_MODE_5 (0x185)
+#define TAPAN_A_BUCK_MODE_5__POR (0x00)
+#define TAPAN_A_BUCK_CTRL_VCL_1 (0x186)
+#define TAPAN_A_BUCK_CTRL_VCL_1__POR (0x08)
+#define TAPAN_A_BUCK_CTRL_VCL_2 (0x187)
+#define TAPAN_A_BUCK_CTRL_VCL_2__POR (0xA3)
+#define TAPAN_A_BUCK_CTRL_VCL_3 (0x188)
+#define TAPAN_A_BUCK_CTRL_VCL_3__POR (0x82)
+#define TAPAN_A_BUCK_CTRL_CCL_1 (0x189)
+#define TAPAN_A_BUCK_CTRL_CCL_1__POR (0x5B)
+#define TAPAN_A_BUCK_CTRL_CCL_2 (0x18A)
+#define TAPAN_A_BUCK_CTRL_CCL_2__POR (0xDC)
+#define TAPAN_A_BUCK_CTRL_CCL_3 (0x18B)
+#define TAPAN_A_BUCK_CTRL_CCL_3__POR (0x6A)
+#define TAPAN_A_BUCK_CTRL_CCL_4 (0x18C)
+#define TAPAN_A_BUCK_CTRL_CCL_4__POR (0x50)
+#define TAPAN_A_BUCK_CTRL_PWM_DRVR_1 (0x18D)
+#define TAPAN_A_BUCK_CTRL_PWM_DRVR_1__POR (0x50)
+#define TAPAN_A_BUCK_CTRL_PWM_DRVR_2 (0x18E)
+#define TAPAN_A_BUCK_CTRL_PWM_DRVR_2__POR (0x64)
+#define TAPAN_A_BUCK_CTRL_PWM_DRVR_3 (0x18F)
+#define TAPAN_A_BUCK_CTRL_PWM_DRVR_3__POR (0x77)
+#define TAPAN_A_BUCK_TMUX_A_D (0x190)
+#define TAPAN_A_BUCK_TMUX_A_D__POR (0x00)
+#define TAPAN_A_NCP_BUCKREF (0x191)
+#define TAPAN_A_NCP_BUCKREF__POR (0x00)
+#define TAPAN_A_NCP_EN (0x192)
+#define TAPAN_A_NCP_EN__POR (0xFE)
+#define TAPAN_A_NCP_CLK (0x193)
+#define TAPAN_A_NCP_CLK__POR (0x94)
+#define TAPAN_A_NCP_STATIC (0x194)
+#define TAPAN_A_NCP_STATIC__POR (0x28)
+#define TAPAN_A_NCP_VTH_LOW (0x195)
+#define TAPAN_A_NCP_VTH_LOW__POR (0x88)
+#define TAPAN_A_NCP_VTH_HIGH (0x196)
+#define TAPAN_A_NCP_VTH_HIGH__POR (0xA0)
+#define TAPAN_A_NCP_ATEST (0x197)
+#define TAPAN_A_NCP_ATEST__POR (0x00)
+#define TAPAN_A_NCP_DTEST (0x198)
+#define TAPAN_A_NCP_DTEST__POR (0x10)
+#define TAPAN_A_NCP_DLY1 (0x199)
+#define TAPAN_A_NCP_DLY1__POR (0x06)
+#define TAPAN_A_NCP_DLY2 (0x19A)
+#define TAPAN_A_NCP_DLY2__POR (0x06)
+#define TAPAN_A_RX_AUX_SW_CTL (0x19B)
+#define TAPAN_A_RX_AUX_SW_CTL__POR (0x00)
+#define TAPAN_A_RX_PA_AUX_IN_CONN (0x19C)
+#define TAPAN_A_RX_PA_AUX_IN_CONN__POR (0x00)
+#define TAPAN_A_RX_COM_TIMER_DIV (0x19E)
+#define TAPAN_A_RX_COM_TIMER_DIV__POR (0xE8)
+#define TAPAN_A_RX_COM_OCP_CTL (0x19F)
+#define TAPAN_A_RX_COM_OCP_CTL__POR (0x1F)
+#define TAPAN_A_RX_COM_OCP_COUNT (0x1A0)
+#define TAPAN_A_RX_COM_OCP_COUNT__POR (0x77)
+#define TAPAN_A_RX_COM_DAC_CTL (0x1A1)
+#define TAPAN_A_RX_COM_DAC_CTL__POR (0x00)
+#define TAPAN_A_RX_COM_BIAS (0x1A2)
+#define TAPAN_A_RX_COM_BIAS__POR (0x00)
+#define TAPAN_A_RX_HPH_AUTO_CHOP (0x1A4)
+#define TAPAN_A_RX_HPH_AUTO_CHOP__POR (0x38)
+#define TAPAN_A_RX_HPH_CHOP_CTL (0x1A5)
+#define TAPAN_A_RX_HPH_CHOP_CTL__POR (0xA4)
+#define TAPAN_A_RX_HPH_BIAS_PA (0x1A6)
+#define TAPAN_A_RX_HPH_BIAS_PA__POR (0x7A)
+#define TAPAN_A_RX_HPH_BIAS_LDO (0x1A7)
+#define TAPAN_A_RX_HPH_BIAS_LDO__POR (0x87)
+#define TAPAN_A_RX_HPH_BIAS_CNP (0x1A8)
+#define TAPAN_A_RX_HPH_BIAS_CNP__POR (0x8A)
+#define TAPAN_A_RX_HPH_BIAS_WG_OCP (0x1A9)
+#define TAPAN_A_RX_HPH_BIAS_WG_OCP__POR (0x2A)
+#define TAPAN_A_RX_HPH_OCP_CTL (0x1AA)
+#define TAPAN_A_RX_HPH_OCP_CTL__POR (0x69)
+#define TAPAN_A_RX_HPH_CNP_EN (0x1AB)
+#define TAPAN_A_RX_HPH_CNP_EN__POR (0x80)
+#define TAPAN_A_RX_HPH_CNP_WG_CTL (0x1AC)
+#define TAPAN_A_RX_HPH_CNP_WG_CTL__POR (0xDE)
+#define TAPAN_A_RX_HPH_CNP_WG_TIME (0x1AD)
+#define TAPAN_A_RX_HPH_CNP_WG_TIME__POR (0x15)
+#define TAPAN_A_RX_HPH_L_GAIN (0x1AE)
+#define TAPAN_A_RX_HPH_L_GAIN__POR (0x00)
+#define TAPAN_A_RX_HPH_L_TEST (0x1AF)
+#define TAPAN_A_RX_HPH_L_TEST__POR (0x00)
+#define TAPAN_A_RX_HPH_L_PA_CTL (0x1B0)
+#define TAPAN_A_RX_HPH_L_PA_CTL__POR (0x40)
+#define TAPAN_A_RX_HPH_L_DAC_CTL (0x1B1)
+#define TAPAN_A_RX_HPH_L_DAC_CTL__POR (0x00)
+#define TAPAN_A_RX_HPH_L_ATEST (0x1B2)
+#define TAPAN_A_RX_HPH_L_ATEST__POR (0x00)
+#define TAPAN_A_RX_HPH_L_STATUS (0x1B3)
+#define TAPAN_A_RX_HPH_L_STATUS__POR (0x00)
+#define TAPAN_A_RX_HPH_R_GAIN (0x1B4)
+#define TAPAN_A_RX_HPH_R_GAIN__POR (0x00)
+#define TAPAN_A_RX_HPH_R_TEST (0x1B5)
+#define TAPAN_A_RX_HPH_R_TEST__POR (0x00)
+#define TAPAN_A_RX_HPH_R_PA_CTL (0x1B6)
+#define TAPAN_A_RX_HPH_R_PA_CTL__POR (0x40)
+#define TAPAN_A_RX_HPH_R_DAC_CTL (0x1B7)
+#define TAPAN_A_RX_HPH_R_DAC_CTL__POR (0x00)
+#define TAPAN_A_RX_HPH_R_ATEST (0x1B8)
+#define TAPAN_A_RX_HPH_R_ATEST__POR (0x00)
+#define TAPAN_A_RX_HPH_R_STATUS (0x1B9)
+#define TAPAN_A_RX_HPH_R_STATUS__POR (0x00)
+#define TAPAN_A_RX_EAR_BIAS_PA (0x1BA)
+#define TAPAN_A_RX_EAR_BIAS_PA__POR (0x76)
+#define TAPAN_A_RX_EAR_BIAS_CMBUFF (0x1BB)
+#define TAPAN_A_RX_EAR_BIAS_CMBUFF__POR (0xA0)
+#define TAPAN_A_RX_EAR_EN (0x1BC)
+#define TAPAN_A_RX_EAR_EN__POR (0x00)
+#define TAPAN_A_RX_EAR_GAIN (0x1BD)
+#define TAPAN_A_RX_EAR_GAIN__POR (0x02)
+#define TAPAN_A_RX_EAR_CMBUFF (0x1BE)
+#define TAPAN_A_RX_EAR_CMBUFF__POR (0x05)
+#define TAPAN_A_RX_EAR_ICTL (0x1BF)
+#define TAPAN_A_RX_EAR_ICTL__POR (0x40)
+#define TAPAN_A_RX_EAR_CCOMP (0x1C0)
+#define TAPAN_A_RX_EAR_CCOMP__POR (0x08)
+#define TAPAN_A_RX_EAR_VCM (0x1C1)
+#define TAPAN_A_RX_EAR_VCM__POR (0x03)
+#define TAPAN_A_RX_EAR_CNP (0x1C2)
+#define TAPAN_A_RX_EAR_CNP__POR (0xF2)
+#define TAPAN_A_RX_EAR_DAC_CTL_ATEST (0x1C3)
+#define TAPAN_A_RX_EAR_DAC_CTL_ATEST__POR (0x00)
+#define TAPAN_A_RX_EAR_STATUS (0x1C5)
+#define TAPAN_A_RX_EAR_STATUS__POR (0x04)
+#define TAPAN_A_RX_LINE_BIAS_PA (0x1C6)
+#define TAPAN_A_RX_LINE_BIAS_PA__POR (0x78)
+#define TAPAN_A_RX_BUCK_BIAS1 (0x1C7)
+#define TAPAN_A_RX_BUCK_BIAS1__POR (0x42)
+#define TAPAN_A_RX_BUCK_BIAS2 (0x1C8)
+#define TAPAN_A_RX_BUCK_BIAS2__POR (0x84)
+#define TAPAN_A_RX_LINE_COM (0x1C9)
+#define TAPAN_A_RX_LINE_COM__POR (0x80)
+#define TAPAN_A_RX_LINE_CNP_EN (0x1CA)
+#define TAPAN_A_RX_LINE_CNP_EN__POR (0x00)
+#define TAPAN_A_RX_LINE_CNP_WG_CTL (0x1CB)
+#define TAPAN_A_RX_LINE_CNP_WG_CTL__POR (0x00)
+#define TAPAN_A_RX_LINE_CNP_WG_TIME (0x1CC)
+#define TAPAN_A_RX_LINE_CNP_WG_TIME__POR (0x04)
+#define TAPAN_A_RX_LINE_1_GAIN (0x1CD)
+#define TAPAN_A_RX_LINE_1_GAIN__POR (0x00)
+#define TAPAN_A_RX_LINE_1_TEST (0x1CE)
+#define TAPAN_A_RX_LINE_1_TEST__POR (0x00)
+#define TAPAN_A_RX_LINE_1_DAC_CTL (0x1CF)
+#define TAPAN_A_RX_LINE_1_DAC_CTL__POR (0x00)
+#define TAPAN_A_RX_LINE_1_STATUS (0x1D0)
+#define TAPAN_A_RX_LINE_1_STATUS__POR (0x00)
+#define TAPAN_A_RX_LINE_2_GAIN (0x1D1)
+#define TAPAN_A_RX_LINE_2_GAIN__POR (0x00)
+#define TAPAN_A_RX_LINE_2_TEST (0x1D2)
+#define TAPAN_A_RX_LINE_2_TEST__POR (0x00)
+#define TAPAN_A_RX_LINE_2_DAC_CTL (0x1D3)
+#define TAPAN_A_RX_LINE_2_DAC_CTL__POR (0x00)
+#define TAPAN_A_RX_LINE_2_STATUS (0x1D4)
+#define TAPAN_A_RX_LINE_2_STATUS__POR (0x00)
+#define TAPAN_A_RX_LINE_CNP_DBG (0x1DD)
+#define TAPAN_A_RX_LINE_CNP_DBG__POR (0x00)
+#define TAPAN_A_SPKR_DRV_EN (0x1DF)
+#define TAPAN_A_SPKR_DRV_EN__POR (0x6F)
+#define TAPAN_A_SPKR_DRV_GAIN (0x1E0)
+#define TAPAN_A_SPKR_DRV_GAIN__POR (0x00)
+#define TAPAN_A_SPKR_DRV_DAC_CTL (0x1E1)
+#define TAPAN_A_SPKR_DRV_DAC_CTL__POR (0x04)
+#define TAPAN_A_SPKR_DRV_OCP_CTL (0x1E2)
+#define TAPAN_A_SPKR_DRV_OCP_CTL__POR (0x98)
+#define TAPAN_A_SPKR_DRV_CLIP_DET (0x1E3)
+#define TAPAN_A_SPKR_DRV_CLIP_DET__POR (0x48)
+#define TAPAN_A_SPKR_DRV_IEC (0x1E4)
+#define TAPAN_A_SPKR_DRV_IEC__POR (0x28)
+#define TAPAN_A_SPKR_DRV_DBG_DAC (0x1E5)
+#define TAPAN_A_SPKR_DRV_DBG_DAC__POR (0x05)
+#define TAPAN_A_SPKR_DRV_DBG_PA (0x1E6)
+#define TAPAN_A_SPKR_DRV_DBG_PA__POR (0x18)
+#define TAPAN_A_SPKR_DRV_DBG_PWRSTG (0x1E7)
+#define TAPAN_A_SPKR_DRV_DBG_PWRSTG__POR (0x00)
+#define TAPAN_A_SPKR_DRV_BIAS_LDO (0x1E8)
+#define TAPAN_A_SPKR_DRV_BIAS_LDO__POR (0x45)
+#define TAPAN_A_SPKR_DRV_BIAS_INT (0x1E9)
+#define TAPAN_A_SPKR_DRV_BIAS_INT__POR (0xA5)
+#define TAPAN_A_SPKR_DRV_BIAS_PA (0x1EA)
+#define TAPAN_A_SPKR_DRV_BIAS_PA__POR (0x55)
+#define TAPAN_A_SPKR_DRV_STATUS_OCP (0x1EB)
+#define TAPAN_A_SPKR_DRV_STATUS_OCP__POR (0x00)
+#define TAPAN_A_SPKR_DRV_STATUS_PA (0x1EC)
+#define TAPAN_A_SPKR_DRV_STATUS_PA__POR (0x00)
+#define TAPAN_A_RC_OSC_FREQ (0x1FA)
+#define TAPAN_A_RC_OSC_FREQ__POR (0x46)
+#define TAPAN_A_RC_OSC_TEST (0x1FB)
+#define TAPAN_A_RC_OSC_TEST__POR (0x0A)
+#define TAPAN_A_RC_OSC_STATUS (0x1FC)
+#define TAPAN_A_RC_OSC_STATUS__POR (0x18)
+#define TAPAN_A_RC_OSC_TUNER (0x1FD)
+#define TAPAN_A_RC_OSC_TUNER__POR (0x00)
+#define TAPAN_A_MBHC_HPH (0x1FE)
+#define TAPAN_A_MBHC_HPH__POR (0x44)
+#define TAPAN_A_CDC_ANC1_B1_CTL (0x200)
+#define TAPAN_A_CDC_ANC1_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_ANC2_B1_CTL (0x280)
+#define TAPAN_A_CDC_ANC2_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_ANC1_SHIFT (0x201)
+#define TAPAN_A_CDC_ANC1_SHIFT__POR (0x00)
+#define TAPAN_A_CDC_ANC2_SHIFT (0x281)
+#define TAPAN_A_CDC_ANC2_SHIFT__POR (0x00)
+#define TAPAN_A_CDC_ANC1_IIR_B1_CTL (0x202)
+#define TAPAN_A_CDC_ANC1_IIR_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_ANC2_IIR_B1_CTL (0x282)
+#define TAPAN_A_CDC_ANC2_IIR_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_ANC1_IIR_B2_CTL (0x203)
+#define TAPAN_A_CDC_ANC1_IIR_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_ANC2_IIR_B2_CTL (0x283)
+#define TAPAN_A_CDC_ANC2_IIR_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_ANC1_IIR_B3_CTL (0x204)
+#define TAPAN_A_CDC_ANC1_IIR_B3_CTL__POR (0x00)
+#define TAPAN_A_CDC_ANC2_IIR_B3_CTL (0x284)
+#define TAPAN_A_CDC_ANC2_IIR_B3_CTL__POR (0x00)
+#define TAPAN_A_CDC_ANC1_LPF_B1_CTL (0x206)
+#define TAPAN_A_CDC_ANC1_LPF_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_ANC2_LPF_B1_CTL (0x286)
+#define TAPAN_A_CDC_ANC2_LPF_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_ANC1_LPF_B2_CTL (0x207)
+#define TAPAN_A_CDC_ANC1_LPF_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_ANC2_LPF_B2_CTL (0x287)
+#define TAPAN_A_CDC_ANC2_LPF_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_ANC1_SPARE (0x209)
+#define TAPAN_A_CDC_ANC1_SPARE__POR (0x00)
+#define TAPAN_A_CDC_ANC2_SPARE (0x289)
+#define TAPAN_A_CDC_ANC2_SPARE__POR (0x00)
+#define TAPAN_A_CDC_ANC1_SMLPF_CTL (0x20A)
+#define TAPAN_A_CDC_ANC1_SMLPF_CTL__POR (0x00)
+#define TAPAN_A_CDC_ANC2_SMLPF_CTL (0x28A)
+#define TAPAN_A_CDC_ANC2_SMLPF_CTL__POR (0x00)
+#define TAPAN_A_CDC_ANC1_DCFLT_CTL (0x20B)
+#define TAPAN_A_CDC_ANC1_DCFLT_CTL__POR (0x00)
+#define TAPAN_A_CDC_ANC2_DCFLT_CTL (0x28B)
+#define TAPAN_A_CDC_ANC2_DCFLT_CTL__POR (0x00)
+#define TAPAN_A_CDC_ANC1_GAIN_CTL (0x20C)
+#define TAPAN_A_CDC_ANC1_GAIN_CTL__POR (0x00)
+#define TAPAN_A_CDC_ANC2_GAIN_CTL (0x28C)
+#define TAPAN_A_CDC_ANC2_GAIN_CTL__POR (0x00)
+#define TAPAN_A_CDC_ANC1_B2_CTL (0x20D)
+#define TAPAN_A_CDC_ANC1_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_ANC2_B2_CTL (0x28D)
+#define TAPAN_A_CDC_ANC2_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_TX1_VOL_CTL_TIMER (0x220)
+#define TAPAN_A_CDC_TX1_VOL_CTL_TIMER__POR (0x00)
+#define TAPAN_A_CDC_TX2_VOL_CTL_TIMER (0x228)
+#define TAPAN_A_CDC_TX2_VOL_CTL_TIMER__POR (0x00)
+#define TAPAN_A_CDC_TX3_VOL_CTL_TIMER (0x230)
+#define TAPAN_A_CDC_TX3_VOL_CTL_TIMER__POR (0x00)
+#define TAPAN_A_CDC_TX4_VOL_CTL_TIMER (0x238)
+#define TAPAN_A_CDC_TX4_VOL_CTL_TIMER__POR (0x00)
+#define TAPAN_A_CDC_TX1_VOL_CTL_GAIN (0x221)
+#define TAPAN_A_CDC_TX1_VOL_CTL_GAIN__POR (0x00)
+#define TAPAN_A_CDC_TX2_VOL_CTL_GAIN (0x229)
+#define TAPAN_A_CDC_TX2_VOL_CTL_GAIN__POR (0x00)
+#define TAPAN_A_CDC_TX3_VOL_CTL_GAIN (0x231)
+#define TAPAN_A_CDC_TX3_VOL_CTL_GAIN__POR (0x00)
+#define TAPAN_A_CDC_TX4_VOL_CTL_GAIN (0x239)
+#define TAPAN_A_CDC_TX4_VOL_CTL_GAIN__POR (0x00)
+#define TAPAN_A_CDC_TX1_VOL_CTL_CFG (0x222)
+#define TAPAN_A_CDC_TX1_VOL_CTL_CFG__POR (0x00)
+#define TAPAN_A_CDC_TX2_VOL_CTL_CFG (0x22A)
+#define TAPAN_A_CDC_TX2_VOL_CTL_CFG__POR (0x00)
+#define TAPAN_A_CDC_TX3_VOL_CTL_CFG (0x232)
+#define TAPAN_A_CDC_TX3_VOL_CTL_CFG__POR (0x00)
+#define TAPAN_A_CDC_TX4_VOL_CTL_CFG (0x23A)
+#define TAPAN_A_CDC_TX4_VOL_CTL_CFG__POR (0x00)
+#define TAPAN_A_CDC_TX1_MUX_CTL (0x223)
+#define TAPAN_A_CDC_TX1_MUX_CTL__POR (0x00)
+#define TAPAN_A_CDC_TX2_MUX_CTL (0x22B)
+#define TAPAN_A_CDC_TX2_MUX_CTL__POR (0x00)
+#define TAPAN_A_CDC_TX3_MUX_CTL (0x233)
+#define TAPAN_A_CDC_TX3_MUX_CTL__POR (0x00)
+#define TAPAN_A_CDC_TX4_MUX_CTL (0x23B)
+#define TAPAN_A_CDC_TX4_MUX_CTL__POR (0x00)
+#define TAPAN_A_CDC_TX1_CLK_FS_CTL (0x224)
+#define TAPAN_A_CDC_TX1_CLK_FS_CTL__POR (0x00)
+#define TAPAN_A_CDC_TX2_CLK_FS_CTL (0x22C)
+#define TAPAN_A_CDC_TX2_CLK_FS_CTL__POR (0x00)
+#define TAPAN_A_CDC_TX3_CLK_FS_CTL (0x234)
+#define TAPAN_A_CDC_TX3_CLK_FS_CTL__POR (0x00)
+#define TAPAN_A_CDC_TX4_CLK_FS_CTL (0x23C)
+#define TAPAN_A_CDC_TX4_CLK_FS_CTL__POR (0x00)
+#define TAPAN_A_CDC_TX1_DMIC_CTL (0x225)
+#define TAPAN_A_CDC_TX1_DMIC_CTL__POR (0x00)
+#define TAPAN_A_CDC_TX2_DMIC_CTL (0x22D)
+#define TAPAN_A_CDC_TX2_DMIC_CTL__POR (0x00)
+#define TAPAN_A_CDC_TX3_DMIC_CTL (0x235)
+#define TAPAN_A_CDC_TX3_DMIC_CTL__POR (0x00)
+#define TAPAN_A_CDC_TX4_DMIC_CTL (0x23D)
+#define TAPAN_A_CDC_TX4_DMIC_CTL__POR (0x00)
+#define TAPAN_A_CDC_DEBUG_B1_CTL (0x278)
+#define TAPAN_A_CDC_DEBUG_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_DEBUG_B2_CTL (0x279)
+#define TAPAN_A_CDC_DEBUG_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_DEBUG_B3_CTL (0x27A)
+#define TAPAN_A_CDC_DEBUG_B3_CTL__POR (0x00)
+#define TAPAN_A_CDC_DEBUG_B4_CTL (0x27B)
+#define TAPAN_A_CDC_DEBUG_B4_CTL__POR (0x00)
+#define TAPAN_A_CDC_DEBUG_B5_CTL (0x27C)
+#define TAPAN_A_CDC_DEBUG_B5_CTL__POR (0x00)
+#define TAPAN_A_CDC_DEBUG_B6_CTL (0x27D)
+#define TAPAN_A_CDC_DEBUG_B6_CTL__POR (0x00)
+#define TAPAN_A_CDC_DEBUG_B7_CTL (0x27E)
+#define TAPAN_A_CDC_DEBUG_B7_CTL__POR (0x00)
+#define TAPAN_A_CDC_SRC1_PDA_CFG (0x2A0)
+#define TAPAN_A_CDC_SRC1_PDA_CFG__POR (0x00)
+#define TAPAN_A_CDC_SRC2_PDA_CFG (0x2A8)
+#define TAPAN_A_CDC_SRC2_PDA_CFG__POR (0x00)
+#define TAPAN_A_CDC_SRC1_FS_CTL (0x2A1)
+#define TAPAN_A_CDC_SRC1_FS_CTL__POR (0x00)
+#define TAPAN_A_CDC_SRC2_FS_CTL (0x2A9)
+#define TAPAN_A_CDC_SRC2_FS_CTL__POR (0x00)
+#define TAPAN_A_CDC_RX1_B1_CTL (0x2B0)
+#define TAPAN_A_CDC_RX1_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_RX2_B1_CTL (0x2B8)
+#define TAPAN_A_CDC_RX2_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_RX3_B1_CTL (0x2C0)
+#define TAPAN_A_CDC_RX3_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_RX4_B1_CTL (0x2C8)
+#define TAPAN_A_CDC_RX4_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_RX1_B2_CTL (0x2B1)
+#define TAPAN_A_CDC_RX1_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_RX2_B2_CTL (0x2B9)
+#define TAPAN_A_CDC_RX2_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_RX3_B2_CTL (0x2C1)
+#define TAPAN_A_CDC_RX3_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_RX4_B2_CTL (0x2C9)
+#define TAPAN_A_CDC_RX4_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_RX1_B3_CTL (0x2B2)
+#define TAPAN_A_CDC_RX1_B3_CTL__POR (0x00)
+#define TAPAN_A_CDC_RX2_B3_CTL (0x2BA)
+#define TAPAN_A_CDC_RX2_B3_CTL__POR (0x00)
+#define TAPAN_A_CDC_RX3_B3_CTL (0x2C2)
+#define TAPAN_A_CDC_RX3_B3_CTL__POR (0x00)
+#define TAPAN_A_CDC_RX4_B3_CTL (0x2CA)
+#define TAPAN_A_CDC_RX4_B3_CTL__POR (0x00)
+#define TAPAN_A_CDC_RX1_B4_CTL (0x2B3)
+#define TAPAN_A_CDC_RX1_B4_CTL__POR (0x00)
+#define TAPAN_A_CDC_RX2_B4_CTL (0x2BB)
+#define TAPAN_A_CDC_RX2_B4_CTL__POR (0x00)
+#define TAPAN_A_CDC_RX3_B4_CTL (0x2C3)
+#define TAPAN_A_CDC_RX3_B4_CTL__POR (0x00)
+#define TAPAN_A_CDC_RX4_B4_CTL (0x2CB)
+#define TAPAN_A_CDC_RX4_B4_CTL__POR (0x00)
+#define TAPAN_A_CDC_RX1_B5_CTL (0x2B4)
+#define TAPAN_A_CDC_RX1_B5_CTL__POR (0x00)
+#define TAPAN_A_CDC_RX2_B5_CTL (0x2BC)
+#define TAPAN_A_CDC_RX2_B5_CTL__POR (0x00)
+#define TAPAN_A_CDC_RX3_B5_CTL (0x2C4)
+#define TAPAN_A_CDC_RX3_B5_CTL__POR (0x00)
+#define TAPAN_A_CDC_RX4_B5_CTL (0x2CC)
+#define TAPAN_A_CDC_RX4_B5_CTL__POR (0x00)
+#define TAPAN_A_CDC_RX1_B6_CTL (0x2B5)
+#define TAPAN_A_CDC_RX1_B6_CTL__POR (0x00)
+#define TAPAN_A_CDC_RX2_B6_CTL (0x2BD)
+#define TAPAN_A_CDC_RX2_B6_CTL__POR (0x00)
+#define TAPAN_A_CDC_RX3_B6_CTL (0x2C5)
+#define TAPAN_A_CDC_RX3_B6_CTL__POR (0x00)
+#define TAPAN_A_CDC_RX4_B6_CTL (0x2CD)
+#define TAPAN_A_CDC_RX4_B6_CTL__POR (0x00)
+#define TAPAN_A_CDC_RX1_VOL_CTL_B1_CTL (0x2B6)
+#define TAPAN_A_CDC_RX1_VOL_CTL_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_RX2_VOL_CTL_B1_CTL (0x2BE)
+#define TAPAN_A_CDC_RX2_VOL_CTL_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_RX3_VOL_CTL_B1_CTL (0x2C6)
+#define TAPAN_A_CDC_RX3_VOL_CTL_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_RX4_VOL_CTL_B1_CTL (0x2CE)
+#define TAPAN_A_CDC_RX4_VOL_CTL_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_RX1_VOL_CTL_B2_CTL (0x2B7)
+#define TAPAN_A_CDC_RX1_VOL_CTL_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_RX2_VOL_CTL_B2_CTL (0x2BF)
+#define TAPAN_A_CDC_RX2_VOL_CTL_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_RX3_VOL_CTL_B2_CTL (0x2C7)
+#define TAPAN_A_CDC_RX3_VOL_CTL_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_RX4_VOL_CTL_B2_CTL (0x2CF)
+#define TAPAN_A_CDC_RX4_VOL_CTL_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_CLK_ANC_RESET_CTL (0x300)
+#define TAPAN_A_CDC_CLK_ANC_RESET_CTL__POR (0x00)
+#define TAPAN_A_CDC_CLK_RX_RESET_CTL (0x301)
+#define TAPAN_A_CDC_CLK_RX_RESET_CTL__POR (0x00)
+#define TAPAN_A_CDC_CLK_TX_RESET_B1_CTL (0x302)
+#define TAPAN_A_CDC_CLK_TX_RESET_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_CLK_TX_RESET_B2_CTL (0x303)
+#define TAPAN_A_CDC_CLK_TX_RESET_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_CLK_DMIC_B1_CTL (0x304)
+#define TAPAN_A_CDC_CLK_DMIC_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_CLK_DMIC_B2_CTL (0x305)
+#define TAPAN_A_CDC_CLK_DMIC_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_CLK_I2S_CTL (0x306)
+#define TAPAN_A_CDC_CLK_I2S_CTL__POR (0x03)
+#define TAPAN_A_CDC_CLK_OTHR_RESET_B1_CTL (0x308)
+#define TAPAN_A_CDC_CLK_OTHR_RESET_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_CLK_OTHR_RESET_B2_CTL (0x309)
+#define TAPAN_A_CDC_CLK_OTHR_RESET_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_CLK_TX_CLK_EN_B1_CTL (0x30A)
+#define TAPAN_A_CDC_CLK_TX_CLK_EN_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_CLK_TX_CLK_EN_B2_CTL (0x30B)
+#define TAPAN_A_CDC_CLK_TX_CLK_EN_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_CLK_OTHR_CTL (0x30C)
+#define TAPAN_A_CDC_CLK_OTHR_CTL__POR (0x00)
+#define TAPAN_A_CDC_CLK_RDAC_CLK_EN_CTL (0x30D)
+#define TAPAN_A_CDC_CLK_RDAC_CLK_EN_CTL__POR (0x00)
+#define TAPAN_A_CDC_CLK_ANC_CLK_EN_CTL (0x30E)
+#define TAPAN_A_CDC_CLK_ANC_CLK_EN_CTL__POR (0x00)
+#define TAPAN_A_CDC_CLK_RX_B1_CTL (0x30F)
+#define TAPAN_A_CDC_CLK_RX_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_CLK_RX_B2_CTL (0x310)
+#define TAPAN_A_CDC_CLK_RX_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_CLK_MCLK_CTL (0x311)
+#define TAPAN_A_CDC_CLK_MCLK_CTL__POR (0x00)
+#define TAPAN_A_CDC_CLK_PDM_CTL (0x312)
+#define TAPAN_A_CDC_CLK_PDM_CTL__POR (0x00)
+#define TAPAN_A_CDC_CLK_SD_CTL (0x313)
+#define TAPAN_A_CDC_CLK_SD_CTL__POR (0x00)
+#define TAPAN_A_CDC_CLK_POWER_CTL (0x314)
+#define TAPAN_A_CDC_CLK_POWER_CTL__POR (0x03)
+#define TAPAN_A_CDC_CLSH_B1_CTL (0x320)
+#define TAPAN_A_CDC_CLSH_B1_CTL__POR (0x22)
+#define TAPAN_A_CDC_CLSH_B2_CTL (0x321)
+#define TAPAN_A_CDC_CLSH_B2_CTL__POR (0x35)
+#define TAPAN_A_CDC_CLSH_B3_CTL (0x322)
+#define TAPAN_A_CDC_CLSH_B3_CTL__POR (0x3B)
+#define TAPAN_A_CDC_CLSH_BUCK_NCP_VARS (0x323)
+#define TAPAN_A_CDC_CLSH_BUCK_NCP_VARS__POR (0x04)
+#define TAPAN_A_CDC_CLSH_IDLE_HPH_THSD (0x324)
+#define TAPAN_A_CDC_CLSH_IDLE_HPH_THSD__POR (0x12)
+#define TAPAN_A_CDC_CLSH_IDLE_EAR_THSD (0x325)
+#define TAPAN_A_CDC_CLSH_IDLE_EAR_THSD__POR (0x0C)
+#define TAPAN_A_CDC_CLSH_FCLKONLY_HPH_THSD (0x326)
+#define TAPAN_A_CDC_CLSH_FCLKONLY_HPH_THSD__POR (0x18)
+#define TAPAN_A_CDC_CLSH_FCLKONLY_EAR_THSD (0x327)
+#define TAPAN_A_CDC_CLSH_FCLKONLY_EAR_THSD__POR (0x23)
+#define TAPAN_A_CDC_CLSH_K_ADDR (0x328)
+#define TAPAN_A_CDC_CLSH_K_ADDR__POR (0x00)
+#define TAPAN_A_CDC_CLSH_K_DATA (0x329)
+#define TAPAN_A_CDC_CLSH_K_DATA__POR (0xA4)
+#define TAPAN_A_CDC_CLSH_I_PA_FACT_HPH_L (0x32A)
+#define TAPAN_A_CDC_CLSH_I_PA_FACT_HPH_L__POR (0xD7)
+#define TAPAN_A_CDC_CLSH_I_PA_FACT_HPH_U (0x32B)
+#define TAPAN_A_CDC_CLSH_I_PA_FACT_HPH_U__POR (0x05)
+#define TAPAN_A_CDC_CLSH_I_PA_FACT_EAR_L (0x32C)
+#define TAPAN_A_CDC_CLSH_I_PA_FACT_EAR_L__POR (0x60)
+#define TAPAN_A_CDC_CLSH_I_PA_FACT_EAR_U (0x32D)
+#define TAPAN_A_CDC_CLSH_I_PA_FACT_EAR_U__POR (0x09)
+#define TAPAN_A_CDC_CLSH_V_PA_HD_EAR (0x32E)
+#define TAPAN_A_CDC_CLSH_V_PA_HD_EAR__POR (0x0D)
+#define TAPAN_A_CDC_CLSH_V_PA_HD_HPH (0x32F)
+#define TAPAN_A_CDC_CLSH_V_PA_HD_HPH__POR (0x0D)
+#define TAPAN_A_CDC_CLSH_V_PA_MIN_EAR (0x330)
+#define TAPAN_A_CDC_CLSH_V_PA_MIN_EAR__POR (0x3A)
+#define TAPAN_A_CDC_CLSH_V_PA_MIN_HPH (0x331)
+#define TAPAN_A_CDC_CLSH_V_PA_MIN_HPH__POR (0x1D)
+#define TAPAN_A_CDC_IIR1_GAIN_B1_CTL (0x340)
+#define TAPAN_A_CDC_IIR1_GAIN_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_IIR2_GAIN_B1_CTL (0x350)
+#define TAPAN_A_CDC_IIR2_GAIN_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_IIR1_GAIN_B2_CTL (0x341)
+#define TAPAN_A_CDC_IIR1_GAIN_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_IIR2_GAIN_B2_CTL (0x351)
+#define TAPAN_A_CDC_IIR2_GAIN_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_IIR1_GAIN_B3_CTL (0x342)
+#define TAPAN_A_CDC_IIR1_GAIN_B3_CTL__POR (0x00)
+#define TAPAN_A_CDC_IIR2_GAIN_B3_CTL (0x352)
+#define TAPAN_A_CDC_IIR2_GAIN_B3_CTL__POR (0x00)
+#define TAPAN_A_CDC_IIR1_GAIN_B4_CTL (0x343)
+#define TAPAN_A_CDC_IIR1_GAIN_B4_CTL__POR (0x00)
+#define TAPAN_A_CDC_IIR2_GAIN_B4_CTL (0x353)
+#define TAPAN_A_CDC_IIR2_GAIN_B4_CTL__POR (0x00)
+#define TAPAN_A_CDC_IIR1_GAIN_B5_CTL (0x344)
+#define TAPAN_A_CDC_IIR1_GAIN_B5_CTL__POR (0x00)
+#define TAPAN_A_CDC_IIR2_GAIN_B5_CTL (0x354)
+#define TAPAN_A_CDC_IIR2_GAIN_B5_CTL__POR (0x00)
+#define TAPAN_A_CDC_IIR1_GAIN_B6_CTL (0x345)
+#define TAPAN_A_CDC_IIR1_GAIN_B6_CTL__POR (0x00)
+#define TAPAN_A_CDC_IIR2_GAIN_B6_CTL (0x355)
+#define TAPAN_A_CDC_IIR2_GAIN_B6_CTL__POR (0x00)
+#define TAPAN_A_CDC_IIR1_GAIN_B7_CTL (0x346)
+#define TAPAN_A_CDC_IIR1_GAIN_B7_CTL__POR (0x00)
+#define TAPAN_A_CDC_IIR2_GAIN_B7_CTL (0x356)
+#define TAPAN_A_CDC_IIR2_GAIN_B7_CTL__POR (0x00)
+#define TAPAN_A_CDC_IIR1_GAIN_B8_CTL (0x347)
+#define TAPAN_A_CDC_IIR1_GAIN_B8_CTL__POR (0x00)
+#define TAPAN_A_CDC_IIR2_GAIN_B8_CTL (0x357)
+#define TAPAN_A_CDC_IIR2_GAIN_B8_CTL__POR (0x00)
+#define TAPAN_A_CDC_IIR1_CTL (0x348)
+#define TAPAN_A_CDC_IIR1_CTL__POR (0x00)
+#define TAPAN_A_CDC_IIR2_CTL (0x358)
+#define TAPAN_A_CDC_IIR2_CTL__POR (0x00)
+#define TAPAN_A_CDC_IIR1_GAIN_TIMER_CTL (0x349)
+#define TAPAN_A_CDC_IIR1_GAIN_TIMER_CTL__POR (0x00)
+#define TAPAN_A_CDC_IIR2_GAIN_TIMER_CTL (0x359)
+#define TAPAN_A_CDC_IIR2_GAIN_TIMER_CTL__POR (0x00)
+#define TAPAN_A_CDC_IIR1_COEF_B1_CTL (0x34A)
+#define TAPAN_A_CDC_IIR1_COEF_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_IIR2_COEF_B1_CTL (0x35A)
+#define TAPAN_A_CDC_IIR2_COEF_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_IIR1_COEF_B2_CTL (0x34B)
+#define TAPAN_A_CDC_IIR1_COEF_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_IIR2_COEF_B2_CTL (0x35B)
+#define TAPAN_A_CDC_IIR2_COEF_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_TOP_GAIN_UPDATE (0x360)
+#define TAPAN_A_CDC_TOP_GAIN_UPDATE__POR (0x00)
+#define TAPAN_A_CDC_COMP0_B1_CTL (0x368)
+#define TAPAN_A_CDC_COMP0_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_COMP1_B1_CTL (0x370)
+#define TAPAN_A_CDC_COMP1_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_COMP2_B1_CTL (0x378)
+#define TAPAN_A_CDC_COMP2_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_COMP0_B2_CTL (0x369)
+#define TAPAN_A_CDC_COMP0_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_COMP1_B2_CTL (0x371)
+#define TAPAN_A_CDC_COMP1_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_COMP2_B2_CTL (0x379)
+#define TAPAN_A_CDC_COMP2_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_COMP0_B3_CTL (0x36A)
+#define TAPAN_A_CDC_COMP0_B3_CTL__POR (0x00)
+#define TAPAN_A_CDC_COMP1_B3_CTL (0x372)
+#define TAPAN_A_CDC_COMP1_B3_CTL__POR (0x00)
+#define TAPAN_A_CDC_COMP2_B3_CTL (0x37A)
+#define TAPAN_A_CDC_COMP2_B3_CTL__POR (0x00)
+#define TAPAN_A_CDC_COMP0_B4_CTL (0x36B)
+#define TAPAN_A_CDC_COMP0_B4_CTL__POR (0x00)
+#define TAPAN_A_CDC_COMP1_B4_CTL (0x373)
+#define TAPAN_A_CDC_COMP1_B4_CTL__POR (0x00)
+#define TAPAN_A_CDC_COMP2_B4_CTL (0x37B)
+#define TAPAN_A_CDC_COMP2_B4_CTL__POR (0x00)
+#define TAPAN_A_CDC_COMP0_B5_CTL (0x36C)
+#define TAPAN_A_CDC_COMP0_B5_CTL__POR (0x00)
+#define TAPAN_A_CDC_COMP1_B5_CTL (0x374)
+#define TAPAN_A_CDC_COMP1_B5_CTL__POR (0x00)
+#define TAPAN_A_CDC_COMP2_B5_CTL (0x37C)
+#define TAPAN_A_CDC_COMP2_B5_CTL__POR (0x00)
+#define TAPAN_A_CDC_COMP0_B6_CTL (0x36D)
+#define TAPAN_A_CDC_COMP0_B6_CTL__POR (0x00)
+#define TAPAN_A_CDC_COMP1_B6_CTL (0x375)
+#define TAPAN_A_CDC_COMP1_B6_CTL__POR (0x00)
+#define TAPAN_A_CDC_COMP2_B6_CTL (0x37D)
+#define TAPAN_A_CDC_COMP2_B6_CTL__POR (0x00)
+#define TAPAN_A_CDC_COMP0_SHUT_DOWN_STATUS (0x36E)
+#define TAPAN_A_CDC_COMP0_SHUT_DOWN_STATUS__POR (0x00)
+#define TAPAN_A_CDC_COMP1_SHUT_DOWN_STATUS (0x376)
+#define TAPAN_A_CDC_COMP1_SHUT_DOWN_STATUS__POR (0x00)
+#define TAPAN_A_CDC_COMP2_SHUT_DOWN_STATUS (0x37E)
+#define TAPAN_A_CDC_COMP2_SHUT_DOWN_STATUS__POR (0x00)
+#define TAPAN_A_CDC_COMP0_FS_CFG (0x36F)
+#define TAPAN_A_CDC_COMP0_FS_CFG__POR (0x00)
+#define TAPAN_A_CDC_COMP1_FS_CFG (0x377)
+#define TAPAN_A_CDC_COMP1_FS_CFG__POR (0x00)
+#define TAPAN_A_CDC_COMP2_FS_CFG (0x37F)
+#define TAPAN_A_CDC_COMP2_FS_CFG__POR (0x00)
+#define TAPAN_A_CDC_CONN_RX1_B1_CTL (0x380)
+#define TAPAN_A_CDC_CONN_RX1_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_RX1_B2_CTL (0x381)
+#define TAPAN_A_CDC_CONN_RX1_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_RX1_B3_CTL (0x382)
+#define TAPAN_A_CDC_CONN_RX1_B3_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_RX2_B1_CTL (0x383)
+#define TAPAN_A_CDC_CONN_RX2_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_RX2_B2_CTL (0x384)
+#define TAPAN_A_CDC_CONN_RX2_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_RX2_B3_CTL (0x385)
+#define TAPAN_A_CDC_CONN_RX2_B3_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_RX3_B1_CTL (0x386)
+#define TAPAN_A_CDC_CONN_RX3_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_RX3_B2_CTL (0x387)
+#define TAPAN_A_CDC_CONN_RX3_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_RX4_B1_CTL (0x388)
+#define TAPAN_A_CDC_CONN_RX4_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_RX4_B2_CTL (0x389)
+#define TAPAN_A_CDC_CONN_RX4_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_RX4_B3_CTL (0x38A)
+#define TAPAN_A_CDC_CONN_RX4_B3_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_ANC_B1_CTL (0x391)
+#define TAPAN_A_CDC_CONN_ANC_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_ANC_B2_CTL (0x392)
+#define TAPAN_A_CDC_CONN_ANC_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_TX_B1_CTL (0x393)
+#define TAPAN_A_CDC_CONN_TX_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_TX_B2_CTL (0x394)
+#define TAPAN_A_CDC_CONN_TX_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_TX_B3_CTL (0x395)
+#define TAPAN_A_CDC_CONN_TX_B3_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_TX_B4_CTL (0x396)
+#define TAPAN_A_CDC_CONN_TX_B4_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_EQ1_B1_CTL (0x397)
+#define TAPAN_A_CDC_CONN_EQ1_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_EQ1_B2_CTL (0x398)
+#define TAPAN_A_CDC_CONN_EQ1_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_EQ1_B3_CTL (0x399)
+#define TAPAN_A_CDC_CONN_EQ1_B3_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_EQ1_B4_CTL (0x39A)
+#define TAPAN_A_CDC_CONN_EQ1_B4_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_EQ2_B1_CTL (0x39B)
+#define TAPAN_A_CDC_CONN_EQ2_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_EQ2_B2_CTL (0x39C)
+#define TAPAN_A_CDC_CONN_EQ2_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_EQ2_B3_CTL (0x39D)
+#define TAPAN_A_CDC_CONN_EQ2_B3_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_EQ2_B4_CTL (0x39E)
+#define TAPAN_A_CDC_CONN_EQ2_B4_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_SRC1_B1_CTL (0x39F)
+#define TAPAN_A_CDC_CONN_SRC1_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_SRC1_B2_CTL (0x3A0)
+#define TAPAN_A_CDC_CONN_SRC1_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_SRC2_B1_CTL (0x3A1)
+#define TAPAN_A_CDC_CONN_SRC2_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_SRC2_B2_CTL (0x3A2)
+#define TAPAN_A_CDC_CONN_SRC2_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_TX_SB_B1_CTL (0x3A3)
+#define TAPAN_A_CDC_CONN_TX_SB_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_TX_SB_B2_CTL (0x3A4)
+#define TAPAN_A_CDC_CONN_TX_SB_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_TX_SB_B3_CTL (0x3A5)
+#define TAPAN_A_CDC_CONN_TX_SB_B3_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_TX_SB_B4_CTL (0x3A6)
+#define TAPAN_A_CDC_CONN_TX_SB_B4_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_TX_SB_B5_CTL (0x3A7)
+#define TAPAN_A_CDC_CONN_TX_SB_B5_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_TX_SB_B11_CTL (0x3AD)
+#define TAPAN_A_CDC_CONN_TX_SB_B11_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_RX_SB_B1_CTL (0x3AE)
+#define TAPAN_A_CDC_CONN_RX_SB_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_RX_SB_B2_CTL (0x3AF)
+#define TAPAN_A_CDC_CONN_RX_SB_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_CLSH_CTL (0x3B0)
+#define TAPAN_A_CDC_CONN_CLSH_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_MISC (0x3B1)
+#define TAPAN_A_CDC_CONN_MISC__POR (0x01)
+#define TAPAN_A_CDC_MBHC_EN_CTL (0x3C0)
+#define TAPAN_A_CDC_MBHC_EN_CTL__POR (0x00)
+#define TAPAN_A_CDC_MBHC_FIR_B1_CFG (0x3C1)
+#define TAPAN_A_CDC_MBHC_FIR_B1_CFG__POR (0x00)
+#define TAPAN_A_CDC_MBHC_FIR_B2_CFG (0x3C2)
+#define TAPAN_A_CDC_MBHC_FIR_B2_CFG__POR (0x06)
+#define TAPAN_A_CDC_MBHC_TIMER_B1_CTL (0x3C3)
+#define TAPAN_A_CDC_MBHC_TIMER_B1_CTL__POR (0x03)
+#define TAPAN_A_CDC_MBHC_TIMER_B2_CTL (0x3C4)
+#define TAPAN_A_CDC_MBHC_TIMER_B2_CTL__POR (0x09)
+#define TAPAN_A_CDC_MBHC_TIMER_B3_CTL (0x3C5)
+#define TAPAN_A_CDC_MBHC_TIMER_B3_CTL__POR (0x1E)
+#define TAPAN_A_CDC_MBHC_TIMER_B4_CTL (0x3C6)
+#define TAPAN_A_CDC_MBHC_TIMER_B4_CTL__POR (0x45)
+#define TAPAN_A_CDC_MBHC_TIMER_B5_CTL (0x3C7)
+#define TAPAN_A_CDC_MBHC_TIMER_B5_CTL__POR (0x04)
+#define TAPAN_A_CDC_MBHC_TIMER_B6_CTL (0x3C8)
+#define TAPAN_A_CDC_MBHC_TIMER_B6_CTL__POR (0x78)
+#define TAPAN_A_CDC_MBHC_B1_STATUS (0x3C9)
+#define TAPAN_A_CDC_MBHC_B1_STATUS__POR (0x00)
+#define TAPAN_A_CDC_MBHC_B2_STATUS (0x3CA)
+#define TAPAN_A_CDC_MBHC_B2_STATUS__POR (0x00)
+#define TAPAN_A_CDC_MBHC_B3_STATUS (0x3CB)
+#define TAPAN_A_CDC_MBHC_B3_STATUS__POR (0x00)
+#define TAPAN_A_CDC_MBHC_B4_STATUS (0x3CC)
+#define TAPAN_A_CDC_MBHC_B4_STATUS__POR (0x00)
+#define TAPAN_A_CDC_MBHC_B5_STATUS (0x3CD)
+#define TAPAN_A_CDC_MBHC_B5_STATUS__POR (0x00)
+#define TAPAN_A_CDC_MBHC_B1_CTL (0x3CE)
+#define TAPAN_A_CDC_MBHC_B1_CTL__POR (0xC0)
+#define TAPAN_A_CDC_MBHC_B2_CTL (0x3CF)
+#define TAPAN_A_CDC_MBHC_B2_CTL__POR (0x5D)
+#define TAPAN_A_CDC_MBHC_VOLT_B1_CTL (0x3D0)
+#define TAPAN_A_CDC_MBHC_VOLT_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_MBHC_VOLT_B2_CTL (0x3D1)
+#define TAPAN_A_CDC_MBHC_VOLT_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_MBHC_VOLT_B3_CTL (0x3D2)
+#define TAPAN_A_CDC_MBHC_VOLT_B3_CTL__POR (0x00)
+#define TAPAN_A_CDC_MBHC_VOLT_B4_CTL (0x3D3)
+#define TAPAN_A_CDC_MBHC_VOLT_B4_CTL__POR (0x00)
+#define TAPAN_A_CDC_MBHC_VOLT_B5_CTL (0x3D4)
+#define TAPAN_A_CDC_MBHC_VOLT_B5_CTL__POR (0x00)
+#define TAPAN_A_CDC_MBHC_VOLT_B6_CTL (0x3D5)
+#define TAPAN_A_CDC_MBHC_VOLT_B6_CTL__POR (0x00)
+#define TAPAN_A_CDC_MBHC_VOLT_B7_CTL (0x3D6)
+#define TAPAN_A_CDC_MBHC_VOLT_B7_CTL__POR (0xFF)
+#define TAPAN_A_CDC_MBHC_VOLT_B8_CTL (0x3D7)
+#define TAPAN_A_CDC_MBHC_VOLT_B8_CTL__POR (0x07)
+#define TAPAN_A_CDC_MBHC_VOLT_B9_CTL (0x3D8)
+#define TAPAN_A_CDC_MBHC_VOLT_B9_CTL__POR (0xFF)
+#define TAPAN_A_CDC_MBHC_VOLT_B10_CTL (0x3D9)
+#define TAPAN_A_CDC_MBHC_VOLT_B10_CTL__POR (0x7F)
+#define TAPAN_A_CDC_MBHC_VOLT_B11_CTL (0x3DA)
+#define TAPAN_A_CDC_MBHC_VOLT_B11_CTL__POR (0x00)
+#define TAPAN_A_CDC_MBHC_VOLT_B12_CTL (0x3DB)
+#define TAPAN_A_CDC_MBHC_VOLT_B12_CTL__POR (0x80)
+#define TAPAN_A_CDC_MBHC_CLK_CTL (0x3DC)
+#define TAPAN_A_CDC_MBHC_CLK_CTL__POR (0x00)
+#define TAPAN_A_CDC_MBHC_INT_CTL (0x3DD)
+#define TAPAN_A_CDC_MBHC_INT_CTL__POR (0x00)
+#define TAPAN_A_CDC_MBHC_DEBUG_CTL (0x3DE)
+#define TAPAN_A_CDC_MBHC_DEBUG_CTL__POR (0x00)
+#define TAPAN_A_CDC_MBHC_SPARE (0x3DF)
+#define TAPAN_A_CDC_MBHC_SPARE__POR (0x00)
+
+
+/* SLIMBUS Slave Registers */
+#define TAPAN_SLIM_PGD_PORT_INT_EN0 (0x30)
+#define TAPAN_SLIM_PGD_PORT_INT_STATUS0 (0x34)
+#define TAPAN_SLIM_PGD_PORT_INT_CLR0 (0x38)
+#define TAPAN_SLIM_PGD_PORT_INT_SOURCE0 (0x60)
+
+/* Macros for Packing Register Writes into a U32 */
+#define TAPAN_PACKED_REG_SIZE sizeof(u32)
+
+#define TAPAN_CODEC_PACK_ENTRY(reg, mask, val) ((val & 0xff)|\
+ ((mask & 0xff) << 8)|((reg & 0xffff) << 16))
+
+#define TAPAN_CODEC_UNPACK_ENTRY(packed, reg, mask, val) \
+ do { \
+ ((reg) = ((packed >> 16) & (0xffff))); \
+ ((mask) = ((packed >> 8) & (0xff))); \
+ ((val) = ((packed) & (0xff))); \
+ } while (0);
+
+#endif
diff --git a/include/linux/mmc/core.h b/include/linux/mmc/core.h
index 83cc723..ea48688 100644
--- a/include/linux/mmc/core.h
+++ b/include/linux/mmc/core.h
@@ -96,6 +96,8 @@
*/
unsigned int cmd_timeout_ms; /* in milliseconds */
+ /* Set this flag only for blocking bkops request */
+ bool bkops_busy;
struct mmc_data *data; /* data segment associated with cmd */
struct mmc_request *mrq; /* associated request */
@@ -153,7 +155,8 @@
extern void mmc_start_delayed_bkops(struct mmc_card *card);
extern void mmc_start_idle_time_bkops(struct work_struct *work);
extern void mmc_bkops_completion_polling(struct work_struct *work);
-extern int __mmc_switch(struct mmc_card *, u8, u8, u8, unsigned int, bool);
+extern int __mmc_switch(struct mmc_card *, u8, u8, u8, unsigned int, bool,
+ bool);
extern int mmc_switch(struct mmc_card *, u8, u8, u8, unsigned int);
extern int mmc_send_ext_csd(struct mmc_card *card, u8 *ext_csd);
diff --git a/include/linux/msm_mdp.h b/include/linux/msm_mdp.h
index abd4f3a..7e67db0 100644
--- a/include/linux/msm_mdp.h
+++ b/include/linux/msm_mdp.h
@@ -145,6 +145,7 @@
#define MDP_DITHER 0x8
#define MDP_BLUR 0x10
#define MDP_BLEND_FG_PREMULT 0x20000
+#define MDP_IS_FG 0x40000
#define MDP_DEINTERLACE 0x80000000
#define MDP_SHARPENING 0x40000000
#define MDP_NO_DMA_BARRIER_START 0x20000000
@@ -298,6 +299,7 @@
#define MDP_OVERLAY_PP_CSC_CFG 0x1
#define MDP_OVERLAY_PP_QSEED_CFG 0x2
+#define MDP_OVERLAY_PP_PA_CFG 0x4
#define MDP_CSC_FLAG_ENABLE 0x1
#define MDP_CSC_FLAG_YUV_IN 0x2
@@ -318,10 +320,19 @@
struct mdp_csc_cfg csc_data;
};
+struct mdp_pa_cfg {
+ uint32_t flags;
+ uint32_t hue_adj;
+ uint32_t sat_adj;
+ uint32_t val_adj;
+ uint32_t cont_adj;
+};
+
struct mdp_overlay_pp_params {
uint32_t config_ops;
struct mdp_csc_cfg csc_cfg;
struct mdp_qseed_cfg qseed_cfg[2];
+ struct mdp_pa_cfg pa_cfg;
};
struct mdp_overlay {
@@ -486,11 +497,7 @@
struct mdp_pa_cfg_data {
uint32_t block;
- uint32_t flags;
- uint32_t hue_adj;
- uint32_t sat_adj;
- uint32_t val_adj;
- uint32_t cont_adj;
+ struct mdp_pa_cfg pa_data;
};
struct mdp_dither_cfg_data {
@@ -511,6 +518,12 @@
uint16_t *b_tbl[MDP_GAMUT_TABLE_NUM];
};
+struct mdp_calib_config_data {
+ uint32_t ops;
+ uint32_t addr;
+ uint32_t data;
+};
+
enum {
mdp_op_pcc_cfg,
mdp_op_csc_cfg,
@@ -520,6 +533,7 @@
mdp_op_pa_cfg,
mdp_op_dither_cfg,
mdp_op_gamut_cfg,
+ mdp_op_calib_cfg,
mdp_op_max,
};
@@ -534,6 +548,7 @@
struct mdp_pa_cfg_data pa_cfg_data;
struct mdp_dither_cfg_data dither_cfg_data;
struct mdp_gamut_cfg_data gamut_cfg_data;
+ struct mdp_calib_config_data calib_cfg;
} data;
};
diff --git a/include/linux/msm_vidc_dec.h b/include/linux/msm_vidc_dec.h
index 3c99562..cc864f0 100644
--- a/include/linux/msm_vidc_dec.h
+++ b/include/linux/msm_vidc_dec.h
@@ -78,6 +78,7 @@
#define VDEC_EXTRADATA_EXT_DATA 0x0800
#define VDEC_EXTRADATA_USER_DATA 0x1000
+#define VDEC_EXTRADATA_EXT_BUFFER 0x2000
#define VDEC_CMDBASE 0x800
#define VDEC_CMD_SET_INTF_VERSION (VDEC_CMDBASE)
@@ -213,6 +214,12 @@
#define VDEC_IOCTL_SET_PERF_CLK \
_IOR(VDEC_IOCTL_MAGIC, 38, struct vdec_ioctl_msg)
+#define VDEC_IOCTL_SET_META_BUFFERS \
+ _IOW(VDEC_IOCTL_MAGIC, 39, struct vdec_ioctl_msg)
+
+#define VDEC_IOCTL_FREE_META_BUFFERS \
+ _IO(VDEC_IOCTL_MAGIC, 40)
+
enum vdec_picture {
PICTURE_TYPE_I,
PICTURE_TYPE_P,
@@ -236,6 +243,7 @@
size_t buffer_size;
uint32_t alignment;
uint32_t buf_poolid;
+ size_t meta_buffer_size;
};
struct vdec_bufferpayload {
@@ -526,6 +534,11 @@
uint32_t par_height;
};
+struct vdec_sep_metadatainfo {
+ void __user *metabufaddr;
+ uint32_t size;
+};
+
struct vdec_output_frameinfo {
void __user *bufferaddr;
size_t offset;
@@ -538,6 +551,7 @@
struct vdec_framesize framesize;
enum vdec_interlaced_format interlaced_format;
struct vdec_aspectratioinfo aspect_ratio_info;
+ struct vdec_sep_metadatainfo metadata_info;
};
union vdec_msgdata {
@@ -571,4 +585,12 @@
int alignment;
};
+struct vdec_meta_buffers {
+ size_t size;
+ int count;
+ int pmem_fd;
+ int pmem_fd_iommu;
+ int offset;
+};
+
#endif /* end of macro _VDECDECODER_H_ */
diff --git a/include/media/msm/vcd_api.h b/include/media/msm/vcd_api.h
index 7104028..e668544 100644
--- a/include/media/msm/vcd_api.h
+++ b/include/media/msm/vcd_api.h
@@ -100,6 +100,7 @@
size_t sz;
u32 align;
u32 buf_pool_id;
+ size_t meta_buffer_size;
};
struct vcd_init_config {
diff --git a/include/media/msm/vcd_property.h b/include/media/msm/vcd_property.h
index ed9bffb..85b28e2 100644
--- a/include/media/msm/vcd_property.h
+++ b/include/media/msm/vcd_property.h
@@ -64,6 +64,8 @@
#define VCD_I_LTR_USE (VCD_START_BASE + 0x30)
#define VCD_I_CAPABILITY_LTR_COUNT (VCD_START_BASE + 0x31)
#define VCD_I_LTR_MARK (VCD_START_BASE + 0x32)
+#define VCD_I_SET_EXT_METABUFFER (VCD_START_BASE + 0x33)
+#define VCD_I_FREE_EXT_METABUFFER (VCD_START_BASE + 0x34)
#define VCD_START_REQ (VCD_START_BASE + 0x1000)
#define VCD_I_REQ_IFRAME (VCD_START_REQ + 0x1)
@@ -122,8 +124,10 @@
#define VCD_METADATA_PASSTHROUGH 0x080
#define VCD_METADATA_ENC_SLICE 0x100
#define VCD_METADATA_LTR_INFO 0x200
+
#define VCD_METADATA_EXT_DATA 0x0800
#define VCD_METADATA_USER_DATA 0x1000
+#define VCD_METADATA_SEPARATE_BUF 0x2000
struct vcd_property_meta_data_enable {
@@ -425,4 +429,19 @@
u32 ltr_frames;
};
+struct vcd_property_meta_buffer {
+ u8 *kernel_virtual_addr;
+ u8 *physical_addr;
+ u32 size;
+ u32 count;
+ int pmem_fd;
+ u32 offset;
+ u8 *dev_addr;
+ void *client_data;
+ u8 *kernel_virt_addr_iommu;
+ u8 *physical_addr_iommu;
+ int pmem_fd_iommu;
+ u8 *dev_addr_iommu;
+ void *client_data_iommu;
+};
#endif
diff --git a/include/media/msm/vidc_init.h b/include/media/msm/vidc_init.h
index f7d4e58..aff231d 100644
--- a/include/media/msm/vidc_init.h
+++ b/include/media/msm/vidc_init.h
@@ -19,6 +19,7 @@
#define VIDC_MAX_NUM_CLIENTS 4
#define MAX_VIDEO_NUM_OF_BUFF 100
+#define MAX_META_BUFFERS 32
enum buffer_dir {
BUFFER_TYPE_INPUT,
@@ -37,6 +38,11 @@
void *client_data;
};
+struct meta_buffer_addr_table {
+ u8 *kernel_vir_addr;
+ u8 *kernel_vir_addr_iommu;
+};
+
struct video_client_ctx {
void *vcd_handle;
u32 num_of_input_buffers;
@@ -49,17 +55,22 @@
wait_queue_head_t msg_wait;
struct completion event;
struct vcd_property_h264_mv_buffer vcd_h264_mv_buffer;
+ struct vcd_property_meta_buffer vcd_meta_buffer;
struct vcd_property_enc_recon_buffer recon_buffer[4];
u32 event_status;
u32 seq_header_set;
u32 stop_msg;
u32 stop_called;
u32 stop_sync_cb;
+ size_t meta_buf_size;
struct ion_client *user_ion_client;
struct ion_handle *seq_hdr_ion_handle;
struct ion_handle *h264_mv_ion_handle;
struct ion_handle *recon_buffer_ion_handle[4];
+ struct ion_handle *meta_buffer_ion_handle;
+ struct ion_handle *meta_buffer_iommu_ion_handle;
u32 dmx_disable;
+ struct meta_buffer_addr_table meta_addr_table[MAX_META_BUFFERS];
};
void __iomem *vidc_get_ioaddr(void);
diff --git a/net/bluetooth/hci_conn.c b/net/bluetooth/hci_conn.c
index 0704394..fb85c02 100644
--- a/net/bluetooth/hci_conn.c
+++ b/net/bluetooth/hci_conn.c
@@ -1409,8 +1409,24 @@
hci_dev_lock_bh(hdev);
conn = hci_conn_hash_lookup_ba(hdev, ACL_LINK, &req.bdaddr);
- if (conn)
+ if (conn) {
conn->auth_type = req.type;
+ switch (conn->auth_type) {
+ case HCI_AT_NO_BONDING:
+ conn->pending_sec_level = BT_SECURITY_LOW;
+ break;
+ case HCI_AT_DEDICATED_BONDING:
+ case HCI_AT_GENERAL_BONDING:
+ conn->pending_sec_level = BT_SECURITY_MEDIUM;
+ break;
+ case HCI_AT_DEDICATED_BONDING_MITM:
+ case HCI_AT_GENERAL_BONDING_MITM:
+ conn->pending_sec_level = BT_SECURITY_HIGH;
+ break;
+ default:
+ break;
+ }
+ }
hci_dev_unlock_bh(hdev);
if (!conn)
diff --git a/net/bluetooth/hci_event.c b/net/bluetooth/hci_event.c
index 3b59e4e..15d3585 100644
--- a/net/bluetooth/hci_event.c
+++ b/net/bluetooth/hci_event.c
@@ -1,6 +1,6 @@
/*
BlueZ - Bluetooth protocol stack for Linux
- Copyright (c) 2000-2001, 2010-2012, Code Aurora Forum. All rights reserved.
+ Copyright (c) 2000-2001, 2010-2012 The Linux Foundation. All rights reserved.
Written 2000,2001 by Maxim Krasnyansky <maxk@qualcomm.com>
@@ -2669,12 +2669,6 @@
BT_DBG("Conn pending sec level is %d, ssp is %d, key len is %d",
conn->pending_sec_level, conn->ssp_mode, key->pin_len);
}
- if (conn && (conn->ssp_mode == 0) &&
- (conn->pending_sec_level == BT_SECURITY_HIGH) &&
- (key->pin_len != 16)) {
- BT_DBG("Security is high ignoring this key");
- goto not_found;
- }
if (key->key_type == 0x04 && conn && conn->auth_type != 0xff &&
(conn->auth_type & 0x01)) {
diff --git a/net/bluetooth/mgmt.c b/net/bluetooth/mgmt.c
index 8568dae7..1cd09f9 100644
--- a/net/bluetooth/mgmt.c
+++ b/net/bluetooth/mgmt.c
@@ -1758,7 +1758,7 @@
return;
}
- if (status)
+ if (status || conn->pending_sec_level < BT_SECURITY_MEDIUM)
pairing_complete(cmd, status);
hci_conn_put(conn);
diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index 1b46499..df34213 100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -295,6 +295,9 @@
config SND_SOC_WCD9320
tristate
+config SND_SOC_WCD9306
+ tristate
+
config SND_SOC_WL1273
tristate
diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
index 42121fe..11338aa 100644
--- a/sound/soc/codecs/Makefile
+++ b/sound/soc/codecs/Makefile
@@ -52,6 +52,7 @@
snd-soc-wcd9310-objs := wcd9310.o wcd9310-tables.o
snd-soc-cs8427-objs := cs8427.o
snd-soc-wcd9320-objs := wcd9xxx-resmgr.o wcd9320.o wcd9320-tables.o wcd9xxx-mbhc.o
+snd-soc-wcd9306-objs := wcd9xxx-resmgr.o wcd9306.o wcd9306-tables.o wcd9xxx-mbhc.o
snd-soc-wl1273-objs := wl1273.o
snd-soc-wm1250-ev1-objs := wm1250-ev1.o
snd-soc-wm2000-objs := wm2000.o
@@ -162,6 +163,7 @@
obj-$(CONFIG_SND_SOC_WCD9310) += snd-soc-wcd9310.o
obj-$(CONFIG_SND_SOC_CS8427) += snd-soc-cs8427.o
obj-$(CONFIG_SND_SOC_WCD9320) += snd-soc-wcd9320.o
+obj-$(CONFIG_SND_SOC_WCD9306) += snd-soc-wcd9306.o
obj-$(CONFIG_SND_SOC_WL1273) += snd-soc-wl1273.o
obj-$(CONFIG_SND_SOC_WM1250_EV1) += snd-soc-wm1250-ev1.o
obj-$(CONFIG_SND_SOC_WM2000) += snd-soc-wm2000.o
diff --git a/sound/soc/codecs/wcd9306-tables.c b/sound/soc/codecs/wcd9306-tables.c
new file mode 100644
index 0000000..21c5636
--- /dev/null
+++ b/sound/soc/codecs/wcd9306-tables.c
@@ -0,0 +1,1015 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+*
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License version 2 and
+* only version 2 as published by the Free Software Foundation.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*/
+
+#include <linux/mfd/wcd9xxx/wcd9306_registers.h>
+#include "wcd9306.h"
+
+const u8 tapan_reg_readable[TAPAN_CACHE_SIZE] = {
+ [TAPAN_A_CHIP_CTL] = 1,
+ [TAPAN_A_CHIP_STATUS] = 1,
+ [TAPAN_A_CHIP_ID_BYTE_0] = 1,
+ [TAPAN_A_CHIP_ID_BYTE_1] = 1,
+ [TAPAN_A_CHIP_ID_BYTE_2] = 1,
+ [TAPAN_A_CHIP_ID_BYTE_3] = 1,
+ [TAPAN_A_CHIP_VERSION] = 1,
+ [TAPAN_A_CHIP_DEBUG_CTL] = 1,
+ [TAPAN_A_SLAVE_ID_1] = 1,
+ [TAPAN_A_SLAVE_ID_2] = 1,
+ [TAPAN_A_SLAVE_ID_3] = 1,
+ [TAPAN_A_PIN_CTL_OE0] = 1,
+ [TAPAN_A_PIN_CTL_DATA0] = 1,
+ [TAPAN_A_HDRIVE_GENERIC] = 1,
+ [TAPAN_A_HDRIVE_OVERRIDE] = 1,
+ [TAPAN_A_ANA_CSR_WAIT_STATE] = 1,
+ [TAPAN_A_PROCESS_MONITOR_CTL0] = 1,
+ [TAPAN_A_PROCESS_MONITOR_CTL1] = 1,
+ [TAPAN_A_PROCESS_MONITOR_CTL2] = 1,
+ [TAPAN_A_PROCESS_MONITOR_CTL3] = 1,
+ [TAPAN_A_QFUSE_CTL] = 1,
+ [TAPAN_A_QFUSE_STATUS] = 1,
+ [TAPAN_A_QFUSE_DATA_OUT0] = 1,
+ [TAPAN_A_QFUSE_DATA_OUT1] = 1,
+ [TAPAN_A_QFUSE_DATA_OUT2] = 1,
+ [TAPAN_A_QFUSE_DATA_OUT3] = 1,
+ [TAPAN_A_QFUSE_DATA_OUT4] = 1,
+ [TAPAN_A_QFUSE_DATA_OUT5] = 1,
+ [TAPAN_A_QFUSE_DATA_OUT6] = 1,
+ [TAPAN_A_QFUSE_DATA_OUT7] = 1,
+ [TAPAN_A_CDC_CTL] = 1,
+ [TAPAN_A_LEAKAGE_CTL] = 1,
+ [TAPAN_A_INTR_MODE] = 1,
+ [TAPAN_A_INTR_MASK0] = 1,
+ [TAPAN_A_INTR_MASK1] = 1,
+ [TAPAN_A_INTR_MASK2] = 1,
+ [TAPAN_A_INTR_MASK3] = 1,
+ [TAPAN_A_INTR_STATUS0] = 1,
+ [TAPAN_A_INTR_STATUS1] = 1,
+ [TAPAN_A_INTR_STATUS2] = 1,
+ [TAPAN_A_INTR_STATUS3] = 1,
+ [TAPAN_A_INTR_CLEAR0] = 0,
+ [TAPAN_A_INTR_CLEAR1] = 0,
+ [TAPAN_A_INTR_CLEAR2] = 0,
+ [TAPAN_A_INTR_CLEAR3] = 0,
+ [TAPAN_A_INTR_LEVEL0] = 1,
+ [TAPAN_A_INTR_LEVEL1] = 1,
+ [TAPAN_A_INTR_LEVEL2] = 1,
+ [TAPAN_A_INTR_LEVEL3] = 1,
+ [TAPAN_A_INTR_TEST0] = 1,
+ [TAPAN_A_INTR_TEST1] = 1,
+ [TAPAN_A_INTR_TEST2] = 1,
+ [TAPAN_A_INTR_TEST3] = 1,
+ [TAPAN_A_INTR_SET0] = 1,
+ [TAPAN_A_INTR_SET1] = 1,
+ [TAPAN_A_INTR_SET2] = 1,
+ [TAPAN_A_INTR_SET3] = 1,
+ [TAPAN_A_INTR_DESTN0] = 1,
+ [TAPAN_A_INTR_DESTN1] = 1,
+ [TAPAN_A_INTR_DESTN2] = 1,
+ [TAPAN_A_INTR_DESTN3] = 1,
+ [TAPAN_A_CDC_DMIC_DATA0_MODE] = 1,
+ [TAPAN_A_CDC_DMIC_CLK0_MODE] = 1,
+ [TAPAN_A_CDC_DMIC_DATA1_MODE] = 1,
+ [TAPAN_A_CDC_DMIC_CLK1_MODE] = 1,
+ [TAPAN_A_CDC_INTR_MODE] = 1,
+ [TAPAN_A_BIAS_REF_CTL] = 1,
+ [TAPAN_A_BIAS_CENTRAL_BG_CTL] = 1,
+ [TAPAN_A_BIAS_PRECHRG_CTL] = 1,
+ [TAPAN_A_BIAS_CURR_CTL_1] = 1,
+ [TAPAN_A_BIAS_CURR_CTL_2] = 1,
+ [TAPAN_A_BIAS_OSC_BG_CTL] = 1,
+ [TAPAN_A_CLK_BUFF_EN1] = 1,
+ [TAPAN_A_CLK_BUFF_EN2] = 1,
+ [TAPAN_A_LDO_H_MODE_1] = 1,
+ [TAPAN_A_LDO_H_MODE_2] = 1,
+ [TAPAN_A_LDO_H_LOOP_CTL] = 1,
+ [TAPAN_A_LDO_H_COMP_1] = 1,
+ [TAPAN_A_LDO_H_COMP_2] = 1,
+ [TAPAN_A_LDO_H_BIAS_1] = 1,
+ [TAPAN_A_LDO_H_BIAS_2] = 1,
+ [TAPAN_A_LDO_H_BIAS_3] = 1,
+ [TAPAN_A_MICB_CFILT_1_CTL] = 1,
+ [TAPAN_A_MICB_CFILT_1_VAL] = 1,
+ [TAPAN_A_MICB_CFILT_1_PRECHRG] = 1,
+ [TAPAN_A_MICB_1_CTL] = 1,
+ [TAPAN_A_MICB_1_INT_RBIAS] = 1,
+ [TAPAN_A_MICB_1_MBHC] = 1,
+ [TAPAN_A_MICB_CFILT_2_CTL] = 1,
+ [TAPAN_A_MICB_CFILT_2_VAL] = 1,
+ [TAPAN_A_MICB_CFILT_2_PRECHRG] = 1,
+ [TAPAN_A_MICB_2_CTL] = 1,
+ [TAPAN_A_MICB_2_INT_RBIAS] = 1,
+ [TAPAN_A_MICB_2_MBHC] = 1,
+ [TAPAN_A_MICB_CFILT_3_CTL] = 1,
+ [TAPAN_A_MICB_CFILT_3_VAL] = 1,
+ [TAPAN_A_MICB_CFILT_3_PRECHRG] = 1,
+ [TAPAN_A_MICB_3_CTL] = 1,
+ [TAPAN_A_MICB_3_INT_RBIAS] = 1,
+ [TAPAN_A_MICB_3_MBHC] = 1,
+ [TAPAN_A_MBHC_INSERT_DETECT] = 1,
+ [TAPAN_A_MBHC_INSERT_DET_STATUS] = 1,
+ [TAPAN_A_TX_COM_BIAS] = 1,
+ [TAPAN_A_MBHC_SCALING_MUX_1] = 1,
+ [TAPAN_A_MBHC_SCALING_MUX_2] = 1,
+ [TAPAN_A_RESERVED_MAD_ANA_CTRL] = 1,
+ [TAPAN_A_TX_SUP_SWITCH_CTRL_1] = 1,
+ [TAPAN_A_TX_SUP_SWITCH_CTRL_2] = 1,
+ [TAPAN_A_TX_1_EN] = 1,
+ [TAPAN_A_TX_2_EN] = 1,
+ [TAPAN_A_TX_1_2_ADC_CH1] = 1,
+ [TAPAN_A_TX_1_2_ADC_CH2] = 1,
+ [TAPAN_A_TX_1_2_ATEST_REFCTRL] = 1,
+ [TAPAN_A_TX_1_2_TEST_CTL] = 1,
+ [TAPAN_A_TX_1_2_TEST_BLOCK_EN] = 1,
+ [TAPAN_A_TX_1_2_TXFE_CLKDIV] = 1,
+ [TAPAN_A_TX_1_2_SAR_ERR_CH1] = 1,
+ [TAPAN_A_TX_1_2_SAR_ERR_CH2] = 1,
+ [TAPAN_A_TX_3_EN] = 1,
+ [TAPAN_A_TX_1_2_TEST_EN] = 1,
+ [TAPAN_A_TX_4_5_TXFE_SC_CTL] = 1,
+ [TAPAN_A_TX_4_5_TEST_EN] = 1,
+ [TAPAN_A_TX_4_EN] = 1,
+ [TAPAN_A_TX_5_EN] = 1,
+ [TAPAN_A_TX_4_5_ADC_CH4] = 1,
+ [TAPAN_A_TX_4_5_ADC_CH5] = 1,
+ [TAPAN_A_TX_4_5_ATEST_REFCTRL] = 1,
+ [TAPAN_A_TX_4_5_TEST_CTL] = 1,
+ [TAPAN_A_TX_4_5_TEST_BLOCK_EN] = 1,
+ [TAPAN_A_TX_4_5_TXFE_CKDIV] = 1,
+ [TAPAN_A_TX_4_5_SAR_ERR_CH4] = 1,
+ [TAPAN_A_TX_4_5_SAR_ERR_CH5] = 1,
+ [TAPAN_A_TX_7_MBHC_EN] = 1,
+ [TAPAN_A_TX_7_MBHC_ATEST_REFCTRL] = 1,
+ [TAPAN_A_TX_7_MBHC_ADC] = 1,
+ [TAPAN_A_TX_7_MBHC_TEST_CTL] = 1,
+ [TAPAN_A_TX_7_MBHC_SAR_ERR] = 1,
+ [TAPAN_A_TX_7_TXFE_CLKDIV] = 1,
+ [TAPAN_A_BUCK_MODE_1] = 1,
+ [TAPAN_A_BUCK_MODE_2] = 1,
+ [TAPAN_A_BUCK_MODE_3] = 1,
+ [TAPAN_A_BUCK_MODE_4] = 1,
+ [TAPAN_A_BUCK_MODE_5] = 1,
+ [TAPAN_A_BUCK_CTRL_VCL_1] = 1,
+ [TAPAN_A_BUCK_CTRL_VCL_2] = 1,
+ [TAPAN_A_BUCK_CTRL_VCL_3] = 1,
+ [TAPAN_A_BUCK_CTRL_CCL_1] = 1,
+ [TAPAN_A_BUCK_CTRL_CCL_2] = 1,
+ [TAPAN_A_BUCK_CTRL_CCL_3] = 1,
+ [TAPAN_A_BUCK_CTRL_CCL_4] = 1,
+ [TAPAN_A_BUCK_CTRL_PWM_DRVR_1] = 1,
+ [TAPAN_A_BUCK_CTRL_PWM_DRVR_2] = 1,
+ [TAPAN_A_BUCK_CTRL_PWM_DRVR_3] = 1,
+ [TAPAN_A_BUCK_TMUX_A_D] = 1,
+ [TAPAN_A_NCP_BUCKREF] = 1,
+ [TAPAN_A_NCP_EN] = 1,
+ [TAPAN_A_NCP_CLK] = 1,
+ [TAPAN_A_NCP_STATIC] = 1,
+ [TAPAN_A_NCP_VTH_LOW] = 1,
+ [TAPAN_A_NCP_VTH_HIGH] = 1,
+ [TAPAN_A_NCP_ATEST] = 1,
+ [TAPAN_A_NCP_DTEST] = 1,
+ [TAPAN_A_NCP_DLY1] = 1,
+ [TAPAN_A_NCP_DLY2] = 1,
+ [TAPAN_A_RX_AUX_SW_CTL] = 1,
+ [TAPAN_A_RX_PA_AUX_IN_CONN] = 1,
+ [TAPAN_A_RX_COM_TIMER_DIV] = 1,
+ [TAPAN_A_RX_COM_OCP_CTL] = 1,
+ [TAPAN_A_RX_COM_OCP_COUNT] = 1,
+ [TAPAN_A_RX_COM_DAC_CTL] = 1,
+ [TAPAN_A_RX_COM_BIAS] = 1,
+ [TAPAN_A_RX_HPH_AUTO_CHOP] = 1,
+ [TAPAN_A_RX_HPH_CHOP_CTL] = 1,
+ [TAPAN_A_RX_HPH_BIAS_PA] = 1,
+ [TAPAN_A_RX_HPH_BIAS_LDO] = 1,
+ [TAPAN_A_RX_HPH_BIAS_CNP] = 1,
+ [TAPAN_A_RX_HPH_BIAS_WG_OCP] = 1,
+ [TAPAN_A_RX_HPH_OCP_CTL] = 1,
+ [TAPAN_A_RX_HPH_CNP_EN] = 1,
+ [TAPAN_A_RX_HPH_CNP_WG_CTL] = 1,
+ [TAPAN_A_RX_HPH_CNP_WG_TIME] = 1,
+ [TAPAN_A_RX_HPH_L_GAIN] = 1,
+ [TAPAN_A_RX_HPH_L_TEST] = 1,
+ [TAPAN_A_RX_HPH_L_PA_CTL] = 1,
+ [TAPAN_A_RX_HPH_L_DAC_CTL] = 1,
+ [TAPAN_A_RX_HPH_L_ATEST] = 1,
+ [TAPAN_A_RX_HPH_L_STATUS] = 1,
+ [TAPAN_A_RX_HPH_R_GAIN] = 1,
+ [TAPAN_A_RX_HPH_R_TEST] = 1,
+ [TAPAN_A_RX_HPH_R_PA_CTL] = 1,
+ [TAPAN_A_RX_HPH_R_DAC_CTL] = 1,
+ [TAPAN_A_RX_HPH_R_ATEST] = 1,
+ [TAPAN_A_RX_HPH_R_STATUS] = 1,
+ [TAPAN_A_RX_EAR_BIAS_PA] = 1,
+ [TAPAN_A_RX_EAR_BIAS_CMBUFF] = 1,
+ [TAPAN_A_RX_EAR_EN] = 1,
+ [TAPAN_A_RX_EAR_GAIN] = 1,
+ [TAPAN_A_RX_EAR_CMBUFF] = 1,
+ [TAPAN_A_RX_EAR_ICTL] = 1,
+ [TAPAN_A_RX_EAR_CCOMP] = 1,
+ [TAPAN_A_RX_EAR_VCM] = 1,
+ [TAPAN_A_RX_EAR_CNP] = 1,
+ [TAPAN_A_RX_EAR_DAC_CTL_ATEST] = 1,
+ [TAPAN_A_RX_EAR_STATUS] = 1,
+ [TAPAN_A_RX_LINE_BIAS_PA] = 1,
+ [TAPAN_A_RX_BUCK_BIAS1] = 1,
+ [TAPAN_A_RX_BUCK_BIAS2] = 1,
+ [TAPAN_A_RX_LINE_COM] = 1,
+ [TAPAN_A_RX_LINE_CNP_EN] = 1,
+ [TAPAN_A_RX_LINE_CNP_WG_CTL] = 1,
+ [TAPAN_A_RX_LINE_CNP_WG_TIME] = 1,
+ [TAPAN_A_RX_LINE_1_GAIN] = 1,
+ [TAPAN_A_RX_LINE_1_TEST] = 1,
+ [TAPAN_A_RX_LINE_1_DAC_CTL] = 1,
+ [TAPAN_A_RX_LINE_1_STATUS] = 1,
+ [TAPAN_A_RX_LINE_2_GAIN] = 1,
+ [TAPAN_A_RX_LINE_2_TEST] = 1,
+ [TAPAN_A_RX_LINE_2_DAC_CTL] = 1,
+ [TAPAN_A_RX_LINE_2_STATUS] = 1,
+ [TAPAN_A_RX_LINE_CNP_DBG] = 1,
+ [TAPAN_A_SPKR_DRV_EN] = 1,
+ [TAPAN_A_SPKR_DRV_GAIN] = 1,
+ [TAPAN_A_SPKR_DRV_DAC_CTL] = 1,
+ [TAPAN_A_SPKR_DRV_OCP_CTL] = 1,
+ [TAPAN_A_SPKR_DRV_CLIP_DET] = 1,
+ [TAPAN_A_SPKR_DRV_IEC] = 1,
+ [TAPAN_A_SPKR_DRV_DBG_DAC] = 1,
+ [TAPAN_A_SPKR_DRV_DBG_PA] = 1,
+ [TAPAN_A_SPKR_DRV_DBG_PWRSTG] = 1,
+ [TAPAN_A_SPKR_DRV_BIAS_LDO] = 1,
+ [TAPAN_A_SPKR_DRV_BIAS_INT] = 1,
+ [TAPAN_A_SPKR_DRV_BIAS_PA] = 1,
+ [TAPAN_A_SPKR_DRV_STATUS_OCP] = 1,
+ [TAPAN_A_SPKR_DRV_STATUS_PA] = 1,
+ [TAPAN_A_RC_OSC_FREQ] = 1,
+ [TAPAN_A_RC_OSC_TEST] = 1,
+ [TAPAN_A_RC_OSC_STATUS] = 1,
+ [TAPAN_A_RC_OSC_TUNER] = 1,
+ [TAPAN_A_MBHC_HPH] = 1,
+ [TAPAN_A_CDC_ANC1_B1_CTL] = 1,
+ [TAPAN_A_CDC_ANC2_B1_CTL] = 1,
+ [TAPAN_A_CDC_ANC1_SHIFT] = 1,
+ [TAPAN_A_CDC_ANC2_SHIFT] = 1,
+ [TAPAN_A_CDC_ANC1_IIR_B1_CTL] = 1,
+ [TAPAN_A_CDC_ANC2_IIR_B1_CTL] = 1,
+ [TAPAN_A_CDC_ANC1_IIR_B2_CTL] = 1,
+ [TAPAN_A_CDC_ANC2_IIR_B2_CTL] = 1,
+ [TAPAN_A_CDC_ANC1_IIR_B3_CTL] = 1,
+ [TAPAN_A_CDC_ANC2_IIR_B3_CTL] = 1,
+ [TAPAN_A_CDC_ANC1_LPF_B1_CTL] = 1,
+ [TAPAN_A_CDC_ANC2_LPF_B1_CTL] = 1,
+ [TAPAN_A_CDC_ANC1_LPF_B2_CTL] = 1,
+ [TAPAN_A_CDC_ANC2_LPF_B2_CTL] = 1,
+ [TAPAN_A_CDC_ANC1_SPARE] = 1,
+ [TAPAN_A_CDC_ANC2_SPARE] = 1,
+ [TAPAN_A_CDC_ANC1_SMLPF_CTL] = 1,
+ [TAPAN_A_CDC_ANC2_SMLPF_CTL] = 1,
+ [TAPAN_A_CDC_ANC1_DCFLT_CTL] = 1,
+ [TAPAN_A_CDC_ANC2_DCFLT_CTL] = 1,
+ [TAPAN_A_CDC_ANC1_GAIN_CTL] = 1,
+ [TAPAN_A_CDC_ANC2_GAIN_CTL] = 1,
+ [TAPAN_A_CDC_ANC1_B2_CTL] = 1,
+ [TAPAN_A_CDC_ANC2_B2_CTL] = 1,
+ [TAPAN_A_CDC_TX1_VOL_CTL_TIMER] = 1,
+ [TAPAN_A_CDC_TX2_VOL_CTL_TIMER] = 1,
+ [TAPAN_A_CDC_TX3_VOL_CTL_TIMER] = 1,
+ [TAPAN_A_CDC_TX4_VOL_CTL_TIMER] = 1,
+ [TAPAN_A_CDC_TX1_VOL_CTL_GAIN] = 1,
+ [TAPAN_A_CDC_TX2_VOL_CTL_GAIN] = 1,
+ [TAPAN_A_CDC_TX3_VOL_CTL_GAIN] = 1,
+ [TAPAN_A_CDC_TX4_VOL_CTL_GAIN] = 1,
+ [TAPAN_A_CDC_TX1_VOL_CTL_CFG] = 1,
+ [TAPAN_A_CDC_TX2_VOL_CTL_CFG] = 1,
+ [TAPAN_A_CDC_TX3_VOL_CTL_CFG] = 1,
+ [TAPAN_A_CDC_TX4_VOL_CTL_CFG] = 1,
+ [TAPAN_A_CDC_TX1_MUX_CTL] = 1,
+ [TAPAN_A_CDC_TX2_MUX_CTL] = 1,
+ [TAPAN_A_CDC_TX3_MUX_CTL] = 1,
+ [TAPAN_A_CDC_TX4_MUX_CTL] = 1,
+ [TAPAN_A_CDC_TX1_CLK_FS_CTL] = 1,
+ [TAPAN_A_CDC_TX2_CLK_FS_CTL] = 1,
+ [TAPAN_A_CDC_TX3_CLK_FS_CTL] = 1,
+ [TAPAN_A_CDC_TX4_CLK_FS_CTL] = 1,
+ [TAPAN_A_CDC_TX1_DMIC_CTL] = 1,
+ [TAPAN_A_CDC_TX2_DMIC_CTL] = 1,
+ [TAPAN_A_CDC_TX3_DMIC_CTL] = 1,
+ [TAPAN_A_CDC_TX4_DMIC_CTL] = 1,
+ [TAPAN_A_CDC_DEBUG_B1_CTL] = 1,
+ [TAPAN_A_CDC_DEBUG_B2_CTL] = 1,
+ [TAPAN_A_CDC_DEBUG_B3_CTL] = 1,
+ [TAPAN_A_CDC_DEBUG_B4_CTL] = 1,
+ [TAPAN_A_CDC_DEBUG_B5_CTL] = 1,
+ [TAPAN_A_CDC_DEBUG_B6_CTL] = 1,
+ [TAPAN_A_CDC_DEBUG_B7_CTL] = 1,
+ [TAPAN_A_CDC_SRC1_PDA_CFG] = 1,
+ [TAPAN_A_CDC_SRC2_PDA_CFG] = 1,
+ [TAPAN_A_CDC_SRC1_FS_CTL] = 1,
+ [TAPAN_A_CDC_SRC2_FS_CTL] = 1,
+ [TAPAN_A_CDC_RX1_B1_CTL] = 1,
+ [TAPAN_A_CDC_RX2_B1_CTL] = 1,
+ [TAPAN_A_CDC_RX3_B1_CTL] = 1,
+ [TAPAN_A_CDC_RX4_B1_CTL] = 1,
+ [TAPAN_A_CDC_RX1_B2_CTL] = 1,
+ [TAPAN_A_CDC_RX2_B2_CTL] = 1,
+ [TAPAN_A_CDC_RX3_B2_CTL] = 1,
+ [TAPAN_A_CDC_RX4_B2_CTL] = 1,
+ [TAPAN_A_CDC_RX1_B3_CTL] = 1,
+ [TAPAN_A_CDC_RX2_B3_CTL] = 1,
+ [TAPAN_A_CDC_RX3_B3_CTL] = 1,
+ [TAPAN_A_CDC_RX4_B3_CTL] = 1,
+ [TAPAN_A_CDC_RX1_B4_CTL] = 1,
+ [TAPAN_A_CDC_RX2_B4_CTL] = 1,
+ [TAPAN_A_CDC_RX3_B4_CTL] = 1,
+ [TAPAN_A_CDC_RX4_B4_CTL] = 1,
+ [TAPAN_A_CDC_RX1_B5_CTL] = 1,
+ [TAPAN_A_CDC_RX2_B5_CTL] = 1,
+ [TAPAN_A_CDC_RX3_B5_CTL] = 1,
+ [TAPAN_A_CDC_RX4_B5_CTL] = 1,
+ [TAPAN_A_CDC_RX1_B6_CTL] = 1,
+ [TAPAN_A_CDC_RX2_B6_CTL] = 1,
+ [TAPAN_A_CDC_RX3_B6_CTL] = 1,
+ [TAPAN_A_CDC_RX4_B6_CTL] = 1,
+ [TAPAN_A_CDC_RX1_VOL_CTL_B1_CTL] = 1,
+ [TAPAN_A_CDC_RX2_VOL_CTL_B1_CTL] = 1,
+ [TAPAN_A_CDC_RX3_VOL_CTL_B1_CTL] = 1,
+ [TAPAN_A_CDC_RX4_VOL_CTL_B1_CTL] = 1,
+ [TAPAN_A_CDC_RX1_VOL_CTL_B2_CTL] = 1,
+ [TAPAN_A_CDC_RX2_VOL_CTL_B2_CTL] = 1,
+ [TAPAN_A_CDC_RX3_VOL_CTL_B2_CTL] = 1,
+ [TAPAN_A_CDC_RX4_VOL_CTL_B2_CTL] = 1,
+ [TAPAN_A_CDC_CLK_ANC_RESET_CTL] = 1,
+ [TAPAN_A_CDC_CLK_RX_RESET_CTL] = 1,
+ [TAPAN_A_CDC_CLK_TX_RESET_B1_CTL] = 1,
+ [TAPAN_A_CDC_CLK_TX_RESET_B2_CTL] = 1,
+ [TAPAN_A_CDC_CLK_DMIC_B1_CTL] = 1,
+ [TAPAN_A_CDC_CLK_DMIC_B2_CTL] = 1,
+ [TAPAN_A_CDC_CLK_I2S_CTL] = 1,
+ [TAPAN_A_CDC_CLK_OTHR_RESET_B1_CTL] = 1,
+ [TAPAN_A_CDC_CLK_OTHR_RESET_B2_CTL] = 1,
+ [TAPAN_A_CDC_CLK_TX_CLK_EN_B1_CTL] = 1,
+ [TAPAN_A_CDC_CLK_TX_CLK_EN_B2_CTL] = 1,
+ [TAPAN_A_CDC_CLK_OTHR_CTL] = 1,
+ [TAPAN_A_CDC_CLK_RDAC_CLK_EN_CTL] = 1,
+ [TAPAN_A_CDC_CLK_ANC_CLK_EN_CTL] = 1,
+ [TAPAN_A_CDC_CLK_RX_B1_CTL] = 1,
+ [TAPAN_A_CDC_CLK_RX_B2_CTL] = 1,
+ [TAPAN_A_CDC_CLK_MCLK_CTL] = 1,
+ [TAPAN_A_CDC_CLK_PDM_CTL] = 1,
+ [TAPAN_A_CDC_CLK_SD_CTL] = 1,
+ [TAPAN_A_CDC_CLK_POWER_CTL] = 1,
+ [TAPAN_A_CDC_CLSH_B1_CTL] = 1,
+ [TAPAN_A_CDC_CLSH_B2_CTL] = 1,
+ [TAPAN_A_CDC_CLSH_B3_CTL] = 1,
+ [TAPAN_A_CDC_CLSH_BUCK_NCP_VARS] = 1,
+ [TAPAN_A_CDC_CLSH_IDLE_HPH_THSD] = 1,
+ [TAPAN_A_CDC_CLSH_IDLE_EAR_THSD] = 1,
+ [TAPAN_A_CDC_CLSH_FCLKONLY_HPH_THSD] = 1,
+ [TAPAN_A_CDC_CLSH_FCLKONLY_EAR_THSD] = 1,
+ [TAPAN_A_CDC_CLSH_K_ADDR] = 1,
+ [TAPAN_A_CDC_CLSH_K_DATA] = 1,
+ [TAPAN_A_CDC_CLSH_I_PA_FACT_HPH_L] = 1,
+ [TAPAN_A_CDC_CLSH_I_PA_FACT_HPH_U] = 1,
+ [TAPAN_A_CDC_CLSH_I_PA_FACT_EAR_L] = 1,
+ [TAPAN_A_CDC_CLSH_I_PA_FACT_EAR_U] = 1,
+ [TAPAN_A_CDC_CLSH_V_PA_HD_EAR] = 1,
+ [TAPAN_A_CDC_CLSH_V_PA_HD_HPH] = 1,
+ [TAPAN_A_CDC_CLSH_V_PA_MIN_EAR] = 1,
+ [TAPAN_A_CDC_CLSH_V_PA_MIN_HPH] = 1,
+ [TAPAN_A_CDC_IIR1_GAIN_B1_CTL] = 1,
+ [TAPAN_A_CDC_IIR2_GAIN_B1_CTL] = 1,
+ [TAPAN_A_CDC_IIR1_GAIN_B2_CTL] = 1,
+ [TAPAN_A_CDC_IIR2_GAIN_B2_CTL] = 1,
+ [TAPAN_A_CDC_IIR1_GAIN_B3_CTL] = 1,
+ [TAPAN_A_CDC_IIR2_GAIN_B3_CTL] = 1,
+ [TAPAN_A_CDC_IIR1_GAIN_B4_CTL] = 1,
+ [TAPAN_A_CDC_IIR2_GAIN_B4_CTL] = 1,
+ [TAPAN_A_CDC_IIR1_GAIN_B5_CTL] = 1,
+ [TAPAN_A_CDC_IIR2_GAIN_B5_CTL] = 1,
+ [TAPAN_A_CDC_IIR1_GAIN_B6_CTL] = 1,
+ [TAPAN_A_CDC_IIR2_GAIN_B6_CTL] = 1,
+ [TAPAN_A_CDC_IIR1_GAIN_B7_CTL] = 1,
+ [TAPAN_A_CDC_IIR2_GAIN_B7_CTL] = 1,
+ [TAPAN_A_CDC_IIR1_GAIN_B8_CTL] = 1,
+ [TAPAN_A_CDC_IIR2_GAIN_B8_CTL] = 1,
+ [TAPAN_A_CDC_IIR1_CTL] = 1,
+ [TAPAN_A_CDC_IIR2_CTL] = 1,
+ [TAPAN_A_CDC_IIR1_GAIN_TIMER_CTL] = 1,
+ [TAPAN_A_CDC_IIR2_GAIN_TIMER_CTL] = 1,
+ [TAPAN_A_CDC_IIR1_COEF_B1_CTL] = 1,
+ [TAPAN_A_CDC_IIR2_COEF_B1_CTL] = 1,
+ [TAPAN_A_CDC_IIR1_COEF_B2_CTL] = 1,
+ [TAPAN_A_CDC_IIR2_COEF_B2_CTL] = 1,
+ [TAPAN_A_CDC_TOP_GAIN_UPDATE] = 1,
+ [TAPAN_A_CDC_COMP0_B1_CTL] = 1,
+ [TAPAN_A_CDC_COMP1_B1_CTL] = 1,
+ [TAPAN_A_CDC_COMP2_B1_CTL] = 1,
+ [TAPAN_A_CDC_COMP0_B2_CTL] = 1,
+ [TAPAN_A_CDC_COMP1_B2_CTL] = 1,
+ [TAPAN_A_CDC_COMP2_B2_CTL] = 1,
+ [TAPAN_A_CDC_COMP0_B3_CTL] = 1,
+ [TAPAN_A_CDC_COMP1_B3_CTL] = 1,
+ [TAPAN_A_CDC_COMP2_B3_CTL] = 1,
+ [TAPAN_A_CDC_COMP0_B4_CTL] = 1,
+ [TAPAN_A_CDC_COMP1_B4_CTL] = 1,
+ [TAPAN_A_CDC_COMP2_B4_CTL] = 1,
+ [TAPAN_A_CDC_COMP0_B5_CTL] = 1,
+ [TAPAN_A_CDC_COMP1_B5_CTL] = 1,
+ [TAPAN_A_CDC_COMP2_B5_CTL] = 1,
+ [TAPAN_A_CDC_COMP0_B6_CTL] = 1,
+ [TAPAN_A_CDC_COMP1_B6_CTL] = 1,
+ [TAPAN_A_CDC_COMP2_B6_CTL] = 1,
+ [TAPAN_A_CDC_COMP0_SHUT_DOWN_STATUS] = 1,
+ [TAPAN_A_CDC_COMP1_SHUT_DOWN_STATUS] = 1,
+ [TAPAN_A_CDC_COMP2_SHUT_DOWN_STATUS] = 1,
+ [TAPAN_A_CDC_COMP0_FS_CFG] = 1,
+ [TAPAN_A_CDC_COMP1_FS_CFG] = 1,
+ [TAPAN_A_CDC_COMP2_FS_CFG] = 1,
+ [TAPAN_A_CDC_CONN_RX1_B1_CTL] = 1,
+ [TAPAN_A_CDC_CONN_RX1_B2_CTL] = 1,
+ [TAPAN_A_CDC_CONN_RX1_B3_CTL] = 1,
+ [TAPAN_A_CDC_CONN_RX2_B1_CTL] = 1,
+ [TAPAN_A_CDC_CONN_RX2_B2_CTL] = 1,
+ [TAPAN_A_CDC_CONN_RX2_B3_CTL] = 1,
+ [TAPAN_A_CDC_CONN_RX3_B1_CTL] = 1,
+ [TAPAN_A_CDC_CONN_RX3_B2_CTL] = 1,
+ [TAPAN_A_CDC_CONN_RX4_B1_CTL] = 1,
+ [TAPAN_A_CDC_CONN_RX4_B2_CTL] = 1,
+ [TAPAN_A_CDC_CONN_RX4_B3_CTL] = 1,
+ [TAPAN_A_CDC_CONN_ANC_B1_CTL] = 1,
+ [TAPAN_A_CDC_CONN_ANC_B2_CTL] = 1,
+ [TAPAN_A_CDC_CONN_TX_B1_CTL] = 1,
+ [TAPAN_A_CDC_CONN_TX_B2_CTL] = 1,
+ [TAPAN_A_CDC_CONN_TX_B3_CTL] = 1,
+ [TAPAN_A_CDC_CONN_TX_B4_CTL] = 1,
+ [TAPAN_A_CDC_CONN_EQ1_B1_CTL] = 1,
+ [TAPAN_A_CDC_CONN_EQ1_B2_CTL] = 1,
+ [TAPAN_A_CDC_CONN_EQ1_B3_CTL] = 1,
+ [TAPAN_A_CDC_CONN_EQ1_B4_CTL] = 1,
+ [TAPAN_A_CDC_CONN_EQ2_B1_CTL] = 1,
+ [TAPAN_A_CDC_CONN_EQ2_B2_CTL] = 1,
+ [TAPAN_A_CDC_CONN_EQ2_B3_CTL] = 1,
+ [TAPAN_A_CDC_CONN_EQ2_B4_CTL] = 1,
+ [TAPAN_A_CDC_CONN_SRC1_B1_CTL] = 1,
+ [TAPAN_A_CDC_CONN_SRC1_B2_CTL] = 1,
+ [TAPAN_A_CDC_CONN_SRC2_B1_CTL] = 1,
+ [TAPAN_A_CDC_CONN_SRC2_B2_CTL] = 1,
+ [TAPAN_A_CDC_CONN_TX_SB_B1_CTL] = 1,
+ [TAPAN_A_CDC_CONN_TX_SB_B2_CTL] = 1,
+ [TAPAN_A_CDC_CONN_TX_SB_B3_CTL] = 1,
+ [TAPAN_A_CDC_CONN_TX_SB_B4_CTL] = 1,
+ [TAPAN_A_CDC_CONN_TX_SB_B5_CTL] = 1,
+ [TAPAN_A_CDC_CONN_TX_SB_B11_CTL] = 1,
+ [TAPAN_A_CDC_CONN_RX_SB_B1_CTL] = 1,
+ [TAPAN_A_CDC_CONN_RX_SB_B2_CTL] = 1,
+ [TAPAN_A_CDC_CONN_CLSH_CTL] = 1,
+ [TAPAN_A_CDC_CONN_MISC] = 1,
+ [TAPAN_A_CDC_MBHC_EN_CTL] = 1,
+ [TAPAN_A_CDC_MBHC_FIR_B1_CFG] = 1,
+ [TAPAN_A_CDC_MBHC_FIR_B2_CFG] = 1,
+ [TAPAN_A_CDC_MBHC_TIMER_B1_CTL] = 1,
+ [TAPAN_A_CDC_MBHC_TIMER_B2_CTL] = 1,
+ [TAPAN_A_CDC_MBHC_TIMER_B3_CTL] = 1,
+ [TAPAN_A_CDC_MBHC_TIMER_B4_CTL] = 1,
+ [TAPAN_A_CDC_MBHC_TIMER_B5_CTL] = 1,
+ [TAPAN_A_CDC_MBHC_TIMER_B6_CTL] = 1,
+ [TAPAN_A_CDC_MBHC_B1_STATUS] = 1,
+ [TAPAN_A_CDC_MBHC_B2_STATUS] = 1,
+ [TAPAN_A_CDC_MBHC_B3_STATUS] = 1,
+ [TAPAN_A_CDC_MBHC_B4_STATUS] = 1,
+ [TAPAN_A_CDC_MBHC_B5_STATUS] = 1,
+ [TAPAN_A_CDC_MBHC_B1_CTL] = 1,
+ [TAPAN_A_CDC_MBHC_B2_CTL] = 1,
+ [TAPAN_A_CDC_MBHC_VOLT_B1_CTL] = 1,
+ [TAPAN_A_CDC_MBHC_VOLT_B2_CTL] = 1,
+ [TAPAN_A_CDC_MBHC_VOLT_B3_CTL] = 1,
+ [TAPAN_A_CDC_MBHC_VOLT_B4_CTL] = 1,
+ [TAPAN_A_CDC_MBHC_VOLT_B5_CTL] = 1,
+ [TAPAN_A_CDC_MBHC_VOLT_B6_CTL] = 1,
+ [TAPAN_A_CDC_MBHC_VOLT_B7_CTL] = 1,
+ [TAPAN_A_CDC_MBHC_VOLT_B8_CTL] = 1,
+ [TAPAN_A_CDC_MBHC_VOLT_B9_CTL] = 1,
+ [TAPAN_A_CDC_MBHC_VOLT_B10_CTL] = 1,
+ [TAPAN_A_CDC_MBHC_VOLT_B11_CTL] = 1,
+ [TAPAN_A_CDC_MBHC_VOLT_B12_CTL] = 1,
+ [TAPAN_A_CDC_MBHC_CLK_CTL] = 1,
+ [TAPAN_A_CDC_MBHC_INT_CTL] = 1,
+ [TAPAN_A_CDC_MBHC_DEBUG_CTL] = 1,
+ [TAPAN_A_CDC_MBHC_SPARE] = 1,
+};
+
+const u8 tapan_reset_reg_defaults[TAPAN_CACHE_SIZE] = {
+ [TAPAN_A_CHIP_CTL] = TAPAN_A_CHIP_CTL__POR,
+ [TAPAN_A_CHIP_STATUS] = TAPAN_A_CHIP_STATUS__POR,
+ [TAPAN_A_CHIP_ID_BYTE_0] = TAPAN_A_CHIP_ID_BYTE_0__POR,
+ [TAPAN_A_CHIP_ID_BYTE_1] = TAPAN_A_CHIP_ID_BYTE_1__POR,
+ [TAPAN_A_CHIP_ID_BYTE_2] = TAPAN_A_CHIP_ID_BYTE_2__POR,
+ [TAPAN_A_CHIP_ID_BYTE_3] = TAPAN_A_CHIP_ID_BYTE_3__POR,
+ [TAPAN_A_CHIP_VERSION] = TAPAN_A_CHIP_VERSION__POR,
+ [TAPAN_A_CHIP_DEBUG_CTL] = TAPAN_A_CHIP_DEBUG_CTL__POR,
+ [TAPAN_A_SLAVE_ID_1] = TAPAN_A_SLAVE_ID_1__POR,
+ [TAPAN_A_SLAVE_ID_2] = TAPAN_A_SLAVE_ID_2__POR,
+ [TAPAN_A_SLAVE_ID_3] = TAPAN_A_SLAVE_ID_3__POR,
+ [TAPAN_A_PIN_CTL_OE0] = TAPAN_A_PIN_CTL_OE0__POR,
+ [TAPAN_A_PIN_CTL_DATA0] = TAPAN_A_PIN_CTL_DATA0__POR,
+ [TAPAN_A_HDRIVE_GENERIC] = TAPAN_A_HDRIVE_GENERIC__POR,
+ [TAPAN_A_HDRIVE_OVERRIDE] = TAPAN_A_HDRIVE_OVERRIDE__POR,
+ [TAPAN_A_ANA_CSR_WAIT_STATE] = TAPAN_A_ANA_CSR_WAIT_STATE__POR,
+ [TAPAN_A_PROCESS_MONITOR_CTL0] = TAPAN_A_PROCESS_MONITOR_CTL0__POR,
+ [TAPAN_A_PROCESS_MONITOR_CTL1] = TAPAN_A_PROCESS_MONITOR_CTL1__POR,
+ [TAPAN_A_PROCESS_MONITOR_CTL2] = TAPAN_A_PROCESS_MONITOR_CTL2__POR,
+ [TAPAN_A_PROCESS_MONITOR_CTL3] = TAPAN_A_PROCESS_MONITOR_CTL3__POR,
+ [TAPAN_A_QFUSE_CTL] = TAPAN_A_QFUSE_CTL__POR,
+ [TAPAN_A_QFUSE_STATUS] = TAPAN_A_QFUSE_STATUS__POR,
+ [TAPAN_A_QFUSE_DATA_OUT0] = TAPAN_A_QFUSE_DATA_OUT0__POR,
+ [TAPAN_A_QFUSE_DATA_OUT1] = TAPAN_A_QFUSE_DATA_OUT1__POR,
+ [TAPAN_A_QFUSE_DATA_OUT2] = TAPAN_A_QFUSE_DATA_OUT2__POR,
+ [TAPAN_A_QFUSE_DATA_OUT3] = TAPAN_A_QFUSE_DATA_OUT3__POR,
+ [TAPAN_A_QFUSE_DATA_OUT4] = TAPAN_A_QFUSE_DATA_OUT4__POR,
+ [TAPAN_A_QFUSE_DATA_OUT5] = TAPAN_A_QFUSE_DATA_OUT5__POR,
+ [TAPAN_A_QFUSE_DATA_OUT6] = TAPAN_A_QFUSE_DATA_OUT6__POR,
+ [TAPAN_A_QFUSE_DATA_OUT7] = TAPAN_A_QFUSE_DATA_OUT7__POR,
+ [TAPAN_A_CDC_CTL] = TAPAN_A_CDC_CTL__POR,
+ [TAPAN_A_LEAKAGE_CTL] = TAPAN_A_LEAKAGE_CTL__POR,
+ [TAPAN_A_INTR_MODE] = TAPAN_A_INTR_MODE__POR,
+ [TAPAN_A_INTR_MASK0] = TAPAN_A_INTR_MASK0__POR,
+ [TAPAN_A_INTR_MASK1] = TAPAN_A_INTR_MASK1__POR,
+ [TAPAN_A_INTR_MASK2] = TAPAN_A_INTR_MASK2__POR,
+ [TAPAN_A_INTR_MASK3] = TAPAN_A_INTR_MASK3__POR,
+ [TAPAN_A_INTR_STATUS0] = TAPAN_A_INTR_STATUS0__POR,
+ [TAPAN_A_INTR_STATUS1] = TAPAN_A_INTR_STATUS1__POR,
+ [TAPAN_A_INTR_STATUS2] = TAPAN_A_INTR_STATUS2__POR,
+ [TAPAN_A_INTR_STATUS3] = TAPAN_A_INTR_STATUS3__POR,
+ [TAPAN_A_INTR_CLEAR0] = TAPAN_A_INTR_CLEAR0__POR,
+ [TAPAN_A_INTR_CLEAR1] = TAPAN_A_INTR_CLEAR1__POR,
+ [TAPAN_A_INTR_CLEAR2] = TAPAN_A_INTR_CLEAR2__POR,
+ [TAPAN_A_INTR_CLEAR3] = TAPAN_A_INTR_CLEAR3__POR,
+ [TAPAN_A_INTR_LEVEL0] = TAPAN_A_INTR_LEVEL0__POR,
+ [TAPAN_A_INTR_LEVEL1] = TAPAN_A_INTR_LEVEL1__POR,
+ [TAPAN_A_INTR_LEVEL2] = TAPAN_A_INTR_LEVEL2__POR,
+ [TAPAN_A_INTR_LEVEL3] = TAPAN_A_INTR_LEVEL3__POR,
+ [TAPAN_A_INTR_TEST0] = TAPAN_A_INTR_TEST0__POR,
+ [TAPAN_A_INTR_TEST1] = TAPAN_A_INTR_TEST1__POR,
+ [TAPAN_A_INTR_TEST2] = TAPAN_A_INTR_TEST2__POR,
+ [TAPAN_A_INTR_TEST3] = TAPAN_A_INTR_TEST3__POR,
+ [TAPAN_A_INTR_SET0] = TAPAN_A_INTR_SET0__POR,
+ [TAPAN_A_INTR_SET1] = TAPAN_A_INTR_SET1__POR,
+ [TAPAN_A_INTR_SET2] = TAPAN_A_INTR_SET2__POR,
+ [TAPAN_A_INTR_SET3] = TAPAN_A_INTR_SET3__POR,
+ [TAPAN_A_INTR_DESTN0] = TAPAN_A_INTR_DESTN0__POR,
+ [TAPAN_A_INTR_DESTN1] = TAPAN_A_INTR_DESTN1__POR,
+ [TAPAN_A_INTR_DESTN2] = TAPAN_A_INTR_DESTN2__POR,
+ [TAPAN_A_INTR_DESTN3] = TAPAN_A_INTR_DESTN3__POR,
+ [TAPAN_A_CDC_DMIC_DATA0_MODE] = TAPAN_A_CDC_DMIC_DATA0_MODE__POR,
+ [TAPAN_A_CDC_DMIC_CLK0_MODE] = TAPAN_A_CDC_DMIC_CLK0_MODE__POR,
+ [TAPAN_A_CDC_DMIC_DATA1_MODE] = TAPAN_A_CDC_DMIC_DATA1_MODE__POR,
+ [TAPAN_A_CDC_DMIC_CLK1_MODE] = TAPAN_A_CDC_DMIC_CLK1_MODE__POR,
+ [TAPAN_A_CDC_INTR_MODE] = TAPAN_A_CDC_INTR_MODE__POR,
+ [TAPAN_A_BIAS_REF_CTL] = TAPAN_A_BIAS_REF_CTL__POR,
+ [TAPAN_A_BIAS_CENTRAL_BG_CTL] = TAPAN_A_BIAS_CENTRAL_BG_CTL__POR,
+ [TAPAN_A_BIAS_PRECHRG_CTL] = TAPAN_A_BIAS_PRECHRG_CTL__POR,
+ [TAPAN_A_BIAS_CURR_CTL_1] = TAPAN_A_BIAS_CURR_CTL_1__POR,
+ [TAPAN_A_BIAS_CURR_CTL_2] = TAPAN_A_BIAS_CURR_CTL_2__POR,
+ [TAPAN_A_BIAS_OSC_BG_CTL] = TAPAN_A_BIAS_OSC_BG_CTL__POR,
+ [TAPAN_A_CLK_BUFF_EN1] = TAPAN_A_CLK_BUFF_EN1__POR,
+ [TAPAN_A_CLK_BUFF_EN2] = TAPAN_A_CLK_BUFF_EN2__POR,
+ [TAPAN_A_LDO_H_MODE_1] = TAPAN_A_LDO_H_MODE_1__POR,
+ [TAPAN_A_LDO_H_MODE_2] = TAPAN_A_LDO_H_MODE_2__POR,
+ [TAPAN_A_LDO_H_LOOP_CTL] = TAPAN_A_LDO_H_LOOP_CTL__POR,
+ [TAPAN_A_LDO_H_COMP_1] = TAPAN_A_LDO_H_COMP_1__POR,
+ [TAPAN_A_LDO_H_COMP_2] = TAPAN_A_LDO_H_COMP_2__POR,
+ [TAPAN_A_LDO_H_BIAS_1] = TAPAN_A_LDO_H_BIAS_1__POR,
+ [TAPAN_A_LDO_H_BIAS_2] = TAPAN_A_LDO_H_BIAS_2__POR,
+ [TAPAN_A_LDO_H_BIAS_3] = TAPAN_A_LDO_H_BIAS_3__POR,
+ [TAPAN_A_MICB_CFILT_1_CTL] = TAPAN_A_MICB_CFILT_1_CTL__POR,
+ [TAPAN_A_MICB_CFILT_1_VAL] = TAPAN_A_MICB_CFILT_1_VAL__POR,
+ [TAPAN_A_MICB_CFILT_1_PRECHRG] = TAPAN_A_MICB_CFILT_1_PRECHRG__POR,
+ [TAPAN_A_MICB_1_CTL] = TAPAN_A_MICB_1_CTL__POR,
+ [TAPAN_A_MICB_1_INT_RBIAS] = TAPAN_A_MICB_1_INT_RBIAS__POR,
+ [TAPAN_A_MICB_1_MBHC] = TAPAN_A_MICB_1_MBHC__POR,
+ [TAPAN_A_MICB_CFILT_2_CTL] = TAPAN_A_MICB_CFILT_2_CTL__POR,
+ [TAPAN_A_MICB_CFILT_2_VAL] = TAPAN_A_MICB_CFILT_2_VAL__POR,
+ [TAPAN_A_MICB_CFILT_2_PRECHRG] = TAPAN_A_MICB_CFILT_2_PRECHRG__POR,
+ [TAPAN_A_MICB_2_CTL] = TAPAN_A_MICB_2_CTL__POR,
+ [TAPAN_A_MICB_2_INT_RBIAS] = TAPAN_A_MICB_2_INT_RBIAS__POR,
+ [TAPAN_A_MICB_2_MBHC] = TAPAN_A_MICB_2_MBHC__POR,
+ [TAPAN_A_MICB_CFILT_3_CTL] = TAPAN_A_MICB_CFILT_3_CTL__POR,
+ [TAPAN_A_MICB_CFILT_3_VAL] = TAPAN_A_MICB_CFILT_3_VAL__POR,
+ [TAPAN_A_MICB_CFILT_3_PRECHRG] = TAPAN_A_MICB_CFILT_3_PRECHRG__POR,
+ [TAPAN_A_MICB_3_CTL] = TAPAN_A_MICB_3_CTL__POR,
+ [TAPAN_A_MICB_3_INT_RBIAS] = TAPAN_A_MICB_3_INT_RBIAS__POR,
+ [TAPAN_A_MICB_3_MBHC] = TAPAN_A_MICB_3_MBHC__POR,
+ [TAPAN_A_MBHC_INSERT_DETECT] = TAPAN_A_MBHC_INSERT_DETECT__POR,
+ [TAPAN_A_MBHC_INSERT_DET_STATUS] = TAPAN_A_MBHC_INSERT_DET_STATUS__POR,
+ [TAPAN_A_TX_COM_BIAS] = TAPAN_A_TX_COM_BIAS__POR,
+ [TAPAN_A_MBHC_SCALING_MUX_1] = TAPAN_A_MBHC_SCALING_MUX_1__POR,
+ [TAPAN_A_MBHC_SCALING_MUX_2] = TAPAN_A_MBHC_SCALING_MUX_2__POR,
+ [TAPAN_A_RESERVED_MAD_ANA_CTRL] = TAPAN_A_RESERVED_MAD_ANA_CTRL__POR,
+ [TAPAN_A_TX_SUP_SWITCH_CTRL_1] = TAPAN_A_TX_SUP_SWITCH_CTRL_1__POR,
+ [TAPAN_A_TX_SUP_SWITCH_CTRL_2] = TAPAN_A_TX_SUP_SWITCH_CTRL_2__POR,
+ [TAPAN_A_TX_1_EN] = TAPAN_A_TX_1_EN__POR,
+ [TAPAN_A_TX_2_EN] = TAPAN_A_TX_2_EN__POR,
+ [TAPAN_A_TX_1_2_ADC_CH1] = TAPAN_A_TX_1_2_ADC_CH1__POR,
+ [TAPAN_A_TX_1_2_ADC_CH2] = TAPAN_A_TX_1_2_ADC_CH2__POR,
+ [TAPAN_A_TX_1_2_ATEST_REFCTRL] = TAPAN_A_TX_1_2_ATEST_REFCTRL__POR,
+ [TAPAN_A_TX_1_2_TEST_CTL] = TAPAN_A_TX_1_2_TEST_CTL__POR,
+ [TAPAN_A_TX_1_2_TEST_BLOCK_EN] = TAPAN_A_TX_1_2_TEST_BLOCK_EN__POR,
+ [TAPAN_A_TX_1_2_TXFE_CLKDIV] = TAPAN_A_TX_1_2_TXFE_CLKDIV__POR,
+ [TAPAN_A_TX_1_2_SAR_ERR_CH1] = TAPAN_A_TX_1_2_SAR_ERR_CH1__POR,
+ [TAPAN_A_TX_1_2_SAR_ERR_CH2] = TAPAN_A_TX_1_2_SAR_ERR_CH2__POR,
+ [TAPAN_A_TX_3_EN] = TAPAN_A_TX_3_EN__POR,
+ [TAPAN_A_TX_1_2_TEST_EN] = TAPAN_A_TX_1_2_TEST_EN__POR,
+ [TAPAN_A_TX_4_5_TXFE_SC_CTL] = TAPAN_A_TX_4_5_TXFE_SC_CTL__POR,
+ [TAPAN_A_TX_4_5_TEST_EN] = TAPAN_A_TX_4_5_TEST_EN__POR,
+ [TAPAN_A_TX_4_EN] = TAPAN_A_TX_4_EN__POR,
+ [TAPAN_A_TX_5_EN] = TAPAN_A_TX_5_EN__POR,
+ [TAPAN_A_TX_4_5_ADC_CH4] = TAPAN_A_TX_4_5_ADC_CH4__POR,
+ [TAPAN_A_TX_4_5_ADC_CH5] = TAPAN_A_TX_4_5_ADC_CH5__POR,
+ [TAPAN_A_TX_4_5_ATEST_REFCTRL] = TAPAN_A_TX_4_5_ATEST_REFCTRL__POR,
+ [TAPAN_A_TX_4_5_TEST_CTL] = TAPAN_A_TX_4_5_TEST_CTL__POR,
+ [TAPAN_A_TX_4_5_TEST_BLOCK_EN] = TAPAN_A_TX_4_5_TEST_BLOCK_EN__POR,
+ [TAPAN_A_TX_4_5_TXFE_CKDIV] = TAPAN_A_TX_4_5_TXFE_CKDIV__POR,
+ [TAPAN_A_TX_4_5_SAR_ERR_CH4] = TAPAN_A_TX_4_5_SAR_ERR_CH4__POR,
+ [TAPAN_A_TX_4_5_SAR_ERR_CH5] = TAPAN_A_TX_4_5_SAR_ERR_CH5__POR,
+ [TAPAN_A_TX_7_MBHC_EN] = TAPAN_A_TX_7_MBHC_EN__POR,
+ [TAPAN_A_TX_7_MBHC_ATEST_REFCTRL] =
+ TAPAN_A_TX_7_MBHC_ATEST_REFCTRL__POR,
+ [TAPAN_A_TX_7_MBHC_ADC] = TAPAN_A_TX_7_MBHC_ADC__POR,
+ [TAPAN_A_TX_7_MBHC_TEST_CTL] = TAPAN_A_TX_7_MBHC_TEST_CTL__POR,
+ [TAPAN_A_TX_7_MBHC_SAR_ERR] = TAPAN_A_TX_7_MBHC_SAR_ERR__POR,
+ [TAPAN_A_TX_7_TXFE_CLKDIV] = TAPAN_A_TX_7_TXFE_CLKDIV__POR,
+ [TAPAN_A_BUCK_MODE_1] = TAPAN_A_BUCK_MODE_1__POR,
+ [TAPAN_A_BUCK_MODE_2] = TAPAN_A_BUCK_MODE_2__POR,
+ [TAPAN_A_BUCK_MODE_3] = TAPAN_A_BUCK_MODE_3__POR,
+ [TAPAN_A_BUCK_MODE_4] = TAPAN_A_BUCK_MODE_4__POR,
+ [TAPAN_A_BUCK_MODE_5] = TAPAN_A_BUCK_MODE_5__POR,
+ [TAPAN_A_BUCK_CTRL_VCL_1] = TAPAN_A_BUCK_CTRL_VCL_1__POR,
+ [TAPAN_A_BUCK_CTRL_VCL_2] = TAPAN_A_BUCK_CTRL_VCL_2__POR,
+ [TAPAN_A_BUCK_CTRL_VCL_3] = TAPAN_A_BUCK_CTRL_VCL_3__POR,
+ [TAPAN_A_BUCK_CTRL_CCL_1] = TAPAN_A_BUCK_CTRL_CCL_1__POR,
+ [TAPAN_A_BUCK_CTRL_CCL_2] = TAPAN_A_BUCK_CTRL_CCL_2__POR,
+ [TAPAN_A_BUCK_CTRL_CCL_3] = TAPAN_A_BUCK_CTRL_CCL_3__POR,
+ [TAPAN_A_BUCK_CTRL_CCL_4] = TAPAN_A_BUCK_CTRL_CCL_4__POR,
+ [TAPAN_A_BUCK_CTRL_PWM_DRVR_1] = TAPAN_A_BUCK_CTRL_PWM_DRVR_1__POR,
+ [TAPAN_A_BUCK_CTRL_PWM_DRVR_2] = TAPAN_A_BUCK_CTRL_PWM_DRVR_2__POR,
+ [TAPAN_A_BUCK_CTRL_PWM_DRVR_3] = TAPAN_A_BUCK_CTRL_PWM_DRVR_3__POR,
+ [TAPAN_A_BUCK_TMUX_A_D] = TAPAN_A_BUCK_TMUX_A_D__POR,
+ [TAPAN_A_NCP_BUCKREF] = TAPAN_A_NCP_BUCKREF__POR,
+ [TAPAN_A_NCP_EN] = TAPAN_A_NCP_EN__POR,
+ [TAPAN_A_NCP_CLK] = TAPAN_A_NCP_CLK__POR,
+ [TAPAN_A_NCP_STATIC] = TAPAN_A_NCP_STATIC__POR,
+ [TAPAN_A_NCP_VTH_LOW] = TAPAN_A_NCP_VTH_LOW__POR,
+ [TAPAN_A_NCP_VTH_HIGH] = TAPAN_A_NCP_VTH_HIGH__POR,
+ [TAPAN_A_NCP_ATEST] = TAPAN_A_NCP_ATEST__POR,
+ [TAPAN_A_NCP_DTEST] = TAPAN_A_NCP_DTEST__POR,
+ [TAPAN_A_NCP_DLY1] = TAPAN_A_NCP_DLY1__POR,
+ [TAPAN_A_NCP_DLY2] = TAPAN_A_NCP_DLY2__POR,
+ [TAPAN_A_RX_AUX_SW_CTL] = TAPAN_A_RX_AUX_SW_CTL__POR,
+ [TAPAN_A_RX_PA_AUX_IN_CONN] = TAPAN_A_RX_PA_AUX_IN_CONN__POR,
+ [TAPAN_A_RX_COM_TIMER_DIV] = TAPAN_A_RX_COM_TIMER_DIV__POR,
+ [TAPAN_A_RX_COM_OCP_CTL] = TAPAN_A_RX_COM_OCP_CTL__POR,
+ [TAPAN_A_RX_COM_OCP_COUNT] = TAPAN_A_RX_COM_OCP_COUNT__POR,
+ [TAPAN_A_RX_COM_DAC_CTL] = TAPAN_A_RX_COM_DAC_CTL__POR,
+ [TAPAN_A_RX_COM_BIAS] = TAPAN_A_RX_COM_BIAS__POR,
+ [TAPAN_A_RX_HPH_AUTO_CHOP] = TAPAN_A_RX_HPH_AUTO_CHOP__POR,
+ [TAPAN_A_RX_HPH_CHOP_CTL] = TAPAN_A_RX_HPH_CHOP_CTL__POR,
+ [TAPAN_A_RX_HPH_BIAS_PA] = TAPAN_A_RX_HPH_BIAS_PA__POR,
+ [TAPAN_A_RX_HPH_BIAS_LDO] = TAPAN_A_RX_HPH_BIAS_LDO__POR,
+ [TAPAN_A_RX_HPH_BIAS_CNP] = TAPAN_A_RX_HPH_BIAS_CNP__POR,
+ [TAPAN_A_RX_HPH_BIAS_WG_OCP] = TAPAN_A_RX_HPH_BIAS_WG_OCP__POR,
+ [TAPAN_A_RX_HPH_OCP_CTL] = TAPAN_A_RX_HPH_OCP_CTL__POR,
+ [TAPAN_A_RX_HPH_CNP_EN] = TAPAN_A_RX_HPH_CNP_EN__POR,
+ [TAPAN_A_RX_HPH_CNP_WG_CTL] = TAPAN_A_RX_HPH_CNP_WG_CTL__POR,
+ [TAPAN_A_RX_HPH_CNP_WG_TIME] = TAPAN_A_RX_HPH_CNP_WG_TIME__POR,
+ [TAPAN_A_RX_HPH_L_GAIN] = TAPAN_A_RX_HPH_L_GAIN__POR,
+ [TAPAN_A_RX_HPH_L_TEST] = TAPAN_A_RX_HPH_L_TEST__POR,
+ [TAPAN_A_RX_HPH_L_PA_CTL] = TAPAN_A_RX_HPH_L_PA_CTL__POR,
+ [TAPAN_A_RX_HPH_L_DAC_CTL] = TAPAN_A_RX_HPH_L_DAC_CTL__POR,
+ [TAPAN_A_RX_HPH_L_ATEST] = TAPAN_A_RX_HPH_L_ATEST__POR,
+ [TAPAN_A_RX_HPH_L_STATUS] = TAPAN_A_RX_HPH_L_STATUS__POR,
+ [TAPAN_A_RX_HPH_R_GAIN] = TAPAN_A_RX_HPH_R_GAIN__POR,
+ [TAPAN_A_RX_HPH_R_TEST] = TAPAN_A_RX_HPH_R_TEST__POR,
+ [TAPAN_A_RX_HPH_R_PA_CTL] = TAPAN_A_RX_HPH_R_PA_CTL__POR,
+ [TAPAN_A_RX_HPH_R_DAC_CTL] = TAPAN_A_RX_HPH_R_DAC_CTL__POR,
+ [TAPAN_A_RX_HPH_R_ATEST] = TAPAN_A_RX_HPH_R_ATEST__POR,
+ [TAPAN_A_RX_HPH_R_STATUS] = TAPAN_A_RX_HPH_R_STATUS__POR,
+ [TAPAN_A_RX_EAR_BIAS_PA] = TAPAN_A_RX_EAR_BIAS_PA__POR,
+ [TAPAN_A_RX_EAR_BIAS_CMBUFF] = TAPAN_A_RX_EAR_BIAS_CMBUFF__POR,
+ [TAPAN_A_RX_EAR_EN] = TAPAN_A_RX_EAR_EN__POR,
+ [TAPAN_A_RX_EAR_GAIN] = TAPAN_A_RX_EAR_GAIN__POR,
+ [TAPAN_A_RX_EAR_CMBUFF] = TAPAN_A_RX_EAR_CMBUFF__POR,
+ [TAPAN_A_RX_EAR_ICTL] = TAPAN_A_RX_EAR_ICTL__POR,
+ [TAPAN_A_RX_EAR_CCOMP] = TAPAN_A_RX_EAR_CCOMP__POR,
+ [TAPAN_A_RX_EAR_VCM] = TAPAN_A_RX_EAR_VCM__POR,
+ [TAPAN_A_RX_EAR_CNP] = TAPAN_A_RX_EAR_CNP__POR,
+ [TAPAN_A_RX_EAR_DAC_CTL_ATEST] = TAPAN_A_RX_EAR_DAC_CTL_ATEST__POR,
+ [TAPAN_A_RX_EAR_STATUS] = TAPAN_A_RX_EAR_STATUS__POR,
+ [TAPAN_A_RX_LINE_BIAS_PA] = TAPAN_A_RX_LINE_BIAS_PA__POR,
+ [TAPAN_A_RX_BUCK_BIAS1] = TAPAN_A_RX_BUCK_BIAS1__POR,
+ [TAPAN_A_RX_BUCK_BIAS2] = TAPAN_A_RX_BUCK_BIAS2__POR,
+ [TAPAN_A_RX_LINE_COM] = TAPAN_A_RX_LINE_COM__POR,
+ [TAPAN_A_RX_LINE_CNP_EN] = TAPAN_A_RX_LINE_CNP_EN__POR,
+ [TAPAN_A_RX_LINE_CNP_WG_CTL] = TAPAN_A_RX_LINE_CNP_WG_CTL__POR,
+ [TAPAN_A_RX_LINE_CNP_WG_TIME] = TAPAN_A_RX_LINE_CNP_WG_TIME__POR,
+ [TAPAN_A_RX_LINE_1_GAIN] = TAPAN_A_RX_LINE_1_GAIN__POR,
+ [TAPAN_A_RX_LINE_1_TEST] = TAPAN_A_RX_LINE_1_TEST__POR,
+ [TAPAN_A_RX_LINE_1_DAC_CTL] = TAPAN_A_RX_LINE_1_DAC_CTL__POR,
+ [TAPAN_A_RX_LINE_1_STATUS] = TAPAN_A_RX_LINE_1_STATUS__POR,
+ [TAPAN_A_RX_LINE_2_GAIN] = TAPAN_A_RX_LINE_2_GAIN__POR,
+ [TAPAN_A_RX_LINE_2_TEST] = TAPAN_A_RX_LINE_2_TEST__POR,
+ [TAPAN_A_RX_LINE_2_DAC_CTL] = TAPAN_A_RX_LINE_2_DAC_CTL__POR,
+ [TAPAN_A_RX_LINE_2_STATUS] = TAPAN_A_RX_LINE_2_STATUS__POR,
+ [TAPAN_A_RX_LINE_CNP_DBG] = TAPAN_A_RX_LINE_CNP_DBG__POR,
+ [TAPAN_A_SPKR_DRV_EN] = TAPAN_A_SPKR_DRV_EN__POR,
+ [TAPAN_A_SPKR_DRV_GAIN] = TAPAN_A_SPKR_DRV_GAIN__POR,
+ [TAPAN_A_SPKR_DRV_DAC_CTL] = TAPAN_A_SPKR_DRV_DAC_CTL__POR,
+ [TAPAN_A_SPKR_DRV_OCP_CTL] = TAPAN_A_SPKR_DRV_OCP_CTL__POR,
+ [TAPAN_A_SPKR_DRV_CLIP_DET] = TAPAN_A_SPKR_DRV_CLIP_DET__POR,
+ [TAPAN_A_SPKR_DRV_IEC] = TAPAN_A_SPKR_DRV_IEC__POR,
+ [TAPAN_A_SPKR_DRV_DBG_DAC] = TAPAN_A_SPKR_DRV_DBG_DAC__POR,
+ [TAPAN_A_SPKR_DRV_DBG_PA] = TAPAN_A_SPKR_DRV_DBG_PA__POR,
+ [TAPAN_A_SPKR_DRV_DBG_PWRSTG] = TAPAN_A_SPKR_DRV_DBG_PWRSTG__POR,
+ [TAPAN_A_SPKR_DRV_BIAS_LDO] = TAPAN_A_SPKR_DRV_BIAS_LDO__POR,
+ [TAPAN_A_SPKR_DRV_BIAS_INT] = TAPAN_A_SPKR_DRV_BIAS_INT__POR,
+ [TAPAN_A_SPKR_DRV_BIAS_PA] = TAPAN_A_SPKR_DRV_BIAS_PA__POR,
+ [TAPAN_A_SPKR_DRV_STATUS_OCP] = TAPAN_A_SPKR_DRV_STATUS_OCP__POR,
+ [TAPAN_A_SPKR_DRV_STATUS_PA] = TAPAN_A_SPKR_DRV_STATUS_PA__POR,
+ [TAPAN_A_RC_OSC_FREQ] = TAPAN_A_RC_OSC_FREQ__POR,
+ [TAPAN_A_RC_OSC_TEST] = TAPAN_A_RC_OSC_TEST__POR,
+ [TAPAN_A_RC_OSC_STATUS] = TAPAN_A_RC_OSC_STATUS__POR,
+ [TAPAN_A_RC_OSC_TUNER] = TAPAN_A_RC_OSC_TUNER__POR,
+ [TAPAN_A_MBHC_HPH] = TAPAN_A_MBHC_HPH__POR,
+ [TAPAN_A_CDC_ANC1_B1_CTL] = TAPAN_A_CDC_ANC1_B1_CTL__POR,
+ [TAPAN_A_CDC_ANC2_B1_CTL] = TAPAN_A_CDC_ANC2_B1_CTL__POR,
+ [TAPAN_A_CDC_ANC1_SHIFT] = TAPAN_A_CDC_ANC1_SHIFT__POR,
+ [TAPAN_A_CDC_ANC2_SHIFT] = TAPAN_A_CDC_ANC2_SHIFT__POR,
+ [TAPAN_A_CDC_ANC1_IIR_B1_CTL] = TAPAN_A_CDC_ANC1_IIR_B1_CTL__POR,
+ [TAPAN_A_CDC_ANC2_IIR_B1_CTL] = TAPAN_A_CDC_ANC2_IIR_B1_CTL__POR,
+ [TAPAN_A_CDC_ANC1_IIR_B2_CTL] = TAPAN_A_CDC_ANC1_IIR_B2_CTL__POR,
+ [TAPAN_A_CDC_ANC2_IIR_B2_CTL] = TAPAN_A_CDC_ANC2_IIR_B2_CTL__POR,
+ [TAPAN_A_CDC_ANC1_IIR_B3_CTL] = TAPAN_A_CDC_ANC1_IIR_B3_CTL__POR,
+ [TAPAN_A_CDC_ANC2_IIR_B3_CTL] = TAPAN_A_CDC_ANC2_IIR_B3_CTL__POR,
+ [TAPAN_A_CDC_ANC1_LPF_B1_CTL] = TAPAN_A_CDC_ANC1_LPF_B1_CTL__POR,
+ [TAPAN_A_CDC_ANC2_LPF_B1_CTL] = TAPAN_A_CDC_ANC2_LPF_B1_CTL__POR,
+ [TAPAN_A_CDC_ANC1_LPF_B2_CTL] = TAPAN_A_CDC_ANC1_LPF_B2_CTL__POR,
+ [TAPAN_A_CDC_ANC2_LPF_B2_CTL] = TAPAN_A_CDC_ANC2_LPF_B2_CTL__POR,
+ [TAPAN_A_CDC_ANC1_SPARE] = TAPAN_A_CDC_ANC1_SPARE__POR,
+ [TAPAN_A_CDC_ANC2_SPARE] = TAPAN_A_CDC_ANC2_SPARE__POR,
+ [TAPAN_A_CDC_ANC1_SMLPF_CTL] = TAPAN_A_CDC_ANC1_SMLPF_CTL__POR,
+ [TAPAN_A_CDC_ANC2_SMLPF_CTL] = TAPAN_A_CDC_ANC2_SMLPF_CTL__POR,
+ [TAPAN_A_CDC_ANC1_DCFLT_CTL] = TAPAN_A_CDC_ANC1_DCFLT_CTL__POR,
+ [TAPAN_A_CDC_ANC2_DCFLT_CTL] = TAPAN_A_CDC_ANC2_DCFLT_CTL__POR,
+ [TAPAN_A_CDC_ANC1_GAIN_CTL] = TAPAN_A_CDC_ANC1_GAIN_CTL__POR,
+ [TAPAN_A_CDC_ANC2_GAIN_CTL] = TAPAN_A_CDC_ANC2_GAIN_CTL__POR,
+ [TAPAN_A_CDC_ANC1_B2_CTL] = TAPAN_A_CDC_ANC1_B2_CTL__POR,
+ [TAPAN_A_CDC_ANC2_B2_CTL] = TAPAN_A_CDC_ANC2_B2_CTL__POR,
+ [TAPAN_A_CDC_TX1_VOL_CTL_TIMER] = TAPAN_A_CDC_TX1_VOL_CTL_TIMER__POR,
+ [TAPAN_A_CDC_TX2_VOL_CTL_TIMER] = TAPAN_A_CDC_TX2_VOL_CTL_TIMER__POR,
+ [TAPAN_A_CDC_TX3_VOL_CTL_TIMER] = TAPAN_A_CDC_TX3_VOL_CTL_TIMER__POR,
+ [TAPAN_A_CDC_TX4_VOL_CTL_TIMER] = TAPAN_A_CDC_TX4_VOL_CTL_TIMER__POR,
+ [TAPAN_A_CDC_TX1_VOL_CTL_GAIN] = TAPAN_A_CDC_TX1_VOL_CTL_GAIN__POR,
+ [TAPAN_A_CDC_TX2_VOL_CTL_GAIN] = TAPAN_A_CDC_TX2_VOL_CTL_GAIN__POR,
+ [TAPAN_A_CDC_TX3_VOL_CTL_GAIN] = TAPAN_A_CDC_TX3_VOL_CTL_GAIN__POR,
+ [TAPAN_A_CDC_TX4_VOL_CTL_GAIN] = TAPAN_A_CDC_TX4_VOL_CTL_GAIN__POR,
+ [TAPAN_A_CDC_TX1_VOL_CTL_CFG] = TAPAN_A_CDC_TX1_VOL_CTL_CFG__POR,
+ [TAPAN_A_CDC_TX2_VOL_CTL_CFG] = TAPAN_A_CDC_TX2_VOL_CTL_CFG__POR,
+ [TAPAN_A_CDC_TX3_VOL_CTL_CFG] = TAPAN_A_CDC_TX3_VOL_CTL_CFG__POR,
+ [TAPAN_A_CDC_TX4_VOL_CTL_CFG] = TAPAN_A_CDC_TX4_VOL_CTL_CFG__POR,
+ [TAPAN_A_CDC_TX1_MUX_CTL] = TAPAN_A_CDC_TX1_MUX_CTL__POR,
+ [TAPAN_A_CDC_TX2_MUX_CTL] = TAPAN_A_CDC_TX2_MUX_CTL__POR,
+ [TAPAN_A_CDC_TX3_MUX_CTL] = TAPAN_A_CDC_TX3_MUX_CTL__POR,
+ [TAPAN_A_CDC_TX4_MUX_CTL] = TAPAN_A_CDC_TX4_MUX_CTL__POR,
+ [TAPAN_A_CDC_TX1_CLK_FS_CTL] = TAPAN_A_CDC_TX1_CLK_FS_CTL__POR,
+ [TAPAN_A_CDC_TX2_CLK_FS_CTL] = TAPAN_A_CDC_TX2_CLK_FS_CTL__POR,
+ [TAPAN_A_CDC_TX3_CLK_FS_CTL] = TAPAN_A_CDC_TX3_CLK_FS_CTL__POR,
+ [TAPAN_A_CDC_TX4_CLK_FS_CTL] = TAPAN_A_CDC_TX4_CLK_FS_CTL__POR,
+ [TAPAN_A_CDC_TX1_DMIC_CTL] = TAPAN_A_CDC_TX1_DMIC_CTL__POR,
+ [TAPAN_A_CDC_TX2_DMIC_CTL] = TAPAN_A_CDC_TX2_DMIC_CTL__POR,
+ [TAPAN_A_CDC_TX3_DMIC_CTL] = TAPAN_A_CDC_TX3_DMIC_CTL__POR,
+ [TAPAN_A_CDC_TX4_DMIC_CTL] = TAPAN_A_CDC_TX4_DMIC_CTL__POR,
+ [TAPAN_A_CDC_DEBUG_B1_CTL] = TAPAN_A_CDC_DEBUG_B1_CTL__POR,
+ [TAPAN_A_CDC_DEBUG_B2_CTL] = TAPAN_A_CDC_DEBUG_B2_CTL__POR,
+ [TAPAN_A_CDC_DEBUG_B3_CTL] = TAPAN_A_CDC_DEBUG_B3_CTL__POR,
+ [TAPAN_A_CDC_DEBUG_B4_CTL] = TAPAN_A_CDC_DEBUG_B4_CTL__POR,
+ [TAPAN_A_CDC_DEBUG_B5_CTL] = TAPAN_A_CDC_DEBUG_B5_CTL__POR,
+ [TAPAN_A_CDC_DEBUG_B6_CTL] = TAPAN_A_CDC_DEBUG_B6_CTL__POR,
+ [TAPAN_A_CDC_DEBUG_B7_CTL] = TAPAN_A_CDC_DEBUG_B7_CTL__POR,
+ [TAPAN_A_CDC_SRC1_PDA_CFG] = TAPAN_A_CDC_SRC1_PDA_CFG__POR,
+ [TAPAN_A_CDC_SRC2_PDA_CFG] = TAPAN_A_CDC_SRC2_PDA_CFG__POR,
+ [TAPAN_A_CDC_SRC1_FS_CTL] = TAPAN_A_CDC_SRC1_FS_CTL__POR,
+ [TAPAN_A_CDC_SRC2_FS_CTL] = TAPAN_A_CDC_SRC2_FS_CTL__POR,
+ [TAPAN_A_CDC_RX1_B1_CTL] = TAPAN_A_CDC_RX1_B1_CTL__POR,
+ [TAPAN_A_CDC_RX2_B1_CTL] = TAPAN_A_CDC_RX2_B1_CTL__POR,
+ [TAPAN_A_CDC_RX3_B1_CTL] = TAPAN_A_CDC_RX3_B1_CTL__POR,
+ [TAPAN_A_CDC_RX4_B1_CTL] = TAPAN_A_CDC_RX4_B1_CTL__POR,
+ [TAPAN_A_CDC_RX1_B2_CTL] = TAPAN_A_CDC_RX1_B2_CTL__POR,
+ [TAPAN_A_CDC_RX2_B2_CTL] = TAPAN_A_CDC_RX2_B2_CTL__POR,
+ [TAPAN_A_CDC_RX3_B2_CTL] = TAPAN_A_CDC_RX3_B2_CTL__POR,
+ [TAPAN_A_CDC_RX4_B2_CTL] = TAPAN_A_CDC_RX4_B2_CTL__POR,
+ [TAPAN_A_CDC_RX1_B3_CTL] = TAPAN_A_CDC_RX1_B3_CTL__POR,
+ [TAPAN_A_CDC_RX2_B3_CTL] = TAPAN_A_CDC_RX2_B3_CTL__POR,
+ [TAPAN_A_CDC_RX3_B3_CTL] = TAPAN_A_CDC_RX3_B3_CTL__POR,
+ [TAPAN_A_CDC_RX4_B3_CTL] = TAPAN_A_CDC_RX4_B3_CTL__POR,
+ [TAPAN_A_CDC_RX1_B4_CTL] = TAPAN_A_CDC_RX1_B4_CTL__POR,
+ [TAPAN_A_CDC_RX2_B4_CTL] = TAPAN_A_CDC_RX2_B4_CTL__POR,
+ [TAPAN_A_CDC_RX3_B4_CTL] = TAPAN_A_CDC_RX3_B4_CTL__POR,
+ [TAPAN_A_CDC_RX4_B4_CTL] = TAPAN_A_CDC_RX4_B4_CTL__POR,
+ [TAPAN_A_CDC_RX1_B5_CTL] = TAPAN_A_CDC_RX1_B5_CTL__POR,
+ [TAPAN_A_CDC_RX2_B5_CTL] = TAPAN_A_CDC_RX2_B5_CTL__POR,
+ [TAPAN_A_CDC_RX3_B5_CTL] = TAPAN_A_CDC_RX3_B5_CTL__POR,
+ [TAPAN_A_CDC_RX4_B5_CTL] = TAPAN_A_CDC_RX4_B5_CTL__POR,
+ [TAPAN_A_CDC_RX1_B6_CTL] = TAPAN_A_CDC_RX1_B6_CTL__POR,
+ [TAPAN_A_CDC_RX2_B6_CTL] = TAPAN_A_CDC_RX2_B6_CTL__POR,
+ [TAPAN_A_CDC_RX3_B6_CTL] = TAPAN_A_CDC_RX3_B6_CTL__POR,
+ [TAPAN_A_CDC_RX4_B6_CTL] = TAPAN_A_CDC_RX4_B6_CTL__POR,
+ [TAPAN_A_CDC_RX1_VOL_CTL_B1_CTL] = TAPAN_A_CDC_RX1_VOL_CTL_B1_CTL__POR,
+ [TAPAN_A_CDC_RX2_VOL_CTL_B1_CTL] = TAPAN_A_CDC_RX2_VOL_CTL_B1_CTL__POR,
+ [TAPAN_A_CDC_RX3_VOL_CTL_B1_CTL] = TAPAN_A_CDC_RX3_VOL_CTL_B1_CTL__POR,
+ [TAPAN_A_CDC_RX4_VOL_CTL_B1_CTL] = TAPAN_A_CDC_RX4_VOL_CTL_B1_CTL__POR,
+ [TAPAN_A_CDC_RX1_VOL_CTL_B2_CTL] = TAPAN_A_CDC_RX1_VOL_CTL_B2_CTL__POR,
+ [TAPAN_A_CDC_RX2_VOL_CTL_B2_CTL] = TAPAN_A_CDC_RX2_VOL_CTL_B2_CTL__POR,
+ [TAPAN_A_CDC_RX3_VOL_CTL_B2_CTL] = TAPAN_A_CDC_RX3_VOL_CTL_B2_CTL__POR,
+ [TAPAN_A_CDC_RX4_VOL_CTL_B2_CTL] = TAPAN_A_CDC_RX4_VOL_CTL_B2_CTL__POR,
+ [TAPAN_A_CDC_CLK_ANC_RESET_CTL] = TAPAN_A_CDC_CLK_ANC_RESET_CTL__POR,
+ [TAPAN_A_CDC_CLK_RX_RESET_CTL] = TAPAN_A_CDC_CLK_RX_RESET_CTL__POR,
+ [TAPAN_A_CDC_CLK_TX_RESET_B1_CTL] =
+ TAPAN_A_CDC_CLK_TX_RESET_B1_CTL__POR,
+ [TAPAN_A_CDC_CLK_TX_RESET_B2_CTL] =
+ TAPAN_A_CDC_CLK_TX_RESET_B2_CTL__POR,
+ [TAPAN_A_CDC_CLK_DMIC_B1_CTL] = TAPAN_A_CDC_CLK_DMIC_B1_CTL__POR,
+ [TAPAN_A_CDC_CLK_DMIC_B2_CTL] = TAPAN_A_CDC_CLK_DMIC_B2_CTL__POR,
+ [TAPAN_A_CDC_CLK_I2S_CTL] = TAPAN_A_CDC_CLK_I2S_CTL__POR,
+ [TAPAN_A_CDC_CLK_OTHR_RESET_B1_CTL] =
+ TAPAN_A_CDC_CLK_OTHR_RESET_B1_CTL__POR,
+ [TAPAN_A_CDC_CLK_OTHR_RESET_B2_CTL] =
+ TAPAN_A_CDC_CLK_OTHR_RESET_B2_CTL__POR,
+ [TAPAN_A_CDC_CLK_TX_CLK_EN_B1_CTL] =
+ TAPAN_A_CDC_CLK_TX_CLK_EN_B1_CTL__POR,
+ [TAPAN_A_CDC_CLK_TX_CLK_EN_B2_CTL] =
+ TAPAN_A_CDC_CLK_TX_CLK_EN_B2_CTL__POR,
+ [TAPAN_A_CDC_CLK_OTHR_CTL] = TAPAN_A_CDC_CLK_OTHR_CTL__POR,
+ [TAPAN_A_CDC_CLK_RDAC_CLK_EN_CTL] =
+ TAPAN_A_CDC_CLK_RDAC_CLK_EN_CTL__POR,
+ [TAPAN_A_CDC_CLK_ANC_CLK_EN_CTL] = TAPAN_A_CDC_CLK_ANC_CLK_EN_CTL__POR,
+ [TAPAN_A_CDC_CLK_RX_B1_CTL] = TAPAN_A_CDC_CLK_RX_B1_CTL__POR,
+ [TAPAN_A_CDC_CLK_RX_B2_CTL] = TAPAN_A_CDC_CLK_RX_B2_CTL__POR,
+ [TAPAN_A_CDC_CLK_MCLK_CTL] = TAPAN_A_CDC_CLK_MCLK_CTL__POR,
+ [TAPAN_A_CDC_CLK_PDM_CTL] = TAPAN_A_CDC_CLK_PDM_CTL__POR,
+ [TAPAN_A_CDC_CLK_SD_CTL] = TAPAN_A_CDC_CLK_SD_CTL__POR,
+ [TAPAN_A_CDC_CLK_POWER_CTL] = TAPAN_A_CDC_CLK_POWER_CTL__POR,
+ [TAPAN_A_CDC_CLSH_B1_CTL] = TAPAN_A_CDC_CLSH_B1_CTL__POR,
+ [TAPAN_A_CDC_CLSH_B2_CTL] = TAPAN_A_CDC_CLSH_B2_CTL__POR,
+ [TAPAN_A_CDC_CLSH_B3_CTL] = TAPAN_A_CDC_CLSH_B3_CTL__POR,
+ [TAPAN_A_CDC_CLSH_BUCK_NCP_VARS] = TAPAN_A_CDC_CLSH_BUCK_NCP_VARS__POR,
+ [TAPAN_A_CDC_CLSH_IDLE_HPH_THSD] = TAPAN_A_CDC_CLSH_IDLE_HPH_THSD__POR,
+ [TAPAN_A_CDC_CLSH_IDLE_EAR_THSD] = TAPAN_A_CDC_CLSH_IDLE_EAR_THSD__POR,
+ [TAPAN_A_CDC_CLSH_FCLKONLY_HPH_THSD] =
+ TAPAN_A_CDC_CLSH_FCLKONLY_HPH_THSD__POR,
+ [TAPAN_A_CDC_CLSH_FCLKONLY_EAR_THSD] =
+ TAPAN_A_CDC_CLSH_FCLKONLY_EAR_THSD__POR,
+ [TAPAN_A_CDC_CLSH_K_ADDR] = TAPAN_A_CDC_CLSH_K_ADDR__POR,
+ [TAPAN_A_CDC_CLSH_K_DATA] = TAPAN_A_CDC_CLSH_K_DATA__POR,
+ [TAPAN_A_CDC_CLSH_I_PA_FACT_HPH_L] =
+ TAPAN_A_CDC_CLSH_I_PA_FACT_HPH_L__POR,
+ [TAPAN_A_CDC_CLSH_I_PA_FACT_HPH_U] =
+ TAPAN_A_CDC_CLSH_I_PA_FACT_HPH_U__POR,
+ [TAPAN_A_CDC_CLSH_I_PA_FACT_EAR_L] =
+ TAPAN_A_CDC_CLSH_I_PA_FACT_EAR_L__POR,
+ [TAPAN_A_CDC_CLSH_I_PA_FACT_EAR_U] =
+ TAPAN_A_CDC_CLSH_I_PA_FACT_EAR_U__POR,
+ [TAPAN_A_CDC_CLSH_V_PA_HD_EAR] = TAPAN_A_CDC_CLSH_V_PA_HD_EAR__POR,
+ [TAPAN_A_CDC_CLSH_V_PA_HD_HPH] = TAPAN_A_CDC_CLSH_V_PA_HD_HPH__POR,
+ [TAPAN_A_CDC_CLSH_V_PA_MIN_EAR] = TAPAN_A_CDC_CLSH_V_PA_MIN_EAR__POR,
+ [TAPAN_A_CDC_CLSH_V_PA_MIN_HPH] = TAPAN_A_CDC_CLSH_V_PA_MIN_HPH__POR,
+ [TAPAN_A_CDC_IIR1_GAIN_B1_CTL] = TAPAN_A_CDC_IIR1_GAIN_B1_CTL__POR,
+ [TAPAN_A_CDC_IIR2_GAIN_B1_CTL] = TAPAN_A_CDC_IIR2_GAIN_B1_CTL__POR,
+ [TAPAN_A_CDC_IIR1_GAIN_B2_CTL] = TAPAN_A_CDC_IIR1_GAIN_B2_CTL__POR,
+ [TAPAN_A_CDC_IIR2_GAIN_B2_CTL] = TAPAN_A_CDC_IIR2_GAIN_B2_CTL__POR,
+ [TAPAN_A_CDC_IIR1_GAIN_B3_CTL] = TAPAN_A_CDC_IIR1_GAIN_B3_CTL__POR,
+ [TAPAN_A_CDC_IIR2_GAIN_B3_CTL] = TAPAN_A_CDC_IIR2_GAIN_B3_CTL__POR,
+ [TAPAN_A_CDC_IIR1_GAIN_B4_CTL] = TAPAN_A_CDC_IIR1_GAIN_B4_CTL__POR,
+ [TAPAN_A_CDC_IIR2_GAIN_B4_CTL] = TAPAN_A_CDC_IIR2_GAIN_B4_CTL__POR,
+ [TAPAN_A_CDC_IIR1_GAIN_B5_CTL] = TAPAN_A_CDC_IIR1_GAIN_B5_CTL__POR,
+ [TAPAN_A_CDC_IIR2_GAIN_B5_CTL] = TAPAN_A_CDC_IIR2_GAIN_B5_CTL__POR,
+ [TAPAN_A_CDC_IIR1_GAIN_B6_CTL] = TAPAN_A_CDC_IIR1_GAIN_B6_CTL__POR,
+ [TAPAN_A_CDC_IIR2_GAIN_B6_CTL] = TAPAN_A_CDC_IIR2_GAIN_B6_CTL__POR,
+ [TAPAN_A_CDC_IIR1_GAIN_B7_CTL] = TAPAN_A_CDC_IIR1_GAIN_B7_CTL__POR,
+ [TAPAN_A_CDC_IIR2_GAIN_B7_CTL] = TAPAN_A_CDC_IIR2_GAIN_B7_CTL__POR,
+ [TAPAN_A_CDC_IIR1_GAIN_B8_CTL] = TAPAN_A_CDC_IIR1_GAIN_B8_CTL__POR,
+ [TAPAN_A_CDC_IIR2_GAIN_B8_CTL] = TAPAN_A_CDC_IIR2_GAIN_B8_CTL__POR,
+ [TAPAN_A_CDC_IIR1_CTL] = TAPAN_A_CDC_IIR1_CTL__POR,
+ [TAPAN_A_CDC_IIR2_CTL] = TAPAN_A_CDC_IIR2_CTL__POR,
+ [TAPAN_A_CDC_IIR1_GAIN_TIMER_CTL] =
+ TAPAN_A_CDC_IIR1_GAIN_TIMER_CTL__POR,
+ [TAPAN_A_CDC_IIR2_GAIN_TIMER_CTL] =
+ TAPAN_A_CDC_IIR2_GAIN_TIMER_CTL__POR,
+ [TAPAN_A_CDC_IIR1_COEF_B1_CTL] = TAPAN_A_CDC_IIR1_COEF_B1_CTL__POR,
+ [TAPAN_A_CDC_IIR2_COEF_B1_CTL] = TAPAN_A_CDC_IIR2_COEF_B1_CTL__POR,
+ [TAPAN_A_CDC_IIR1_COEF_B2_CTL] = TAPAN_A_CDC_IIR1_COEF_B2_CTL__POR,
+ [TAPAN_A_CDC_IIR2_COEF_B2_CTL] = TAPAN_A_CDC_IIR2_COEF_B2_CTL__POR,
+ [TAPAN_A_CDC_TOP_GAIN_UPDATE] = TAPAN_A_CDC_TOP_GAIN_UPDATE__POR,
+ [TAPAN_A_CDC_COMP0_B1_CTL] = TAPAN_A_CDC_COMP0_B1_CTL__POR,
+ [TAPAN_A_CDC_COMP1_B1_CTL] = TAPAN_A_CDC_COMP1_B1_CTL__POR,
+ [TAPAN_A_CDC_COMP2_B1_CTL] = TAPAN_A_CDC_COMP2_B1_CTL__POR,
+ [TAPAN_A_CDC_COMP0_B2_CTL] = TAPAN_A_CDC_COMP0_B2_CTL__POR,
+ [TAPAN_A_CDC_COMP1_B2_CTL] = TAPAN_A_CDC_COMP1_B2_CTL__POR,
+ [TAPAN_A_CDC_COMP2_B2_CTL] = TAPAN_A_CDC_COMP2_B2_CTL__POR,
+ [TAPAN_A_CDC_COMP0_B3_CTL] = TAPAN_A_CDC_COMP0_B3_CTL__POR,
+ [TAPAN_A_CDC_COMP1_B3_CTL] = TAPAN_A_CDC_COMP1_B3_CTL__POR,
+ [TAPAN_A_CDC_COMP2_B3_CTL] = TAPAN_A_CDC_COMP2_B3_CTL__POR,
+ [TAPAN_A_CDC_COMP0_B4_CTL] = TAPAN_A_CDC_COMP0_B4_CTL__POR,
+ [TAPAN_A_CDC_COMP1_B4_CTL] = TAPAN_A_CDC_COMP1_B4_CTL__POR,
+ [TAPAN_A_CDC_COMP2_B4_CTL] = TAPAN_A_CDC_COMP2_B4_CTL__POR,
+ [TAPAN_A_CDC_COMP0_B5_CTL] = TAPAN_A_CDC_COMP0_B5_CTL__POR,
+ [TAPAN_A_CDC_COMP1_B5_CTL] = TAPAN_A_CDC_COMP1_B5_CTL__POR,
+ [TAPAN_A_CDC_COMP2_B5_CTL] = TAPAN_A_CDC_COMP2_B5_CTL__POR,
+ [TAPAN_A_CDC_COMP0_B6_CTL] = TAPAN_A_CDC_COMP0_B6_CTL__POR,
+ [TAPAN_A_CDC_COMP1_B6_CTL] = TAPAN_A_CDC_COMP1_B6_CTL__POR,
+ [TAPAN_A_CDC_COMP2_B6_CTL] = TAPAN_A_CDC_COMP2_B6_CTL__POR,
+ [TAPAN_A_CDC_COMP0_SHUT_DOWN_STATUS] =
+ TAPAN_A_CDC_COMP0_SHUT_DOWN_STATUS__POR,
+ [TAPAN_A_CDC_COMP1_SHUT_DOWN_STATUS] =
+ TAPAN_A_CDC_COMP1_SHUT_DOWN_STATUS__POR,
+ [TAPAN_A_CDC_COMP2_SHUT_DOWN_STATUS] =
+ TAPAN_A_CDC_COMP2_SHUT_DOWN_STATUS__POR,
+ [TAPAN_A_CDC_COMP0_FS_CFG] = TAPAN_A_CDC_COMP0_FS_CFG__POR,
+ [TAPAN_A_CDC_COMP1_FS_CFG] = TAPAN_A_CDC_COMP1_FS_CFG__POR,
+ [TAPAN_A_CDC_COMP2_FS_CFG] = TAPAN_A_CDC_COMP2_FS_CFG__POR,
+ [TAPAN_A_CDC_CONN_RX1_B1_CTL] = TAPAN_A_CDC_CONN_RX1_B1_CTL__POR,
+ [TAPAN_A_CDC_CONN_RX1_B2_CTL] = TAPAN_A_CDC_CONN_RX1_B2_CTL__POR,
+ [TAPAN_A_CDC_CONN_RX1_B3_CTL] = TAPAN_A_CDC_CONN_RX1_B3_CTL__POR,
+ [TAPAN_A_CDC_CONN_RX2_B1_CTL] = TAPAN_A_CDC_CONN_RX2_B1_CTL__POR,
+ [TAPAN_A_CDC_CONN_RX2_B2_CTL] = TAPAN_A_CDC_CONN_RX2_B2_CTL__POR,
+ [TAPAN_A_CDC_CONN_RX2_B3_CTL] = TAPAN_A_CDC_CONN_RX2_B3_CTL__POR,
+ [TAPAN_A_CDC_CONN_RX3_B1_CTL] = TAPAN_A_CDC_CONN_RX3_B1_CTL__POR,
+ [TAPAN_A_CDC_CONN_RX3_B2_CTL] = TAPAN_A_CDC_CONN_RX3_B2_CTL__POR,
+ [TAPAN_A_CDC_CONN_RX4_B1_CTL] = TAPAN_A_CDC_CONN_RX4_B1_CTL__POR,
+ [TAPAN_A_CDC_CONN_RX4_B2_CTL] = TAPAN_A_CDC_CONN_RX4_B2_CTL__POR,
+ [TAPAN_A_CDC_CONN_RX4_B3_CTL] = TAPAN_A_CDC_CONN_RX4_B3_CTL__POR,
+ [TAPAN_A_CDC_CONN_ANC_B1_CTL] = TAPAN_A_CDC_CONN_ANC_B1_CTL__POR,
+ [TAPAN_A_CDC_CONN_ANC_B2_CTL] = TAPAN_A_CDC_CONN_ANC_B2_CTL__POR,
+ [TAPAN_A_CDC_CONN_TX_B1_CTL] = TAPAN_A_CDC_CONN_TX_B1_CTL__POR,
+ [TAPAN_A_CDC_CONN_TX_B2_CTL] = TAPAN_A_CDC_CONN_TX_B2_CTL__POR,
+ [TAPAN_A_CDC_CONN_TX_B3_CTL] = TAPAN_A_CDC_CONN_TX_B3_CTL__POR,
+ [TAPAN_A_CDC_CONN_TX_B4_CTL] = TAPAN_A_CDC_CONN_TX_B4_CTL__POR,
+ [TAPAN_A_CDC_CONN_EQ1_B1_CTL] = TAPAN_A_CDC_CONN_EQ1_B1_CTL__POR,
+ [TAPAN_A_CDC_CONN_EQ1_B2_CTL] = TAPAN_A_CDC_CONN_EQ1_B2_CTL__POR,
+ [TAPAN_A_CDC_CONN_EQ1_B3_CTL] = TAPAN_A_CDC_CONN_EQ1_B3_CTL__POR,
+ [TAPAN_A_CDC_CONN_EQ1_B4_CTL] = TAPAN_A_CDC_CONN_EQ1_B4_CTL__POR,
+ [TAPAN_A_CDC_CONN_EQ2_B1_CTL] = TAPAN_A_CDC_CONN_EQ2_B1_CTL__POR,
+ [TAPAN_A_CDC_CONN_EQ2_B2_CTL] = TAPAN_A_CDC_CONN_EQ2_B2_CTL__POR,
+ [TAPAN_A_CDC_CONN_EQ2_B3_CTL] = TAPAN_A_CDC_CONN_EQ2_B3_CTL__POR,
+ [TAPAN_A_CDC_CONN_EQ2_B4_CTL] = TAPAN_A_CDC_CONN_EQ2_B4_CTL__POR,
+ [TAPAN_A_CDC_CONN_SRC1_B1_CTL] = TAPAN_A_CDC_CONN_SRC1_B1_CTL__POR,
+ [TAPAN_A_CDC_CONN_SRC1_B2_CTL] = TAPAN_A_CDC_CONN_SRC1_B2_CTL__POR,
+ [TAPAN_A_CDC_CONN_SRC2_B1_CTL] = TAPAN_A_CDC_CONN_SRC2_B1_CTL__POR,
+ [TAPAN_A_CDC_CONN_SRC2_B2_CTL] = TAPAN_A_CDC_CONN_SRC2_B2_CTL__POR,
+ [TAPAN_A_CDC_CONN_TX_SB_B1_CTL] = TAPAN_A_CDC_CONN_TX_SB_B1_CTL__POR,
+ [TAPAN_A_CDC_CONN_TX_SB_B2_CTL] = TAPAN_A_CDC_CONN_TX_SB_B2_CTL__POR,
+ [TAPAN_A_CDC_CONN_TX_SB_B3_CTL] = TAPAN_A_CDC_CONN_TX_SB_B3_CTL__POR,
+ [TAPAN_A_CDC_CONN_TX_SB_B4_CTL] = TAPAN_A_CDC_CONN_TX_SB_B4_CTL__POR,
+ [TAPAN_A_CDC_CONN_TX_SB_B5_CTL] = TAPAN_A_CDC_CONN_TX_SB_B5_CTL__POR,
+ [TAPAN_A_CDC_CONN_TX_SB_B11_CTL] = TAPAN_A_CDC_CONN_TX_SB_B11_CTL__POR,
+ [TAPAN_A_CDC_CONN_RX_SB_B1_CTL] = TAPAN_A_CDC_CONN_RX_SB_B1_CTL__POR,
+ [TAPAN_A_CDC_CONN_RX_SB_B2_CTL] = TAPAN_A_CDC_CONN_RX_SB_B2_CTL__POR,
+ [TAPAN_A_CDC_CONN_CLSH_CTL] = TAPAN_A_CDC_CONN_CLSH_CTL__POR,
+ [TAPAN_A_CDC_CONN_MISC] = TAPAN_A_CDC_CONN_MISC__POR,
+ [TAPAN_A_CDC_MBHC_EN_CTL] = TAPAN_A_CDC_MBHC_EN_CTL__POR,
+ [TAPAN_A_CDC_MBHC_FIR_B1_CFG] = TAPAN_A_CDC_MBHC_FIR_B1_CFG__POR,
+ [TAPAN_A_CDC_MBHC_FIR_B2_CFG] = TAPAN_A_CDC_MBHC_FIR_B2_CFG__POR,
+ [TAPAN_A_CDC_MBHC_TIMER_B1_CTL] = TAPAN_A_CDC_MBHC_TIMER_B1_CTL__POR,
+ [TAPAN_A_CDC_MBHC_TIMER_B2_CTL] = TAPAN_A_CDC_MBHC_TIMER_B2_CTL__POR,
+ [TAPAN_A_CDC_MBHC_TIMER_B3_CTL] = TAPAN_A_CDC_MBHC_TIMER_B3_CTL__POR,
+ [TAPAN_A_CDC_MBHC_TIMER_B4_CTL] = TAPAN_A_CDC_MBHC_TIMER_B4_CTL__POR,
+ [TAPAN_A_CDC_MBHC_TIMER_B5_CTL] = TAPAN_A_CDC_MBHC_TIMER_B5_CTL__POR,
+ [TAPAN_A_CDC_MBHC_TIMER_B6_CTL] = TAPAN_A_CDC_MBHC_TIMER_B6_CTL__POR,
+ [TAPAN_A_CDC_MBHC_B1_STATUS] = TAPAN_A_CDC_MBHC_B1_STATUS__POR,
+ [TAPAN_A_CDC_MBHC_B2_STATUS] = TAPAN_A_CDC_MBHC_B2_STATUS__POR,
+ [TAPAN_A_CDC_MBHC_B3_STATUS] = TAPAN_A_CDC_MBHC_B3_STATUS__POR,
+ [TAPAN_A_CDC_MBHC_B4_STATUS] = TAPAN_A_CDC_MBHC_B4_STATUS__POR,
+ [TAPAN_A_CDC_MBHC_B5_STATUS] = TAPAN_A_CDC_MBHC_B5_STATUS__POR,
+ [TAPAN_A_CDC_MBHC_B1_CTL] = TAPAN_A_CDC_MBHC_B1_CTL__POR,
+ [TAPAN_A_CDC_MBHC_B2_CTL] = TAPAN_A_CDC_MBHC_B2_CTL__POR,
+ [TAPAN_A_CDC_MBHC_VOLT_B1_CTL] = TAPAN_A_CDC_MBHC_VOLT_B1_CTL__POR,
+ [TAPAN_A_CDC_MBHC_VOLT_B2_CTL] = TAPAN_A_CDC_MBHC_VOLT_B2_CTL__POR,
+ [TAPAN_A_CDC_MBHC_VOLT_B3_CTL] = TAPAN_A_CDC_MBHC_VOLT_B3_CTL__POR,
+ [TAPAN_A_CDC_MBHC_VOLT_B4_CTL] = TAPAN_A_CDC_MBHC_VOLT_B4_CTL__POR,
+ [TAPAN_A_CDC_MBHC_VOLT_B5_CTL] = TAPAN_A_CDC_MBHC_VOLT_B5_CTL__POR,
+ [TAPAN_A_CDC_MBHC_VOLT_B6_CTL] = TAPAN_A_CDC_MBHC_VOLT_B6_CTL__POR,
+ [TAPAN_A_CDC_MBHC_VOLT_B7_CTL] = TAPAN_A_CDC_MBHC_VOLT_B7_CTL__POR,
+ [TAPAN_A_CDC_MBHC_VOLT_B8_CTL] = TAPAN_A_CDC_MBHC_VOLT_B8_CTL__POR,
+ [TAPAN_A_CDC_MBHC_VOLT_B9_CTL] = TAPAN_A_CDC_MBHC_VOLT_B9_CTL__POR,
+ [TAPAN_A_CDC_MBHC_VOLT_B10_CTL] = TAPAN_A_CDC_MBHC_VOLT_B10_CTL__POR,
+ [TAPAN_A_CDC_MBHC_VOLT_B11_CTL] = TAPAN_A_CDC_MBHC_VOLT_B11_CTL__POR,
+ [TAPAN_A_CDC_MBHC_VOLT_B12_CTL] = TAPAN_A_CDC_MBHC_VOLT_B12_CTL__POR,
+ [TAPAN_A_CDC_MBHC_CLK_CTL] = TAPAN_A_CDC_MBHC_CLK_CTL__POR,
+ [TAPAN_A_CDC_MBHC_INT_CTL] = TAPAN_A_CDC_MBHC_INT_CTL__POR,
+ [TAPAN_A_CDC_MBHC_DEBUG_CTL] = TAPAN_A_CDC_MBHC_DEBUG_CTL__POR,
+ [TAPAN_A_CDC_MBHC_SPARE] = TAPAN_A_CDC_MBHC_SPARE__POR,
+};
diff --git a/sound/soc/codecs/wcd9306.c b/sound/soc/codecs/wcd9306.c
new file mode 100644
index 0000000..b0cf27b
--- /dev/null
+++ b/sound/soc/codecs/wcd9306.c
@@ -0,0 +1,3856 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/firmware.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+#include <linux/device.h>
+#include <linux/printk.h>
+#include <linux/ratelimit.h>
+#include <linux/debugfs.h>
+#include <linux/mfd/wcd9xxx/core.h>
+#include <linux/mfd/wcd9xxx/wcd9xxx_registers.h>
+#include <linux/mfd/wcd9xxx/wcd9306_registers.h>
+#include <linux/mfd/wcd9xxx/pdata.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <sound/soc-dapm.h>
+#include <sound/tlv.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/pm_runtime.h>
+#include <linux/kernel.h>
+#include <linux/gpio.h>
+#include "wcd9306.h"
+#include "wcd9xxx-resmgr.h"
+
+#define WCD9306_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
+ SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
+ SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
+
+#define NUM_DECIMATORS 4
+#define NUM_INTERPOLATORS 4
+#define BITS_PER_REG 8
+#define TAPAN_TX_PORT_NUMBER 16
+
+#define TAPAN_I2S_MASTER_MODE_MASK 0x08
+
+enum {
+ AIF1_PB = 0,
+ AIF1_CAP,
+ AIF2_PB,
+ AIF2_CAP,
+ AIF3_PB,
+ AIF3_CAP,
+ NUM_CODEC_DAIS,
+};
+
+enum {
+ RX_MIX1_INP_SEL_ZERO = 0,
+ RX_MIX1_INP_SEL_SRC1,
+ RX_MIX1_INP_SEL_SRC2,
+ RX_MIX1_INP_SEL_IIR1,
+ RX_MIX1_INP_SEL_IIR2,
+ RX_MIX1_INP_SEL_RX1,
+ RX_MIX1_INP_SEL_RX2,
+ RX_MIX1_INP_SEL_RX3,
+ RX_MIX1_INP_SEL_RX4,
+ RX_MIX1_INP_SEL_RX5,
+ RX_MIX1_INP_SEL_RX6,
+ RX_MIX1_INP_SEL_RX7,
+ RX_MIX1_INP_SEL_AUXRX,
+};
+
+#define TAPAN_COMP_DIGITAL_GAIN_OFFSET 3
+
+static const DECLARE_TLV_DB_SCALE(digital_gain, 0, 1, 0);
+static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
+static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
+static struct snd_soc_dai_driver tapan_dai[];
+static const DECLARE_TLV_DB_SCALE(aux_pga_gain, 0, 2, 0);
+
+/* Codec supports 2 IIR filters */
+enum {
+ IIR1 = 0,
+ IIR2,
+ IIR_MAX,
+};
+/* Codec supports 5 bands */
+enum {
+ BAND1 = 0,
+ BAND2,
+ BAND3,
+ BAND4,
+ BAND5,
+ BAND_MAX,
+};
+
+enum {
+ COMPANDER_1 = 0,
+ COMPANDER_2,
+ COMPANDER_MAX,
+};
+
+enum {
+ COMPANDER_FS_8KHZ = 0,
+ COMPANDER_FS_16KHZ,
+ COMPANDER_FS_32KHZ,
+ COMPANDER_FS_48KHZ,
+ COMPANDER_FS_96KHZ,
+ COMPANDER_FS_192KHZ,
+ COMPANDER_FS_MAX,
+};
+
+struct comp_sample_dependent_params {
+ u32 peak_det_timeout;
+ u32 rms_meter_div_fact;
+ u32 rms_meter_resamp_fact;
+};
+
+struct hpf_work {
+ struct tapan_priv *tapan;
+ u32 decimator;
+ u8 tx_hpf_cut_of_freq;
+ struct delayed_work dwork;
+};
+
+static struct hpf_work tx_hpf_work[NUM_DECIMATORS];
+
+static const struct wcd9xxx_ch tapan_rx_chs[TAPAN_RX_MAX] = {
+ WCD9XXX_CH(16, 0),
+ WCD9XXX_CH(17, 1),
+ WCD9XXX_CH(18, 2),
+ WCD9XXX_CH(19, 3),
+ WCD9XXX_CH(20, 4),
+};
+
+static const struct wcd9xxx_ch tapan_tx_chs[TAPAN_TX_MAX] = {
+ WCD9XXX_CH(0, 0),
+ WCD9XXX_CH(1, 1),
+ WCD9XXX_CH(2, 2),
+ WCD9XXX_CH(3, 3),
+ WCD9XXX_CH(4, 4),
+};
+
+static const u32 vport_check_table[NUM_CODEC_DAIS] = {
+ 0, /* AIF1_PB */
+ (1 << AIF2_CAP) | (1 << AIF3_CAP), /* AIF1_CAP */
+ 0, /* AIF2_PB */
+ (1 << AIF1_CAP) | (1 << AIF3_CAP), /* AIF2_CAP */
+ 0, /* AIF2_PB */
+ (1 << AIF1_CAP) | (1 << AIF2_CAP), /* AIF2_CAP */
+};
+
+struct tapan_priv {
+ struct snd_soc_codec *codec;
+ u32 adc_count;
+ u32 rx_bias_count;
+ s32 dmic_1_2_clk_cnt;
+ s32 dmic_3_4_clk_cnt;
+ s32 dmic_5_6_clk_cnt;
+
+ u32 anc_slot;
+
+ /*track tapan interface type*/
+ u8 intf_type;
+
+ /* num of slim ports required */
+ struct wcd9xxx_codec_dai_data dai[NUM_CODEC_DAIS];
+
+ /* Maintain the status of AUX PGA */
+ int aux_pga_cnt;
+ u8 aux_l_gain;
+ u8 aux_r_gain;
+
+ /* resmgr module */
+ struct wcd9xxx_resmgr resmgr;
+ /* mbhc module */
+ struct wcd9xxx_mbhc mbhc;
+};
+
+static const u32 comp_shift[] = {
+ 0,
+ 2,
+};
+
+static unsigned short rx_digital_gain_reg[] = {
+ TAPAN_A_CDC_RX1_VOL_CTL_B2_CTL,
+ TAPAN_A_CDC_RX2_VOL_CTL_B2_CTL,
+ TAPAN_A_CDC_RX3_VOL_CTL_B2_CTL,
+ TAPAN_A_CDC_RX4_VOL_CTL_B2_CTL,
+};
+
+static unsigned short tx_digital_gain_reg[] = {
+ TAPAN_A_CDC_TX1_VOL_CTL_GAIN,
+ TAPAN_A_CDC_TX2_VOL_CTL_GAIN,
+ TAPAN_A_CDC_TX3_VOL_CTL_GAIN,
+ TAPAN_A_CDC_TX4_VOL_CTL_GAIN,
+};
+
+static int tapan_codec_enable_class_h_clk(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = w->codec;
+
+ dev_dbg(codec->dev, "%s %s %d\n", __func__, w->name, event);
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ snd_soc_update_bits(codec, TAPAN_A_CDC_CLSH_B1_CTL, 0x01, 0x01);
+ break;
+ case SND_SOC_DAPM_PRE_PMD:
+ snd_soc_update_bits(codec, TAPAN_A_BUCK_MODE_1, 0x80, 0x00);
+ snd_soc_update_bits(codec, TAPAN_A_CDC_CLSH_B1_CTL, 0x01, 0x00);
+ break;
+ }
+ return 0;
+}
+
+static int tapan_codec_enable_class_h(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = w->codec;
+
+ dev_dbg(codec->dev, "%s %s %d\n", __func__, w->name, event);
+
+ switch (event) {
+ case SND_SOC_DAPM_POST_PMU:
+ snd_soc_update_bits(codec, TAPAN_A_BUCK_MODE_5, 0x02, 0x02);
+ snd_soc_update_bits(codec, TAPAN_A_BUCK_MODE_4, 0xFF, 0xFF);
+ snd_soc_update_bits(codec, TAPAN_A_BUCK_MODE_1, 0x04, 0x04);
+ snd_soc_update_bits(codec, TAPAN_A_BUCK_MODE_1, 0x04, 0x00);
+ snd_soc_update_bits(codec, TAPAN_A_BUCK_MODE_3, 0x04, 0x00);
+ snd_soc_update_bits(codec, TAPAN_A_BUCK_MODE_3, 0x08, 0x00);
+ snd_soc_update_bits(codec, TAPAN_A_BUCK_MODE_1, 0x80, 0x80);
+ usleep_range(1000, 1000);
+ break;
+ }
+ return 0;
+}
+
+static int tapan_codec_enable_charge_pump(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = w->codec;
+
+ dev_dbg(codec->dev, "%s %s %d\n", __func__, w->name, event);
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ snd_soc_update_bits(codec, w->reg, 0x01, 0x01);
+ snd_soc_update_bits(codec, w->reg, 0x40, 0x00);
+ snd_soc_update_bits(codec, TAPAN_A_NCP_STATIC, 0x0f, 0x01);
+ break;
+
+ case SND_SOC_DAPM_POST_PMU:
+ usleep_range(1000, 1000);
+ break;
+
+ case SND_SOC_DAPM_PRE_PMD:
+ snd_soc_update_bits(codec, w->reg, 0x01, 0x00);
+ snd_soc_update_bits(codec, w->reg, 0x40, 0x40);
+ snd_soc_update_bits(codec, TAPAN_A_NCP_STATIC, 0x0f, 0x08);
+ break;
+ }
+ return 0;
+}
+
+static int tapan_pa_gain_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ u8 ear_pa_gain;
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+
+ ear_pa_gain = snd_soc_read(codec, TAPAN_A_RX_EAR_GAIN);
+
+ ear_pa_gain = ear_pa_gain >> 5;
+
+ if (ear_pa_gain == 0x00) {
+ ucontrol->value.integer.value[0] = 0;
+ } else if (ear_pa_gain == 0x04) {
+ ucontrol->value.integer.value[0] = 1;
+ } else {
+ pr_err("%s: ERROR: Unsupported Ear Gain = 0x%x\n",
+ __func__, ear_pa_gain);
+ return -EINVAL;
+ }
+
+ dev_dbg(codec->dev, "%s: ear_pa_gain = 0x%x\n", __func__, ear_pa_gain);
+
+ return 0;
+}
+
+static int tapan_pa_gain_put(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ u8 ear_pa_gain;
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+
+ dev_dbg(codec->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
+ __func__, ucontrol->value.integer.value[0]);
+
+ switch (ucontrol->value.integer.value[0]) {
+ case 0:
+ ear_pa_gain = 0x00;
+ break;
+ case 1:
+ ear_pa_gain = 0x80;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ snd_soc_update_bits(codec, TAPAN_A_RX_EAR_GAIN, 0xE0, ear_pa_gain);
+ return 0;
+}
+
+static int tapan_get_iir_enable_audio_mixer(
+ struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+ int iir_idx = ((struct soc_multi_mixer_control *)
+ kcontrol->private_value)->reg;
+ int band_idx = ((struct soc_multi_mixer_control *)
+ kcontrol->private_value)->shift;
+
+ ucontrol->value.integer.value[0] =
+ snd_soc_read(codec, (TAPAN_A_CDC_IIR1_CTL + 16 * iir_idx)) &
+ (1 << band_idx);
+
+ dev_dbg(codec->dev, "%s: IIR #%d band #%d enable %d\n", __func__,
+ iir_idx, band_idx,
+ (uint32_t)ucontrol->value.integer.value[0]);
+ return 0;
+}
+
+static int tapan_put_iir_enable_audio_mixer(
+ struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+ int iir_idx = ((struct soc_multi_mixer_control *)
+ kcontrol->private_value)->reg;
+ int band_idx = ((struct soc_multi_mixer_control *)
+ kcontrol->private_value)->shift;
+ int value = ucontrol->value.integer.value[0];
+
+ /* Mask first 5 bits, 6-8 are reserved */
+ snd_soc_update_bits(codec, (TAPAN_A_CDC_IIR1_CTL + 16 * iir_idx),
+ (1 << band_idx), (value << band_idx));
+
+ dev_dbg(codec->dev, "%s: IIR #%d band #%d enable %d\n", __func__,
+ iir_idx, band_idx, value);
+ return 0;
+}
+static uint32_t get_iir_band_coeff(struct snd_soc_codec *codec,
+ int iir_idx, int band_idx,
+ int coeff_idx)
+{
+ /* Address does not automatically update if reading */
+ snd_soc_write(codec,
+ (TAPAN_A_CDC_IIR1_COEF_B1_CTL + 16 * iir_idx),
+ (band_idx * BAND_MAX + coeff_idx) & 0x1F);
+
+ /* Mask bits top 2 bits since they are reserved */
+ return ((snd_soc_read(codec,
+ (TAPAN_A_CDC_IIR1_COEF_B2_CTL + 16 * iir_idx)) << 24)) &
+ 0x3FFFFFFF;
+}
+
+static int tapan_get_iir_band_audio_mixer(
+ struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+ int iir_idx = ((struct soc_multi_mixer_control *)
+ kcontrol->private_value)->reg;
+ int band_idx = ((struct soc_multi_mixer_control *)
+ kcontrol->private_value)->shift;
+
+ ucontrol->value.integer.value[0] =
+ get_iir_band_coeff(codec, iir_idx, band_idx, 0);
+ ucontrol->value.integer.value[1] =
+ get_iir_band_coeff(codec, iir_idx, band_idx, 1);
+ ucontrol->value.integer.value[2] =
+ get_iir_band_coeff(codec, iir_idx, band_idx, 2);
+ ucontrol->value.integer.value[3] =
+ get_iir_band_coeff(codec, iir_idx, band_idx, 3);
+ ucontrol->value.integer.value[4] =
+ get_iir_band_coeff(codec, iir_idx, band_idx, 4);
+
+ dev_dbg(codec->dev, "%s: IIR #%d band #%d b0 = 0x%x\n"
+ "%s: IIR #%d band #%d b1 = 0x%x\n"
+ "%s: IIR #%d band #%d b2 = 0x%x\n"
+ "%s: IIR #%d band #%d a1 = 0x%x\n"
+ "%s: IIR #%d band #%d a2 = 0x%x\n",
+ __func__, iir_idx, band_idx,
+ (uint32_t)ucontrol->value.integer.value[0],
+ __func__, iir_idx, band_idx,
+ (uint32_t)ucontrol->value.integer.value[1],
+ __func__, iir_idx, band_idx,
+ (uint32_t)ucontrol->value.integer.value[2],
+ __func__, iir_idx, band_idx,
+ (uint32_t)ucontrol->value.integer.value[3],
+ __func__, iir_idx, band_idx,
+ (uint32_t)ucontrol->value.integer.value[4]);
+ return 0;
+}
+
+static void set_iir_band_coeff(struct snd_soc_codec *codec,
+ int iir_idx, int band_idx,
+ int coeff_idx, uint32_t value)
+{
+ /* Mask top 3 bits, 6-8 are reserved */
+ /* Update address manually each time */
+ snd_soc_write(codec,
+ (TAPAN_A_CDC_IIR1_COEF_B1_CTL + 16 * iir_idx),
+ (band_idx * BAND_MAX + coeff_idx) & 0x1F);
+
+ /* Mask top 2 bits, 7-8 are reserved */
+ snd_soc_write(codec,
+ (TAPAN_A_CDC_IIR1_COEF_B2_CTL + 16 * iir_idx),
+ (value >> 24) & 0x3F);
+
+}
+
+static int tapan_put_iir_band_audio_mixer(
+ struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+ int iir_idx = ((struct soc_multi_mixer_control *)
+ kcontrol->private_value)->reg;
+ int band_idx = ((struct soc_multi_mixer_control *)
+ kcontrol->private_value)->shift;
+
+ set_iir_band_coeff(codec, iir_idx, band_idx, 0,
+ ucontrol->value.integer.value[0]);
+ set_iir_band_coeff(codec, iir_idx, band_idx, 1,
+ ucontrol->value.integer.value[1]);
+ set_iir_band_coeff(codec, iir_idx, band_idx, 2,
+ ucontrol->value.integer.value[2]);
+ set_iir_band_coeff(codec, iir_idx, band_idx, 3,
+ ucontrol->value.integer.value[3]);
+ set_iir_band_coeff(codec, iir_idx, band_idx, 4,
+ ucontrol->value.integer.value[4]);
+
+ dev_dbg(codec->dev, "%s: IIR #%d band #%d b0 = 0x%x\n"
+ "%s: IIR #%d band #%d b1 = 0x%x\n"
+ "%s: IIR #%d band #%d b2 = 0x%x\n"
+ "%s: IIR #%d band #%d a1 = 0x%x\n"
+ "%s: IIR #%d band #%d a2 = 0x%x\n",
+ __func__, iir_idx, band_idx,
+ get_iir_band_coeff(codec, iir_idx, band_idx, 0),
+ __func__, iir_idx, band_idx,
+ get_iir_band_coeff(codec, iir_idx, band_idx, 1),
+ __func__, iir_idx, band_idx,
+ get_iir_band_coeff(codec, iir_idx, band_idx, 2),
+ __func__, iir_idx, band_idx,
+ get_iir_band_coeff(codec, iir_idx, band_idx, 3),
+ __func__, iir_idx, band_idx,
+ get_iir_band_coeff(codec, iir_idx, band_idx, 4));
+ return 0;
+}
+
+static const char * const tapan_ear_pa_gain_text[] = {"POS_6_DB", "POS_2_DB"};
+static const struct soc_enum tapan_ear_pa_gain_enum[] = {
+ SOC_ENUM_SINGLE_EXT(2, tapan_ear_pa_gain_text),
+};
+
+/*cut of frequency for high pass filter*/
+static const char * const cf_text[] = {
+ "MIN_3DB_4Hz", "MIN_3DB_75Hz", "MIN_3DB_150Hz"
+};
+
+static const struct soc_enum cf_dec1_enum =
+ SOC_ENUM_SINGLE(TAPAN_A_CDC_TX1_MUX_CTL, 4, 3, cf_text);
+
+static const struct soc_enum cf_dec2_enum =
+ SOC_ENUM_SINGLE(TAPAN_A_CDC_TX2_MUX_CTL, 4, 3, cf_text);
+
+static const struct soc_enum cf_dec3_enum =
+ SOC_ENUM_SINGLE(TAPAN_A_CDC_TX3_MUX_CTL, 4, 3, cf_text);
+
+static const struct soc_enum cf_dec4_enum =
+ SOC_ENUM_SINGLE(TAPAN_A_CDC_TX4_MUX_CTL, 4, 3, cf_text);
+
+static const struct soc_enum cf_rxmix1_enum =
+ SOC_ENUM_SINGLE(TAPAN_A_CDC_RX1_B4_CTL, 1, 3, cf_text);
+
+static const struct soc_enum cf_rxmix2_enum =
+ SOC_ENUM_SINGLE(TAPAN_A_CDC_RX2_B4_CTL, 1, 3, cf_text);
+
+static const struct soc_enum cf_rxmix3_enum =
+ SOC_ENUM_SINGLE(TAPAN_A_CDC_RX3_B4_CTL, 1, 3, cf_text);
+
+static const struct soc_enum cf_rxmix4_enum =
+ SOC_ENUM_SINGLE(TAPAN_A_CDC_RX4_B4_CTL, 1, 3, cf_text);
+
+static const struct snd_kcontrol_new tapan_snd_controls[] = {
+
+ SOC_ENUM_EXT("EAR PA Gain", tapan_ear_pa_gain_enum[0],
+ tapan_pa_gain_get, tapan_pa_gain_put),
+
+ SOC_SINGLE_TLV("LINEOUT1 Volume", TAPAN_A_RX_LINE_1_GAIN, 0, 12, 1,
+ line_gain),
+ SOC_SINGLE_TLV("LINEOUT2 Volume", TAPAN_A_RX_LINE_2_GAIN, 0, 12, 1,
+ line_gain),
+
+ SOC_SINGLE_TLV("HPHL Volume", TAPAN_A_RX_HPH_L_GAIN, 0, 12, 1,
+ line_gain),
+ SOC_SINGLE_TLV("HPHR Volume", TAPAN_A_RX_HPH_R_GAIN, 0, 12, 1,
+ line_gain),
+
+ SOC_SINGLE_S8_TLV("RX1 Digital Volume", TAPAN_A_CDC_RX1_VOL_CTL_B2_CTL,
+ -84, 40, digital_gain),
+ SOC_SINGLE_S8_TLV("RX2 Digital Volume", TAPAN_A_CDC_RX2_VOL_CTL_B2_CTL,
+ -84, 40, digital_gain),
+ SOC_SINGLE_S8_TLV("RX3 Digital Volume", TAPAN_A_CDC_RX3_VOL_CTL_B2_CTL,
+ -84, 40, digital_gain),
+ SOC_SINGLE_S8_TLV("RX4 Digital Volume", TAPAN_A_CDC_RX4_VOL_CTL_B2_CTL,
+ -84, 40, digital_gain),
+
+ SOC_SINGLE_S8_TLV("DEC1 Volume", TAPAN_A_CDC_TX1_VOL_CTL_GAIN, -84, 40,
+ digital_gain),
+ SOC_SINGLE_S8_TLV("DEC2 Volume", TAPAN_A_CDC_TX2_VOL_CTL_GAIN, -84, 40,
+ digital_gain),
+ SOC_SINGLE_S8_TLV("DEC3 Volume", TAPAN_A_CDC_TX3_VOL_CTL_GAIN, -84, 40,
+ digital_gain),
+ SOC_SINGLE_S8_TLV("DEC4 Volume", TAPAN_A_CDC_TX4_VOL_CTL_GAIN, -84, 40,
+ digital_gain),
+
+ SOC_SINGLE_S8_TLV("IIR1 INP1 Volume", TAPAN_A_CDC_IIR1_GAIN_B1_CTL, -84,
+ 40, digital_gain),
+ SOC_SINGLE_S8_TLV("IIR1 INP2 Volume", TAPAN_A_CDC_IIR1_GAIN_B2_CTL, -84,
+ 40, digital_gain),
+ SOC_SINGLE_S8_TLV("IIR1 INP3 Volume", TAPAN_A_CDC_IIR1_GAIN_B3_CTL, -84,
+ 40, digital_gain),
+ SOC_SINGLE_S8_TLV("IIR1 INP4 Volume", TAPAN_A_CDC_IIR1_GAIN_B4_CTL, -84,
+ 40, digital_gain),
+
+ SOC_SINGLE("MICBIAS1 CAPLESS Switch", TAPAN_A_MICB_1_CTL, 4, 1, 1),
+ SOC_SINGLE("MICBIAS2 CAPLESS Switch", TAPAN_A_MICB_2_CTL, 4, 1, 1),
+ SOC_SINGLE("MICBIAS3 CAPLESS Switch", TAPAN_A_MICB_3_CTL, 4, 1, 1),
+
+ SOC_ENUM("TX1 HPF cut off", cf_dec1_enum),
+ SOC_ENUM("TX2 HPF cut off", cf_dec2_enum),
+ SOC_ENUM("TX3 HPF cut off", cf_dec3_enum),
+ SOC_ENUM("TX4 HPF cut off", cf_dec4_enum),
+
+ SOC_SINGLE("TX1 HPF Switch", TAPAN_A_CDC_TX1_MUX_CTL, 3, 1, 0),
+ SOC_SINGLE("TX2 HPF Switch", TAPAN_A_CDC_TX2_MUX_CTL, 3, 1, 0),
+ SOC_SINGLE("TX3 HPF Switch", TAPAN_A_CDC_TX3_MUX_CTL, 3, 1, 0),
+ SOC_SINGLE("TX4 HPF Switch", TAPAN_A_CDC_TX4_MUX_CTL, 3, 1, 0),
+
+ SOC_SINGLE("RX1 HPF Switch", TAPAN_A_CDC_RX1_B5_CTL, 2, 1, 0),
+ SOC_SINGLE("RX2 HPF Switch", TAPAN_A_CDC_RX2_B5_CTL, 2, 1, 0),
+ SOC_SINGLE("RX3 HPF Switch", TAPAN_A_CDC_RX3_B5_CTL, 2, 1, 0),
+ SOC_SINGLE("RX4 HPF Switch", TAPAN_A_CDC_RX4_B5_CTL, 2, 1, 0),
+
+ SOC_ENUM("RX1 HPF cut off", cf_rxmix1_enum),
+ SOC_ENUM("RX2 HPF cut off", cf_rxmix2_enum),
+ SOC_ENUM("RX3 HPF cut off", cf_rxmix3_enum),
+ SOC_ENUM("RX4 HPF cut off", cf_rxmix4_enum),
+
+ SOC_SINGLE_EXT("IIR1 Enable Band1", IIR1, BAND1, 1, 0,
+ tapan_get_iir_enable_audio_mixer, tapan_put_iir_enable_audio_mixer),
+ SOC_SINGLE_EXT("IIR1 Enable Band2", IIR1, BAND2, 1, 0,
+ tapan_get_iir_enable_audio_mixer, tapan_put_iir_enable_audio_mixer),
+ SOC_SINGLE_EXT("IIR1 Enable Band3", IIR1, BAND3, 1, 0,
+ tapan_get_iir_enable_audio_mixer, tapan_put_iir_enable_audio_mixer),
+ SOC_SINGLE_EXT("IIR1 Enable Band4", IIR1, BAND4, 1, 0,
+ tapan_get_iir_enable_audio_mixer, tapan_put_iir_enable_audio_mixer),
+ SOC_SINGLE_EXT("IIR1 Enable Band5", IIR1, BAND5, 1, 0,
+ tapan_get_iir_enable_audio_mixer, tapan_put_iir_enable_audio_mixer),
+ SOC_SINGLE_EXT("IIR2 Enable Band1", IIR2, BAND1, 1, 0,
+ tapan_get_iir_enable_audio_mixer, tapan_put_iir_enable_audio_mixer),
+ SOC_SINGLE_EXT("IIR2 Enable Band2", IIR2, BAND2, 1, 0,
+ tapan_get_iir_enable_audio_mixer, tapan_put_iir_enable_audio_mixer),
+ SOC_SINGLE_EXT("IIR2 Enable Band3", IIR2, BAND3, 1, 0,
+ tapan_get_iir_enable_audio_mixer, tapan_put_iir_enable_audio_mixer),
+ SOC_SINGLE_EXT("IIR2 Enable Band4", IIR2, BAND4, 1, 0,
+ tapan_get_iir_enable_audio_mixer, tapan_put_iir_enable_audio_mixer),
+ SOC_SINGLE_EXT("IIR2 Enable Band5", IIR2, BAND5, 1, 0,
+ tapan_get_iir_enable_audio_mixer, tapan_put_iir_enable_audio_mixer),
+
+ SOC_SINGLE_MULTI_EXT("IIR1 Band1", IIR1, BAND1, 255, 0, 5,
+ tapan_get_iir_band_audio_mixer, tapan_put_iir_band_audio_mixer),
+ SOC_SINGLE_MULTI_EXT("IIR1 Band2", IIR1, BAND2, 255, 0, 5,
+ tapan_get_iir_band_audio_mixer, tapan_put_iir_band_audio_mixer),
+ SOC_SINGLE_MULTI_EXT("IIR1 Band3", IIR1, BAND3, 255, 0, 5,
+ tapan_get_iir_band_audio_mixer, tapan_put_iir_band_audio_mixer),
+ SOC_SINGLE_MULTI_EXT("IIR1 Band4", IIR1, BAND4, 255, 0, 5,
+ tapan_get_iir_band_audio_mixer, tapan_put_iir_band_audio_mixer),
+ SOC_SINGLE_MULTI_EXT("IIR1 Band5", IIR1, BAND5, 255, 0, 5,
+ tapan_get_iir_band_audio_mixer, tapan_put_iir_band_audio_mixer),
+ SOC_SINGLE_MULTI_EXT("IIR2 Band1", IIR2, BAND1, 255, 0, 5,
+ tapan_get_iir_band_audio_mixer, tapan_put_iir_band_audio_mixer),
+ SOC_SINGLE_MULTI_EXT("IIR2 Band2", IIR2, BAND2, 255, 0, 5,
+ tapan_get_iir_band_audio_mixer, tapan_put_iir_band_audio_mixer),
+ SOC_SINGLE_MULTI_EXT("IIR2 Band3", IIR2, BAND3, 255, 0, 5,
+ tapan_get_iir_band_audio_mixer, tapan_put_iir_band_audio_mixer),
+ SOC_SINGLE_MULTI_EXT("IIR2 Band4", IIR2, BAND4, 255, 0, 5,
+ tapan_get_iir_band_audio_mixer, tapan_put_iir_band_audio_mixer),
+ SOC_SINGLE_MULTI_EXT("IIR2 Band5", IIR2, BAND5, 255, 0, 5,
+ tapan_get_iir_band_audio_mixer, tapan_put_iir_band_audio_mixer),
+
+};
+
+static const char * const rx_mix1_text[] = {
+ "ZERO", "SRC1", "SRC2", "IIR1", "IIR2", "RX1", "RX2", "RX3", "RX4",
+ "RX5", "RX6", "RX7"
+};
+
+static const char * const rx_mix2_text[] = {
+ "ZERO", "SRC1", "SRC2", "IIR1", "IIR2"
+};
+
+static const char * const rx_rdac5_text[] = {
+ "DEM4", "DEM3_INV"
+};
+
+static const char * const rx_rdac7_text[] = {
+ "DEM6", "DEM5_INV"
+};
+
+static const char * const sb_tx1_mux_text[] = {
+ "ZERO", "RMIX1", "RMIX2", "RMIX3", "RMIX4", "RMIX5", "RMIX6", "RMIX7",
+ "DEC1"
+};
+
+static const char * const sb_tx2_mux_text[] = {
+ "ZERO", "RMIX1", "RMIX2", "RMIX3", "RMIX4", "RMIX5", "RMIX6", "RMIX7",
+ "DEC2"
+};
+
+static const char * const sb_tx3_mux_text[] = {
+ "ZERO", "RMIX1", "RMIX2", "RMIX3", "RMIX4", "RMIX5", "RMIX6", "RMIX7",
+ "DEC3"
+};
+
+static const char * const sb_tx4_mux_text[] = {
+ "ZERO", "RMIX1", "RMIX2", "RMIX3", "RMIX4", "RMIX5", "RMIX6", "RMIX7",
+ "DEC4"
+};
+
+static const char * const dec1_mux_text[] = {
+ "ZERO", "DMIC1", "ADC6",
+};
+
+static const char * const dec2_mux_text[] = {
+ "ZERO", "DMIC2", "ADC5",
+};
+
+static const char * const dec3_mux_text[] = {
+ "ZERO", "DMIC3", "ADC4",
+};
+
+static const char * const dec4_mux_text[] = {
+ "ZERO", "DMIC4", "ADC3",
+};
+
+static const char * const anc_mux_text[] = {
+ "ZERO", "ADC1", "ADC2", "ADC3", "ADC4", "ADC5", "ADC6", "ADC_MB",
+ "RSVD_1", "DMIC1", "DMIC2", "DMIC3", "DMIC4", "DMIC5", "DMIC6"
+};
+
+static const char * const anc1_fb_mux_text[] = {
+ "ZERO", "EAR_HPH_L", "EAR_LINE_1",
+};
+
+static const char * const iir1_inp1_text[] = {
+ "ZERO", "DEC1", "DEC2", "DEC3", "DEC4", "DEC5", "DEC6", "DEC7", "DEC8",
+ "DEC9", "DEC10", "RX1", "RX2", "RX3", "RX4", "RX5", "RX6", "RX7"
+};
+
+static const struct soc_enum rx_mix1_inp1_chain_enum =
+ SOC_ENUM_SINGLE(TAPAN_A_CDC_CONN_RX1_B1_CTL, 0, 12, rx_mix1_text);
+
+static const struct soc_enum rx_mix1_inp2_chain_enum =
+ SOC_ENUM_SINGLE(TAPAN_A_CDC_CONN_RX1_B1_CTL, 4, 12, rx_mix1_text);
+
+static const struct soc_enum rx_mix1_inp3_chain_enum =
+ SOC_ENUM_SINGLE(TAPAN_A_CDC_CONN_RX1_B2_CTL, 0, 12, rx_mix1_text);
+
+static const struct soc_enum rx2_mix1_inp1_chain_enum =
+ SOC_ENUM_SINGLE(TAPAN_A_CDC_CONN_RX2_B1_CTL, 0, 12, rx_mix1_text);
+
+static const struct soc_enum rx2_mix1_inp2_chain_enum =
+ SOC_ENUM_SINGLE(TAPAN_A_CDC_CONN_RX2_B1_CTL, 4, 12, rx_mix1_text);
+
+static const struct soc_enum rx3_mix1_inp1_chain_enum =
+ SOC_ENUM_SINGLE(TAPAN_A_CDC_CONN_RX3_B1_CTL, 0, 12, rx_mix1_text);
+
+static const struct soc_enum rx3_mix1_inp2_chain_enum =
+ SOC_ENUM_SINGLE(TAPAN_A_CDC_CONN_RX3_B1_CTL, 4, 12, rx_mix1_text);
+
+static const struct soc_enum rx4_mix1_inp1_chain_enum =
+ SOC_ENUM_SINGLE(TAPAN_A_CDC_CONN_RX4_B1_CTL, 0, 12, rx_mix1_text);
+
+static const struct soc_enum rx4_mix1_inp2_chain_enum =
+ SOC_ENUM_SINGLE(TAPAN_A_CDC_CONN_RX4_B1_CTL, 4, 12, rx_mix1_text);
+
+static const struct soc_enum rx1_mix2_inp1_chain_enum =
+ SOC_ENUM_SINGLE(TAPAN_A_CDC_CONN_RX1_B3_CTL, 0, 5, rx_mix2_text);
+
+static const struct soc_enum rx1_mix2_inp2_chain_enum =
+ SOC_ENUM_SINGLE(TAPAN_A_CDC_CONN_RX1_B3_CTL, 3, 5, rx_mix2_text);
+
+static const struct soc_enum rx2_mix2_inp1_chain_enum =
+ SOC_ENUM_SINGLE(TAPAN_A_CDC_CONN_RX2_B3_CTL, 0, 5, rx_mix2_text);
+
+static const struct soc_enum rx2_mix2_inp2_chain_enum =
+ SOC_ENUM_SINGLE(TAPAN_A_CDC_CONN_RX2_B3_CTL, 3, 5, rx_mix2_text);
+
+static const struct soc_enum rx_rdac5_enum =
+ SOC_ENUM_SINGLE(TAPAN_A_CDC_CONN_MISC, 2, 2, rx_rdac5_text);
+
+static const struct soc_enum rx_rdac7_enum =
+ SOC_ENUM_SINGLE(TAPAN_A_CDC_CONN_MISC, 1, 2, rx_rdac7_text);
+
+static const struct soc_enum sb_tx1_mux_enum =
+ SOC_ENUM_SINGLE(TAPAN_A_CDC_CONN_TX_SB_B1_CTL, 0, 9, sb_tx1_mux_text);
+
+static const struct soc_enum sb_tx2_mux_enum =
+ SOC_ENUM_SINGLE(TAPAN_A_CDC_CONN_TX_SB_B2_CTL, 0, 9, sb_tx2_mux_text);
+
+static const struct soc_enum sb_tx3_mux_enum =
+ SOC_ENUM_SINGLE(TAPAN_A_CDC_CONN_TX_SB_B3_CTL, 0, 9, sb_tx3_mux_text);
+
+static const struct soc_enum sb_tx4_mux_enum =
+ SOC_ENUM_SINGLE(TAPAN_A_CDC_CONN_TX_SB_B4_CTL, 0, 9, sb_tx4_mux_text);
+
+static const struct soc_enum dec1_mux_enum =
+ SOC_ENUM_SINGLE(TAPAN_A_CDC_CONN_TX_B1_CTL, 0, 3, dec1_mux_text);
+
+static const struct soc_enum dec2_mux_enum =
+ SOC_ENUM_SINGLE(TAPAN_A_CDC_CONN_TX_B1_CTL, 2, 3, dec2_mux_text);
+
+static const struct soc_enum dec3_mux_enum =
+ SOC_ENUM_SINGLE(TAPAN_A_CDC_CONN_TX_B1_CTL, 4, 3, dec3_mux_text);
+
+static const struct soc_enum dec4_mux_enum =
+ SOC_ENUM_SINGLE(TAPAN_A_CDC_CONN_TX_B1_CTL, 6, 3, dec4_mux_text);
+
+static const struct soc_enum iir1_inp1_mux_enum =
+ SOC_ENUM_SINGLE(TAPAN_A_CDC_CONN_EQ1_B1_CTL, 0, 18, iir1_inp1_text);
+
+static const struct snd_kcontrol_new rx_mix1_inp1_mux =
+ SOC_DAPM_ENUM("RX1 MIX1 INP1 Mux", rx_mix1_inp1_chain_enum);
+
+static const struct snd_kcontrol_new rx_mix1_inp2_mux =
+ SOC_DAPM_ENUM("RX1 MIX1 INP2 Mux", rx_mix1_inp2_chain_enum);
+
+static const struct snd_kcontrol_new rx_mix1_inp3_mux =
+ SOC_DAPM_ENUM("RX1 MIX1 INP3 Mux", rx_mix1_inp3_chain_enum);
+
+static const struct snd_kcontrol_new rx2_mix1_inp1_mux =
+ SOC_DAPM_ENUM("RX2 MIX1 INP1 Mux", rx2_mix1_inp1_chain_enum);
+
+static const struct snd_kcontrol_new rx2_mix1_inp2_mux =
+ SOC_DAPM_ENUM("RX2 MIX1 INP2 Mux", rx2_mix1_inp2_chain_enum);
+
+static const struct snd_kcontrol_new rx3_mix1_inp1_mux =
+ SOC_DAPM_ENUM("RX3 MIX1 INP1 Mux", rx3_mix1_inp1_chain_enum);
+
+static const struct snd_kcontrol_new rx3_mix1_inp2_mux =
+ SOC_DAPM_ENUM("RX3 MIX1 INP2 Mux", rx3_mix1_inp2_chain_enum);
+
+static const struct snd_kcontrol_new rx4_mix1_inp1_mux =
+ SOC_DAPM_ENUM("RX4 MIX1 INP1 Mux", rx4_mix1_inp1_chain_enum);
+
+static const struct snd_kcontrol_new rx4_mix1_inp2_mux =
+ SOC_DAPM_ENUM("RX4 MIX1 INP2 Mux", rx4_mix1_inp2_chain_enum);
+
+static const struct snd_kcontrol_new rx1_mix2_inp1_mux =
+ SOC_DAPM_ENUM("RX1 MIX2 INP1 Mux", rx1_mix2_inp1_chain_enum);
+
+static const struct snd_kcontrol_new rx1_mix2_inp2_mux =
+ SOC_DAPM_ENUM("RX1 MIX2 INP2 Mux", rx1_mix2_inp2_chain_enum);
+
+static const struct snd_kcontrol_new rx2_mix2_inp1_mux =
+ SOC_DAPM_ENUM("RX2 MIX2 INP1 Mux", rx2_mix2_inp1_chain_enum);
+
+static const struct snd_kcontrol_new rx2_mix2_inp2_mux =
+ SOC_DAPM_ENUM("RX2 MIX2 INP2 Mux", rx2_mix2_inp2_chain_enum);
+
+static const struct snd_kcontrol_new rx_dac5_mux =
+ SOC_DAPM_ENUM("RDAC5 MUX Mux", rx_rdac5_enum);
+
+static const struct snd_kcontrol_new sb_tx1_mux =
+ SOC_DAPM_ENUM("SLIM TX1 MUX Mux", sb_tx1_mux_enum);
+
+static const struct snd_kcontrol_new sb_tx2_mux =
+ SOC_DAPM_ENUM("SLIM TX2 MUX Mux", sb_tx2_mux_enum);
+
+static const struct snd_kcontrol_new sb_tx3_mux =
+ SOC_DAPM_ENUM("SLIM TX3 MUX Mux", sb_tx3_mux_enum);
+
+static const struct snd_kcontrol_new sb_tx4_mux =
+ SOC_DAPM_ENUM("SLIM TX4 MUX Mux", sb_tx4_mux_enum);
+
+/*static const struct snd_kcontrol_new sb_tx5_mux =
+ SOC_DAPM_ENUM("SLIM TX5 MUX Mux", sb_tx5_mux_enum);
+*/
+
+static int wcd9306_put_dec_enum(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
+ struct snd_soc_dapm_widget *w = wlist->widgets[0];
+ struct snd_soc_codec *codec = w->codec;
+ struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
+ unsigned int dec_mux, decimator;
+ char *dec_name = NULL;
+ char *widget_name = NULL;
+ char *temp;
+ u16 tx_mux_ctl_reg;
+ u8 adc_dmic_sel = 0x0;
+ int ret = 0;
+
+ if (ucontrol->value.enumerated.item[0] > e->max - 1)
+ return -EINVAL;
+
+ dec_mux = ucontrol->value.enumerated.item[0];
+
+ widget_name = kstrndup(w->name, 15, GFP_KERNEL);
+ if (!widget_name)
+ return -ENOMEM;
+ temp = widget_name;
+
+ dec_name = strsep(&widget_name, " ");
+ widget_name = temp;
+ if (!dec_name) {
+ pr_err("%s: Invalid decimator = %s\n", __func__, w->name);
+ ret = -EINVAL;
+ goto out;
+ }
+
+ ret = kstrtouint(strpbrk(dec_name, "1234"), 10, &decimator);
+ if (ret < 0) {
+ pr_err("%s: Invalid decimator = %s\n", __func__, dec_name);
+ ret = -EINVAL;
+ goto out;
+ }
+
+ dev_dbg(w->dapm->dev, "%s(): widget = %s decimator = %u dec_mux = %u\n"
+ , __func__, w->name, decimator, dec_mux);
+
+ switch (decimator) {
+ case 1:
+ case 2:
+ case 3:
+ case 4:
+ case 5:
+ case 6:
+ if (dec_mux == 1)
+ adc_dmic_sel = 0x1;
+ else
+ adc_dmic_sel = 0x0;
+ break;
+ case 7:
+ case 8:
+ case 9:
+ case 10:
+ if ((dec_mux == 1) || (dec_mux == 2))
+ adc_dmic_sel = 0x1;
+ else
+ adc_dmic_sel = 0x0;
+ break;
+ default:
+ pr_err("%s: Invalid Decimator = %u\n", __func__, decimator);
+ ret = -EINVAL;
+ goto out;
+ }
+
+ tx_mux_ctl_reg = TAPAN_A_CDC_TX1_MUX_CTL + 8 * (decimator - 1);
+
+ snd_soc_update_bits(codec, tx_mux_ctl_reg, 0x1, adc_dmic_sel);
+
+ ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
+
+out:
+ kfree(widget_name);
+ return ret;
+}
+
+#define WCD9306_DEC_ENUM(xname, xenum) \
+{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
+ .info = snd_soc_info_enum_double, \
+ .get = snd_soc_dapm_get_enum_double, \
+ .put = wcd9306_put_dec_enum, \
+ .private_value = (unsigned long)&xenum }
+
+static const struct snd_kcontrol_new dec1_mux =
+ WCD9306_DEC_ENUM("DEC1 MUX Mux", dec1_mux_enum);
+
+static const struct snd_kcontrol_new dec2_mux =
+ WCD9306_DEC_ENUM("DEC2 MUX Mux", dec2_mux_enum);
+
+static const struct snd_kcontrol_new dec3_mux =
+ WCD9306_DEC_ENUM("DEC3 MUX Mux", dec3_mux_enum);
+
+static const struct snd_kcontrol_new dec4_mux =
+ WCD9306_DEC_ENUM("DEC4 MUX Mux", dec4_mux_enum);
+
+static const struct snd_kcontrol_new iir1_inp1_mux =
+ SOC_DAPM_ENUM("IIR1 INP1 Mux", iir1_inp1_mux_enum);
+
+static const struct snd_kcontrol_new dac1_switch[] = {
+ SOC_DAPM_SINGLE("Switch", TAPAN_A_RX_EAR_EN, 5, 1, 0)
+};
+static const struct snd_kcontrol_new hphl_switch[] = {
+ SOC_DAPM_SINGLE("Switch", TAPAN_A_RX_HPH_L_DAC_CTL, 6, 1, 0)
+};
+
+static const struct snd_kcontrol_new hphl_pa_mix[] = {
+ SOC_DAPM_SINGLE("AUX_PGA_L Switch", TAPAN_A_RX_PA_AUX_IN_CONN,
+ 7, 1, 0),
+};
+
+static const struct snd_kcontrol_new hphr_pa_mix[] = {
+ SOC_DAPM_SINGLE("AUX_PGA_R Switch", TAPAN_A_RX_PA_AUX_IN_CONN,
+ 6, 1, 0),
+};
+
+static const struct snd_kcontrol_new ear_pa_mix[] = {
+ SOC_DAPM_SINGLE("AUX_PGA_L Switch", TAPAN_A_RX_PA_AUX_IN_CONN,
+ 5, 1, 0),
+};
+static const struct snd_kcontrol_new lineout1_pa_mix[] = {
+ SOC_DAPM_SINGLE("AUX_PGA_L Switch", TAPAN_A_RX_PA_AUX_IN_CONN,
+ 4, 1, 0),
+};
+
+static const struct snd_kcontrol_new lineout2_pa_mix[] = {
+ SOC_DAPM_SINGLE("AUX_PGA_R Switch", TAPAN_A_RX_PA_AUX_IN_CONN,
+ 3, 1, 0),
+};
+
+static const struct snd_kcontrol_new lineout3_pa_mix[] = {
+ SOC_DAPM_SINGLE("AUX_PGA_L Switch", TAPAN_A_RX_PA_AUX_IN_CONN,
+ 2, 1, 0),
+};
+
+static const struct snd_kcontrol_new lineout4_pa_mix[] = {
+ SOC_DAPM_SINGLE("AUX_PGA_R Switch", TAPAN_A_RX_PA_AUX_IN_CONN,
+ 1, 1, 0),
+};
+
+/* virtual port entries */
+static int slim_tx_mixer_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
+ struct snd_soc_dapm_widget *widget = wlist->widgets[0];
+
+ ucontrol->value.integer.value[0] = widget->value;
+ return 0;
+}
+
+static int slim_tx_mixer_put(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
+ struct snd_soc_dapm_widget *widget = wlist->widgets[0];
+ struct snd_soc_codec *codec = widget->codec;
+ struct tapan_priv *tapan_p = snd_soc_codec_get_drvdata(codec);
+ struct wcd9xxx *core = dev_get_drvdata(codec->dev->parent);
+ struct soc_multi_mixer_control *mixer =
+ ((struct soc_multi_mixer_control *)kcontrol->private_value);
+ u32 dai_id = widget->shift;
+ u32 port_id = mixer->shift;
+ u32 enable = ucontrol->value.integer.value[0];
+
+ dev_dbg(codec->dev, "%s: wname %s cname %s\n",
+ __func__, widget->name, ucontrol->id.name);
+ dev_dbg(codec->dev, "%s: value %u shift %d item %ld\n",
+ __func__, widget->value, widget->shift,
+ ucontrol->value.integer.value[0]);
+
+ mutex_lock(&codec->mutex);
+
+ if (tapan_p->intf_type != WCD9XXX_INTERFACE_TYPE_SLIMBUS) {
+ if (dai_id != AIF1_CAP) {
+ dev_err(codec->dev, "%s: invalid AIF for I2C mode\n",
+ __func__);
+ mutex_unlock(&codec->mutex);
+ return -EINVAL;
+ }
+ }
+ switch (dai_id) {
+ case AIF1_CAP:
+ case AIF2_CAP:
+ case AIF3_CAP:
+ /* only add to the list if value not set
+ */
+ if (enable && !(widget->value & 1 << port_id)) {
+ if (wcd9xxx_tx_vport_validation(
+ vport_check_table[dai_id],
+ port_id,
+ tapan_p->dai)) {
+ dev_dbg(codec->dev, "%s: TX%u is used by other virtual port\n",
+ __func__, port_id + 1);
+ mutex_unlock(&codec->mutex);
+ return -EINVAL;
+ }
+ widget->value |= 1 << port_id;
+ list_add_tail(&core->tx_chs[port_id].list,
+ &tapan_p->dai[dai_id].wcd9xxx_ch_list
+ );
+ } else if (!enable && (widget->value & 1 << port_id)) {
+ widget->value &= ~(1 << port_id);
+ list_del_init(&core->tx_chs[port_id].list);
+ } else {
+ if (enable)
+ dev_dbg(codec->dev, "%s: TX%u port is used by this virtual port\n",
+ __func__, port_id + 1);
+ else
+ dev_dbg(codec->dev, "%s: TX%u port is not used by this virtual port\n",
+ __func__, port_id + 1);
+ /* avoid update power function */
+ mutex_unlock(&codec->mutex);
+ return 0;
+ }
+ break;
+ default:
+ pr_err("Unknown AIF %d\n", dai_id);
+ mutex_unlock(&codec->mutex);
+ return -EINVAL;
+ }
+ dev_dbg(codec->dev, "%s: name %s sname %s updated value %u shift %d\n",
+ __func__, widget->name, widget->sname,
+ widget->value, widget->shift);
+
+ snd_soc_dapm_mixer_update_power(widget, kcontrol, enable);
+
+ mutex_unlock(&codec->mutex);
+ return 0;
+}
+
+static int slim_rx_mux_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
+ struct snd_soc_dapm_widget *widget = wlist->widgets[0];
+
+ ucontrol->value.enumerated.item[0] = widget->value;
+ return 0;
+}
+
+static const char *const slim_rx_mux_text[] = {
+ "ZERO", "AIF1_PB", "AIF2_PB", "AIF3_PB"
+};
+
+static int slim_rx_mux_put(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
+ struct snd_soc_dapm_widget *widget = wlist->widgets[0];
+ struct snd_soc_codec *codec = widget->codec;
+ struct tapan_priv *tapan_p = snd_soc_codec_get_drvdata(codec);
+ struct wcd9xxx *core = dev_get_drvdata(codec->dev->parent);
+ struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
+ u32 port_id = widget->shift;
+
+ dev_dbg(codec->dev, "%s: wname %s cname %s value %u shift %d item %ld\n",
+ __func__, widget->name, ucontrol->id.name, widget->value,
+ widget->shift, ucontrol->value.integer.value[0]);
+
+ widget->value = ucontrol->value.enumerated.item[0];
+
+ mutex_lock(&codec->mutex);
+
+ if (tapan_p->intf_type != WCD9XXX_INTERFACE_TYPE_SLIMBUS) {
+ if (widget->value > 1) {
+ dev_err(codec->dev, "%s: invalid AIF for I2C mode\n",
+ __func__);
+ goto err;
+ }
+ }
+ /* value need to match the Virtual port and AIF number
+ */
+ switch (widget->value) {
+ case 0:
+ list_del_init(&core->rx_chs[port_id].list);
+ break;
+ case 1:
+ if (wcd9xxx_rx_vport_validation(port_id + core->num_tx_port,
+ &tapan_p->dai[AIF1_PB].wcd9xxx_ch_list))
+ goto pr_err;
+ list_add_tail(&core->rx_chs[port_id].list,
+ &tapan_p->dai[AIF1_PB].wcd9xxx_ch_list);
+ break;
+ case 2:
+ if (wcd9xxx_rx_vport_validation(port_id + core->num_tx_port,
+ &tapan_p->dai[AIF1_PB].wcd9xxx_ch_list))
+ goto pr_err;
+ list_add_tail(&core->rx_chs[port_id].list,
+ &tapan_p->dai[AIF2_PB].wcd9xxx_ch_list);
+ break;
+ case 3:
+ if (wcd9xxx_rx_vport_validation(port_id + core->num_tx_port,
+ &tapan_p->dai[AIF1_PB].wcd9xxx_ch_list))
+ goto pr_err;
+ list_add_tail(&core->rx_chs[port_id].list,
+ &tapan_p->dai[AIF3_PB].wcd9xxx_ch_list);
+ break;
+ default:
+ pr_err("Unknown AIF %d\n", widget->value);
+ goto err;
+ }
+
+ snd_soc_dapm_mux_update_power(widget, kcontrol, 1, widget->value, e);
+
+ mutex_unlock(&codec->mutex);
+ return 0;
+pr_err:
+ pr_err("%s: RX%u is used by current requesting AIF_PB itself\n",
+ __func__, port_id + 1);
+err:
+ mutex_unlock(&codec->mutex);
+ return -EINVAL;
+}
+
+static const struct soc_enum slim_rx_mux_enum =
+ SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(slim_rx_mux_text), slim_rx_mux_text);
+
+static const struct snd_kcontrol_new slim_rx_mux[TAPAN_RX_MAX] = {
+ SOC_DAPM_ENUM_EXT("SLIM RX1 Mux", slim_rx_mux_enum,
+ slim_rx_mux_get, slim_rx_mux_put),
+ SOC_DAPM_ENUM_EXT("SLIM RX2 Mux", slim_rx_mux_enum,
+ slim_rx_mux_get, slim_rx_mux_put),
+ SOC_DAPM_ENUM_EXT("SLIM RX3 Mux", slim_rx_mux_enum,
+ slim_rx_mux_get, slim_rx_mux_put),
+ SOC_DAPM_ENUM_EXT("SLIM RX4 Mux", slim_rx_mux_enum,
+ slim_rx_mux_get, slim_rx_mux_put),
+ SOC_DAPM_ENUM_EXT("SLIM RX5 Mux", slim_rx_mux_enum,
+ slim_rx_mux_get, slim_rx_mux_put),
+};
+
+static const struct snd_kcontrol_new aif_cap_mixer[] = {
+ SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, TAPAN_TX1, 1, 0,
+ slim_tx_mixer_get, slim_tx_mixer_put),
+ SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, TAPAN_TX2, 1, 0,
+ slim_tx_mixer_get, slim_tx_mixer_put),
+ SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, TAPAN_TX3, 1, 0,
+ slim_tx_mixer_get, slim_tx_mixer_put),
+ SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, TAPAN_TX4, 1, 0,
+ slim_tx_mixer_get, slim_tx_mixer_put),
+ SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, TAPAN_TX5, 1, 0,
+ slim_tx_mixer_get, slim_tx_mixer_put),
+};
+
+static int tapan_codec_enable_aux_pga(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = w->codec;
+ struct tapan_priv *tapan = snd_soc_codec_get_drvdata(codec);
+
+ dev_dbg(codec->dev, "%s: %d\n", __func__, event);
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ WCD9XXX_BCL_LOCK(&tapan->resmgr);
+ wcd9xxx_resmgr_get_bandgap(&tapan->resmgr,
+ WCD9XXX_BANDGAP_AUDIO_MODE);
+ /* AUX PGA requires RCO or MCLK */
+ wcd9xxx_resmgr_get_clk_block(&tapan->resmgr, WCD9XXX_CLK_RCO);
+ wcd9xxx_resmgr_enable_rx_bias(&tapan->resmgr, 1);
+ WCD9XXX_BCL_UNLOCK(&tapan->resmgr);
+ break;
+
+ case SND_SOC_DAPM_POST_PMD:
+ WCD9XXX_BCL_LOCK(&tapan->resmgr);
+ wcd9xxx_resmgr_enable_rx_bias(&tapan->resmgr, 0);
+ wcd9xxx_resmgr_put_bandgap(&tapan->resmgr,
+ WCD9XXX_BANDGAP_AUDIO_MODE);
+ wcd9xxx_resmgr_put_clk_block(&tapan->resmgr, WCD9XXX_CLK_RCO);
+ WCD9XXX_BCL_UNLOCK(&tapan->resmgr);
+ break;
+ }
+ return 0;
+}
+
+static int tapan_codec_enable_lineout(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = w->codec;
+ u16 lineout_gain_reg;
+
+ dev_dbg(codec->dev, "%s %d %s\n", __func__, event, w->name);
+
+ switch (w->shift) {
+ case 0:
+ lineout_gain_reg = TAPAN_A_RX_LINE_1_GAIN;
+ break;
+ case 1:
+ lineout_gain_reg = TAPAN_A_RX_LINE_2_GAIN;
+ break;
+ default:
+ pr_err("%s: Error, incorrect lineout register value\n",
+ __func__);
+ return -EINVAL;
+ }
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ snd_soc_update_bits(codec, lineout_gain_reg, 0x40, 0x40);
+ break;
+ case SND_SOC_DAPM_POST_PMU:
+ dev_dbg(codec->dev, "%s: sleeping 16 ms after %s PA turn on\n",
+ __func__, w->name);
+ usleep_range(16000, 16000);
+ break;
+ case SND_SOC_DAPM_POST_PMD:
+ snd_soc_update_bits(codec, lineout_gain_reg, 0x40, 0x00);
+ break;
+ }
+ return 0;
+}
+
+static int tapan_codec_enable_spk_pa(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ dev_dbg(w->codec->dev, "%s %d %s\n", __func__, event, w->name);
+ return 0;
+}
+
+static int tapan_codec_enable_dmic(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = w->codec;
+ struct tapan_priv *tapan = snd_soc_codec_get_drvdata(codec);
+ u8 dmic_clk_en;
+ u16 dmic_clk_reg;
+ s32 *dmic_clk_cnt;
+ unsigned int dmic;
+ int ret;
+
+ ret = kstrtouint(strpbrk(w->name, "123456"), 10, &dmic);
+ if (ret < 0) {
+ pr_err("%s: Invalid DMIC line on the codec\n", __func__);
+ return -EINVAL;
+ }
+
+ switch (dmic) {
+ case 1:
+ case 2:
+ dmic_clk_en = 0x01;
+ dmic_clk_cnt = &(tapan->dmic_1_2_clk_cnt);
+ dmic_clk_reg = TAPAN_A_CDC_CLK_DMIC_B1_CTL;
+ dev_dbg(codec->dev, "%s() event %d DMIC%d dmic_1_2_clk_cnt %d\n",
+ __func__, event, dmic, *dmic_clk_cnt);
+
+ break;
+
+ case 3:
+ case 4:
+ dmic_clk_en = 0x10;
+ dmic_clk_cnt = &(tapan->dmic_3_4_clk_cnt);
+ dmic_clk_reg = TAPAN_A_CDC_CLK_DMIC_B1_CTL;
+
+ dev_dbg(codec->dev, "%s() event %d DMIC%d dmic_3_4_clk_cnt %d\n",
+ __func__, event, dmic, *dmic_clk_cnt);
+ break;
+
+ case 5:
+ case 6:
+ dmic_clk_en = 0x01;
+ dmic_clk_cnt = &(tapan->dmic_5_6_clk_cnt);
+ dmic_clk_reg = TAPAN_A_CDC_CLK_DMIC_B2_CTL;
+
+ dev_dbg(codec->dev, "%s() event %d DMIC%d dmic_5_6_clk_cnt %d\n",
+ __func__, event, dmic, *dmic_clk_cnt);
+
+ break;
+
+ default:
+ pr_err("%s: Invalid DMIC Selection\n", __func__);
+ return -EINVAL;
+ }
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+
+ (*dmic_clk_cnt)++;
+ if (*dmic_clk_cnt == 1)
+ snd_soc_update_bits(codec, dmic_clk_reg,
+ dmic_clk_en, dmic_clk_en);
+
+ break;
+ case SND_SOC_DAPM_POST_PMD:
+
+ (*dmic_clk_cnt)--;
+ if (*dmic_clk_cnt == 0)
+ snd_soc_update_bits(codec, dmic_clk_reg,
+ dmic_clk_en, 0);
+ break;
+ }
+ return 0;
+}
+
+static int tapan_codec_enable_anc(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = w->codec;
+ const char *filename;
+ const struct firmware *fw;
+ int i;
+ int ret;
+ int num_anc_slots;
+ struct anc_header *anc_head;
+ struct tapan_priv *tapan = snd_soc_codec_get_drvdata(codec);
+ u32 anc_writes_size = 0;
+ int anc_size_remaining;
+ u32 *anc_ptr;
+ u16 reg;
+ u8 mask, val;
+
+ dev_dbg(codec->dev, "%s %d\n", __func__, event);
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+
+ filename = "wcd9306/wcd9306_anc.bin";
+
+ ret = request_firmware(&fw, filename, codec->dev);
+ if (ret != 0) {
+ dev_err(codec->dev, "Failed to acquire ANC data: %d\n",
+ ret);
+ return -ENODEV;
+ }
+
+ if (fw->size < sizeof(struct anc_header)) {
+ dev_err(codec->dev, "Not enough data\n");
+ release_firmware(fw);
+ return -ENOMEM;
+ }
+
+ /* First number is the number of register writes */
+ anc_head = (struct anc_header *)(fw->data);
+ anc_ptr = (u32 *)((u32)fw->data + sizeof(struct anc_header));
+ anc_size_remaining = fw->size - sizeof(struct anc_header);
+ num_anc_slots = anc_head->num_anc_slots;
+
+ if (tapan->anc_slot >= num_anc_slots) {
+ dev_err(codec->dev, "Invalid ANC slot selected\n");
+ release_firmware(fw);
+ return -EINVAL;
+ }
+
+ for (i = 0; i < num_anc_slots; i++) {
+
+ if (anc_size_remaining < TAPAN_PACKED_REG_SIZE) {
+ dev_err(codec->dev, "Invalid register format\n");
+ release_firmware(fw);
+ return -EINVAL;
+ }
+ anc_writes_size = (u32)(*anc_ptr);
+ anc_size_remaining -= sizeof(u32);
+ anc_ptr += 1;
+
+ if (anc_writes_size * TAPAN_PACKED_REG_SIZE
+ > anc_size_remaining) {
+ dev_err(codec->dev, "Invalid register format\n");
+ release_firmware(fw);
+ return -ENOMEM;
+ }
+
+ if (tapan->anc_slot == i)
+ break;
+
+ anc_size_remaining -= (anc_writes_size *
+ TAPAN_PACKED_REG_SIZE);
+ anc_ptr += anc_writes_size;
+ }
+ if (i == num_anc_slots) {
+ dev_err(codec->dev, "Selected ANC slot not present\n");
+ release_firmware(fw);
+ return -ENOMEM;
+ }
+
+ for (i = 0; i < anc_writes_size; i++) {
+ TAPAN_CODEC_UNPACK_ENTRY(anc_ptr[i], reg,
+ mask, val);
+ snd_soc_write(codec, reg, val);
+ }
+ release_firmware(fw);
+
+ break;
+ case SND_SOC_DAPM_POST_PMD:
+ snd_soc_write(codec, TAPAN_A_CDC_CLK_ANC_RESET_CTL, 0xFF);
+ snd_soc_write(codec, TAPAN_A_CDC_CLK_ANC_CLK_EN_CTL, 0);
+ break;
+ }
+ return 0;
+}
+
+static int tapan_codec_enable_micbias(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = w->codec;
+ struct tapan_priv *tapan = snd_soc_codec_get_drvdata(codec);
+ u16 micb_int_reg;
+ u8 cfilt_sel_val = 0;
+ char *internal1_text = "Internal1";
+ char *internal2_text = "Internal2";
+ char *internal3_text = "Internal3";
+ enum wcd9xxx_notify_event e_post_off, e_pre_on, e_post_on;
+
+ dev_dbg(codec->dev, "%s %d\n", __func__, event);
+ switch (w->reg) {
+ case TAPAN_A_MICB_1_CTL:
+ micb_int_reg = TAPAN_A_MICB_1_INT_RBIAS;
+ cfilt_sel_val = tapan->resmgr.pdata->micbias.bias1_cfilt_sel;
+ e_pre_on = WCD9XXX_EVENT_PRE_MICBIAS_1_ON;
+ e_post_on = WCD9XXX_EVENT_POST_MICBIAS_1_ON;
+ e_post_off = WCD9XXX_EVENT_POST_MICBIAS_1_OFF;
+ break;
+ case TAPAN_A_MICB_2_CTL:
+ micb_int_reg = TAPAN_A_MICB_2_INT_RBIAS;
+ cfilt_sel_val = tapan->resmgr.pdata->micbias.bias2_cfilt_sel;
+ e_pre_on = WCD9XXX_EVENT_PRE_MICBIAS_2_ON;
+ e_post_on = WCD9XXX_EVENT_POST_MICBIAS_2_ON;
+ e_post_off = WCD9XXX_EVENT_POST_MICBIAS_2_OFF;
+ break;
+ case TAPAN_A_MICB_3_CTL:
+ micb_int_reg = TAPAN_A_MICB_3_INT_RBIAS;
+ cfilt_sel_val = tapan->resmgr.pdata->micbias.bias3_cfilt_sel;
+ e_pre_on = WCD9XXX_EVENT_PRE_MICBIAS_3_ON;
+ e_post_on = WCD9XXX_EVENT_POST_MICBIAS_3_ON;
+ e_post_off = WCD9XXX_EVENT_POST_MICBIAS_3_OFF;
+ break;
+ default:
+ pr_err("%s: Error, invalid micbias register\n", __func__);
+ return -EINVAL;
+ }
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ /* Let MBHC module know so micbias switch to be off */
+ wcd9xxx_resmgr_notifier_call(&tapan->resmgr, e_pre_on);
+
+ /* Get cfilt */
+ wcd9xxx_resmgr_cfilt_get(&tapan->resmgr, cfilt_sel_val);
+
+ if (strnstr(w->name, internal1_text, 30))
+ snd_soc_update_bits(codec, micb_int_reg, 0xE0, 0xE0);
+ else if (strnstr(w->name, internal2_text, 30))
+ snd_soc_update_bits(codec, micb_int_reg, 0x1C, 0x1C);
+ else if (strnstr(w->name, internal3_text, 30))
+ snd_soc_update_bits(codec, micb_int_reg, 0x3, 0x3);
+
+ break;
+ case SND_SOC_DAPM_POST_PMU:
+ usleep_range(20000, 20000);
+ /* Let MBHC module know so micbias is on */
+ wcd9xxx_resmgr_notifier_call(&tapan->resmgr, e_post_on);
+ break;
+ case SND_SOC_DAPM_POST_PMD:
+ /* Let MBHC module know so micbias switch to be off */
+ wcd9xxx_resmgr_notifier_call(&tapan->resmgr, e_post_off);
+
+ if (strnstr(w->name, internal1_text, 30))
+ snd_soc_update_bits(codec, micb_int_reg, 0x80, 0x00);
+ else if (strnstr(w->name, internal2_text, 30))
+ snd_soc_update_bits(codec, micb_int_reg, 0x10, 0x00);
+ else if (strnstr(w->name, internal3_text, 30))
+ snd_soc_update_bits(codec, micb_int_reg, 0x2, 0x0);
+
+ /* Put cfilt */
+ wcd9xxx_resmgr_cfilt_put(&tapan->resmgr, cfilt_sel_val);
+ break;
+ }
+
+ return 0;
+}
+
+static void tx_hpf_corner_freq_callback(struct work_struct *work)
+{
+ struct delayed_work *hpf_delayed_work;
+ struct hpf_work *hpf_work;
+ struct tapan_priv *tapan;
+ struct snd_soc_codec *codec;
+ u16 tx_mux_ctl_reg;
+ u8 hpf_cut_of_freq;
+
+ hpf_delayed_work = to_delayed_work(work);
+ hpf_work = container_of(hpf_delayed_work, struct hpf_work, dwork);
+ tapan = hpf_work->tapan;
+ codec = hpf_work->tapan->codec;
+ hpf_cut_of_freq = hpf_work->tx_hpf_cut_of_freq;
+
+ tx_mux_ctl_reg = TAPAN_A_CDC_TX1_MUX_CTL +
+ (hpf_work->decimator - 1) * 8;
+
+ dev_dbg(codec->dev, "%s(): decimator %u hpf_cut_of_freq 0x%x\n",
+ __func__, hpf_work->decimator, (unsigned int)hpf_cut_of_freq);
+
+ snd_soc_update_bits(codec, tx_mux_ctl_reg, 0x30, hpf_cut_of_freq << 4);
+}
+
+#define TX_MUX_CTL_CUT_OFF_FREQ_MASK 0x30
+#define CF_MIN_3DB_4HZ 0x0
+#define CF_MIN_3DB_75HZ 0x1
+#define CF_MIN_3DB_150HZ 0x2
+
+static int tapan_codec_enable_dec(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = w->codec;
+ unsigned int decimator;
+ char *dec_name = NULL;
+ char *widget_name = NULL;
+ char *temp;
+ int ret = 0;
+ u16 dec_reset_reg, tx_vol_ctl_reg, tx_mux_ctl_reg;
+ u8 dec_hpf_cut_of_freq;
+ int offset;
+
+ dev_dbg(codec->dev, "%s %d\n", __func__, event);
+
+ widget_name = kstrndup(w->name, 15, GFP_KERNEL);
+ if (!widget_name)
+ return -ENOMEM;
+ temp = widget_name;
+
+ dec_name = strsep(&widget_name, " ");
+ widget_name = temp;
+ if (!dec_name) {
+ pr_err("%s: Invalid decimator = %s\n", __func__, w->name);
+ ret = -EINVAL;
+ goto out;
+ }
+
+ ret = kstrtouint(strpbrk(dec_name, "123456789"), 10, &decimator);
+ if (ret < 0) {
+ pr_err("%s: Invalid decimator = %s\n", __func__, dec_name);
+ ret = -EINVAL;
+ goto out;
+ }
+
+ dev_dbg(codec->dev, "%s(): widget = %s dec_name = %s decimator = %u\n",
+ __func__, w->name, dec_name, decimator);
+
+ if (w->reg == TAPAN_A_CDC_CLK_TX_CLK_EN_B1_CTL) {
+ dec_reset_reg = TAPAN_A_CDC_CLK_TX_RESET_B1_CTL;
+ offset = 0;
+ } else if (w->reg == TAPAN_A_CDC_CLK_TX_CLK_EN_B2_CTL) {
+ dec_reset_reg = TAPAN_A_CDC_CLK_TX_RESET_B2_CTL;
+ offset = 8;
+ } else {
+ pr_err("%s: Error, incorrect dec\n", __func__);
+ ret = -EINVAL;
+ goto out;
+ }
+
+ tx_vol_ctl_reg = TAPAN_A_CDC_TX1_VOL_CTL_CFG + 8 * (decimator - 1);
+ tx_mux_ctl_reg = TAPAN_A_CDC_TX1_MUX_CTL + 8 * (decimator - 1);
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+
+ /* Enableable TX digital mute */
+ snd_soc_update_bits(codec, tx_vol_ctl_reg, 0x01, 0x01);
+
+ snd_soc_update_bits(codec, dec_reset_reg, 1 << w->shift,
+ 1 << w->shift);
+ snd_soc_update_bits(codec, dec_reset_reg, 1 << w->shift, 0x0);
+
+ dec_hpf_cut_of_freq = snd_soc_read(codec, tx_mux_ctl_reg);
+
+ dec_hpf_cut_of_freq = (dec_hpf_cut_of_freq & 0x30) >> 4;
+
+ tx_hpf_work[decimator - 1].tx_hpf_cut_of_freq =
+ dec_hpf_cut_of_freq;
+
+ if ((dec_hpf_cut_of_freq != CF_MIN_3DB_150HZ)) {
+
+ /* set cut of freq to CF_MIN_3DB_150HZ (0x1); */
+ snd_soc_update_bits(codec, tx_mux_ctl_reg, 0x30,
+ CF_MIN_3DB_150HZ << 4);
+ }
+
+ /* enable HPF */
+ snd_soc_update_bits(codec, tx_mux_ctl_reg , 0x08, 0x00);
+
+ break;
+
+ case SND_SOC_DAPM_POST_PMU:
+
+ /* Disable TX digital mute */
+ snd_soc_update_bits(codec, tx_vol_ctl_reg, 0x01, 0x00);
+
+ if (tx_hpf_work[decimator - 1].tx_hpf_cut_of_freq !=
+ CF_MIN_3DB_150HZ) {
+
+ schedule_delayed_work(&tx_hpf_work[decimator - 1].dwork,
+ msecs_to_jiffies(300));
+ }
+ /* apply the digital gain after the decimator is enabled*/
+ if ((w->shift) < ARRAY_SIZE(tx_digital_gain_reg))
+ snd_soc_write(codec,
+ tx_digital_gain_reg[w->shift + offset],
+ snd_soc_read(codec,
+ tx_digital_gain_reg[w->shift + offset])
+ );
+
+ break;
+
+ case SND_SOC_DAPM_PRE_PMD:
+
+ snd_soc_update_bits(codec, tx_vol_ctl_reg, 0x01, 0x01);
+ cancel_delayed_work_sync(&tx_hpf_work[decimator - 1].dwork);
+ break;
+
+ case SND_SOC_DAPM_POST_PMD:
+
+ snd_soc_update_bits(codec, tx_mux_ctl_reg, 0x08, 0x08);
+ snd_soc_update_bits(codec, tx_mux_ctl_reg, 0x30,
+ (tx_hpf_work[decimator - 1].tx_hpf_cut_of_freq) << 4);
+
+ break;
+ }
+out:
+ kfree(widget_name);
+ return ret;
+}
+
+static int tapan_codec_enable_interpolator(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = w->codec;
+
+ dev_dbg(codec->dev, "%s %d %s\n", __func__, event, w->name);
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ snd_soc_update_bits(codec, TAPAN_A_CDC_CLK_RX_RESET_CTL,
+ 1 << w->shift, 1 << w->shift);
+ snd_soc_update_bits(codec, TAPAN_A_CDC_CLK_RX_RESET_CTL,
+ 1 << w->shift, 0x0);
+ break;
+ case SND_SOC_DAPM_POST_PMU:
+ /* apply the digital gain after the interpolator is enabled*/
+ if ((w->shift) < ARRAY_SIZE(rx_digital_gain_reg))
+ snd_soc_write(codec,
+ rx_digital_gain_reg[w->shift],
+ snd_soc_read(codec,
+ rx_digital_gain_reg[w->shift])
+ );
+ break;
+ }
+ return 0;
+}
+
+static int tapan_codec_enable_ldo_h(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ switch (event) {
+ case SND_SOC_DAPM_POST_PMU:
+ case SND_SOC_DAPM_POST_PMD:
+ usleep_range(1000, 1000);
+ break;
+ }
+ return 0;
+}
+
+static int tapan_codec_enable_rx_bias(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = w->codec;
+ struct tapan_priv *tapan = snd_soc_codec_get_drvdata(codec);
+
+ dev_dbg(codec->dev, "%s %d\n", __func__, event);
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ wcd9xxx_resmgr_enable_rx_bias(&tapan->resmgr, 1);
+ break;
+ case SND_SOC_DAPM_POST_PMD:
+ wcd9xxx_resmgr_enable_rx_bias(&tapan->resmgr, 0);
+ break;
+ }
+ return 0;
+}
+static int tapan_hphr_dac_event(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = w->codec;
+
+ dev_dbg(codec->dev, "%s %s %d\n", __func__, w->name, event);
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ snd_soc_update_bits(codec, w->reg, 0x40, 0x40);
+ break;
+ case SND_SOC_DAPM_POST_PMD:
+ snd_soc_update_bits(codec, w->reg, 0x40, 0x00);
+ break;
+ }
+ return 0;
+}
+
+static int tapan_hph_pa_event(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = w->codec;
+ struct tapan_priv *tapan = snd_soc_codec_get_drvdata(codec);
+ enum wcd9xxx_notify_event e_pre_on, e_post_off;
+
+ dev_dbg(codec->dev, "%s: %s event = %d\n", __func__, w->name, event);
+ if (w->shift == 5) {
+ e_pre_on = WCD9XXX_EVENT_PRE_HPHR_PA_ON;
+ e_post_off = WCD9XXX_EVENT_POST_HPHR_PA_OFF;
+ } else if (w->shift == 4) {
+ e_pre_on = WCD9XXX_EVENT_PRE_HPHL_PA_ON;
+ e_post_off = WCD9XXX_EVENT_POST_HPHL_PA_OFF;
+ } else {
+ pr_err("%s: Invalid w->shift %d\n", __func__, w->shift);
+ return -EINVAL;
+ }
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ /* Let MBHC module know PA is turning on */
+ wcd9xxx_resmgr_notifier_call(&tapan->resmgr, e_pre_on);
+ break;
+
+ case SND_SOC_DAPM_POST_PMU:
+ usleep_range(10000, 10000);
+
+ snd_soc_update_bits(codec, TAPAN_A_BUCK_MODE_5, 0x02, 0x00);
+ snd_soc_update_bits(codec, TAPAN_A_NCP_STATIC, 0x20, 0x00);
+ snd_soc_update_bits(codec, TAPAN_A_BUCK_MODE_3, 0x04, 0x04);
+ snd_soc_update_bits(codec, TAPAN_A_BUCK_MODE_3, 0x08, 0x00);
+
+ usleep_range(10, 10);
+ break;
+
+ case SND_SOC_DAPM_POST_PMD:
+ /* Let MBHC module know PA turned off */
+ wcd9xxx_resmgr_notifier_call(&tapan->resmgr, e_post_off);
+
+ /*
+ * schedule work is required because at the time HPH PA DAPM
+ * event callback is called by DAPM framework, CODEC dapm mutex
+ * would have been locked while snd_soc_jack_report also
+ * attempts to acquire same lock.
+ */
+ dev_dbg(codec->dev, "%s: sleep 10 ms after %s PA disable.\n",
+ __func__, w->name);
+ usleep_range(5000, 5000);
+ break;
+ }
+ return 0;
+}
+
+static int tapan_lineout_dac_event(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = w->codec;
+
+ dev_dbg(codec->dev, "%s %s %d\n", __func__, w->name, event);
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ snd_soc_update_bits(codec, w->reg, 0x40, 0x40);
+ break;
+
+ case SND_SOC_DAPM_POST_PMD:
+ snd_soc_update_bits(codec, w->reg, 0x40, 0x00);
+ break;
+ }
+ return 0;
+}
+
+static int tapan_spk_dac_event(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = w->codec;
+
+ dev_dbg(codec->dev, "%s %s %d\n", __func__, w->name, event);
+ return 0;
+}
+
+static const struct snd_soc_dapm_route audio_i2s_map[] = {
+ {"RX_I2S_CLK", NULL, "CDC_CONN"},
+ {"SLIM RX1", NULL, "RX_I2S_CLK"},
+ {"SLIM RX2", NULL, "RX_I2S_CLK"},
+
+ {"SLIM TX1 MUX", NULL, "TX_I2S_CLK"},
+ {"SLIM TX2 MUX", NULL, "TX_I2S_CLK"},
+};
+
+static const struct snd_soc_dapm_route audio_map[] = {
+ /* SLIMBUS Connections */
+ {"AIF1 CAP", NULL, "AIF1_CAP Mixer"},
+ {"AIF2 CAP", NULL, "AIF2_CAP Mixer"},
+ {"AIF3 CAP", NULL, "AIF3_CAP Mixer"},
+
+ /* SLIM_MIXER("AIF1_CAP Mixer"),*/
+ {"AIF1_CAP Mixer", "SLIM TX1", "SLIM TX1 MUX"},
+ {"AIF1_CAP Mixer", "SLIM TX2", "SLIM TX2 MUX"},
+ {"AIF1_CAP Mixer", "SLIM TX3", "SLIM TX3 MUX"},
+ {"AIF1_CAP Mixer", "SLIM TX4", "SLIM TX4 MUX"},
+ {"AIF1_CAP Mixer", "SLIM TX5", "SLIM TX5 MUX"},
+ {"AIF1_CAP Mixer", "SLIM TX6", "SLIM TX6 MUX"},
+ {"AIF1_CAP Mixer", "SLIM TX7", "SLIM TX7 MUX"},
+ {"AIF1_CAP Mixer", "SLIM TX8", "SLIM TX8 MUX"},
+ {"AIF1_CAP Mixer", "SLIM TX9", "SLIM TX9 MUX"},
+ {"AIF1_CAP Mixer", "SLIM TX10", "SLIM TX10 MUX"},
+ /* SLIM_MIXER("AIF2_CAP Mixer"),*/
+ {"AIF2_CAP Mixer", "SLIM TX1", "SLIM TX1 MUX"},
+ {"AIF2_CAP Mixer", "SLIM TX2", "SLIM TX2 MUX"},
+ {"AIF2_CAP Mixer", "SLIM TX3", "SLIM TX3 MUX"},
+ {"AIF2_CAP Mixer", "SLIM TX4", "SLIM TX4 MUX"},
+ {"AIF2_CAP Mixer", "SLIM TX5", "SLIM TX5 MUX"},
+ {"AIF2_CAP Mixer", "SLIM TX6", "SLIM TX6 MUX"},
+ {"AIF2_CAP Mixer", "SLIM TX7", "SLIM TX7 MUX"},
+ {"AIF2_CAP Mixer", "SLIM TX8", "SLIM TX8 MUX"},
+ {"AIF2_CAP Mixer", "SLIM TX9", "SLIM TX9 MUX"},
+ {"AIF2_CAP Mixer", "SLIM TX10", "SLIM TX10 MUX"},
+ /* SLIM_MIXER("AIF3_CAP Mixer"),*/
+ {"AIF3_CAP Mixer", "SLIM TX1", "SLIM TX1 MUX"},
+ {"AIF3_CAP Mixer", "SLIM TX2", "SLIM TX2 MUX"},
+ {"AIF3_CAP Mixer", "SLIM TX3", "SLIM TX3 MUX"},
+ {"AIF3_CAP Mixer", "SLIM TX4", "SLIM TX4 MUX"},
+ {"AIF3_CAP Mixer", "SLIM TX5", "SLIM TX5 MUX"},
+ {"AIF3_CAP Mixer", "SLIM TX6", "SLIM TX6 MUX"},
+ {"AIF3_CAP Mixer", "SLIM TX7", "SLIM TX7 MUX"},
+ {"AIF3_CAP Mixer", "SLIM TX8", "SLIM TX8 MUX"},
+ {"AIF3_CAP Mixer", "SLIM TX9", "SLIM TX9 MUX"},
+ {"AIF3_CAP Mixer", "SLIM TX10", "SLIM TX10 MUX"},
+
+ {"SLIM TX1 MUX", "DEC1", "DEC1 MUX"},
+
+ {"SLIM TX2 MUX", "DEC2", "DEC2 MUX"},
+
+ {"SLIM TX3 MUX", "DEC3", "DEC3 MUX"},
+ {"SLIM TX3 MUX", "RMIX1", "RX1 MIX1"},
+ {"SLIM TX3 MUX", "RMIX2", "RX2 MIX1"},
+ {"SLIM TX3 MUX", "RMIX3", "RX3 MIX1"},
+ {"SLIM TX3 MUX", "RMIX4", "RX4 MIX1"},
+ {"SLIM TX3 MUX", "RMIX5", "RX5 MIX1"},
+ {"SLIM TX3 MUX", "RMIX6", "RX6 MIX1"},
+ {"SLIM TX3 MUX", "RMIX7", "RX7 MIX1"},
+
+ {"SLIM TX4 MUX", "DEC4", "DEC4 MUX"},
+
+ {"SLIM TX5 MUX", "DEC5", "DEC5 MUX"},
+ {"SLIM TX5 MUX", "RMIX1", "RX1 MIX1"},
+ {"SLIM TX5 MUX", "RMIX2", "RX2 MIX1"},
+ {"SLIM TX5 MUX", "RMIX3", "RX3 MIX1"},
+ {"SLIM TX5 MUX", "RMIX4", "RX4 MIX1"},
+ {"SLIM TX5 MUX", "RMIX5", "RX5 MIX1"},
+ {"SLIM TX5 MUX", "RMIX6", "RX6 MIX1"},
+ {"SLIM TX5 MUX", "RMIX7", "RX7 MIX1"},
+
+ {"SLIM TX6 MUX", "DEC6", "DEC6 MUX"},
+
+ {"SLIM TX7 MUX", "DEC1", "DEC1 MUX"},
+ {"SLIM TX7 MUX", "DEC2", "DEC2 MUX"},
+ {"SLIM TX7 MUX", "DEC3", "DEC3 MUX"},
+ {"SLIM TX7 MUX", "DEC4", "DEC4 MUX"},
+ {"SLIM TX7 MUX", "DEC5", "DEC5 MUX"},
+ {"SLIM TX7 MUX", "DEC6", "DEC6 MUX"},
+ {"SLIM TX7 MUX", "DEC7", "DEC7 MUX"},
+ {"SLIM TX7 MUX", "DEC8", "DEC8 MUX"},
+ {"SLIM TX7 MUX", "DEC9", "DEC9 MUX"},
+ {"SLIM TX7 MUX", "DEC10", "DEC10 MUX"},
+ {"SLIM TX7 MUX", "RMIX1", "RX1 MIX1"},
+ {"SLIM TX7 MUX", "RMIX2", "RX2 MIX1"},
+ {"SLIM TX7 MUX", "RMIX3", "RX3 MIX1"},
+ {"SLIM TX7 MUX", "RMIX4", "RX4 MIX1"},
+ {"SLIM TX7 MUX", "RMIX5", "RX5 MIX1"},
+ {"SLIM TX7 MUX", "RMIX6", "RX6 MIX1"},
+ {"SLIM TX7 MUX", "RMIX7", "RX7 MIX1"},
+
+ {"SLIM TX8 MUX", "DEC1", "DEC1 MUX"},
+ {"SLIM TX8 MUX", "DEC2", "DEC2 MUX"},
+ {"SLIM TX8 MUX", "DEC3", "DEC3 MUX"},
+ {"SLIM TX8 MUX", "DEC4", "DEC4 MUX"},
+ {"SLIM TX8 MUX", "DEC5", "DEC5 MUX"},
+ {"SLIM TX8 MUX", "DEC6", "DEC6 MUX"},
+ {"SLIM TX8 MUX", "DEC7", "DEC7 MUX"},
+ {"SLIM TX8 MUX", "DEC8", "DEC8 MUX"},
+ {"SLIM TX8 MUX", "DEC9", "DEC9 MUX"},
+ {"SLIM TX8 MUX", "DEC10", "DEC10 MUX"},
+
+ {"SLIM TX9 MUX", "DEC1", "DEC1 MUX"},
+ {"SLIM TX9 MUX", "DEC2", "DEC2 MUX"},
+ {"SLIM TX9 MUX", "DEC3", "DEC3 MUX"},
+ {"SLIM TX9 MUX", "DEC4", "DEC4 MUX"},
+ {"SLIM TX9 MUX", "DEC5", "DEC5 MUX"},
+ {"SLIM TX9 MUX", "DEC6", "DEC6 MUX"},
+ {"SLIM TX9 MUX", "DEC7", "DEC7 MUX"},
+ {"SLIM TX9 MUX", "DEC8", "DEC8 MUX"},
+ {"SLIM TX9 MUX", "DEC9", "DEC9 MUX"},
+ {"SLIM TX9 MUX", "DEC10", "DEC10 MUX"},
+
+ {"SLIM TX10 MUX", "DEC1", "DEC1 MUX"},
+ {"SLIM TX10 MUX", "DEC2", "DEC2 MUX"},
+ {"SLIM TX10 MUX", "DEC3", "DEC3 MUX"},
+ {"SLIM TX10 MUX", "DEC4", "DEC4 MUX"},
+ {"SLIM TX10 MUX", "DEC5", "DEC5 MUX"},
+ {"SLIM TX10 MUX", "DEC6", "DEC6 MUX"},
+ {"SLIM TX10 MUX", "DEC7", "DEC7 MUX"},
+ {"SLIM TX10 MUX", "DEC8", "DEC8 MUX"},
+ {"SLIM TX10 MUX", "DEC9", "DEC9 MUX"},
+ {"SLIM TX10 MUX", "DEC10", "DEC10 MUX"},
+
+ /* Earpiece (RX MIX1) */
+ {"EAR", NULL, "EAR PA"},
+ {"EAR PA", NULL, "EAR_PA_MIXER"},
+ {"EAR_PA_MIXER", NULL, "DAC1"},
+ {"DAC1", NULL, "CP"},
+ {"CP", NULL, "CLASS_H_EAR"},
+ {"CLASS_H_EAR", NULL, "CLASS_H_CLK"},
+
+ {"ANC1 FB MUX", "EAR_HPH_L", "RX1 MIX2"},
+ {"ANC1 FB MUX", "EAR_LINE_1", "RX2 MIX2"},
+ {"ANC", NULL, "ANC1 FB MUX"},
+
+ /* Headset (RX MIX1 and RX MIX2) */
+ {"HEADPHONE", NULL, "HPHL"},
+ {"HEADPHONE", NULL, "HPHR"},
+
+ {"HPHL", NULL, "HPHL_PA_MIXER"},
+ {"HPHL_PA_MIXER", NULL, "HPHL DAC"},
+
+ {"HPHR", NULL, "HPHR_PA_MIXER"},
+ {"HPHR_PA_MIXER", NULL, "HPHR DAC"},
+
+ {"HPHL DAC", NULL, "CP"},
+ {"CP", NULL, "CLASS_H_HPH_L"},
+ {"CLASS_H_HPH_L", NULL, "CLASS_H_CLK"},
+
+ {"HPHR DAC", NULL, "CP"},
+ {"CP", NULL, "CLASS_H_HPH_R"},
+ {"CLASS_H_HPH_R", NULL, "CLASS_H_CLK"},
+
+ {"ANC", NULL, "ANC1 MUX"},
+ {"ANC", NULL, "ANC2 MUX"},
+ {"ANC1 MUX", "ADC1", "ADC1"},
+ {"ANC1 MUX", "ADC2", "ADC2"},
+ {"ANC1 MUX", "ADC3", "ADC3"},
+ {"ANC1 MUX", "ADC4", "ADC4"},
+ {"ANC2 MUX", "ADC1", "ADC1"},
+ {"ANC2 MUX", "ADC2", "ADC2"},
+ {"ANC2 MUX", "ADC3", "ADC3"},
+ {"ANC2 MUX", "ADC4", "ADC4"},
+
+ {"ANC", NULL, "CDC_CONN"},
+
+ {"DAC1", "Switch", "RX1 CHAIN"},
+ {"HPHL DAC", "Switch", "RX1 CHAIN"},
+ {"HPHR DAC", NULL, "RX2 CHAIN"},
+
+ {"LINEOUT1", NULL, "LINEOUT1 PA"},
+ {"LINEOUT2", NULL, "LINEOUT2 PA"},
+ {"LINEOUT3", NULL, "LINEOUT3 PA"},
+ {"LINEOUT4", NULL, "LINEOUT4 PA"},
+ {"SPK_OUT", NULL, "SPK PA"},
+
+ {"LINEOUT1 PA", NULL, "CP"},
+ {"LINEOUT1 PA", NULL, "LINEOUT1_PA_MIXER"},
+ {"LINEOUT1_PA_MIXER", NULL, "LINEOUT1 DAC"},
+
+ {"LINEOUT2 PA", NULL, "CP"},
+ {"LINEOUT2 PA", NULL, "LINEOUT2_PA_MIXER"},
+ {"LINEOUT2_PA_MIXER", NULL, "LINEOUT2 DAC"},
+
+ {"LINEOUT3 PA", NULL, "CP"},
+ {"LINEOUT3 PA", NULL, "LINEOUT3_PA_MIXER"},
+ {"LINEOUT3_PA_MIXER", NULL, "LINEOUT3 DAC"},
+
+ {"LINEOUT4 PA", NULL, "CP"},
+ {"LINEOUT4 PA", NULL, "LINEOUT4_PA_MIXER"},
+ {"LINEOUT4_PA_MIXER", NULL, "LINEOUT4 DAC"},
+
+ {"CP", NULL, "CLASS_H_LINEOUTS_PA"},
+ {"CLASS_H_LINEOUTS_PA", NULL, "CLASS_H_CLK"},
+
+ {"LINEOUT1 DAC", NULL, "RX3 MIX1"},
+
+ {"RDAC5 MUX", "DEM3_INV", "RX3 MIX1"},
+ {"RDAC5 MUX", "DEM4", "RX4 MIX1"},
+
+ {"LINEOUT3 DAC", NULL, "RDAC5 MUX"},
+
+ {"LINEOUT2 DAC", NULL, "RX5 MIX1"},
+
+ {"RDAC7 MUX", "DEM5_INV", "RX5 MIX1"},
+ {"RDAC7 MUX", "DEM6", "RX6 MIX1"},
+
+ {"LINEOUT4 DAC", NULL, "RDAC7 MUX"},
+
+ {"SPK PA", NULL, "SPK DAC"},
+ {"SPK DAC", NULL, "RX7 MIX2"},
+
+ {"RX1 CHAIN", NULL, "RX1 MIX2"},
+ {"RX2 CHAIN", NULL, "RX2 MIX2"},
+ {"RX1 CHAIN", NULL, "ANC"},
+ {"RX2 CHAIN", NULL, "ANC"},
+
+ {"CLASS_H_CLK", NULL, "RX_BIAS"},
+ {"LINEOUT1 DAC", NULL, "RX_BIAS"},
+ {"LINEOUT2 DAC", NULL, "RX_BIAS"},
+ {"LINEOUT3 DAC", NULL, "RX_BIAS"},
+ {"LINEOUT4 DAC", NULL, "RX_BIAS"},
+ {"SPK DAC", NULL, "RX_BIAS"},
+
+ {"RX1 MIX1", NULL, "COMP1_CLK"},
+ {"RX2 MIX1", NULL, "COMP1_CLK"},
+ {"RX3 MIX1", NULL, "COMP2_CLK"},
+ {"RX5 MIX1", NULL, "COMP2_CLK"},
+
+ {"RX1 MIX1", NULL, "RX1 MIX1 INP1"},
+ {"RX1 MIX1", NULL, "RX1 MIX1 INP2"},
+ {"RX1 MIX1", NULL, "RX1 MIX1 INP3"},
+ {"RX2 MIX1", NULL, "RX2 MIX1 INP1"},
+ {"RX2 MIX1", NULL, "RX2 MIX1 INP2"},
+ {"RX3 MIX1", NULL, "RX3 MIX1 INP1"},
+ {"RX3 MIX1", NULL, "RX3 MIX1 INP2"},
+ {"RX4 MIX1", NULL, "RX4 MIX1 INP1"},
+ {"RX4 MIX1", NULL, "RX4 MIX1 INP2"},
+ {"RX5 MIX1", NULL, "RX5 MIX1 INP1"},
+ {"RX5 MIX1", NULL, "RX5 MIX1 INP2"},
+ {"RX6 MIX1", NULL, "RX6 MIX1 INP1"},
+ {"RX6 MIX1", NULL, "RX6 MIX1 INP2"},
+ {"RX7 MIX1", NULL, "RX7 MIX1 INP1"},
+ {"RX7 MIX1", NULL, "RX7 MIX1 INP2"},
+ {"RX1 MIX2", NULL, "RX1 MIX1"},
+ {"RX1 MIX2", NULL, "RX1 MIX2 INP1"},
+ {"RX1 MIX2", NULL, "RX1 MIX2 INP2"},
+ {"RX2 MIX2", NULL, "RX2 MIX1"},
+ {"RX2 MIX2", NULL, "RX2 MIX2 INP1"},
+ {"RX2 MIX2", NULL, "RX2 MIX2 INP2"},
+ {"RX7 MIX2", NULL, "RX7 MIX1"},
+ {"RX7 MIX2", NULL, "RX7 MIX2 INP1"},
+ {"RX7 MIX2", NULL, "RX7 MIX2 INP2"},
+
+ /* SLIM_MUX("AIF1_PB", "AIF1 PB"),*/
+ {"SLIM RX1 MUX", "AIF1_PB", "AIF1 PB"},
+ {"SLIM RX2 MUX", "AIF1_PB", "AIF1 PB"},
+ {"SLIM RX3 MUX", "AIF1_PB", "AIF1 PB"},
+ {"SLIM RX4 MUX", "AIF1_PB", "AIF1 PB"},
+ {"SLIM RX5 MUX", "AIF1_PB", "AIF1 PB"},
+ {"SLIM RX6 MUX", "AIF1_PB", "AIF1 PB"},
+ {"SLIM RX7 MUX", "AIF1_PB", "AIF1 PB"},
+ /* SLIM_MUX("AIF2_PB", "AIF2 PB"),*/
+ {"SLIM RX1 MUX", "AIF2_PB", "AIF2 PB"},
+ {"SLIM RX2 MUX", "AIF2_PB", "AIF2 PB"},
+ {"SLIM RX3 MUX", "AIF2_PB", "AIF2 PB"},
+ {"SLIM RX4 MUX", "AIF2_PB", "AIF2 PB"},
+ {"SLIM RX5 MUX", "AIF2_PB", "AIF2 PB"},
+ {"SLIM RX6 MUX", "AIF2_PB", "AIF2 PB"},
+ {"SLIM RX7 MUX", "AIF2_PB", "AIF2 PB"},
+ /* SLIM_MUX("AIF3_PB", "AIF3 PB"),*/
+ {"SLIM RX1 MUX", "AIF3_PB", "AIF3 PB"},
+ {"SLIM RX2 MUX", "AIF3_PB", "AIF3 PB"},
+ {"SLIM RX3 MUX", "AIF3_PB", "AIF3 PB"},
+ {"SLIM RX4 MUX", "AIF3_PB", "AIF3 PB"},
+ {"SLIM RX5 MUX", "AIF3_PB", "AIF3 PB"},
+ {"SLIM RX6 MUX", "AIF3_PB", "AIF3 PB"},
+ {"SLIM RX7 MUX", "AIF3_PB", "AIF3 PB"},
+
+ {"SLIM RX1", NULL, "SLIM RX1 MUX"},
+ {"SLIM RX2", NULL, "SLIM RX2 MUX"},
+ {"SLIM RX3", NULL, "SLIM RX3 MUX"},
+ {"SLIM RX4", NULL, "SLIM RX4 MUX"},
+ {"SLIM RX5", NULL, "SLIM RX5 MUX"},
+ {"SLIM RX6", NULL, "SLIM RX6 MUX"},
+ {"SLIM RX7", NULL, "SLIM RX7 MUX"},
+
+ {"RX1 MIX1 INP1", "RX1", "SLIM RX1"},
+ {"RX1 MIX1 INP1", "RX2", "SLIM RX2"},
+ {"RX1 MIX1 INP1", "RX3", "SLIM RX3"},
+ {"RX1 MIX1 INP1", "RX4", "SLIM RX4"},
+ {"RX1 MIX1 INP1", "RX5", "SLIM RX5"},
+ {"RX1 MIX1 INP1", "RX6", "SLIM RX6"},
+ {"RX1 MIX1 INP1", "RX7", "SLIM RX7"},
+ {"RX1 MIX1 INP1", "IIR1", "IIR1"},
+ {"RX1 MIX1 INP2", "RX1", "SLIM RX1"},
+ {"RX1 MIX1 INP2", "RX2", "SLIM RX2"},
+ {"RX1 MIX1 INP2", "RX3", "SLIM RX3"},
+ {"RX1 MIX1 INP2", "RX4", "SLIM RX4"},
+ {"RX1 MIX1 INP2", "RX5", "SLIM RX5"},
+ {"RX1 MIX1 INP2", "RX6", "SLIM RX6"},
+ {"RX1 MIX1 INP2", "RX7", "SLIM RX7"},
+ {"RX1 MIX1 INP2", "IIR1", "IIR1"},
+ {"RX1 MIX1 INP3", "RX1", "SLIM RX1"},
+ {"RX1 MIX1 INP3", "RX2", "SLIM RX2"},
+ {"RX1 MIX1 INP3", "RX3", "SLIM RX3"},
+ {"RX1 MIX1 INP3", "RX4", "SLIM RX4"},
+ {"RX1 MIX1 INP3", "RX5", "SLIM RX5"},
+ {"RX1 MIX1 INP3", "RX6", "SLIM RX6"},
+ {"RX1 MIX1 INP3", "RX7", "SLIM RX7"},
+ {"RX2 MIX1 INP1", "RX1", "SLIM RX1"},
+ {"RX2 MIX1 INP1", "RX2", "SLIM RX2"},
+ {"RX2 MIX1 INP1", "RX3", "SLIM RX3"},
+ {"RX2 MIX1 INP1", "RX4", "SLIM RX4"},
+ {"RX2 MIX1 INP1", "RX5", "SLIM RX5"},
+ {"RX2 MIX1 INP1", "RX6", "SLIM RX6"},
+ {"RX2 MIX1 INP1", "RX7", "SLIM RX7"},
+ {"RX2 MIX1 INP1", "IIR1", "IIR1"},
+ {"RX2 MIX1 INP2", "RX1", "SLIM RX1"},
+ {"RX2 MIX1 INP2", "RX2", "SLIM RX2"},
+ {"RX2 MIX1 INP2", "RX3", "SLIM RX3"},
+ {"RX2 MIX1 INP2", "RX4", "SLIM RX4"},
+ {"RX2 MIX1 INP2", "RX5", "SLIM RX5"},
+ {"RX2 MIX1 INP2", "RX6", "SLIM RX6"},
+ {"RX2 MIX1 INP2", "RX7", "SLIM RX7"},
+ {"RX2 MIX1 INP2", "IIR1", "IIR1"},
+ {"RX3 MIX1 INP1", "RX1", "SLIM RX1"},
+ {"RX3 MIX1 INP1", "RX2", "SLIM RX2"},
+ {"RX3 MIX1 INP1", "RX3", "SLIM RX3"},
+ {"RX3 MIX1 INP1", "RX4", "SLIM RX4"},
+ {"RX3 MIX1 INP1", "RX5", "SLIM RX5"},
+ {"RX3 MIX1 INP1", "RX6", "SLIM RX6"},
+ {"RX3 MIX1 INP1", "RX7", "SLIM RX7"},
+ {"RX3 MIX1 INP1", "IIR1", "IIR1"},
+ {"RX3 MIX1 INP2", "RX1", "SLIM RX1"},
+ {"RX3 MIX1 INP2", "RX2", "SLIM RX2"},
+ {"RX3 MIX1 INP2", "RX3", "SLIM RX3"},
+ {"RX3 MIX1 INP2", "RX4", "SLIM RX4"},
+ {"RX3 MIX1 INP2", "RX5", "SLIM RX5"},
+ {"RX3 MIX1 INP2", "RX6", "SLIM RX6"},
+ {"RX3 MIX1 INP2", "RX7", "SLIM RX7"},
+ {"RX3 MIX1 INP2", "IIR1", "IIR1"},
+ {"RX4 MIX1 INP1", "RX1", "SLIM RX1"},
+ {"RX4 MIX1 INP1", "RX2", "SLIM RX2"},
+ {"RX4 MIX1 INP1", "RX3", "SLIM RX3"},
+ {"RX4 MIX1 INP1", "RX4", "SLIM RX4"},
+ {"RX4 MIX1 INP1", "RX5", "SLIM RX5"},
+ {"RX4 MIX1 INP1", "RX6", "SLIM RX6"},
+ {"RX4 MIX1 INP1", "RX7", "SLIM RX7"},
+ {"RX4 MIX1 INP1", "IIR1", "IIR1"},
+ {"RX4 MIX1 INP2", "RX1", "SLIM RX1"},
+ {"RX4 MIX1 INP2", "RX2", "SLIM RX2"},
+ {"RX4 MIX1 INP2", "RX3", "SLIM RX3"},
+ {"RX4 MIX1 INP2", "RX5", "SLIM RX5"},
+ {"RX4 MIX1 INP2", "RX4", "SLIM RX4"},
+ {"RX4 MIX1 INP2", "RX6", "SLIM RX6"},
+ {"RX4 MIX1 INP2", "RX7", "SLIM RX7"},
+ {"RX4 MIX1 INP2", "IIR1", "IIR1"},
+ {"RX5 MIX1 INP1", "RX1", "SLIM RX1"},
+ {"RX5 MIX1 INP1", "RX2", "SLIM RX2"},
+ {"RX5 MIX1 INP1", "RX3", "SLIM RX3"},
+ {"RX5 MIX1 INP1", "RX4", "SLIM RX4"},
+ {"RX5 MIX1 INP1", "RX5", "SLIM RX5"},
+ {"RX5 MIX1 INP1", "RX6", "SLIM RX6"},
+ {"RX5 MIX1 INP1", "RX7", "SLIM RX7"},
+ {"RX5 MIX1 INP1", "IIR1", "IIR1"},
+ {"RX5 MIX1 INP2", "RX1", "SLIM RX1"},
+ {"RX5 MIX1 INP2", "RX2", "SLIM RX2"},
+ {"RX5 MIX1 INP2", "RX3", "SLIM RX3"},
+ {"RX5 MIX1 INP2", "RX4", "SLIM RX4"},
+ {"RX5 MIX1 INP2", "RX5", "SLIM RX5"},
+ {"RX5 MIX1 INP2", "RX6", "SLIM RX6"},
+ {"RX5 MIX1 INP2", "RX7", "SLIM RX7"},
+ {"RX5 MIX1 INP2", "IIR1", "IIR1"},
+ {"RX6 MIX1 INP1", "RX1", "SLIM RX1"},
+ {"RX6 MIX1 INP1", "RX2", "SLIM RX2"},
+ {"RX6 MIX1 INP1", "RX3", "SLIM RX3"},
+ {"RX6 MIX1 INP1", "RX4", "SLIM RX4"},
+ {"RX6 MIX1 INP1", "RX5", "SLIM RX5"},
+ {"RX6 MIX1 INP1", "RX6", "SLIM RX6"},
+ {"RX6 MIX1 INP1", "RX7", "SLIM RX7"},
+ {"RX6 MIX1 INP1", "IIR1", "IIR1"},
+ {"RX6 MIX1 INP2", "RX1", "SLIM RX1"},
+ {"RX6 MIX1 INP2", "RX2", "SLIM RX2"},
+ {"RX6 MIX1 INP2", "RX3", "SLIM RX3"},
+ {"RX6 MIX1 INP2", "RX4", "SLIM RX4"},
+ {"RX6 MIX1 INP2", "RX5", "SLIM RX5"},
+ {"RX6 MIX1 INP2", "RX6", "SLIM RX6"},
+ {"RX6 MIX1 INP2", "RX7", "SLIM RX7"},
+ {"RX6 MIX1 INP2", "IIR1", "IIR1"},
+ {"RX7 MIX1 INP1", "RX1", "SLIM RX1"},
+ {"RX7 MIX1 INP1", "RX2", "SLIM RX2"},
+ {"RX7 MIX1 INP1", "RX3", "SLIM RX3"},
+ {"RX7 MIX1 INP1", "RX4", "SLIM RX4"},
+ {"RX7 MIX1 INP1", "RX5", "SLIM RX5"},
+ {"RX7 MIX1 INP1", "RX6", "SLIM RX6"},
+ {"RX7 MIX1 INP1", "RX7", "SLIM RX7"},
+ {"RX7 MIX1 INP1", "IIR1", "IIR1"},
+ {"RX7 MIX1 INP2", "RX1", "SLIM RX1"},
+ {"RX7 MIX1 INP2", "RX2", "SLIM RX2"},
+ {"RX7 MIX1 INP2", "RX3", "SLIM RX3"},
+ {"RX7 MIX1 INP2", "RX4", "SLIM RX4"},
+ {"RX7 MIX1 INP2", "RX5", "SLIM RX5"},
+ {"RX7 MIX1 INP2", "RX6", "SLIM RX6"},
+ {"RX7 MIX1 INP2", "RX7", "SLIM RX7"},
+ {"RX7 MIX1 INP2", "IIR1", "IIR1"},
+ {"RX1 MIX2 INP1", "IIR1", "IIR1"},
+ {"RX1 MIX2 INP2", "IIR1", "IIR1"},
+ {"RX2 MIX2 INP1", "IIR1", "IIR1"},
+ {"RX2 MIX2 INP2", "IIR1", "IIR1"},
+ {"RX7 MIX2 INP1", "IIR1", "IIR1"},
+ {"RX7 MIX2 INP2", "IIR1", "IIR1"},
+
+ /* Decimator Inputs */
+ {"DEC1 MUX", "DMIC1", "DMIC1"},
+ {"DEC1 MUX", "ADC6", "ADC6"},
+ {"DEC1 MUX", NULL, "CDC_CONN"},
+ {"DEC2 MUX", "DMIC2", "DMIC2"},
+ {"DEC2 MUX", "ADC5", "ADC5"},
+ {"DEC2 MUX", NULL, "CDC_CONN"},
+ {"DEC3 MUX", "DMIC3", "DMIC3"},
+ {"DEC3 MUX", "ADC4", "ADC4"},
+ {"DEC3 MUX", NULL, "CDC_CONN"},
+ {"DEC4 MUX", "DMIC4", "DMIC4"},
+ {"DEC4 MUX", "ADC3", "ADC3"},
+ {"DEC4 MUX", NULL, "CDC_CONN"},
+ {"DEC5 MUX", "DMIC5", "DMIC5"},
+ {"DEC5 MUX", "ADC2", "ADC2"},
+ {"DEC5 MUX", NULL, "CDC_CONN"},
+ {"DEC6 MUX", "DMIC6", "DMIC6"},
+ {"DEC6 MUX", "ADC1", "ADC1"},
+ {"DEC6 MUX", NULL, "CDC_CONN"},
+ {"DEC7 MUX", "DMIC1", "DMIC1"},
+ {"DEC7 MUX", "DMIC6", "DMIC6"},
+ {"DEC7 MUX", "ADC1", "ADC1"},
+ {"DEC7 MUX", "ADC6", "ADC6"},
+ {"DEC7 MUX", NULL, "CDC_CONN"},
+ {"DEC8 MUX", "DMIC2", "DMIC2"},
+ {"DEC8 MUX", "DMIC5", "DMIC5"},
+ {"DEC8 MUX", "ADC2", "ADC2"},
+ {"DEC8 MUX", "ADC5", "ADC5"},
+ {"DEC8 MUX", NULL, "CDC_CONN"},
+ {"DEC9 MUX", "DMIC4", "DMIC4"},
+ {"DEC9 MUX", "DMIC5", "DMIC5"},
+ {"DEC9 MUX", "ADC2", "ADC2"},
+ {"DEC9 MUX", "ADC3", "ADC3"},
+ {"DEC9 MUX", NULL, "CDC_CONN"},
+ {"DEC10 MUX", "DMIC3", "DMIC3"},
+ {"DEC10 MUX", "DMIC6", "DMIC6"},
+ {"DEC10 MUX", "ADC1", "ADC1"},
+ {"DEC10 MUX", "ADC4", "ADC4"},
+ {"DEC10 MUX", NULL, "CDC_CONN"},
+
+ /* ADC Connections */
+ {"ADC1", NULL, "AMIC1"},
+ {"ADC2", NULL, "AMIC2"},
+ {"ADC3", NULL, "AMIC3"},
+ {"ADC4", NULL, "AMIC4"},
+ {"ADC5", NULL, "AMIC5"},
+ {"ADC6", NULL, "AMIC6"},
+
+ /* AUX PGA Connections */
+ {"EAR_PA_MIXER", "AUX_PGA_L Switch", "AUX_PGA_Left"},
+ {"HPHL_PA_MIXER", "AUX_PGA_L Switch", "AUX_PGA_Left"},
+ {"HPHR_PA_MIXER", "AUX_PGA_R Switch", "AUX_PGA_Right"},
+ {"LINEOUT1_PA_MIXER", "AUX_PGA_L Switch", "AUX_PGA_Left"},
+ {"LINEOUT2_PA_MIXER", "AUX_PGA_R Switch", "AUX_PGA_Right"},
+ {"LINEOUT3_PA_MIXER", "AUX_PGA_L Switch", "AUX_PGA_Left"},
+ {"LINEOUT4_PA_MIXER", "AUX_PGA_R Switch", "AUX_PGA_Right"},
+ {"AUX_PGA_Left", NULL, "AMIC5"},
+ {"AUX_PGA_Right", NULL, "AMIC6"},
+
+ {"IIR1", NULL, "IIR1 INP1 MUX"},
+ {"IIR1 INP1 MUX", "DEC1", "DEC1 MUX"},
+ {"IIR1 INP1 MUX", "DEC2", "DEC2 MUX"},
+ {"IIR1 INP1 MUX", "DEC3", "DEC3 MUX"},
+ {"IIR1 INP1 MUX", "DEC4", "DEC4 MUX"},
+ {"IIR1 INP1 MUX", "DEC5", "DEC5 MUX"},
+ {"IIR1 INP1 MUX", "DEC6", "DEC6 MUX"},
+ {"IIR1 INP1 MUX", "DEC7", "DEC7 MUX"},
+ {"IIR1 INP1 MUX", "DEC8", "DEC8 MUX"},
+ {"IIR1 INP1 MUX", "DEC9", "DEC9 MUX"},
+ {"IIR1 INP1 MUX", "DEC10", "DEC10 MUX"},
+
+ {"MIC BIAS1 Internal1", NULL, "LDO_H"},
+ {"MIC BIAS1 Internal2", NULL, "LDO_H"},
+ {"MIC BIAS1 External", NULL, "LDO_H"},
+ {"MIC BIAS2 Internal1", NULL, "LDO_H"},
+ {"MIC BIAS2 Internal2", NULL, "LDO_H"},
+ {"MIC BIAS2 Internal3", NULL, "LDO_H"},
+ {"MIC BIAS2 External", NULL, "LDO_H"},
+ {"MIC BIAS3 Internal1", NULL, "LDO_H"},
+ {"MIC BIAS3 Internal2", NULL, "LDO_H"},
+ {"MIC BIAS3 External", NULL, "LDO_H"},
+ {"MIC BIAS4 External", NULL, "LDO_H"},
+};
+
+static int tapan_readable(struct snd_soc_codec *ssc, unsigned int reg)
+{
+ return tapan_reg_readable[reg];
+}
+
+static bool tapan_is_digital_gain_register(unsigned int reg)
+{
+ bool rtn = false;
+ switch (reg) {
+ case TAPAN_A_CDC_RX1_VOL_CTL_B2_CTL:
+ case TAPAN_A_CDC_RX2_VOL_CTL_B2_CTL:
+ case TAPAN_A_CDC_RX3_VOL_CTL_B2_CTL:
+ case TAPAN_A_CDC_RX4_VOL_CTL_B2_CTL:
+ case TAPAN_A_CDC_TX1_VOL_CTL_GAIN:
+ case TAPAN_A_CDC_TX2_VOL_CTL_GAIN:
+ case TAPAN_A_CDC_TX3_VOL_CTL_GAIN:
+ case TAPAN_A_CDC_TX4_VOL_CTL_GAIN:
+ rtn = true;
+ break;
+ default:
+ break;
+ }
+ return rtn;
+}
+
+static int tapan_volatile(struct snd_soc_codec *ssc, unsigned int reg)
+{
+ /* Registers lower than 0x100 are top level registers which can be
+ * written by the Taiko core driver.
+ */
+
+ if ((reg >= TAPAN_A_CDC_MBHC_EN_CTL) || (reg < 0x100))
+ return 1;
+
+ /* IIR Coeff registers are not cacheable */
+ if ((reg >= TAPAN_A_CDC_IIR1_COEF_B1_CTL) &&
+ (reg <= TAPAN_A_CDC_IIR2_COEF_B2_CTL))
+ return 1;
+
+ /* Digital gain register is not cacheable so we have to write
+ * the setting even it is the same
+ */
+ if (tapan_is_digital_gain_register(reg))
+ return 1;
+
+ /* HPH status registers */
+ if (reg == TAPAN_A_RX_HPH_L_STATUS || reg == TAPAN_A_RX_HPH_R_STATUS)
+ return 1;
+
+ if (reg == TAPAN_A_MBHC_INSERT_DET_STATUS)
+ return 1;
+
+ return 0;
+}
+
+#define TAPAN_FORMATS (SNDRV_PCM_FMTBIT_S16_LE)
+static int tapan_write(struct snd_soc_codec *codec, unsigned int reg,
+ unsigned int value)
+{
+ int ret;
+
+ if (reg == SND_SOC_NOPM)
+ return 0;
+
+ BUG_ON(reg > TAPAN_MAX_REGISTER);
+
+ if (!tapan_volatile(codec, reg)) {
+ ret = snd_soc_cache_write(codec, reg, value);
+ if (ret != 0)
+ dev_err(codec->dev, "Cache write to %x failed: %d\n",
+ reg, ret);
+ }
+
+ return wcd9xxx_reg_write(codec->control_data, reg, value);
+}
+static unsigned int tapan_read(struct snd_soc_codec *codec,
+ unsigned int reg)
+{
+ unsigned int val;
+ int ret;
+
+ if (reg == SND_SOC_NOPM)
+ return 0;
+
+ BUG_ON(reg > TAPAN_MAX_REGISTER);
+
+ if (!tapan_volatile(codec, reg) && tapan_readable(codec, reg) &&
+ reg < codec->driver->reg_cache_size) {
+ ret = snd_soc_cache_read(codec, reg, &val);
+ if (ret >= 0) {
+ return val;
+ } else
+ dev_err(codec->dev, "Cache read from %x failed: %d\n",
+ reg, ret);
+ }
+
+ val = wcd9xxx_reg_read(codec->control_data, reg);
+ return val;
+}
+
+static int tapan_startup(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *dai)
+{
+ struct wcd9xxx *tapan_core = dev_get_drvdata(dai->codec->dev->parent);
+ dev_dbg(dai->codec->dev, "%s(): substream = %s stream = %d\n",
+ __func__, substream->name, substream->stream);
+ if ((tapan_core != NULL) &&
+ (tapan_core->dev != NULL) &&
+ (tapan_core->dev->parent != NULL))
+ pm_runtime_get_sync(tapan_core->dev->parent);
+
+ return 0;
+}
+
+static void tapan_shutdown(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *dai)
+{
+ struct wcd9xxx *tapan_core = dev_get_drvdata(dai->codec->dev->parent);
+ dev_dbg(dai->codec->dev, "%s(): substream = %s stream = %d\n",
+ __func__, substream->name, substream->stream);
+ if ((tapan_core != NULL) &&
+ (tapan_core->dev != NULL) &&
+ (tapan_core->dev->parent != NULL)) {
+ pm_runtime_mark_last_busy(tapan_core->dev->parent);
+ pm_runtime_put(tapan_core->dev->parent);
+ }
+}
+
+int tapan_mclk_enable(struct snd_soc_codec *codec, int mclk_enable, bool dapm)
+{
+ struct tapan_priv *tapan = snd_soc_codec_get_drvdata(codec);
+
+ dev_dbg(codec->dev, "%s: mclk_enable = %u, dapm = %d\n", __func__,
+ mclk_enable, dapm);
+
+ WCD9XXX_BCL_LOCK(&tapan->resmgr);
+ if (mclk_enable) {
+ wcd9xxx_resmgr_get_bandgap(&tapan->resmgr,
+ WCD9XXX_BANDGAP_AUDIO_MODE);
+ wcd9xxx_resmgr_get_clk_block(&tapan->resmgr, WCD9XXX_CLK_MCLK);
+ } else {
+ /* Put clock and BG */
+ wcd9xxx_resmgr_put_clk_block(&tapan->resmgr, WCD9XXX_CLK_MCLK);
+ wcd9xxx_resmgr_put_bandgap(&tapan->resmgr,
+ WCD9XXX_BANDGAP_AUDIO_MODE);
+ }
+ WCD9XXX_BCL_UNLOCK(&tapan->resmgr);
+
+ return 0;
+}
+
+static int tapan_set_dai_sysclk(struct snd_soc_dai *dai,
+ int clk_id, unsigned int freq, int dir)
+{
+ dev_dbg(dai->codec->dev, "%s\n", __func__);
+ return 0;
+}
+
+static int tapan_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
+{
+ return 0;
+}
+
+static int tapan_set_channel_map(struct snd_soc_dai *dai,
+ unsigned int tx_num, unsigned int *tx_slot,
+ unsigned int rx_num, unsigned int *rx_slot)
+
+{
+ struct tapan_priv *tapan = snd_soc_codec_get_drvdata(dai->codec);
+ struct wcd9xxx *core = dev_get_drvdata(dai->codec->dev->parent);
+ if (!tx_slot && !rx_slot) {
+ pr_err("%s: Invalid\n", __func__);
+ return -EINVAL;
+ }
+ dev_dbg(dai->codec->dev, "%s(): dai_name = %s DAI-ID %x\n",
+ __func__, dai->name, dai->id);
+ dev_dbg(dai->codec->dev, "%s(): tx_ch %d rx_ch %d\n intf_type %d\n",
+ __func__, tx_num, rx_num, tapan->intf_type);
+
+ if (tapan->intf_type == WCD9XXX_INTERFACE_TYPE_SLIMBUS)
+ wcd9xxx_init_slimslave(core, core->slim->laddr,
+ tx_num, tx_slot, rx_num, rx_slot);
+ return 0;
+}
+
+static int tapan_get_channel_map(struct snd_soc_dai *dai,
+ unsigned int *tx_num, unsigned int *tx_slot,
+ unsigned int *rx_num, unsigned int *rx_slot)
+
+{
+ struct tapan_priv *tapan_p = snd_soc_codec_get_drvdata(dai->codec);
+ u32 i = 0;
+ struct wcd9xxx_ch *ch;
+
+ switch (dai->id) {
+ case AIF1_PB:
+ case AIF2_PB:
+ case AIF3_PB:
+ if (!rx_slot || !rx_num) {
+ pr_err("%s: Invalid rx_slot %d or rx_num %d\n",
+ __func__, (u32) rx_slot, (u32) rx_num);
+ return -EINVAL;
+ }
+ list_for_each_entry(ch, &tapan_p->dai[dai->id].wcd9xxx_ch_list,
+ list) {
+ dev_dbg(dai->codec->dev, "%s: rx_slot[%d] %d ch->ch_num %d\n",
+ __func__, i, rx_slot[i], ch->ch_num);
+ rx_slot[i++] = ch->ch_num;
+ }
+ dev_dbg(dai->codec->dev, "%s: rx_num %d\n", __func__, i);
+ *rx_num = i;
+ break;
+ case AIF1_CAP:
+ case AIF2_CAP:
+ case AIF3_CAP:
+ if (!tx_slot || !tx_num) {
+ pr_err("%s: Invalid tx_slot %d or tx_num %d\n",
+ __func__, (u32) tx_slot, (u32) tx_num);
+ return -EINVAL;
+ }
+ list_for_each_entry(ch, &tapan_p->dai[dai->id].wcd9xxx_ch_list,
+ list) {
+ dev_dbg(dai->codec->dev, "%s: tx_slot[%d] %d, ch->ch_num %d\n",
+ __func__, i, tx_slot[i], ch->ch_num);
+ tx_slot[i++] = ch->ch_num;
+ }
+ dev_dbg(dai->codec->dev, "%s: tx_num %d\n", __func__, i);
+ *tx_num = i;
+ break;
+
+ default:
+ pr_err("%s: Invalid DAI ID %x\n", __func__, dai->id);
+ break;
+ }
+
+ return 0;
+}
+
+static int tapan_set_interpolator_rate(struct snd_soc_dai *dai,
+ u8 rx_fs_rate_reg_val, u32 sample_rate)
+{
+ u32 j;
+ u8 rx_mix1_inp;
+ u16 rx_mix_1_reg_1, rx_mix_1_reg_2;
+ u16 rx_fs_reg;
+ u8 rx_mix_1_reg_1_val, rx_mix_1_reg_2_val;
+ struct snd_soc_codec *codec = dai->codec;
+ struct wcd9xxx_ch *ch;
+ struct tapan_priv *tapan = snd_soc_codec_get_drvdata(codec);
+
+ list_for_each_entry(ch, &tapan->dai[dai->id].wcd9xxx_ch_list, list) {
+ /* for RX port starting from 16 instead of 10 like tabla */
+ rx_mix1_inp = ch->port + RX_MIX1_INP_SEL_RX1 -
+ TAPAN_TX_PORT_NUMBER;
+ if ((rx_mix1_inp < RX_MIX1_INP_SEL_RX1) ||
+ (rx_mix1_inp > RX_MIX1_INP_SEL_RX7)) {
+ pr_err("%s: Invalid TAPAN_RX%u port. Dai ID is %d\n",
+ __func__, rx_mix1_inp - 5 , dai->id);
+ return -EINVAL;
+ }
+
+ rx_mix_1_reg_1 = TAPAN_A_CDC_CONN_RX1_B1_CTL;
+
+ for (j = 0; j < NUM_INTERPOLATORS; j++) {
+ rx_mix_1_reg_2 = rx_mix_1_reg_1 + 1;
+
+ rx_mix_1_reg_1_val = snd_soc_read(codec,
+ rx_mix_1_reg_1);
+ rx_mix_1_reg_2_val = snd_soc_read(codec,
+ rx_mix_1_reg_2);
+
+ if (((rx_mix_1_reg_1_val & 0x0F) == rx_mix1_inp) ||
+ (((rx_mix_1_reg_1_val >> 4) & 0x0F)
+ == rx_mix1_inp) ||
+ ((rx_mix_1_reg_2_val & 0x0F) == rx_mix1_inp)) {
+
+ rx_fs_reg = TAPAN_A_CDC_RX1_B5_CTL + 8 * j;
+
+ dev_dbg(codec->dev, "%s: AIF_PB DAI(%d) connected to RX%u\n",
+ __func__, dai->id, j + 1);
+
+ dev_dbg(codec->dev, "%s: set RX%u sample rate to %u\n",
+ __func__, j + 1, sample_rate);
+
+ snd_soc_update_bits(codec, rx_fs_reg,
+ 0xE0, rx_fs_rate_reg_val);
+
+ }
+ if (j <= 2)
+ rx_mix_1_reg_1 += 3;
+ else
+ rx_mix_1_reg_1 += 2;
+ }
+ }
+ return 0;
+}
+
+static int tapan_set_decimator_rate(struct snd_soc_dai *dai,
+ u8 tx_fs_rate_reg_val, u32 sample_rate)
+{
+ struct snd_soc_codec *codec = dai->codec;
+ struct wcd9xxx_ch *ch;
+ struct tapan_priv *tapan = snd_soc_codec_get_drvdata(codec);
+ u32 tx_port;
+ u16 tx_port_reg, tx_fs_reg;
+ u8 tx_port_reg_val;
+ s8 decimator;
+
+ list_for_each_entry(ch, &tapan->dai[dai->id].wcd9xxx_ch_list, list) {
+
+ tx_port = ch->port + 1;
+ dev_dbg(codec->dev, "%s: dai->id = %d, tx_port = %d",
+ __func__, dai->id, tx_port);
+
+ if ((tx_port < 1) || (tx_port > NUM_DECIMATORS)) {
+ pr_err("%s: Invalid SLIM TX%u port. DAI ID is %d\n",
+ __func__, tx_port, dai->id);
+ return -EINVAL;
+ }
+
+ tx_port_reg = TAPAN_A_CDC_CONN_TX_SB_B1_CTL + (tx_port - 1);
+ tx_port_reg_val = snd_soc_read(codec, tx_port_reg);
+
+ decimator = 0;
+
+ if ((tx_port >= 1) && (tx_port <= 6)) {
+
+ tx_port_reg_val = tx_port_reg_val & 0x0F;
+ if (tx_port_reg_val == 0x8)
+ decimator = tx_port;
+
+ } else if ((tx_port >= 7) && (tx_port <= NUM_DECIMATORS)) {
+
+ tx_port_reg_val = tx_port_reg_val & 0x1F;
+
+ if ((tx_port_reg_val >= 0x8) &&
+ (tx_port_reg_val <= 0x11)) {
+
+ decimator = (tx_port_reg_val - 0x8) + 1;
+ }
+ }
+
+ if (decimator) { /* SLIM_TX port has a DEC as input */
+
+ tx_fs_reg = TAPAN_A_CDC_TX1_CLK_FS_CTL +
+ 8 * (decimator - 1);
+
+ dev_dbg(codec->dev, "%s: set DEC%u (-> SLIM_TX%u) rate to %u\n",
+ __func__, decimator, tx_port, sample_rate);
+
+ snd_soc_update_bits(codec, tx_fs_reg, 0x07,
+ tx_fs_rate_reg_val);
+
+ } else {
+ if ((tx_port_reg_val >= 0x1) &&
+ (tx_port_reg_val <= 0x7)) {
+
+ dev_dbg(codec->dev, "%s: RMIX%u going to SLIM TX%u\n",
+ __func__, tx_port_reg_val, tx_port);
+
+ } else if ((tx_port_reg_val >= 0x8) &&
+ (tx_port_reg_val <= 0x11)) {
+
+ pr_err("%s: ERROR: Should not be here\n",
+ __func__);
+ pr_err("%s: ERROR: DEC connected to SLIM TX%u\n",
+ __func__, tx_port);
+ return -EINVAL;
+
+ } else if (tx_port_reg_val == 0) {
+ dev_dbg(codec->dev, "%s: no signal to SLIM TX%u\n",
+ __func__, tx_port);
+ } else {
+ pr_err("%s: ERROR: wrong signal to SLIM TX%u\n",
+ __func__, tx_port);
+ pr_err("%s: ERROR: wrong signal = %u\n",
+ __func__, tx_port_reg_val);
+ return -EINVAL;
+ }
+ }
+ }
+ return 0;
+}
+
+static int tapan_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params,
+ struct snd_soc_dai *dai)
+{
+ struct tapan_priv *tapan = snd_soc_codec_get_drvdata(dai->codec);
+ u8 tx_fs_rate, rx_fs_rate;
+ int ret;
+
+ dev_dbg(dai->codec->dev, "%s: dai_name = %s DAI-ID %x rate %d num_ch %d\n",
+ __func__, dai->name, dai->id,
+ params_rate(params), params_channels(params));
+
+ switch (params_rate(params)) {
+ case 8000:
+ tx_fs_rate = 0x00;
+ rx_fs_rate = 0x00;
+ break;
+ case 16000:
+ tx_fs_rate = 0x01;
+ rx_fs_rate = 0x20;
+ break;
+ case 32000:
+ tx_fs_rate = 0x02;
+ rx_fs_rate = 0x40;
+ break;
+ case 48000:
+ tx_fs_rate = 0x03;
+ rx_fs_rate = 0x60;
+ break;
+ case 96000:
+ tx_fs_rate = 0x04;
+ rx_fs_rate = 0x80;
+ break;
+ case 192000:
+ tx_fs_rate = 0x05;
+ rx_fs_rate = 0xA0;
+ break;
+ default:
+ pr_err("%s: Invalid sampling rate %d\n", __func__,
+ params_rate(params));
+ return -EINVAL;
+ }
+
+ switch (substream->stream) {
+ case SNDRV_PCM_STREAM_CAPTURE:
+ ret = tapan_set_decimator_rate(dai, tx_fs_rate,
+ params_rate(params));
+ if (ret < 0) {
+ pr_err("%s: set decimator rate failed %d\n", __func__,
+ ret);
+ return ret;
+ }
+
+ if (tapan->intf_type == WCD9XXX_INTERFACE_TYPE_I2C)
+ pr_err("%s: I2C interface not yet supported\n",
+ __func__);
+ else
+ tapan->dai[dai->id].rate = params_rate(params);
+
+ break;
+
+ case SNDRV_PCM_STREAM_PLAYBACK:
+ ret = tapan_set_interpolator_rate(dai, rx_fs_rate,
+ params_rate(params));
+ if (ret < 0) {
+ pr_err("%s: set decimator rate failed %d\n", __func__,
+ ret);
+ return ret;
+ }
+ if (tapan->intf_type == WCD9XXX_INTERFACE_TYPE_I2C)
+ pr_err("%s: I2C interface not yet supported\n",
+ __func__);
+ else
+ tapan->dai[dai->id].rate = params_rate(params);
+
+ break;
+ default:
+ pr_err("%s: Invalid stream type %d\n", __func__,
+ substream->stream);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static struct snd_soc_dai_ops tapan_dai_ops = {
+ .startup = tapan_startup,
+ .shutdown = tapan_shutdown,
+ .hw_params = tapan_hw_params,
+ .set_sysclk = tapan_set_dai_sysclk,
+ .set_fmt = tapan_set_dai_fmt,
+ .set_channel_map = tapan_set_channel_map,
+ .get_channel_map = tapan_get_channel_map,
+};
+
+static struct snd_soc_dai_driver tapan_dai[] = {
+ {
+ .name = "tapan_rx1",
+ .id = AIF1_PB,
+ .playback = {
+ .stream_name = "AIF1 Playback",
+ .rates = WCD9306_RATES,
+ .formats = TAPAN_FORMATS,
+ .rate_max = 192000,
+ .rate_min = 8000,
+ .channels_min = 1,
+ .channels_max = 2,
+ },
+ .ops = &tapan_dai_ops,
+ },
+ {
+ .name = "tapan_tx1",
+ .id = AIF1_CAP,
+ .capture = {
+ .stream_name = "AIF1 Capture",
+ .rates = WCD9306_RATES,
+ .formats = TAPAN_FORMATS,
+ .rate_max = 192000,
+ .rate_min = 8000,
+ .channels_min = 1,
+ .channels_max = 4,
+ },
+ .ops = &tapan_dai_ops,
+ },
+ {
+ .name = "tapan_rx2",
+ .id = AIF2_PB,
+ .playback = {
+ .stream_name = "AIF2 Playback",
+ .rates = WCD9306_RATES,
+ .formats = TAPAN_FORMATS,
+ .rate_min = 8000,
+ .rate_max = 192000,
+ .channels_min = 1,
+ .channels_max = 2,
+ },
+ .ops = &tapan_dai_ops,
+ },
+ {
+ .name = "tapan_tx2",
+ .id = AIF2_CAP,
+ .capture = {
+ .stream_name = "AIF2 Capture",
+ .rates = WCD9306_RATES,
+ .formats = TAPAN_FORMATS,
+ .rate_max = 192000,
+ .rate_min = 8000,
+ .channels_min = 1,
+ .channels_max = 4,
+ },
+ .ops = &tapan_dai_ops,
+ },
+ {
+ .name = "tapan_tx3",
+ .id = AIF3_CAP,
+ .capture = {
+ .stream_name = "AIF3 Capture",
+ .rates = WCD9306_RATES,
+ .formats = TAPAN_FORMATS,
+ .rate_max = 48000,
+ .rate_min = 8000,
+ .channels_min = 1,
+ .channels_max = 2,
+ },
+ .ops = &tapan_dai_ops,
+ },
+ {
+ .name = "tapan_rx3",
+ .id = AIF3_PB,
+ .playback = {
+ .stream_name = "AIF3 Playback",
+ .rates = WCD9306_RATES,
+ .formats = TAPAN_FORMATS,
+ .rate_min = 8000,
+ .rate_max = 192000,
+ .channels_min = 1,
+ .channels_max = 2,
+ },
+ .ops = &tapan_dai_ops,
+ },
+};
+
+static struct snd_soc_dai_driver tapan_i2s_dai[] = {
+ {
+ .name = "tapan_i2s_rx1",
+ .id = AIF1_PB,
+ .playback = {
+ .stream_name = "AIF1 Playback",
+ .rates = WCD9306_RATES,
+ .formats = TAPAN_FORMATS,
+ .rate_max = 192000,
+ .rate_min = 8000,
+ .channels_min = 1,
+ .channels_max = 4,
+ },
+ .ops = &tapan_dai_ops,
+ },
+ {
+ .name = "tapan_i2s_tx1",
+ .id = AIF1_CAP,
+ .capture = {
+ .stream_name = "AIF1 Capture",
+ .rates = WCD9306_RATES,
+ .formats = TAPAN_FORMATS,
+ .rate_max = 192000,
+ .rate_min = 8000,
+ .channels_min = 1,
+ .channels_max = 4,
+ },
+ .ops = &tapan_dai_ops,
+ },
+};
+
+static int tapan_codec_enable_slimrx(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol,
+ int event)
+{
+ struct wcd9xxx *core;
+ struct snd_soc_codec *codec = w->codec;
+ struct tapan_priv *tapan_p = snd_soc_codec_get_drvdata(codec);
+ u32 ret = 0;
+ struct wcd9xxx_codec_dai_data *dai;
+
+ core = dev_get_drvdata(codec->dev->parent);
+
+ dev_dbg(codec->dev, "%s: event called! codec name %s\n",
+ __func__, w->codec->name);
+ dev_dbg(codec->dev, "%s: num_dai %d stream name %s event %d\n",
+ __func__, w->codec->num_dai, w->sname, event);
+
+ /* Execute the callback only if interface type is slimbus */
+ if (tapan_p->intf_type != WCD9XXX_INTERFACE_TYPE_SLIMBUS)
+ return 0;
+
+ dai = &tapan_p->dai[w->shift];
+ dev_dbg(codec->dev, "%s: w->name %s w->shift %d event %d\n",
+ __func__, w->name, w->shift, event);
+
+ switch (event) {
+ case SND_SOC_DAPM_POST_PMU:
+ ret = wcd9xxx_cfg_slim_sch_rx(core, &dai->wcd9xxx_ch_list,
+ dai->rate, dai->bit_width,
+ &dai->grph);
+ break;
+ case SND_SOC_DAPM_POST_PMD:
+ ret = wcd9xxx_close_slim_sch_rx(core, &dai->wcd9xxx_ch_list,
+ dai->grph);
+ usleep_range(15000, 15000);
+ break;
+ }
+ return ret;
+}
+
+static int tapan_codec_enable_slimtx(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol,
+ int event)
+{
+ struct wcd9xxx *core;
+ struct snd_soc_codec *codec = w->codec;
+ struct tapan_priv *tapan_p = snd_soc_codec_get_drvdata(codec);
+ u32 ret = 0;
+ struct wcd9xxx_codec_dai_data *dai;
+
+ core = dev_get_drvdata(codec->dev->parent);
+
+ dev_dbg(codec->dev, "%s: event called! codec name %s\n",
+ __func__, w->codec->name);
+ dev_dbg(codec->dev, "%s: num_dai %d stream name %s\n",
+ __func__, w->codec->num_dai, w->sname);
+
+ /* Execute the callback only if interface type is slimbus */
+ if (tapan_p->intf_type != WCD9XXX_INTERFACE_TYPE_SLIMBUS)
+ return 0;
+
+ dev_dbg(codec->dev, "%s(): w->name %s event %d w->shift %d\n",
+ __func__, w->name, event, w->shift);
+
+ dai = &tapan_p->dai[w->shift];
+ switch (event) {
+ case SND_SOC_DAPM_POST_PMU:
+ ret = wcd9xxx_cfg_slim_sch_tx(core, &dai->wcd9xxx_ch_list,
+ dai->rate, dai->bit_width,
+ &dai->grph);
+ break;
+ case SND_SOC_DAPM_POST_PMD:
+ ret = wcd9xxx_close_slim_sch_tx(core, &dai->wcd9xxx_ch_list,
+ dai->grph);
+ break;
+ }
+ return ret;
+}
+
+static int tapan_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = w->codec;
+
+ dev_dbg(codec->dev, "%s %s %d\n", __func__, w->name, event);
+
+ switch (event) {
+
+ case SND_SOC_DAPM_POST_PMU:
+
+ snd_soc_update_bits(codec, TAPAN_A_BUCK_MODE_5, 0x02, 0x00);
+ snd_soc_update_bits(codec, TAPAN_A_NCP_STATIC, 0x20, 0x00);
+ snd_soc_update_bits(codec, TAPAN_A_BUCK_MODE_3, 0x04, 0x04);
+ snd_soc_update_bits(codec, TAPAN_A_BUCK_MODE_3, 0x08, 0x00);
+
+ usleep_range(5000, 5000);
+ break;
+ }
+ return 0;
+}
+
+/* Todo: Have seperate dapm widgets for I2S and Slimbus.
+ * Might Need to have callbacks registered only for slimbus
+ */
+static const struct snd_soc_dapm_widget tapan_dapm_widgets[] = {
+ /*RX stuff */
+ SND_SOC_DAPM_OUTPUT("EAR"),
+
+ SND_SOC_DAPM_PGA_E("EAR PA", TAPAN_A_RX_EAR_EN, 4, 0, NULL, 0,
+ tapan_codec_enable_ear_pa, SND_SOC_DAPM_POST_PMU),
+
+ SND_SOC_DAPM_MIXER("DAC1", TAPAN_A_RX_EAR_EN, 6, 0, dac1_switch,
+ ARRAY_SIZE(dac1_switch)),
+
+ SND_SOC_DAPM_AIF_IN_E("AIF1 PB", "AIF1 Playback", 0, SND_SOC_NOPM,
+ AIF1_PB, 0, tapan_codec_enable_slimrx,
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_AIF_IN_E("AIF2 PB", "AIF2 Playback", 0, SND_SOC_NOPM,
+ AIF2_PB, 0, tapan_codec_enable_slimrx,
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_AIF_IN_E("AIF3 PB", "AIF3 Playback", 0, SND_SOC_NOPM,
+ AIF3_PB, 0, tapan_codec_enable_slimrx,
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_MUX("SLIM RX1 MUX", SND_SOC_NOPM, TAPAN_RX1, 0,
+ &slim_rx_mux[TAPAN_RX1]),
+ SND_SOC_DAPM_MUX("SLIM RX2 MUX", SND_SOC_NOPM, TAPAN_RX2, 0,
+ &slim_rx_mux[TAPAN_RX2]),
+ SND_SOC_DAPM_MUX("SLIM RX3 MUX", SND_SOC_NOPM, TAPAN_RX3, 0,
+ &slim_rx_mux[TAPAN_RX3]),
+ SND_SOC_DAPM_MUX("SLIM RX4 MUX", SND_SOC_NOPM, TAPAN_RX4, 0,
+ &slim_rx_mux[TAPAN_RX4]),
+ SND_SOC_DAPM_MUX("SLIM RX5 MUX", SND_SOC_NOPM, TAPAN_RX5, 0,
+ &slim_rx_mux[TAPAN_RX5]),
+
+ SND_SOC_DAPM_MIXER("SLIM RX1", SND_SOC_NOPM, 0, 0, NULL, 0),
+ SND_SOC_DAPM_MIXER("SLIM RX2", SND_SOC_NOPM, 0, 0, NULL, 0),
+ SND_SOC_DAPM_MIXER("SLIM RX3", SND_SOC_NOPM, 0, 0, NULL, 0),
+ SND_SOC_DAPM_MIXER("SLIM RX4", SND_SOC_NOPM, 0, 0, NULL, 0),
+ SND_SOC_DAPM_MIXER("SLIM RX5", SND_SOC_NOPM, 0, 0, NULL, 0),
+
+ /* Headphone */
+ SND_SOC_DAPM_OUTPUT("HEADPHONE"),
+ SND_SOC_DAPM_PGA_E("HPHL", TAPAN_A_RX_HPH_CNP_EN, 5, 0, NULL, 0,
+ tapan_hph_pa_event, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_MIXER("HPHL DAC", TAPAN_A_RX_HPH_L_DAC_CTL, 7, 0,
+ hphl_switch, ARRAY_SIZE(hphl_switch)),
+
+ SND_SOC_DAPM_PGA_E("HPHR", TAPAN_A_RX_HPH_CNP_EN, 4, 0, NULL, 0,
+ tapan_hph_pa_event, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_DAC_E("HPHR DAC", NULL, TAPAN_A_RX_HPH_R_DAC_CTL, 7, 0,
+ tapan_hphr_dac_event,
+ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+
+ /* Speaker */
+ SND_SOC_DAPM_OUTPUT("LINEOUT1"),
+ SND_SOC_DAPM_OUTPUT("LINEOUT2"),
+ SND_SOC_DAPM_OUTPUT("SPK_OUT"),
+
+ SND_SOC_DAPM_PGA_E("LINEOUT1 PA", TAPAN_A_RX_LINE_CNP_EN, 0, 0, NULL,
+ 0, tapan_codec_enable_lineout, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_PGA_E("LINEOUT2 PA", TAPAN_A_RX_LINE_CNP_EN, 1, 0, NULL,
+ 0, tapan_codec_enable_lineout, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_PGA_E("SPK PA", TAPAN_A_SPKR_DRV_EN, 7, 0 , NULL,
+ 0, tapan_codec_enable_spk_pa, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_DAC_E("LINEOUT1 DAC", NULL, TAPAN_A_RX_LINE_1_DAC_CTL, 7, 0
+ , tapan_lineout_dac_event,
+ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_DAC_E("LINEOUT2 DAC", NULL, TAPAN_A_RX_LINE_2_DAC_CTL, 7, 0
+ , tapan_lineout_dac_event,
+ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_DAC_E("SPK DAC", NULL, SND_SOC_NOPM, 0, 0,
+ tapan_spk_dac_event,
+ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_MIXER("RX1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
+ SND_SOC_DAPM_MIXER("RX2 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
+
+ SND_SOC_DAPM_MIXER_E("RX1 MIX2", TAPAN_A_CDC_CLK_RX_B1_CTL, 0, 0, NULL,
+ 0, tapan_codec_enable_interpolator, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMU),
+ SND_SOC_DAPM_MIXER_E("RX2 MIX2", TAPAN_A_CDC_CLK_RX_B1_CTL, 1, 0, NULL,
+ 0, tapan_codec_enable_interpolator, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMU),
+ SND_SOC_DAPM_MIXER_E("RX3 MIX1", TAPAN_A_CDC_CLK_RX_B1_CTL, 2, 0, NULL,
+ 0, tapan_codec_enable_interpolator, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMU),
+ SND_SOC_DAPM_MIXER_E("RX4 MIX1", TAPAN_A_CDC_CLK_RX_B1_CTL, 3, 0, NULL,
+ 0, tapan_codec_enable_interpolator, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMU),
+ SND_SOC_DAPM_MIXER_E("RX5 MIX1", TAPAN_A_CDC_CLK_RX_B1_CTL, 4, 0, NULL,
+ 0, tapan_codec_enable_interpolator, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMU),
+
+ SND_SOC_DAPM_MIXER("RX1 CHAIN", TAPAN_A_CDC_RX1_B6_CTL, 5, 0, NULL, 0),
+ SND_SOC_DAPM_MIXER("RX2 CHAIN", TAPAN_A_CDC_RX2_B6_CTL, 5, 0, NULL, 0),
+
+ SND_SOC_DAPM_MUX("RX1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
+ &rx_mix1_inp1_mux),
+ SND_SOC_DAPM_MUX("RX1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
+ &rx_mix1_inp2_mux),
+ SND_SOC_DAPM_MUX("RX1 MIX1 INP3", SND_SOC_NOPM, 0, 0,
+ &rx_mix1_inp3_mux),
+ SND_SOC_DAPM_MUX("RX2 MIX1 INP1", SND_SOC_NOPM, 0, 0,
+ &rx2_mix1_inp1_mux),
+ SND_SOC_DAPM_MUX("RX2 MIX1 INP2", SND_SOC_NOPM, 0, 0,
+ &rx2_mix1_inp2_mux),
+ SND_SOC_DAPM_MUX("RX3 MIX1 INP1", SND_SOC_NOPM, 0, 0,
+ &rx3_mix1_inp1_mux),
+ SND_SOC_DAPM_MUX("RX3 MIX1 INP2", SND_SOC_NOPM, 0, 0,
+ &rx3_mix1_inp2_mux),
+ SND_SOC_DAPM_MUX("RX4 MIX1 INP1", SND_SOC_NOPM, 0, 0,
+ &rx4_mix1_inp1_mux),
+ SND_SOC_DAPM_MUX("RX4 MIX1 INP2", SND_SOC_NOPM, 0, 0,
+ &rx4_mix1_inp2_mux),
+ SND_SOC_DAPM_MUX("RX1 MIX2 INP1", SND_SOC_NOPM, 0, 0,
+ &rx1_mix2_inp1_mux),
+ SND_SOC_DAPM_MUX("RX1 MIX2 INP2", SND_SOC_NOPM, 0, 0,
+ &rx1_mix2_inp2_mux),
+ SND_SOC_DAPM_MUX("RX2 MIX2 INP1", SND_SOC_NOPM, 0, 0,
+ &rx2_mix2_inp1_mux),
+ SND_SOC_DAPM_MUX("RX2 MIX2 INP2", SND_SOC_NOPM, 0, 0,
+ &rx2_mix2_inp2_mux),
+
+ SND_SOC_DAPM_MUX("RDAC5 MUX", SND_SOC_NOPM, 0, 0,
+ &rx_dac5_mux),
+
+ SND_SOC_DAPM_SUPPLY("CLASS_H_CLK", TAPAN_A_CDC_CLK_OTHR_CTL, 0, 0,
+ tapan_codec_enable_class_h_clk, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_PRE_PMD),
+
+ SND_SOC_DAPM_SUPPLY("CLASS_H_EAR", TAPAN_A_CDC_CLSH_B1_CTL, 4, 0,
+ tapan_codec_enable_class_h, SND_SOC_DAPM_POST_PMU),
+
+ SND_SOC_DAPM_SUPPLY("CLASS_H_HPH_L", TAPAN_A_CDC_CLSH_B1_CTL, 3, 0,
+ tapan_codec_enable_class_h, SND_SOC_DAPM_POST_PMU),
+
+ SND_SOC_DAPM_SUPPLY("CLASS_H_HPH_R", TAPAN_A_CDC_CLSH_B1_CTL, 2, 0,
+ tapan_codec_enable_class_h, SND_SOC_DAPM_POST_PMU),
+
+ SND_SOC_DAPM_SUPPLY("CLASS_H_LINEOUTS_PA", SND_SOC_NOPM, 0, 0,
+ tapan_codec_enable_class_h, SND_SOC_DAPM_POST_PMU),
+
+ SND_SOC_DAPM_SUPPLY("CP", TAPAN_A_NCP_EN, 0, 0,
+ tapan_codec_enable_charge_pump, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
+
+ SND_SOC_DAPM_SUPPLY("RX_BIAS", SND_SOC_NOPM, 0, 0,
+ tapan_codec_enable_rx_bias, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMD),
+
+ /* TX */
+
+ SND_SOC_DAPM_SUPPLY("CDC_CONN", TAPAN_A_CDC_CLK_OTHR_CTL, 2, 0, NULL,
+ 0),
+
+ SND_SOC_DAPM_SUPPLY("LDO_H", TAPAN_A_LDO_H_MODE_1, 7, 0,
+ tapan_codec_enable_ldo_h, SND_SOC_DAPM_POST_PMU),
+
+ SND_SOC_DAPM_INPUT("AMIC1"),
+ SND_SOC_DAPM_MICBIAS_E("MIC BIAS1 External", TAPAN_A_MICB_1_CTL, 7, 0,
+ tapan_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_MICBIAS_E("MIC BIAS1 Internal1", TAPAN_A_MICB_1_CTL, 7, 0,
+ tapan_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_MICBIAS_E("MIC BIAS1 Internal2", TAPAN_A_MICB_1_CTL, 7, 0,
+ tapan_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_INPUT("AMIC3"),
+
+ SND_SOC_DAPM_INPUT("AMIC4"),
+
+ SND_SOC_DAPM_INPUT("AMIC5"),
+
+ SND_SOC_DAPM_MUX_E("DEC1 MUX", TAPAN_A_CDC_CLK_TX_CLK_EN_B1_CTL, 0, 0,
+ &dec1_mux, tapan_codec_enable_dec,
+ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
+ SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_MUX_E("DEC2 MUX", TAPAN_A_CDC_CLK_TX_CLK_EN_B1_CTL, 1, 0,
+ &dec2_mux, tapan_codec_enable_dec,
+ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
+ SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_MUX_E("DEC3 MUX", TAPAN_A_CDC_CLK_TX_CLK_EN_B1_CTL, 2, 0,
+ &dec3_mux, tapan_codec_enable_dec,
+ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
+ SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_MUX_E("DEC4 MUX", TAPAN_A_CDC_CLK_TX_CLK_EN_B1_CTL, 3, 0,
+ &dec4_mux, tapan_codec_enable_dec,
+ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
+ SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_MIXER_E("ANC", SND_SOC_NOPM, 0, 0, NULL, 0,
+ tapan_codec_enable_anc, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_INPUT("AMIC2"),
+ SND_SOC_DAPM_MICBIAS_E("MIC BIAS2 External", TAPAN_A_MICB_2_CTL, 7, 0,
+ tapan_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_MICBIAS_E("MIC BIAS2 Internal1", TAPAN_A_MICB_2_CTL, 7, 0,
+ tapan_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_MICBIAS_E("MIC BIAS2 Internal2", TAPAN_A_MICB_2_CTL, 7, 0,
+ tapan_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_MICBIAS_E("MIC BIAS2 Internal3", TAPAN_A_MICB_2_CTL, 7, 0,
+ tapan_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_MICBIAS_E("MIC BIAS3 External", TAPAN_A_MICB_3_CTL, 7, 0,
+ tapan_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_MICBIAS_E("MIC BIAS3 Internal1", TAPAN_A_MICB_3_CTL, 7, 0,
+ tapan_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_MICBIAS_E("MIC BIAS3 Internal2", TAPAN_A_MICB_3_CTL, 7, 0,
+ tapan_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_AIF_OUT_E("AIF1 CAP", "AIF1 Capture", 0, SND_SOC_NOPM,
+ AIF1_CAP, 0, tapan_codec_enable_slimtx,
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_AIF_OUT_E("AIF2 CAP", "AIF2 Capture", 0, SND_SOC_NOPM,
+ AIF2_CAP, 0, tapan_codec_enable_slimtx,
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_AIF_OUT_E("AIF3 CAP", "AIF3 Capture", 0, SND_SOC_NOPM,
+ AIF3_CAP, 0, tapan_codec_enable_slimtx,
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_MIXER("AIF1_CAP Mixer", SND_SOC_NOPM, AIF1_CAP, 0,
+ aif_cap_mixer, ARRAY_SIZE(aif_cap_mixer)),
+
+ SND_SOC_DAPM_MIXER("AIF2_CAP Mixer", SND_SOC_NOPM, AIF2_CAP, 0,
+ aif_cap_mixer, ARRAY_SIZE(aif_cap_mixer)),
+
+ SND_SOC_DAPM_MIXER("AIF3_CAP Mixer", SND_SOC_NOPM, AIF3_CAP, 0,
+ aif_cap_mixer, ARRAY_SIZE(aif_cap_mixer)),
+
+ SND_SOC_DAPM_MUX("SLIM TX1 MUX", SND_SOC_NOPM, TAPAN_TX1, 0,
+ &sb_tx1_mux),
+ SND_SOC_DAPM_MUX("SLIM TX2 MUX", SND_SOC_NOPM, TAPAN_TX2, 0,
+ &sb_tx2_mux),
+ SND_SOC_DAPM_MUX("SLIM TX3 MUX", SND_SOC_NOPM, TAPAN_TX3, 0,
+ &sb_tx3_mux),
+ SND_SOC_DAPM_MUX("SLIM TX4 MUX", SND_SOC_NOPM, TAPAN_TX4, 0,
+ &sb_tx4_mux),
+
+ /* Digital Mic Inputs */
+ SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
+ tapan_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 0, 0,
+ tapan_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 0, 0,
+ tapan_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 0, 0,
+ tapan_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMD),
+
+ /* Sidetone */
+ SND_SOC_DAPM_MUX("IIR1 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp1_mux),
+ SND_SOC_DAPM_PGA("IIR1", TAPAN_A_CDC_CLK_SD_CTL, 0, 0, NULL, 0),
+
+ /* AUX PGA */
+ SND_SOC_DAPM_ADC_E("AUX_PGA_Left", NULL, TAPAN_A_RX_AUX_SW_CTL, 7, 0,
+ tapan_codec_enable_aux_pga, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_ADC_E("AUX_PGA_Right", NULL, TAPAN_A_RX_AUX_SW_CTL, 6, 0,
+ tapan_codec_enable_aux_pga, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMD),
+
+ /* Lineout, ear and HPH PA Mixers */
+
+ SND_SOC_DAPM_MIXER("EAR_PA_MIXER", SND_SOC_NOPM, 0, 0,
+ ear_pa_mix, ARRAY_SIZE(ear_pa_mix)),
+
+ SND_SOC_DAPM_MIXER("HPHL_PA_MIXER", SND_SOC_NOPM, 0, 0,
+ hphl_pa_mix, ARRAY_SIZE(hphl_pa_mix)),
+
+ SND_SOC_DAPM_MIXER("HPHR_PA_MIXER", SND_SOC_NOPM, 0, 0,
+ hphr_pa_mix, ARRAY_SIZE(hphr_pa_mix)),
+
+ SND_SOC_DAPM_MIXER("LINEOUT1_PA_MIXER", SND_SOC_NOPM, 0, 0,
+ lineout1_pa_mix, ARRAY_SIZE(lineout1_pa_mix)),
+
+ SND_SOC_DAPM_MIXER("LINEOUT2_PA_MIXER", SND_SOC_NOPM, 0, 0,
+ lineout2_pa_mix, ARRAY_SIZE(lineout2_pa_mix)),
+
+};
+
+static unsigned long slimbus_value;
+
+static irqreturn_t tapan_slimbus_irq(int irq, void *data)
+{
+ struct tapan_priv *priv = data;
+ struct snd_soc_codec *codec = priv->codec;
+ int i, j;
+ u8 val;
+
+ for (i = 0; i < WCD9XXX_SLIM_NUM_PORT_REG; i++) {
+ slimbus_value = wcd9xxx_interface_reg_read(codec->control_data,
+ TAPAN_SLIM_PGD_PORT_INT_STATUS0 + i);
+ for_each_set_bit(j, &slimbus_value, BITS_PER_BYTE) {
+ val = wcd9xxx_interface_reg_read(codec->control_data,
+ TAPAN_SLIM_PGD_PORT_INT_SOURCE0 + i*8 + j);
+ if (val & 0x1)
+ pr_err_ratelimited(
+ "overflow error on port %x, value %x\n",
+ i*8 + j, val);
+ if (val & 0x2)
+ pr_err_ratelimited(
+ "underflow error on port %x, value %x\n",
+ i*8 + j, val);
+ }
+ wcd9xxx_interface_reg_write(codec->control_data,
+ TAPAN_SLIM_PGD_PORT_INT_CLR0 + i, 0xFF);
+
+ }
+ return IRQ_HANDLED;
+}
+
+static const struct tapan_reg_mask_val tapan_1_0_class_h_ear[] = {
+
+ /* CLASS-H EAR IDLE_THRESHOLD Table */
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_IDLE_EAR_THSD, 0x26),
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_FCLKONLY_EAR_THSD, 0x2C),
+
+ /* CLASS-H EAR I_PA_FACT Table. */
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_I_PA_FACT_EAR_L, 0xA9),
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_I_PA_FACT_EAR_U, 0x07),
+
+ /* CLASS-H EAR Voltage Headroom , Voltage Min. */
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_V_PA_HD_EAR, 0x0D),
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_V_PA_MIN_EAR, 0x3A),
+
+ /* CLASS-H EAR K values --chnages from load. */
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_K_ADDR, 0x08),
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_K_DATA, 0x1B),
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_K_DATA, 0x00),
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_K_DATA, 0x2D),
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_K_DATA, 0x00),
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_K_DATA, 0x36),
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_K_DATA, 0x00),
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_K_DATA, 0x37),
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_K_DATA, 0x00),
+ /** end of Ear PA load 32 */
+};
+
+static const struct tapan_reg_mask_val tapan_1_0_class_h_hph[] = {
+
+ /* CLASS-H HPH IDLE_THRESHOLD Table */
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_IDLE_HPH_THSD, 0x13),
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_FCLKONLY_HPH_THSD, 0x19),
+
+ /* CLASS-H HPH I_PA_FACT Table */
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_I_PA_FACT_HPH_L, 0x9A),
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_I_PA_FACT_HPH_U, 0x06),
+
+ /* CLASS-H HPH Voltage Headroom , Voltage Min */
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_V_PA_HD_HPH, 0x0D),
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_V_PA_MIN_HPH, 0x1D),
+
+ /* CLASS-H HPH K values --chnages from load .*/
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_K_ADDR, 0x00),
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_K_DATA, 0xAE),
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_K_DATA, 0x01),
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_K_DATA, 0x1C),
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_K_DATA, 0x00),
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_K_DATA, 0x25),
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_K_DATA, 0x00),
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_K_DATA, 0x27),
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_K_DATA, 0x00),
+};
+
+static int tapan_config_ear_class_h(struct snd_soc_codec *codec, u32 ear_load)
+{
+ u32 i;
+
+ if (ear_load != 32)
+ return -EINVAL;
+
+ for (i = 0; i < ARRAY_SIZE(tapan_1_0_class_h_ear); i++)
+ snd_soc_write(codec, tapan_1_0_class_h_ear[i].reg,
+ tapan_1_0_class_h_ear[i].val);
+ return 0;
+}
+
+static int tapan_config_hph_class_h(struct snd_soc_codec *codec, u32 hph_load)
+{
+ u32 i;
+ if (hph_load != 16)
+ return -EINVAL;
+
+ for (i = 0; i < ARRAY_SIZE(tapan_1_0_class_h_hph); i++)
+ snd_soc_write(codec, tapan_1_0_class_h_hph[i].reg,
+ tapan_1_0_class_h_hph[i].val);
+ return 0;
+}
+
+static int tapan_handle_pdata(struct tapan_priv *tapan)
+{
+ struct snd_soc_codec *codec = tapan->codec;
+ struct wcd9xxx_pdata *pdata = tapan->resmgr.pdata;
+ int k1, k2, k3, rc = 0;
+ u8 leg_mode, txfe_bypass, txfe_buff, flag;
+ u8 value = 0;
+
+ if (!pdata) {
+ pr_err("%s: NULL pdata\n", __func__);
+ rc = -ENODEV;
+ goto done;
+ }
+
+ leg_mode = pdata->amic_settings.legacy_mode;
+ txfe_bypass = pdata->amic_settings.txfe_enable;
+ txfe_buff = pdata->amic_settings.txfe_buff;
+ flag = pdata->amic_settings.use_pdata;
+
+ /* Make sure settings are correct */
+ if ((pdata->micbias.ldoh_v > WCD9XXX_LDOH_3P0_V) ||
+ (pdata->micbias.bias1_cfilt_sel > WCD9XXX_CFILT3_SEL) ||
+ (pdata->micbias.bias2_cfilt_sel > WCD9XXX_CFILT3_SEL) ||
+ (pdata->micbias.bias3_cfilt_sel > WCD9XXX_CFILT3_SEL)) {
+ rc = -EINVAL;
+ goto done;
+ }
+ /* figure out k value */
+ k1 = wcd9xxx_resmgr_get_k_val(&tapan->resmgr, pdata->micbias.cfilt1_mv);
+ k2 = wcd9xxx_resmgr_get_k_val(&tapan->resmgr, pdata->micbias.cfilt2_mv);
+ k3 = wcd9xxx_resmgr_get_k_val(&tapan->resmgr, pdata->micbias.cfilt3_mv);
+
+ if (IS_ERR_VALUE(k1) || IS_ERR_VALUE(k2) || IS_ERR_VALUE(k3)) {
+ rc = -EINVAL;
+ goto done;
+ }
+ /* Set voltage level and always use LDO */
+ snd_soc_update_bits(codec, TAPAN_A_LDO_H_MODE_1, 0x0C,
+ (pdata->micbias.ldoh_v << 2));
+
+ snd_soc_update_bits(codec, TAPAN_A_MICB_CFILT_1_VAL, 0xFC, (k1 << 2));
+ snd_soc_update_bits(codec, TAPAN_A_MICB_CFILT_2_VAL, 0xFC, (k2 << 2));
+ snd_soc_update_bits(codec, TAPAN_A_MICB_CFILT_3_VAL, 0xFC, (k3 << 2));
+
+ snd_soc_update_bits(codec, TAPAN_A_MICB_1_CTL, 0x60,
+ (pdata->micbias.bias1_cfilt_sel << 5));
+ snd_soc_update_bits(codec, TAPAN_A_MICB_2_CTL, 0x60,
+ (pdata->micbias.bias2_cfilt_sel << 5));
+ snd_soc_update_bits(codec, TAPAN_A_MICB_3_CTL, 0x60,
+ (pdata->micbias.bias3_cfilt_sel << 5));
+
+ if (flag & 0x40) {
+ value = (leg_mode & 0x40) ? 0x10 : 0x00;
+ value = value | ((txfe_bypass & 0x40) ? 0x02 : 0x00);
+ value = value | ((txfe_buff & 0x40) ? 0x01 : 0x00);
+ snd_soc_update_bits(codec, TAPAN_A_TX_7_MBHC_EN,
+ 0x13, value);
+ }
+
+ if (pdata->ocp.use_pdata) {
+ /* not defined in CODEC specification */
+ if (pdata->ocp.hph_ocp_limit == 1 ||
+ pdata->ocp.hph_ocp_limit == 5) {
+ rc = -EINVAL;
+ goto done;
+ }
+ snd_soc_update_bits(codec, TAPAN_A_RX_COM_OCP_CTL,
+ 0x0F, pdata->ocp.num_attempts);
+ snd_soc_write(codec, TAPAN_A_RX_COM_OCP_COUNT,
+ ((pdata->ocp.run_time << 4) | pdata->ocp.wait_time));
+ snd_soc_update_bits(codec, TAPAN_A_RX_HPH_OCP_CTL,
+ 0xE0, (pdata->ocp.hph_ocp_limit << 5));
+ }
+
+ tapan_config_ear_class_h(codec, 32);
+ tapan_config_hph_class_h(codec, 16);
+
+done:
+ return rc;
+}
+
+static const struct tapan_reg_mask_val tapan_reg_defaults[] = {
+
+ /* set MCLk to 9.6 */
+ TAPAN_REG_VAL(TAPAN_A_CHIP_CTL, 0x0A),
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLK_POWER_CTL, 0x03),
+
+ /* EAR PA deafults */
+ TAPAN_REG_VAL(TAPAN_A_RX_EAR_CMBUFF, 0x05),
+
+ /** BUCK and NCP defaults for EAR and HS */
+ TAPAN_REG_VAL(TAPAN_A_BUCK_CTRL_CCL_4, 0x50),
+ TAPAN_REG_VAL(TAPAN_A_BUCK_CTRL_CCL_1, 0x5B),
+
+ /* CLASS-H defaults for EAR and HS */
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_BUCK_NCP_VARS, 0x00),
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_BUCK_NCP_VARS, 0x04),
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_B2_CTL, 0x01),
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_B2_CTL, 0x05),
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_B2_CTL, 0x35),
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_B3_CTL, 0x30),
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_B3_CTL, 0x3B),
+
+ /*
+ * For CLASS-H, Enable ANC delay buffer,
+ * set HPHL and EAR PA ref gain to 0 DB.
+ */
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_B1_CTL, 0x26),
+
+ /* RX deafults */
+ TAPAN_REG_VAL(TAPAN_A_CDC_RX1_B5_CTL, 0x78),
+ TAPAN_REG_VAL(TAPAN_A_CDC_RX2_B5_CTL, 0x78),
+ TAPAN_REG_VAL(TAPAN_A_CDC_RX3_B5_CTL, 0x78),
+ TAPAN_REG_VAL(TAPAN_A_CDC_RX4_B5_CTL, 0x78),
+
+ /* RX1 and RX2 defaults */
+ TAPAN_REG_VAL(TAPAN_A_CDC_RX1_B6_CTL, 0xA0),
+ TAPAN_REG_VAL(TAPAN_A_CDC_RX2_B6_CTL, 0xA0),
+
+ /* RX3 to RX7 defaults */
+ TAPAN_REG_VAL(TAPAN_A_CDC_RX3_B6_CTL, 0x80),
+ TAPAN_REG_VAL(TAPAN_A_CDC_RX4_B6_CTL, 0x80),
+
+ /*
+ * The following only need to be written for Taiko 1.0 parts.
+ * Taiko 2.0 will have appropriate defaults for these registers.
+ */
+ /* Choose max non-overlap time for NCP */
+ TAPAN_REG_VAL(TAPAN_A_NCP_CLK, 0xFC),
+ /* Use 25mV/50mV for deltap/m to reduce ripple */
+ TAPAN_REG_VAL(TAPAN_A_BUCK_CTRL_VCL_1, 0x08),
+ /*
+ * Set DISABLE_MODE_SEL<1:0> to 0b10 (disable PWM in auto mode).
+ * Note that the other bits of this register will be changed during
+ * Rx PA bring up.
+ */
+ TAPAN_REG_VAL(TAPAN_A_BUCK_MODE_3, 0xCE),
+ /* Reduce HPH DAC bias to 70% */
+ TAPAN_REG_VAL(TAPAN_A_RX_HPH_BIAS_PA, 0x7A),
+ /*Reduce EAR DAC bias to 70% */
+ TAPAN_REG_VAL(TAPAN_A_RX_EAR_BIAS_PA, 0x76),
+ /* Reduce LINE DAC bias to 70% */
+ TAPAN_REG_VAL(TAPAN_A_RX_LINE_BIAS_PA, 0x78),
+
+ /*
+ * There is a diode to pull down the micbias while doing
+ * insertion detection. This diode can cause leakage.
+ * Set bit 0 to 1 to prevent leakage.
+ * Setting this bit of micbias 2 prevents leakage for all other micbias.
+ */
+ TAPAN_REG_VAL(TAPAN_A_MICB_2_MBHC, 0x41),
+
+ /* Disable TX7 internal biasing path which can cause leakage */
+ TAPAN_REG_VAL(TAPAN_A_TX_SUP_SWITCH_CTRL_1, 0xBF),
+};
+
+static void tapan_update_reg_defaults(struct snd_soc_codec *codec)
+{
+ u32 i;
+
+ for (i = 0; i < ARRAY_SIZE(tapan_reg_defaults); i++)
+ snd_soc_write(codec, tapan_reg_defaults[i].reg,
+ tapan_reg_defaults[i].val);
+}
+
+static const struct tapan_reg_mask_val tapan_codec_reg_init_val[] = {
+ /* Initialize current threshold to 350MA
+ * number of wait and run cycles to 4096
+ */
+ {TAPAN_A_RX_HPH_OCP_CTL, 0xE1, 0x61},
+ {TAPAN_A_RX_COM_OCP_COUNT, 0xFF, 0xFF},
+
+ /* Initialize gain registers to use register gain */
+ {TAPAN_A_RX_HPH_L_GAIN, 0x20, 0x20},
+ {TAPAN_A_RX_HPH_R_GAIN, 0x20, 0x20},
+ {TAPAN_A_RX_LINE_1_GAIN, 0x20, 0x20},
+ {TAPAN_A_RX_LINE_2_GAIN, 0x20, 0x20},
+
+ /* CLASS H config */
+ {TAPAN_A_CDC_CONN_CLSH_CTL, 0x3C, 0x14},
+
+ /* Use 16 bit sample size for TX1 to TX6 */
+ {TAPAN_A_CDC_CONN_TX_SB_B1_CTL, 0x30, 0x20},
+ {TAPAN_A_CDC_CONN_TX_SB_B2_CTL, 0x30, 0x20},
+ {TAPAN_A_CDC_CONN_TX_SB_B3_CTL, 0x30, 0x20},
+ {TAPAN_A_CDC_CONN_TX_SB_B4_CTL, 0x30, 0x20},
+ {TAPAN_A_CDC_CONN_TX_SB_B5_CTL, 0x30, 0x20},
+
+ /* Use 16 bit sample size for RX */
+ {TAPAN_A_CDC_CONN_RX_SB_B1_CTL, 0xFF, 0xAA},
+ {TAPAN_A_CDC_CONN_RX_SB_B2_CTL, 0xFF, 0x2A},
+
+ /*enable HPF filter for TX paths */
+ {TAPAN_A_CDC_TX1_MUX_CTL, 0x8, 0x0},
+ {TAPAN_A_CDC_TX2_MUX_CTL, 0x8, 0x0},
+ {TAPAN_A_CDC_TX3_MUX_CTL, 0x8, 0x0},
+ {TAPAN_A_CDC_TX4_MUX_CTL, 0x8, 0x0},
+
+ /* config Decimator for DMIC CLK_MODE_1(3.2Mhz@9.6Mhz mclk) */
+ {TAPAN_A_CDC_TX1_DMIC_CTL, 0x7, 0x1},
+ {TAPAN_A_CDC_TX2_DMIC_CTL, 0x7, 0x1},
+ {TAPAN_A_CDC_TX3_DMIC_CTL, 0x7, 0x1},
+ {TAPAN_A_CDC_TX4_DMIC_CTL, 0x7, 0x1},
+
+ /* config DMIC clk to CLK_MODE_1 (3.2Mhz@9.6Mhz mclk) */
+ {TAPAN_A_CDC_CLK_DMIC_B1_CTL, 0xEE, 0x22},
+ {TAPAN_A_CDC_CLK_DMIC_B2_CTL, 0x0E, 0x02},
+
+};
+
+static void tapan_codec_init_reg(struct snd_soc_codec *codec)
+{
+ u32 i;
+
+ for (i = 0; i < ARRAY_SIZE(tapan_codec_reg_init_val); i++)
+ snd_soc_update_bits(codec, tapan_codec_reg_init_val[i].reg,
+ tapan_codec_reg_init_val[i].mask,
+ tapan_codec_reg_init_val[i].val);
+}
+
+static int tapan_setup_irqs(struct tapan_priv *tapan)
+{
+ int i;
+ int ret = 0;
+ struct snd_soc_codec *codec = tapan->codec;
+
+ ret = wcd9xxx_request_irq(codec->control_data, WCD9XXX_IRQ_SLIMBUS,
+ tapan_slimbus_irq, "SLIMBUS Slave", tapan);
+ if (ret) {
+ pr_err("%s: Failed to request irq %d\n", __func__,
+ WCD9XXX_IRQ_SLIMBUS);
+ goto exit;
+ }
+
+ for (i = 0; i < WCD9XXX_SLIM_NUM_PORT_REG; i++)
+ wcd9xxx_interface_reg_write(codec->control_data,
+ TAPAN_SLIM_PGD_PORT_INT_EN0 + i,
+ 0xFF);
+exit:
+ return ret;
+}
+
+int tapan_hs_detect(struct snd_soc_codec *codec,
+ struct wcd9xxx_mbhc_config *mbhc_cfg)
+{
+ struct tapan_priv *tapan = snd_soc_codec_get_drvdata(codec);
+ return wcd9xxx_mbhc_start(&tapan->mbhc, mbhc_cfg);
+}
+EXPORT_SYMBOL_GPL(tapan_hs_detect);
+
+static struct wcd9xxx_reg_address tapan_reg_address = {
+};
+
+static int tapan_codec_probe(struct snd_soc_codec *codec)
+{
+ struct wcd9xxx *control;
+ struct tapan_priv *tapan;
+ struct wcd9xxx_pdata *pdata;
+ struct wcd9xxx *wcd9xxx;
+ struct snd_soc_dapm_context *dapm = &codec->dapm;
+ int ret = 0;
+ int i;
+ void *ptr = NULL;
+
+ codec->control_data = dev_get_drvdata(codec->dev->parent);
+ control = codec->control_data;
+
+ dev_info(codec->dev, "%s()\n", __func__);
+
+ tapan = kzalloc(sizeof(struct tapan_priv), GFP_KERNEL);
+ if (!tapan) {
+ dev_err(codec->dev, "Failed to allocate private data\n");
+ return -ENOMEM;
+ }
+ for (i = 0 ; i < NUM_DECIMATORS; i++) {
+ tx_hpf_work[i].tapan = tapan;
+ tx_hpf_work[i].decimator = i + 1;
+ INIT_DELAYED_WORK(&tx_hpf_work[i].dwork,
+ tx_hpf_corner_freq_callback);
+ }
+
+ snd_soc_codec_set_drvdata(codec, tapan);
+
+ /* codec resmgr module init */
+ wcd9xxx = codec->control_data;
+ pdata = dev_get_platdata(codec->dev->parent);
+ ret = wcd9xxx_resmgr_init(&tapan->resmgr, codec, wcd9xxx, pdata,
+ &tapan_reg_address);
+ if (ret) {
+ pr_err("%s: wcd9xxx init failed %d\n", __func__, ret);
+ goto err_codec;
+ }
+
+ /* init and start mbhc */
+ ret = wcd9xxx_mbhc_init(&tapan->mbhc, &tapan->resmgr, codec);
+ if (ret) {
+ pr_err("%s: mbhc init failed %d\n", __func__, ret);
+ goto err_codec;
+ }
+
+ tapan->codec = codec;
+
+ tapan->intf_type = wcd9xxx_get_intf_type();
+ tapan->aux_pga_cnt = 0;
+ tapan->aux_l_gain = 0x1F;
+ tapan->aux_r_gain = 0x1F;
+ tapan_update_reg_defaults(codec);
+ tapan_codec_init_reg(codec);
+ ret = tapan_handle_pdata(tapan);
+ if (IS_ERR_VALUE(ret)) {
+ pr_err("%s: bad pdata\n", __func__);
+ goto err_codec;
+ }
+
+ ptr = kmalloc((sizeof(tapan_rx_chs) +
+ sizeof(tapan_tx_chs)), GFP_KERNEL);
+ if (!ptr) {
+ pr_err("%s: no mem for slim chan ctl data\n", __func__);
+ ret = -ENOMEM;
+ goto err_nomem_slimch;
+ }
+
+ if (tapan->intf_type == WCD9XXX_INTERFACE_TYPE_I2C) {
+ pr_err("%s: I2C interface not supported yet\n",
+ __func__);
+ } else if (tapan->intf_type == WCD9XXX_INTERFACE_TYPE_SLIMBUS) {
+ for (i = 0; i < NUM_CODEC_DAIS; i++) {
+ INIT_LIST_HEAD(&tapan->dai[i].wcd9xxx_ch_list);
+ init_waitqueue_head(&tapan->dai[i].dai_wait);
+ }
+ }
+
+ control->num_rx_port = TAPAN_RX_MAX;
+ control->rx_chs = ptr;
+ memcpy(control->rx_chs, tapan_rx_chs, sizeof(tapan_rx_chs));
+ control->num_tx_port = TAPAN_TX_MAX;
+ control->tx_chs = ptr + sizeof(tapan_rx_chs);
+ memcpy(control->tx_chs, tapan_tx_chs, sizeof(tapan_tx_chs));
+
+ snd_soc_dapm_sync(dapm);
+
+ (void) tapan_setup_irqs(tapan);
+
+ codec->ignore_pmdown_time = 1;
+ return ret;
+
+err_nomem_slimch:
+ kfree(ptr);
+err_codec:
+ kfree(tapan);
+ return ret;
+}
+
+static int tapan_codec_remove(struct snd_soc_codec *codec)
+{
+ struct tapan_priv *tapan = snd_soc_codec_get_drvdata(codec);
+
+ /* cleanup MBHC */
+ wcd9xxx_mbhc_deinit(&tapan->mbhc);
+ /* cleanup resmgr */
+ wcd9xxx_resmgr_deinit(&tapan->resmgr);
+
+ kfree(tapan);
+ return 0;
+}
+
+static struct snd_soc_codec_driver soc_codec_dev_tapan = {
+ .probe = tapan_codec_probe,
+ .remove = tapan_codec_remove,
+
+ .read = tapan_read,
+ .write = tapan_write,
+
+ .readable_register = tapan_readable,
+ .volatile_register = tapan_volatile,
+
+ .reg_cache_size = TAPAN_CACHE_SIZE,
+ .reg_cache_default = tapan_reset_reg_defaults,
+ .reg_word_size = 1,
+
+ .controls = tapan_snd_controls,
+ .num_controls = ARRAY_SIZE(tapan_snd_controls),
+ .dapm_widgets = tapan_dapm_widgets,
+ .num_dapm_widgets = ARRAY_SIZE(tapan_dapm_widgets),
+ .dapm_routes = audio_map,
+ .num_dapm_routes = ARRAY_SIZE(audio_map),
+};
+
+#ifdef CONFIG_PM
+static int tapan_suspend(struct device *dev)
+{
+ dev_dbg(dev, "%s: system suspend\n", __func__);
+ return 0;
+}
+
+static int tapan_resume(struct device *dev)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct tapan_priv *tapan = platform_get_drvdata(pdev);
+ dev_dbg(dev, "%s: system resume\n", __func__);
+ wcd9xxx_resmgr_notifier_call(&tapan->resmgr, WCD9XXX_EVENT_POST_RESUME);
+ return 0;
+}
+
+static const struct dev_pm_ops tapan_pm_ops = {
+ .suspend = tapan_suspend,
+ .resume = tapan_resume,
+};
+#endif
+
+static int __devinit tapan_probe(struct platform_device *pdev)
+{
+ int ret = 0;
+ if (wcd9xxx_get_intf_type() == WCD9XXX_INTERFACE_TYPE_SLIMBUS)
+ ret = snd_soc_register_codec(&pdev->dev, &soc_codec_dev_tapan,
+ tapan_dai, ARRAY_SIZE(tapan_dai));
+ else if (wcd9xxx_get_intf_type() == WCD9XXX_INTERFACE_TYPE_I2C)
+ ret = snd_soc_register_codec(&pdev->dev, &soc_codec_dev_tapan,
+ tapan_i2s_dai, ARRAY_SIZE(tapan_i2s_dai));
+ return ret;
+}
+static int __devexit tapan_remove(struct platform_device *pdev)
+{
+ snd_soc_unregister_codec(&pdev->dev);
+ return 0;
+}
+static struct platform_driver tapan_codec_driver = {
+ .probe = tapan_probe,
+ .remove = tapan_remove,
+ .driver = {
+ .name = "tapan_codec",
+ .owner = THIS_MODULE,
+#ifdef CONFIG_PM
+ .pm = &tapan_pm_ops,
+#endif
+ },
+};
+
+static int __init tapan_codec_init(void)
+{
+ return platform_driver_register(&tapan_codec_driver);
+}
+
+static void __exit tapan_codec_exit(void)
+{
+ platform_driver_unregister(&tapan_codec_driver);
+}
+
+module_init(tapan_codec_init);
+module_exit(tapan_codec_exit);
+
+MODULE_DESCRIPTION("Tapan codec driver");
+MODULE_LICENSE("GPL v2");
diff --git a/sound/soc/codecs/wcd9306.h b/sound/soc/codecs/wcd9306.h
new file mode 100644
index 0000000..61d47b5
--- /dev/null
+++ b/sound/soc/codecs/wcd9306.h
@@ -0,0 +1,84 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef WCD9306_H
+#define WCD9306_H
+
+#include <sound/soc.h>
+#include <sound/jack.h>
+#include <linux/mfd/wcd9xxx/wcd9xxx-slimslave.h>
+#include "wcd9xxx-mbhc.h"
+#include "wcd9xxx-resmgr.h"
+
+#define TAPAN_NUM_REGISTERS 0x400
+#define TAPAN_MAX_REGISTER (TAPAN_NUM_REGISTERS-1)
+#define TAPAN_CACHE_SIZE TAPAN_NUM_REGISTERS
+
+#define TAPAN_REG_VAL(reg, val) {reg, 0, val}
+
+extern const u8 tapan_reg_readable[TAPAN_CACHE_SIZE];
+extern const u8 tapan_reset_reg_defaults[TAPAN_CACHE_SIZE];
+struct tapan_codec_dai_data {
+ u32 rate;
+ u32 *ch_num;
+ u32 ch_act;
+ u32 ch_tot;
+};
+
+enum tapan_pid_current {
+ TAPAN_PID_MIC_2P5_UA,
+ TAPAN_PID_MIC_5_UA,
+ TAPAN_PID_MIC_10_UA,
+ TAPAN_PID_MIC_20_UA,
+};
+
+struct tapan_reg_mask_val {
+ u16 reg;
+ u8 mask;
+ u8 val;
+};
+
+enum tapan_mbhc_analog_pwr_cfg {
+ TAPAN_ANALOG_PWR_COLLAPSED = 0,
+ TAPAN_ANALOG_PWR_ON,
+ TAPAN_NUM_ANALOG_PWR_CONFIGS,
+};
+
+/* Number of input and output Slimbus port */
+enum {
+ TAPAN_RX1 = 0,
+ TAPAN_RX2,
+ TAPAN_RX3,
+ TAPAN_RX4,
+ TAPAN_RX5,
+ TAPAN_RX_MAX,
+};
+
+enum {
+ TAPAN_TX1 = 0,
+ TAPAN_TX2,
+ TAPAN_TX3,
+ TAPAN_TX4,
+ TAPAN_TX5,
+ TAPAN_TX_MAX,
+};
+
+struct anc_header {
+ u32 reserved[3];
+ u32 num_anc_slots;
+};
+
+extern int tapan_mclk_enable(struct snd_soc_codec *codec, int mclk_enable,
+ bool dapm);
+extern int tapan_hs_detect(struct snd_soc_codec *codec,
+ struct wcd9xxx_mbhc_config *mbhc_cfg);
+
+#endif
diff --git a/sound/soc/msm/Kconfig b/sound/soc/msm/Kconfig
index ee4a3f3..20b9d2d 100644
--- a/sound/soc/msm/Kconfig
+++ b/sound/soc/msm/Kconfig
@@ -107,7 +107,7 @@
config SND_SOC_MSM_QDSP6V2_INTF
bool "SoC Q6 audio driver for MSM8974"
- depends on MSM_QDSP6_APRV2
+ depends on MSM_QDSP6_APR
help
To add support for SoC audio on MSM8974.
This will enable all the platform specific