qup_i2c: Set the clock rate before enabling the clock.
There is a warning during boot up since the driver
enables the QUP clock before setting its rate. Hence,
make sure clock rate is set for applicable targets to
fix warning.
Change-Id: I249d642f5f14c5ff627c00766f9d399f48f55610
Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
diff --git a/drivers/i2c/busses/i2c-qup.c b/drivers/i2c/busses/i2c-qup.c
index 8476033..195c99b 100644
--- a/drivers/i2c/busses/i2c-qup.c
+++ b/drivers/i2c/busses/i2c-qup.c
@@ -761,16 +761,9 @@
return -EIO;
}
- if (dev->clk_state == 0) {
- if (dev->clk_ctl == 0) {
- if (dev->pdata->src_clk_rate > 0)
- clk_set_rate(dev->clk,
- dev->pdata->src_clk_rate);
- else
- dev->pdata->src_clk_rate = 19200000;
- }
+ if (dev->clk_state == 0)
qup_i2c_pwr_mgmt(dev, 1);
- }
+
/* Initialize QUP registers during first transfer */
if (dev->clk_ctl == 0) {
int fs_div;
@@ -1257,6 +1250,12 @@
* If bootloaders leave a pending interrupt on certain GSBI's,
* then we reset the core before registering for interrupts.
*/
+
+ if (dev->pdata->src_clk_rate > 0)
+ clk_set_rate(dev->clk, dev->pdata->src_clk_rate);
+ else
+ dev->pdata->src_clk_rate = 19200000;
+
clk_prepare_enable(dev->clk);
clk_prepare_enable(dev->pclk);
writel_relaxed(1, dev->base + QUP_SW_RESET);