commit d6f56b80b57cd6b20334f75e79b6f9b8cdf30bc7
author Pushkar Joshi <pushkarj@codeaurora.org> Wed Jul 03 11:25:27 2013 -0700
committer Pushkar Joshi <pushkarj@codeaurora.org> Fri Jul 19 16:24:39 2013 -0700
tree 69b7657ed181628aea7a2e353be7ea8d1abee7e3
parent dd3fd9994290181008038bf0e5bf5fa48efd7b90

msm: clock-8084: Add clock entry for CoreSight CTI drivers

Add mapping for the clock for the various CoreSight cross-trigger
interface components so that the CTI driver can operate on and
manage the clock for those.

Change-Id: I7d24e66efccff88520bd74d127b453ce7388387f
Signed-off-by: Pushkar Joshi <pushkarj@codeaurora.org>

arch/arm/mach-msm/clock-8084.c

diff --git a/arch/arm/mach-msm/clock-8084.c b/arch/arm/mach-msm/clock-8084.c
index 3c6975f..4e47064 100644
--- a/arch/arm/mach-msm/clock-8084.c
+++ b/arch/arm/mach-msm/clock-8084.c
@@ -397,6 +397,20 @@
 	CLK_DUMMY("core_clk", qdss_clk.c, "fc355000.funnel", OFF),
 	CLK_DUMMY("core_clk", qdss_clk.c, "fc36c000.funnel", OFF),
 	CLK_DUMMY("core_clk", qdss_clk.c, "fc302000.stm", OFF),
+	CLK_DUMMY("core_clk", qdss_clk.c, "fc310000.cti", OFF),
+	CLK_DUMMY("core_clk", qdss_clk.c, "fc311000.cti", OFF),
+	CLK_DUMMY("core_clk", qdss_clk.c, "fc312000.cti", OFF),
+	CLK_DUMMY("core_clk", qdss_clk.c, "fc313000.cti", OFF),
+	CLK_DUMMY("core_clk", qdss_clk.c, "fc314000.cti", OFF),
+	CLK_DUMMY("core_clk", qdss_clk.c, "fc315000.cti", OFF),
+	CLK_DUMMY("core_clk", qdss_clk.c, "fc316000.cti", OFF),
+	CLK_DUMMY("core_clk", qdss_clk.c, "fc317000.cti", OFF),
+	CLK_DUMMY("core_clk", qdss_clk.c, "fc318000.cti", OFF),
+	CLK_DUMMY("core_clk", qdss_clk.c, "fc340000.cti", OFF),
+	CLK_DUMMY("core_clk", qdss_clk.c, "fc341000.cti", OFF),
+	CLK_DUMMY("core_clk", qdss_clk.c, "fc342000.cti", OFF),
+	CLK_DUMMY("core_clk", qdss_clk.c, "fc343000.cti", OFF),
+	CLK_DUMMY("core_clk", qdss_clk.c, "fc344000.cti", OFF),
 
 	CLK_DUMMY("core_a_clk", qdss_a_clk.c, "fc326000.tmc", OFF),
 	CLK_DUMMY("core_a_clk", qdss_a_clk.c, "fc324000.replicator", OFF),
@@ -408,6 +422,20 @@
 	CLK_DUMMY("core_a_clk", qdss_a_clk.c, "fc355000.funnel", OFF),
 	CLK_DUMMY("core_a_clk", qdss_a_clk.c, "fc36c000.funnel", OFF),
 	CLK_DUMMY("core_a_clk", qdss_a_clk.c, "fc302000.stm", OFF),
+	CLK_DUMMY("core_a_clk", qdss_a_clk.c, "fc310000.cti", OFF),
+	CLK_DUMMY("core_a_clk", qdss_a_clk.c, "fc311000.cti", OFF),
+	CLK_DUMMY("core_a_clk", qdss_a_clk.c, "fc312000.cti", OFF),
+	CLK_DUMMY("core_a_clk", qdss_a_clk.c, "fc313000.cti", OFF),
+	CLK_DUMMY("core_a_clk", qdss_a_clk.c, "fc314000.cti", OFF),
+	CLK_DUMMY("core_a_clk", qdss_a_clk.c, "fc315000.cti", OFF),
+	CLK_DUMMY("core_a_clk", qdss_a_clk.c, "fc316000.cti", OFF),
+	CLK_DUMMY("core_a_clk", qdss_a_clk.c, "fc317000.cti", OFF),
+	CLK_DUMMY("core_a_clk", qdss_a_clk.c, "fc318000.cti", OFF),
+	CLK_DUMMY("core_a_clk", qdss_a_clk.c, "fc340000.cti", OFF),
+	CLK_DUMMY("core_a_clk", qdss_a_clk.c, "fc341000.cti", OFF),
+	CLK_DUMMY("core_a_clk", qdss_a_clk.c, "fc342000.cti", OFF),
+	CLK_DUMMY("core_a_clk", qdss_a_clk.c, "fc343000.cti", OFF),
+	CLK_DUMMY("core_a_clk", qdss_a_clk.c, "fc344000.cti", OFF),
 };
 
 struct clock_init_data msm8084_clock_init_data __initdata = {