qup_i2c: Fix delay when polling for write ready
We wait for FIFO number of bytes to ensure that the
I2C state machine is not idle.
Change-Id: I24d2a22ac261bd1b53ca57a83c812c3c9f0fbdc4
Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
diff --git a/drivers/i2c/busses/i2c-qup.c b/drivers/i2c/busses/i2c-qup.c
index 8f2a942..c6bbb0d 100644
--- a/drivers/i2c/busses/i2c-qup.c
+++ b/drivers/i2c/busses/i2c-qup.c
@@ -335,8 +335,15 @@
else /* 1-bit delay before we check for bus busy */
udelay(dev->one_bit_t);
}
- if (retries++ == 1000)
- udelay(100);
+ if (retries++ == 1000) {
+ /*
+ * Wait for FIFO number of bytes to be absolutely sure
+ * that I2C write state machine is not idle. Each byte
+ * takes 9 clock cycles. (8 bits + 1 ack)
+ */
+ usleep_range((dev->one_bit_t * (dev->out_fifo_sz * 9)),
+ (dev->one_bit_t * (dev->out_fifo_sz * 9)));
+ }
}
qup_print_status(dev);
return -ETIMEDOUT;
@@ -1076,7 +1083,7 @@
platform_set_drvdata(pdev, dev);
- dev->one_bit_t = USEC_PER_SEC/pdata->clk_freq;
+ dev->one_bit_t = (USEC_PER_SEC/pdata->clk_freq) + 1;
dev->pdata = pdata;
dev->clk_ctl = 0;
dev->pos = 0;