tree 4a9002e6fca4d4763b40908403fc177153b9a6a8
parent f91e2c3bd427239c198351f44814dd39db91afe0
author Catalin Marinas <catalin.marinas@arm.com> 1291737389 +0100
committer Russell King <rmk+kernel@arm.linux.org.uk> 1292196358 +0000

ARM: 6528/1: Use CTR for the I-cache line size on ARMv7

The current implementation of the v7_coherent_*_range function assumes
that the D and I cache lines have the same size, which is incorrect
architecturally. This patch adds the icache_line_size macro which reads
the CTR register. The main loop in v7_coherent_*_range is split in two
independent loops or the D and I caches. This also has the performance
advantage that the DSB is moved outside the main loop.

Reported-by: Kevin Sapp <ksapp@quicinc.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>