arm/imx: change mxc_init_l2x0() to an imx31/35 specific call
The mxc_init_l2x0() should really be an imx31/35 specific call.
The patch removes early_initcall from mxc_init_l2x0() and get imx31
and imx35 soc specific function calls mxc_init_l2x0(), so that it's
not necessarily to be called for all imx socs when we build single
image for multiple imx socs.
Thus the function can be renamed to imx3_init_l2x0() and put into
mm-imx3.c. It also changes the return type from integer to void.
From what I see, the integer was picked just to satisfy early_initcall
prototype.
With the patch 'ARM: l2x0: add empty l2x0_of_init' applied, the code
compiles even without CONFIG_CACHE_L2X0 enabled.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c
index e06eed1..ffa33b4 100644
--- a/arch/arm/mach-imx/mm-imx3.c
+++ b/arch/arm/mach-imx/mm-imx3.c
@@ -21,6 +21,7 @@
#include <linux/err.h>
#include <asm/pgtable.h>
+#include <asm/hardware/cache-l2x0.h>
#include <asm/mach/map.h>
#include <mach/common.h>
@@ -29,6 +30,39 @@
#include <mach/iomux-v3.h>
#include <mach/irqs.h>
+void imx3_init_l2x0(void)
+{
+ void __iomem *l2x0_base;
+ void __iomem *clkctl_base;
+
+/*
+ * First of all, we must repair broken chip settings. There are some
+ * i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These
+ * misconfigured CPUs will run amok immediately when the L2 cache gets enabled.
+ * Workaraound is to setup the correct register setting prior enabling the
+ * L2 cache. This should not hurt already working CPUs, as they are using the
+ * same value.
+ */
+#define L2_MEM_VAL 0x10
+
+ clkctl_base = ioremap(MX35_CLKCTL_BASE_ADDR, 4096);
+ if (clkctl_base != NULL) {
+ writel(0x00000515, clkctl_base + L2_MEM_VAL);
+ iounmap(clkctl_base);
+ } else {
+ pr_err("L2 cache: Cannot fix timing. Trying to continue without\n");
+ }
+
+ l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096);
+ if (IS_ERR(l2x0_base)) {
+ printk(KERN_ERR "remapping L2 cache area failed with %ld\n",
+ PTR_ERR(l2x0_base));
+ return;
+ }
+
+ l2x0_init(l2x0_base, 0x00030024, 0x00000000);
+}
+
static struct map_desc mx31_io_desc[] __initdata = {
imx_map_entry(MX31, X_MEMC, MT_DEVICE),
imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED),
@@ -102,6 +136,8 @@
{
int to_version = mx31_revision() >> 4;
+ imx3_init_l2x0();
+
mxc_register_gpio("imx31-gpio", 0, MX31_GPIO1_BASE_ADDR, SZ_16K, MX31_INT_GPIO1, 0);
mxc_register_gpio("imx31-gpio", 1, MX31_GPIO2_BASE_ADDR, SZ_16K, MX31_INT_GPIO2, 0);
mxc_register_gpio("imx31-gpio", 2, MX31_GPIO3_BASE_ADDR, SZ_16K, MX31_INT_GPIO3, 0);
@@ -154,6 +190,8 @@
{
int to_version = mx35_revision() >> 4;
+ imx3_init_l2x0();
+
/* i.mx35 has the i.mx31 type gpio */
mxc_register_gpio("imx31-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0);
mxc_register_gpio("imx31-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0);