tree 0ca95c60c3fb1ee67f2506c6082e5c0c08cbbec0
parent 192db7bee39f7c2f632c07cf6d88dca384afbffb
author Tianyi Gou <tgou@codeaurora.org> 1327450039 -0800
committer Tianyi Gou <tgou@codeaurora.org> 1328501594 -0800

msm: clock-8960: Fix SR2 PLL regulator voting for 8064

8064's SR2 PLL is powered by LVS7. Update the code to reflect
this.

Change-Id: If9b90996f20006b54f40c2807639f6135fadbd76
Signed-off-by: Tianyi Gou <tgou@codeaurora.org>