msm: platsmp-8625: Support core1 boot after power collapse.
On 8625 target the cores enter the power collapse only when both the
cores are in GDFS state. Once out of power collpase core0 needs to
bring core1 out of GDFS and that is achieved by raising an SPI from
core0. Writing to the MP_CORE_IPC register generates the interrupt on
ACSR_MP_CORE_IPC1. To enable the core1 to receive an SPI we need to
configure the gic after we come out of power collapse, which is
identified based on the flag which gets updated once we
enter power collapse.
Once core1 is in reset, we need to clear the ACSR_MP_CORE_IPC1
and also clear the pending SPI.
Change-Id: I0e3bd5ad516289e2a8490205cf2eb39df07eca99
Signed-off-by: Taniya Das <tdas@codeaurora.org>
diff --git a/arch/arm/mach-msm/pm2.c b/arch/arm/mach-msm/pm2.c
index 6b026ac..94bc98f 100644
--- a/arch/arm/mach-msm/pm2.c
+++ b/arch/arm/mach-msm/pm2.c
@@ -80,6 +80,7 @@
};
static int msm_pm_debug_mask;
+int power_collapsed;
module_param_named(
debug_mask, msm_pm_debug_mask, int, S_IRUGO | S_IWUSR | S_IWGRP
);