msm: clock-8960: add clock support for 8930
Update clock driver to support 8930 clock changes. Also update
board file to use 8930 clock data.
Change-Id: Ia5b9af192a93e664e1182071df77b6c25ce6c85d
Signed-off-by: Tianyi Gou <tgou@codeaurora.org>
diff --git a/arch/arm/mach-msm/board-8930.c b/arch/arm/mach-msm/board-8930.c
index 2a2cc42..f2bd41b 100644
--- a/arch/arm/mach-msm/board-8930.c
+++ b/arch/arm/mach-msm/board-8930.c
@@ -2171,7 +2171,7 @@
if (msm_xo_init())
pr_err("Failed to initialize XO votes\n");
platform_device_register(&msm8930_device_rpm_regulator);
- msm_clock_init(&msm8960_clock_init_data);
+ msm_clock_init(&msm8930_clock_init_data);
msm8960_device_otg.dev.platform_data = &msm_otg_pdata;
msm_device_hsic_host.dev.platform_data = &msm_hsic_pdata;
msm8930_init_gpiomux();
diff --git a/arch/arm/mach-msm/clock-8960.c b/arch/arm/mach-msm/clock-8960.c
index 2ed150d..3421bc1 100644
--- a/arch/arm/mach-msm/clock-8960.c
+++ b/arch/arm/mach-msm/clock-8960.c
@@ -811,8 +811,8 @@
},
};
-/* For 8064, gfx3d_axi_clk is set as a dependency of gmem_axi_clk at runtime */
-static struct branch_clk gfx3d_axi_clk = {
+/* gfx3d_axi_clk is set as a dependency of gmem_axi_clk at runtime */
+static struct branch_clk gfx3d_axi_clk_8064 = {
.b = {
.ctl_reg = MAXI_EN5_REG,
.en_mask = BIT(25),
@@ -824,7 +824,23 @@
.c = {
.dbg_name = "gfx3d_axi_clk",
.ops = &clk_ops_branch,
- CLK_INIT(gfx3d_axi_clk.c),
+ CLK_INIT(gfx3d_axi_clk_8064.c),
+ },
+};
+
+static struct branch_clk gfx3d_axi_clk_8930 = {
+ .b = {
+ .ctl_reg = MAXI_EN5_REG,
+ .en_mask = BIT(12),
+ .reset_reg = SW_RESET_AXI_REG,
+ .reset_mask = BIT(16),
+ .halt_reg = DBG_BUS_VEC_J_REG,
+ .halt_bit = 12,
+ },
+ .c = {
+ .dbg_name = "gfx3d_axi_clk",
+ .ops = &clk_ops_branch,
+ CLK_INIT(gfx3d_axi_clk_8930.c),
},
};
@@ -3322,12 +3338,40 @@
F_END
};
+static struct clk_freq_tbl clk_tbl_gfx3d_8930[] = {
+ F_GFX3D( 0, gnd, 0, 0),
+ F_GFX3D( 27000000, pxo, 0, 0),
+ F_GFX3D( 48000000, pll8, 1, 8),
+ F_GFX3D( 54857000, pll8, 1, 7),
+ F_GFX3D( 64000000, pll8, 1, 6),
+ F_GFX3D( 76800000, pll8, 1, 5),
+ F_GFX3D( 96000000, pll8, 1, 4),
+ F_GFX3D(128000000, pll8, 1, 3),
+ F_GFX3D(145455000, pll2, 2, 11),
+ F_GFX3D(160000000, pll2, 1, 5),
+ F_GFX3D(177778000, pll2, 2, 9),
+ F_GFX3D(200000000, pll2, 1, 4),
+ F_GFX3D(228571000, pll2, 2, 7),
+ F_GFX3D(266667000, pll2, 1, 3),
+ F_GFX3D(300000000, pll3, 1, 4),
+ F_GFX3D(320000000, pll2, 2, 5),
+ F_GFX3D(400000000, pll2, 1, 2),
+ F_GFX3D(450000000, pll15, 1, 2),
+ F_END
+};
+
static unsigned long fmax_gfx3d_8064[MAX_VDD_LEVELS] __initdata = {
[VDD_DIG_LOW] = 128000000,
[VDD_DIG_NOMINAL] = 325000000,
[VDD_DIG_HIGH] = 400000000
};
+static unsigned long fmax_gfx3d_8930[MAX_VDD_LEVELS] __initdata = {
+ [VDD_DIG_LOW] = 128000000,
+ [VDD_DIG_NOMINAL] = 320000000,
+ [VDD_DIG_HIGH] = 450000000
+};
+
static struct bank_masks bmnd_info_gfx3d = {
.bank_sel_mask = BIT(11),
.bank0_mask = {
@@ -4649,10 +4693,11 @@
{ TEST_MM_HS(0x32), &csi_rdi2_clk.c },
{ TEST_MM_HS(0x33), &vcap_clk.c },
{ TEST_MM_HS(0x34), &vcap_npl_clk.c },
+ { TEST_MM_HS(0x34), &gfx3d_axi_clk_8930.c },
{ TEST_MM_HS(0x35), &vcap_axi_clk.c },
{ TEST_MM_HS(0x36), &rgb_tv_clk.c },
{ TEST_MM_HS(0x37), &npl_tv_clk.c },
- { TEST_MM_HS(0x38), &gfx3d_axi_clk.c },
+ { TEST_MM_HS(0x38), &gfx3d_axi_clk_8064.c },
{ TEST_LPA(0x0F), &mi2s_bit_clk.c },
{ TEST_LPA(0x10), &codec_i2s_mic_bit_clk.c },
@@ -4995,7 +5040,8 @@
CLK_LOOKUP("core_clk", gfx3d_clk.c, "kgsl-3d0.0"),
CLK_LOOKUP("core_clk", gfx3d_clk.c, "footswitch-8x60.2"),
- CLK_LOOKUP("bus_clk", gfx3d_axi_clk.c, "footswitch-8x60.2"),
+ CLK_LOOKUP("bus_clk",
+ gfx3d_axi_clk_8064.c, "footswitch-8x60.2"),
CLK_LOOKUP("iface_clk", vcap_p_clk.c, ""),
CLK_LOOKUP("iface_clk", vcap_p_clk.c, "footswitch-8x60.10"),
CLK_LOOKUP("bus_clk", vcap_axi_clk.c, "footswitch-8x60.10"),
@@ -5095,7 +5141,7 @@
CLK_LOOKUP("core_clk", vfe_axi_clk.c, ""),
CLK_LOOKUP("core_clk", vcodec_axi_a_clk.c, ""),
CLK_LOOKUP("core_clk", vcodec_axi_b_clk.c, ""),
- CLK_LOOKUP("core_clk", gfx3d_axi_clk.c, ""),
+ CLK_LOOKUP("core_clk", gfx3d_axi_clk_8064.c, ""),
CLK_LOOKUP("dfab_dsps_clk", dfab_dsps_clk.c, NULL),
CLK_LOOKUP("core_clk", dfab_usb_hs_clk.c, "msm_otg"),
@@ -5126,8 +5172,8 @@
CLK_LOOKUP("core_clk", vfe_axi_clk.c, "msm_iommu.6"),
CLK_LOOKUP("core_clk", vcodec_axi_a_clk.c, "msm_iommu.7"),
CLK_LOOKUP("core_clk", vcodec_axi_b_clk.c, "msm_iommu.8"),
- CLK_LOOKUP("core_clk", gfx3d_axi_clk.c, "msm_iommu.9"),
- CLK_LOOKUP("core_clk", gfx3d_axi_clk.c, "msm_iommu.10"),
+ CLK_LOOKUP("core_clk", gfx3d_axi_clk_8064.c, "msm_iommu.9"),
+ CLK_LOOKUP("core_clk", gfx3d_axi_clk_8064.c, "msm_iommu.10"),
CLK_LOOKUP("core_clk", vcap_axi_clk.c, "msm_iommu.11"),
CLK_LOOKUP("mem_clk", ebi1_adm_clk.c, "msm_dmov"),
@@ -5198,7 +5244,7 @@
CLK_LOOKUP("core_clk", gsbi6_qup_clk.c, ""),
CLK_LOOKUP("core_clk", gsbi7_qup_clk.c, ""),
CLK_LOOKUP("core_clk", gsbi8_qup_clk.c, ""),
- CLK_LOOKUP("core_clk", gsbi9_qup_clk.c, "qup_i2c.0"),
+ CLK_LOOKUP("core_clk", gsbi9_qup_clk.c, ""),
CLK_LOOKUP("core_clk", gsbi10_qup_clk.c, "qup_i2c.10"),
CLK_LOOKUP("core_clk", gsbi11_qup_clk.c, ""),
CLK_LOOKUP("core_clk", gsbi12_qup_clk.c, "qup_i2c.12"),
@@ -5239,7 +5285,7 @@
CLK_LOOKUP("iface_clk", gsbi6_p_clk.c, "msm_serial_hs.0"),
CLK_LOOKUP("iface_clk", gsbi7_p_clk.c, ""),
CLK_LOOKUP("iface_clk", gsbi8_p_clk.c, ""),
- CLK_LOOKUP("iface_clk", gsbi9_p_clk.c, "qup_i2c.0"),
+ CLK_LOOKUP("iface_clk", gsbi9_p_clk.c, ""),
CLK_LOOKUP("iface_clk", gsbi10_p_clk.c, "qup_i2c.10"),
CLK_LOOKUP("iface_clk", gsbi11_p_clk.c, ""),
CLK_LOOKUP("iface_clk", gsbi12_p_clk.c, "qup_i2c.12"),
@@ -5433,6 +5479,276 @@
CLK_LOOKUP("q6_func_clk", q6_func_clk, ""),
};
+static struct clk_lookup msm_clocks_8930[] = {
+ CLK_LOOKUP("xo", cxo_clk.c, "msm_otg"),
+ CLK_LOOKUP("cxo", cxo_clk.c, "wcnss_wlan.0"),
+ CLK_LOOKUP("cxo", cxo_clk.c, "pil_riva"),
+ CLK_LOOKUP("xo", pxo_clk.c, "pil_qdsp6v4.0"),
+ CLK_LOOKUP("xo", cxo_clk.c, "pil_qdsp6v4.1"),
+ CLK_LOOKUP("xo", cxo_clk.c, "pil_qdsp6v4.2"),
+ CLK_LOOKUP("xo", cxo_clk.c, "BAM_RMNT"),
+ CLK_LOOKUP("pll2", pll2_clk.c, NULL),
+ CLK_LOOKUP("pll8", pll8_clk.c, NULL),
+ CLK_LOOKUP("pll4", pll4_clk.c, NULL),
+ CLK_LOOKUP("measure", measure_clk.c, "debug"),
+
+ CLK_LOOKUP("bus_clk", afab_clk.c, "msm_apps_fab"),
+ CLK_LOOKUP("bus_a_clk", afab_a_clk.c, "msm_apps_fab"),
+ CLK_LOOKUP("bus_clk", cfpb_clk.c, "msm_cpss_fpb"),
+ CLK_LOOKUP("bus_a_clk", cfpb_a_clk.c, "msm_cpss_fpb"),
+ CLK_LOOKUP("bus_clk", sfab_clk.c, "msm_sys_fab"),
+ CLK_LOOKUP("bus_a_clk", sfab_msmbus_a_clk.c, "msm_sys_fab"),
+ CLK_LOOKUP("bus_clk", sfpb_clk.c, "msm_sys_fpb"),
+ CLK_LOOKUP("bus_a_clk", sfpb_a_clk.c, "msm_sys_fpb"),
+ CLK_LOOKUP("bus_clk", mmfab_clk.c, "msm_mm_fab"),
+ CLK_LOOKUP("bus_a_clk", mmfab_a_clk.c, "msm_mm_fab"),
+ CLK_LOOKUP("mem_clk", ebi1_msmbus_clk.c, "msm_bus"),
+ CLK_LOOKUP("mem_a_clk", ebi1_a_clk.c, "msm_bus"),
+
+ CLK_LOOKUP("ebi1_clk", ebi1_clk.c, NULL),
+ CLK_LOOKUP("dfab_clk", dfab_clk.c, NULL),
+ CLK_LOOKUP("dfab_a_clk", dfab_a_clk.c, NULL),
+ CLK_LOOKUP("mmfpb_clk", mmfpb_clk.c, NULL),
+ CLK_LOOKUP("mmfpb_a_clk", mmfpb_a_clk.c, "clock-8960"),
+ CLK_LOOKUP("cfpb_a_clk", cfpb_a_clk.c, "clock-8960"),
+
+ CLK_LOOKUP("core_clk", gp0_clk.c, ""),
+ CLK_LOOKUP("core_clk", gp1_clk.c, ""),
+ CLK_LOOKUP("core_clk", gp2_clk.c, ""),
+ CLK_LOOKUP("core_clk", gsbi1_uart_clk.c, ""),
+ CLK_LOOKUP("core_clk", gsbi2_uart_clk.c, ""),
+ CLK_LOOKUP("core_clk", gsbi3_uart_clk.c, ""),
+ CLK_LOOKUP("core_clk", gsbi4_uart_clk.c, ""),
+ CLK_LOOKUP("core_clk", gsbi5_uart_clk.c, "msm_serial_hsl.0"),
+ CLK_LOOKUP("core_clk", gsbi6_uart_clk.c, "msm_serial_hs.0"),
+ CLK_LOOKUP("core_clk", gsbi7_uart_clk.c, ""),
+ CLK_LOOKUP("core_clk", gsbi8_uart_clk.c, ""),
+ CLK_LOOKUP("core_clk", gsbi9_uart_clk.c, ""),
+ CLK_LOOKUP("core_clk", gsbi10_uart_clk.c, ""),
+ CLK_LOOKUP("core_clk", gsbi11_uart_clk.c, ""),
+ CLK_LOOKUP("core_clk", gsbi12_uart_clk.c, ""),
+ CLK_LOOKUP("core_clk", gsbi1_qup_clk.c, "spi_qsd.0"),
+ CLK_LOOKUP("core_clk", gsbi2_qup_clk.c, ""),
+ CLK_LOOKUP("core_clk", gsbi3_qup_clk.c, "qup_i2c.3"),
+ CLK_LOOKUP("core_clk", gsbi4_qup_clk.c, "qup_i2c.4"),
+ CLK_LOOKUP("core_clk", gsbi5_qup_clk.c, ""),
+ CLK_LOOKUP("core_clk", gsbi6_qup_clk.c, ""),
+ CLK_LOOKUP("core_clk", gsbi7_qup_clk.c, ""),
+ CLK_LOOKUP("core_clk", gsbi8_qup_clk.c, ""),
+ CLK_LOOKUP("core_clk", gsbi9_qup_clk.c, "qup_i2c.0"),
+ CLK_LOOKUP("core_clk", gsbi10_qup_clk.c, "qup_i2c.10"),
+ CLK_LOOKUP("core_clk", gsbi11_qup_clk.c, ""),
+ CLK_LOOKUP("core_clk", gsbi12_qup_clk.c, "qup_i2c.12"),
+ CLK_LOOKUP("core_clk", pdm_clk.c, ""),
+ CLK_LOOKUP("mem_clk", pmem_clk.c, "msm_sps"),
+ CLK_LOOKUP("core_clk", prng_clk.c, "msm_rng.0"),
+ CLK_LOOKUP("core_clk", sdc1_clk.c, "msm_sdcc.1"),
+ CLK_LOOKUP("core_clk", sdc2_clk.c, "msm_sdcc.2"),
+ CLK_LOOKUP("core_clk", sdc3_clk.c, "msm_sdcc.3"),
+ CLK_LOOKUP("core_clk", sdc4_clk.c, "msm_sdcc.4"),
+ CLK_LOOKUP("core_clk", sdc5_clk.c, "msm_sdcc.5"),
+ CLK_LOOKUP("ref_clk", tsif_ref_clk.c, ""),
+ CLK_LOOKUP("core_clk", tssc_clk.c, ""),
+ CLK_LOOKUP("alt_core_clk", usb_hs1_xcvr_clk.c, "msm_otg"),
+ CLK_LOOKUP("phy_clk", usb_phy0_clk.c, "msm_otg"),
+ CLK_LOOKUP("alt_core_clk", usb_fs1_xcvr_clk.c, ""),
+ CLK_LOOKUP("sys_clk", usb_fs1_sys_clk.c, ""),
+ CLK_LOOKUP("src_clk", usb_fs1_src_clk.c, ""),
+ CLK_LOOKUP("alt_core_clk", usb_fs2_xcvr_clk.c, ""),
+ CLK_LOOKUP("sys_clk", usb_fs2_sys_clk.c, ""),
+ CLK_LOOKUP("src_clk", usb_fs2_src_clk.c, ""),
+ CLK_LOOKUP("alt_core_clk", usb_hsic_xcvr_fs_clk.c, "msm_hsic_host"),
+ CLK_LOOKUP("phy_clk", usb_hsic_hsic_clk.c, "msm_hsic_host"),
+ CLK_LOOKUP("cal_clk", usb_hsic_hsio_cal_clk.c, "msm_hsic_host"),
+ CLK_LOOKUP("core_clk", usb_hsic_system_clk.c, "msm_hsic_host"),
+ CLK_LOOKUP("iface_clk", usb_hsic_p_clk.c, "msm_hsic_host"),
+ CLK_LOOKUP("iface_clk", ce1_p_clk.c, "qce.0"),
+ CLK_LOOKUP("iface_clk", ce1_p_clk.c, "qcrypto.0"),
+ CLK_LOOKUP("core_clk", ce1_core_clk.c, "qce.0"),
+ CLK_LOOKUP("core_clk", ce1_core_clk.c, "qcrypto.0"),
+ CLK_LOOKUP("dma_bam_pclk", dma_bam_p_clk.c, NULL),
+ CLK_LOOKUP("iface_clk", gsbi1_p_clk.c, "spi_qsd.0"),
+ CLK_LOOKUP("iface_clk", gsbi2_p_clk.c, ""),
+ CLK_LOOKUP("iface_clk", gsbi3_p_clk.c, "qup_i2c.3"),
+ CLK_LOOKUP("iface_clk", gsbi4_p_clk.c, "qup_i2c.4"),
+ CLK_LOOKUP("iface_clk", gsbi5_p_clk.c, "msm_serial_hsl.0"),
+ CLK_LOOKUP("iface_clk", gsbi6_p_clk.c, "msm_serial_hs.0"),
+ CLK_LOOKUP("iface_clk", gsbi7_p_clk.c, ""),
+ CLK_LOOKUP("iface_clk", gsbi8_p_clk.c, ""),
+ CLK_LOOKUP("iface_clk", gsbi9_p_clk.c, "qup_i2c.0"),
+ CLK_LOOKUP("iface_clk", gsbi10_p_clk.c, "qup_i2c.10"),
+ CLK_LOOKUP("iface_clk", gsbi11_p_clk.c, ""),
+ CLK_LOOKUP("iface_clk", gsbi12_p_clk.c, "qup_i2c.12"),
+ CLK_LOOKUP("iface_clk", tsif_p_clk.c, ""),
+ CLK_LOOKUP("iface_clk", usb_fs1_p_clk.c, ""),
+ CLK_LOOKUP("iface_clk", usb_fs2_p_clk.c, ""),
+ CLK_LOOKUP("iface_clk", usb_hs1_p_clk.c, "msm_otg"),
+ CLK_LOOKUP("iface_clk", sdc1_p_clk.c, "msm_sdcc.1"),
+ CLK_LOOKUP("iface_clk", sdc2_p_clk.c, "msm_sdcc.2"),
+ CLK_LOOKUP("iface_clk", sdc3_p_clk.c, "msm_sdcc.3"),
+ CLK_LOOKUP("iface_clk", sdc4_p_clk.c, "msm_sdcc.4"),
+ CLK_LOOKUP("iface_clk", sdc5_p_clk.c, "msm_sdcc.5"),
+ CLK_LOOKUP("core_clk", adm0_clk.c, "msm_dmov"),
+ CLK_LOOKUP("iface_clk", adm0_p_clk.c, "msm_dmov"),
+ CLK_LOOKUP("iface_clk", pmic_arb0_p_clk.c, ""),
+ CLK_LOOKUP("iface_clk", pmic_arb1_p_clk.c, ""),
+ CLK_LOOKUP("core_clk", pmic_ssbi2_clk.c, ""),
+ CLK_LOOKUP("mem_clk", rpm_msg_ram_p_clk.c, ""),
+ CLK_LOOKUP("core_clk", amp_clk.c, ""),
+ CLK_LOOKUP("cam_clk", cam0_clk.c, "4-001a"),
+ CLK_LOOKUP("cam_clk", cam0_clk.c, "4-006c"),
+ CLK_LOOKUP("cam_clk", cam0_clk.c, "4-0048"),
+ CLK_LOOKUP("cam_clk", cam2_clk.c, NULL),
+ CLK_LOOKUP("cam_clk", cam0_clk.c, "4-0020"),
+ CLK_LOOKUP("csi_src_clk", csi0_src_clk.c, "msm_csid.0"),
+ CLK_LOOKUP("csi_src_clk", csi1_src_clk.c, "msm_csid.1"),
+ CLK_LOOKUP("csi_src_clk", csi2_src_clk.c, "msm_csid.2"),
+ CLK_LOOKUP("csi_clk", csi0_clk.c, "msm_csid.0"),
+ CLK_LOOKUP("csi_clk", csi1_clk.c, "msm_csid.1"),
+ CLK_LOOKUP("csi_clk", csi2_clk.c, "msm_csid.2"),
+ CLK_LOOKUP("csi_phy_clk", csi0_phy_clk.c, "msm_csid.0"),
+ CLK_LOOKUP("csi_phy_clk", csi1_phy_clk.c, "msm_csid.1"),
+ CLK_LOOKUP("csi_phy_clk", csi2_phy_clk.c, "msm_csid.2"),
+ CLK_LOOKUP("csi_pix_clk", csi_pix_clk.c, "msm_ispif.0"),
+ CLK_LOOKUP("csi_rdi_clk", csi_rdi_clk.c, "msm_ispif.0"),
+ CLK_LOOKUP("csi_src_clk", csi2_src_clk.c, NULL),
+ CLK_LOOKUP("csi_clk", csi2_clk.c, NULL),
+ CLK_LOOKUP("csi_pix1_clk", csi_pix1_clk.c, "msm_ispif.0"),
+ CLK_LOOKUP("csi_rdi1_clk", csi_rdi1_clk.c, "msm_ispif.0"),
+ CLK_LOOKUP("csi_rdi2_clk", csi_rdi2_clk.c, "msm_ispif.0"),
+ CLK_LOOKUP("csi_phy_clk", csi2_phy_clk.c, NULL),
+ CLK_LOOKUP("csi2phy_timer_clk", csi2phy_timer_clk.c, NULL),
+ CLK_LOOKUP("csiphy_timer_src_clk",
+ csiphy_timer_src_clk.c, "msm_csiphy.0"),
+ CLK_LOOKUP("csiphy_timer_src_clk",
+ csiphy_timer_src_clk.c, "msm_csiphy.1"),
+ CLK_LOOKUP("csiphy_timer_src_clk",
+ csiphy_timer_src_clk.c, "msm_csiphy.2"),
+ CLK_LOOKUP("csiphy_timer_clk", csi0phy_timer_clk.c, "msm_csiphy.0"),
+ CLK_LOOKUP("csiphy_timer_clk", csi1phy_timer_clk.c, "msm_csiphy.1"),
+ CLK_LOOKUP("csiphy_timer_clk", csi2phy_timer_clk.c, "msm_csiphy.2"),
+ CLK_LOOKUP("dsi_byte_div_clk", dsi1_byte_clk.c, NULL),
+ CLK_LOOKUP("dsi_esc_clk", dsi1_esc_clk.c, NULL),
+ CLK_LOOKUP("core_clk", gfx3d_clk.c, "kgsl-3d0.0"),
+ CLK_LOOKUP("core_clk", gfx3d_clk.c, "footswitch-8x60.2"),
+ CLK_LOOKUP("bus_clk",
+ gfx3d_axi_clk_8930.c, "footswitch-8x60.2"),
+ CLK_LOOKUP("bus_clk", ijpeg_axi_clk.c, "footswitch-8x60.3"),
+ CLK_LOOKUP("imem_clk", imem_axi_clk.c, NULL),
+ CLK_LOOKUP("ijpeg_clk", ijpeg_clk.c, NULL),
+ CLK_LOOKUP("core_clk", ijpeg_clk.c, "footswitch-8x60.3"),
+ CLK_LOOKUP("mdp_clk", mdp_clk.c, NULL),
+ CLK_LOOKUP("core_clk", mdp_clk.c, "footswitch-8x60.4"),
+ CLK_LOOKUP("mdp_vsync_clk", mdp_vsync_clk.c, NULL),
+ CLK_LOOKUP("vsync_clk", mdp_vsync_clk.c, "footswitch-8x60.4"),
+ CLK_LOOKUP("lut_mdp", lut_mdp_clk.c, NULL),
+ CLK_LOOKUP("lut_clk", lut_mdp_clk.c, "footswitch-8x60.4"),
+ CLK_LOOKUP("core_clk", rot_clk.c, "msm_rotator.0"),
+ CLK_LOOKUP("core_clk", rot_clk.c, "footswitch-8x60.6"),
+ CLK_LOOKUP("tv_src_clk", tv_src_clk.c, NULL),
+ CLK_LOOKUP("tv_src_clk", tv_src_clk.c, "footswitch-8x60.4"),
+ CLK_LOOKUP("tv_dac_clk", tv_dac_clk.c, NULL),
+ CLK_LOOKUP("core_clk", vcodec_clk.c, "msm_vidc.0"),
+ CLK_LOOKUP("core_clk", vcodec_clk.c, "footswitch-8x60.7"),
+ CLK_LOOKUP("mdp_tv_clk", mdp_tv_clk.c, NULL),
+ CLK_LOOKUP("tv_clk", mdp_tv_clk.c, "footswitch-8x60.4"),
+ CLK_LOOKUP("hdmi_clk", hdmi_tv_clk.c, NULL),
+ CLK_LOOKUP("core_clk", hdmi_app_clk.c, "hdmi_msm.1"),
+ CLK_LOOKUP("vpe_clk", vpe_clk.c, "msm_vpe.0"),
+ CLK_LOOKUP("core_clk", vpe_clk.c, "footswitch-8x60.9"),
+ CLK_LOOKUP("vfe_clk", vfe_clk.c, "msm_vfe.0"),
+ CLK_LOOKUP("core_clk", vfe_clk.c, "footswitch-8x60.8"),
+ CLK_LOOKUP("csi_vfe_clk", csi_vfe_clk.c, "msm_vfe.0"),
+ CLK_LOOKUP("bus_clk", vfe_axi_clk.c, "footswitch-8x60.8"),
+ CLK_LOOKUP("bus_clk", mdp_axi_clk.c, "footswitch-8x60.4"),
+ CLK_LOOKUP("bus_clk", rot_axi_clk.c, "footswitch-8x60.6"),
+ CLK_LOOKUP("bus_clk", vcodec_axi_clk.c, "footswitch-8x60.7"),
+ CLK_LOOKUP("bus_a_clk", vcodec_axi_a_clk.c, "footswitch-8x60.7"),
+ CLK_LOOKUP("bus_b_clk", vcodec_axi_b_clk.c, "footswitch-8x60.7"),
+ CLK_LOOKUP("bus_clk", vpe_axi_clk.c, "footswitch-8x60.9"),
+ CLK_LOOKUP("amp_pclk", amp_p_clk.c, NULL),
+ CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.0"),
+ CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.1"),
+ CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.2"),
+ CLK_LOOKUP("dsi_m_pclk", dsi1_m_p_clk.c, NULL),
+ CLK_LOOKUP("dsi_s_pclk", dsi1_s_p_clk.c, NULL),
+ CLK_LOOKUP("iface_clk", gfx3d_p_clk.c, "kgsl-3d0.0"),
+ CLK_LOOKUP("iface_clk", gfx3d_p_clk.c, "footswitch-8x60.2"),
+ CLK_LOOKUP("master_iface_clk", hdmi_m_p_clk.c, "hdmi_msm.1"),
+ CLK_LOOKUP("slave_iface_clk", hdmi_s_p_clk.c, "hdmi_msm.1"),
+ CLK_LOOKUP("ijpeg_pclk", ijpeg_p_clk.c, NULL),
+ CLK_LOOKUP("iface_clk", ijpeg_p_clk.c, "footswitch-8x60.3"),
+ CLK_LOOKUP("mem_iface_clk", imem_p_clk.c, "kgsl-3d0.0"),
+ CLK_LOOKUP("mdp_pclk", mdp_p_clk.c, NULL),
+ CLK_LOOKUP("iface_clk", mdp_p_clk.c, "footswitch-8x60.4"),
+ CLK_LOOKUP("iface_clk", smmu_p_clk.c, "msm_iommu"),
+ CLK_LOOKUP("iface_clk", rot_p_clk.c, "msm_rotator.0"),
+ CLK_LOOKUP("iface_clk", rot_p_clk.c, "footswitch-8x60.6"),
+ CLK_LOOKUP("iface_clk", vcodec_p_clk.c, "msm_vidc.0"),
+ CLK_LOOKUP("iface_clk", vcodec_p_clk.c, "footswitch-8x60.7"),
+ CLK_LOOKUP("vfe_pclk", vfe_p_clk.c, "msm_vfe.0"),
+ CLK_LOOKUP("iface_clk", vfe_p_clk.c, "footswitch-8x60.8"),
+ CLK_LOOKUP("vpe_pclk", vpe_p_clk.c, "msm_vpe.0"),
+ CLK_LOOKUP("iface_clk", vpe_p_clk.c, "footswitch-8x60.9"),
+ CLK_LOOKUP("bit_clk", mi2s_bit_clk.c, "msm-dai-q6.6"),
+ CLK_LOOKUP("osr_clk", mi2s_osr_clk.c, "msm-dai-q6.6"),
+ CLK_LOOKUP("bit_clk", codec_i2s_mic_bit_clk.c,
+ "msm-dai-q6.1"),
+ CLK_LOOKUP("osr_clk", codec_i2s_mic_osr_clk.c,
+ "msm-dai-q6.1"),
+ CLK_LOOKUP("bit_clk", spare_i2s_mic_bit_clk.c,
+ "msm-dai-q6.5"),
+ CLK_LOOKUP("osr_clk", spare_i2s_mic_osr_clk.c,
+ "msm-dai-q6.5"),
+ CLK_LOOKUP("bit_clk", codec_i2s_spkr_bit_clk.c,
+ "msm-dai-q6.16384"),
+ CLK_LOOKUP("osr_clk", codec_i2s_spkr_osr_clk.c,
+ "msm-dai-q6.16384"),
+ CLK_LOOKUP("bit_clk", spare_i2s_spkr_bit_clk.c,
+ "msm-dai-q6.4"),
+ CLK_LOOKUP("osr_clk", spare_i2s_spkr_osr_clk.c,
+ "msm-dai-q6.4"),
+ CLK_LOOKUP("pcm_clk", pcm_clk.c, "msm-dai-q6.2"),
+ CLK_LOOKUP("sps_slimbus_clk", sps_slimbus_clk.c, NULL),
+ CLK_LOOKUP("core_clk", audio_slimbus_clk.c, "msm_slim_ctrl.1"),
+ CLK_LOOKUP("core_clk", vpe_axi_clk.c, "msm_iommu.1"),
+ CLK_LOOKUP("core_clk", mdp_axi_clk.c, "msm_iommu.2"),
+ CLK_LOOKUP("core_clk", mdp_axi_clk.c, "msm_iommu.3"),
+ CLK_LOOKUP("core_clk", rot_axi_clk.c, "msm_iommu.4"),
+ CLK_LOOKUP("core_clk", ijpeg_axi_clk.c, "msm_iommu.5"),
+ CLK_LOOKUP("core_clk", vfe_axi_clk.c, "msm_iommu.6"),
+ CLK_LOOKUP("core_clk", vcodec_axi_a_clk.c, "msm_iommu.7"),
+ CLK_LOOKUP("core_clk", vcodec_axi_b_clk.c, "msm_iommu.8"),
+ CLK_LOOKUP("core_clk", gfx3d_axi_clk_8930.c, "msm_iommu.9"),
+ CLK_LOOKUP("core_clk", gfx3d_axi_clk_8930.c, "msm_iommu.10"),
+
+ CLK_LOOKUP("mdp_iommu_clk", mdp_axi_clk.c, "msm_vidc.0"),
+ CLK_LOOKUP("rot_iommu_clk", rot_axi_clk.c, "msm_vidc.0"),
+ CLK_LOOKUP("vcodec_iommu0_clk", vcodec_axi_a_clk.c, "msm_vidc.0"),
+ CLK_LOOKUP("vcodec_iommu1_clk", vcodec_axi_b_clk.c, "msm_vidc.0"),
+ CLK_LOOKUP("smmu_iface_clk", smmu_p_clk.c, "msm_vidc.0"),
+
+ CLK_LOOKUP("dfab_dsps_clk", dfab_dsps_clk.c, NULL),
+ CLK_LOOKUP("core_clk", dfab_usb_hs_clk.c, "msm_otg"),
+ CLK_LOOKUP("bus_clk", dfab_sdc1_clk.c, "msm_sdcc.1"),
+ CLK_LOOKUP("bus_clk", dfab_sdc2_clk.c, "msm_sdcc.2"),
+ CLK_LOOKUP("bus_clk", dfab_sdc3_clk.c, "msm_sdcc.3"),
+ CLK_LOOKUP("bus_clk", dfab_sdc4_clk.c, "msm_sdcc.4"),
+ CLK_LOOKUP("bus_clk", dfab_sdc5_clk.c, "msm_sdcc.5"),
+ CLK_LOOKUP("dfab_clk", dfab_sps_clk.c, "msm_sps"),
+ CLK_LOOKUP("bus_clk", dfab_bam_dmux_clk.c, "BAM_RMNT"),
+ CLK_LOOKUP("bus_clk", dfab_scm_clk.c, "scm"),
+ CLK_LOOKUP("bus_clk", dfab_qseecom_clk.c, "qseecom"),
+
+ CLK_LOOKUP("mem_clk", ebi1_adm_clk.c, "msm_dmov"),
+
+ CLK_LOOKUP("l2_mclk", l2_m_clk, ""),
+ CLK_LOOKUP("krait0_mclk", krait0_m_clk, ""),
+ CLK_LOOKUP("krait1_mclk", krait1_m_clk, ""),
+ CLK_LOOKUP("q6sw_clk", q6sw_clk, ""),
+ CLK_LOOKUP("q6fw_clk", q6fw_clk, ""),
+ CLK_LOOKUP("q6_func_clk", q6_func_clk, ""),
+};
/*
* Miscellaneous clock register initializations
*/
@@ -5476,8 +5792,8 @@
writel_relaxed(0, SW_RESET_ALL_REG);
/*
- * Some bits are only used on either 8960 or 8064 and are marked as
- * reserved bits on the other SoC. Writing to these reserved bits
+ * Some bits are only used on 8960 or 8064 or 8930 and are marked as
+ * reserved bits on the other SoCs. Writing to these reserved bits
* should have no effect.
*/
/*
@@ -5517,6 +5833,8 @@
rmwreg(0x0027FCFF, MAXI_EN3_REG, 0x003FFFFF);
if (cpu_is_apq8064())
rmwreg(0x009FE4FF, MAXI_EN5_REG, 0x01FFEFFF);
+ if (cpu_is_msm8930())
+ rmwreg(0x000004FF, MAXI_EN5_REG, 0x00000FFF);
if (cpu_is_msm8960())
rmwreg(0x00003C38, SAXI_EN_REG, 0x00003FFF);
else
@@ -5535,12 +5853,9 @@
rmwreg(0x00000000, CSI0_CC_REG, 0x00000410);
rmwreg(0x00000000, CSI1_CC_REG, 0x00000410);
rmwreg(0x80FF0000, DSI1_BYTE_CC_REG, 0xE0FF0010);
- rmwreg(0x80FF0000, DSI2_BYTE_CC_REG, 0xE0FF0010);
rmwreg(0x80FF0000, DSI_PIXEL_CC_REG, 0xE0FF0010);
- rmwreg(0x80FF0000, DSI2_PIXEL_CC_REG, 0xE0FF0010);
rmwreg(0xC0FF0000, GFX3D_CC_REG, 0xE0FF0010);
rmwreg(0x80FF0000, IJPEG_CC_REG, 0xE0FF0010);
- rmwreg(0x80FF0000, JPEGD_CC_REG, 0xE0FF0010);
rmwreg(0x80FF0000, MDP_CC_REG, 0xE1FF0010);
rmwreg(0x80FF0000, MDP_LUT_CC_REG, 0xE0FF0010);
rmwreg(0x80FF0000, ROT_CC_REG, 0xE0FF0010);
@@ -5549,10 +5864,17 @@
rmwreg(0x80FF0000, VFE_CC_REG, 0xE0FF4010);
rmwreg(0x800000FF, VFE_CC2_REG, 0xE00000FF);
rmwreg(0x80FF0000, VPE_CC_REG, 0xE0FF0010);
- if (cpu_is_msm8960() || cpu_is_msm8930()) {
+ if (cpu_is_msm8960() || cpu_is_apq8064()) {
+ rmwreg(0x80FF0000, DSI2_BYTE_CC_REG, 0xE0FF0010);
+ rmwreg(0x80FF0000, DSI2_PIXEL_CC_REG, 0xE0FF0010);
+ rmwreg(0x80FF0000, JPEGD_CC_REG, 0xE0FF0010);
+ }
+ if (cpu_is_msm8960() || cpu_is_msm8930())
+ rmwreg(0x80FF0000, TV_CC_REG, 0xE1FFC010);
+
+ if (cpu_is_msm8960()) {
rmwreg(0x80FF0000, GFX2D0_CC_REG, 0xE0FF0010);
rmwreg(0x80FF0000, GFX2D1_CC_REG, 0xE0FF0010);
- rmwreg(0x80FF0000, TV_CC_REG, 0xE1FFC010);
}
if (cpu_is_apq8064()) {
rmwreg(0x00000000, TV_CC_REG, 0x00004010);
@@ -5594,12 +5916,13 @@
writel_relaxed(BIT(15), PDM_CLK_NS_REG);
/* Source SLIMBus xo src from slimbus reference clock */
- if (cpu_is_msm8960() || cpu_is_msm8930())
+ if (cpu_is_msm8960())
writel_relaxed(0x3, SLIMBUS_XO_SRC_CLK_CTL_REG);
/* Source the dsi_byte_clks from the DSI PHY PLLs */
rmwreg(0x1, DSI1_BYTE_NS_REG, 0x7);
- rmwreg(0x2, DSI2_BYTE_NS_REG, 0x7);
+ if (cpu_is_msm8960() || cpu_is_apq8064())
+ rmwreg(0x2, DSI2_BYTE_NS_REG, 0x7);
/* Source the sata_phy_ref_clk from PXO */
if (cpu_is_apq8064())
@@ -5692,7 +6015,21 @@
memcpy(vfe_clk.c.fmax, fmax_vfe_8064,
sizeof(vfe_clk.c.fmax));
- gmem_axi_clk.c.depends = &gfx3d_axi_clk.c;
+ gmem_axi_clk.c.depends = &gfx3d_axi_clk_8064.c;
+ }
+
+ /*
+ * Change the freq tables and voltage requirements for
+ * clocks which differ between 8960 and 8930.
+ */
+ if (cpu_is_msm8930()) {
+ gfx3d_clk.freq_tbl = clk_tbl_gfx3d_8930;
+
+ memcpy(gfx3d_clk.c.fmax, fmax_gfx3d_8930,
+ sizeof(gfx3d_clk.c.fmax));
+
+ pll15_clk.c.rate = 900000000;
+ gmem_axi_clk.c.depends = &gfx3d_axi_clk_8930.c;
}
vote_vdd_level(&vdd_dig, VDD_DIG_HIGH);
@@ -5792,3 +6129,10 @@
.init = msm8960_clock_init,
.late_init = msm8960_clock_late_init,
};
+
+struct clock_init_data msm8930_clock_init_data __initdata = {
+ .table = msm_clocks_8930,
+ .size = ARRAY_SIZE(msm_clocks_8930),
+ .init = msm8960_clock_init,
+ .late_init = msm8960_clock_late_init,
+};
diff --git a/arch/arm/mach-msm/clock.h b/arch/arm/mach-msm/clock.h
index bce2e0f..785e838 100644
--- a/arch/arm/mach-msm/clock.h
+++ b/arch/arm/mach-msm/clock.h
@@ -149,6 +149,7 @@
extern struct clock_init_data msm8x60_clock_init_data;
extern struct clock_init_data qds8x50_clock_init_data;
extern struct clock_init_data msm8625_dummy_clock_init_data;
+extern struct clock_init_data msm8930_clock_init_data;
void msm_clock_init(struct clock_init_data *data);
int vote_vdd_level(struct clk_vdd_class *vdd_class, int level);