Merge "msm: kgsl: Add event tracepoints"
diff --git a/arch/arm/mach-msm/board-8064-gpiomux.c b/arch/arm/mach-msm/board-8064-gpiomux.c
index 0dee8f5..0f88287 100644
--- a/arch/arm/mach-msm/board-8064-gpiomux.c
+++ b/arch/arm/mach-msm/board-8064-gpiomux.c
@@ -1729,13 +1729,6 @@
},
};
-static struct gpiomux_setting fsm8064_ep_sync_drsync_cfg = {
- .func = GPIOMUX_FUNC_GPIO,
- .drv = GPIOMUX_DRV_2MA,
- .pull = GPIOMUX_PULL_UP,
- .dir = GPIOMUX_OUT_HIGH,
-};
-
static struct gpiomux_setting fsm8064_ep_sync_input_cfg = {
.func = GPIOMUX_FUNC_GPIO,
.drv = GPIOMUX_DRV_4MA,
@@ -1746,7 +1739,7 @@
{
.gpio = 6, /* GPSPPSIN_DRSYNC */
.settings = {
- [GPIOMUX_SUSPENDED] = &fsm8064_ep_sync_drsync_cfg,
+ [GPIOMUX_SUSPENDED] = &fsm8064_ep_sync_input_cfg,
},
},
{
diff --git a/arch/arm/mach-msm/board-8064-pmic.c b/arch/arm/mach-msm/board-8064-pmic.c
index 0b3366c..a1ed251 100644
--- a/arch/arm/mach-msm/board-8064-pmic.c
+++ b/arch/arm/mach-msm/board-8064-pmic.c
@@ -137,7 +137,7 @@
PM8921_GPIO_OUTPUT_VIN(14, 1, PM_GPIO_VIN_VPH),
/* PPS_SRC_SEL_N, chooses between WGR7640 PPS source (high) or
* CW GPS module PPS source (low) */
- PM8921_GPIO_OUTPUT_VIN(19, 1, PM_GPIO_VIN_VPH), /* PPS_SRC_SEL_N */
+ PM8921_GPIO_OUTPUT_VIN(19, 0, PM_GPIO_VIN_VPH), /* PPS_SRC_SEL_N */
PM8921_GPIO_OUTPUT_VIN(13, 1, PM_GPIO_VIN_VPH), /* PCIE_CLK_PWR_EN */
PM8921_GPIO_OUTPUT_VIN(37, 1, PM_GPIO_VIN_VPH), /* PCIE_RST_N */
diff --git a/arch/arm/mach-msm/board-8064.c b/arch/arm/mach-msm/board-8064.c
index 9ed71da..f3d648e 100644
--- a/arch/arm/mach-msm/board-8064.c
+++ b/arch/arm/mach-msm/board-8064.c
@@ -4005,6 +4005,7 @@
.init_early = apq8064_allocate_memory_regions,
.init_very_early = apq8064_early_reserve,
.restart = msm_restart,
+ .smp = &msm8960_smp_ops,
MACHINE_END
MACHINE_START(APQ8064_MTP, "QCT APQ8064 MTP")
diff --git a/arch/arm/mach-msm/include/mach/iommu_perfmon.h b/arch/arm/mach-msm/include/mach/iommu_perfmon.h
index 5a01bee..c03c752 100644
--- a/arch/arm/mach-msm/include/mach/iommu_perfmon.h
+++ b/arch/arm/mach-msm/include/mach/iommu_perfmon.h
@@ -12,6 +12,7 @@
#include <linux/err.h>
#include <linux/mutex.h>
#include <linux/list.h>
+#include <linux/irqreturn.h>
#ifndef MSM_IOMMU_PERFMON_H
#define MSM_IOMMU_PERFMON_H
diff --git a/drivers/power/qpnp-bms.c b/drivers/power/qpnp-bms.c
index eb75475..ec0b0e7 100644
--- a/drivers/power/qpnp-bms.c
+++ b/drivers/power/qpnp-bms.c
@@ -1095,60 +1095,6 @@
return 1;
}
-#define BMS_OVERRIDE_MODE_EN_BIT BIT(7)
-#define EN_VBAT_BIT BIT(0)
-#define OVERRIDE_MODE_DELAY_MS 20
-static int override_mode_batt_v_and_i(
- struct qpnp_bms_chip *chip, int *ibat_ua, int *vbat_uv)
-{
- int16_t vsense_raw, vbat_raw;
- int vsense_uv, rc;
- u8 delay;
-
- mutex_lock(&chip->bms_output_lock);
-
- delay = 0x00;
- rc = qpnp_write_wrapper(chip, &delay,
- chip->base + BMS1_S1_DELAY_CTL, 1);
- if (rc)
- pr_err("unable to write into BMS1_S1_DELAY, rc: %d\n", rc);
-
- rc = qpnp_masked_write(chip, BMS1_MODE_CTL,
- BMS_OVERRIDE_MODE_EN_BIT | EN_VBAT_BIT,
- BMS_OVERRIDE_MODE_EN_BIT | EN_VBAT_BIT);
- if (rc)
- pr_err("unable to write into BMS1_MODE_CTL, rc: %d\n", rc);
-
- msleep(OVERRIDE_MODE_DELAY_MS);
-
- lock_output_data(chip);
- qpnp_read_wrapper(chip, (u8 *)&vsense_raw,
- chip->base + BMS1_VSENSE_AVG_DATA0, 2);
- qpnp_read_wrapper(chip, (u8 *)&vbat_raw,
- chip->base + BMS1_VBAT_AVG_DATA0, 2);
- unlock_output_data(chip);
-
- rc = qpnp_masked_write(chip, BMS1_MODE_CTL,
- BMS_OVERRIDE_MODE_EN_BIT | EN_VBAT_BIT, 0);
-
- delay = 0x0B;
- rc = qpnp_write_wrapper(chip, &delay,
- chip->base + BMS1_S1_DELAY_CTL, 1);
- if (rc)
- pr_err("unable to write into BMS1_S1_DELAY, rc: %d\n", rc);
-
- mutex_unlock(&chip->bms_output_lock);
-
- *vbat_uv = convert_vbatt_raw_to_uv(chip, vbat_raw);
- vsense_uv = convert_vsense_to_uv(chip, vsense_raw);
- *ibat_ua = div_s64(vsense_uv * 1000000LL, (int)chip->r_sense_uohm);
-
- pr_debug("vsense_raw = 0x%x vbat_raw = 0x%x ibat_ua = %d vbat_uv = %d\n",
- (uint16_t)vsense_raw, (uint16_t)vbat_raw,
- *ibat_ua, *vbat_uv);
- return 0;
-}
-
static bool is_battery_charging(struct qpnp_bms_chip *chip)
{
union power_supply_propval ret = {0,};
@@ -1188,23 +1134,21 @@
static int get_simultaneous_batt_v_and_i(struct qpnp_bms_chip *chip,
int *ibat_ua, int *vbat_uv)
{
+ struct qpnp_iadc_result i_result;
+ struct qpnp_vadc_result v_result;
+ enum qpnp_iadc_channels iadc_channel;
int rc;
- if (is_batfet_open(chip)) {
- pr_debug("batfet is open using separate vbat and ibat meas\n");
- rc = get_battery_voltage(vbat_uv);
- if (rc < 0) {
- pr_err("adc vbat failed err = %d\n", rc);
- return rc;
- }
- rc = get_battery_current(chip, ibat_ua);
- if (rc < 0) {
- pr_err("bms ibat failed err = %d\n", rc);
- return rc;
- }
- } else {
- return override_mode_batt_v_and_i(chip, ibat_ua, vbat_uv);
+ iadc_channel = chip->use_external_rsense ?
+ EXTERNAL_RSENSE : INTERNAL_RSENSE;
+ rc = qpnp_iadc_vadc_sync_read(iadc_channel, &i_result,
+ VBAT_SNS, &v_result);
+ if (rc) {
+ pr_err("vadc read failed with rc: %d\n", rc);
+ return rc;
}
+ *ibat_ua = (int)i_result.result_ua;
+ *vbat_uv = (int)v_result.physical;
return 0;
}
@@ -1231,7 +1175,7 @@
static int reset_bms_for_test(struct qpnp_bms_chip *chip)
{
- int ibat_ua, vbat_uv, rc;
+ int ibat_ua = 0, vbat_uv = 0, rc;
int ocv_est_uv;
if (!chip) {