usb: otg: Add delay between ASSERT and DEASSERT in clock reset

If target dont have phy_reset_clk , there is no waiting between
link_clk_reset assert and deassert, which cause the reset to fail.
10 useconds waiting is added.

Change-Id: I34a94710767a3e7bf6b48d28c917129bc9d9767f
Signed-off-by: Bar Weiner <bweiner@codeaurora.org>
diff --git a/drivers/usb/otg/msm_otg.c b/drivers/usb/otg/msm_otg.c
index c6fe765..a315587 100644
--- a/drivers/usb/otg/msm_otg.c
+++ b/drivers/usb/otg/msm_otg.c
@@ -485,6 +485,9 @@
 	ret = msm_otg_phy_clk_reset(motg);
 	if (ret)
 		return ret;
+	/* 10 usec delay is required according to spec */
+	if (IS_ERR(motg->phy_reset_clk))
+		usleep_range(10, 12);
 	ret = msm_otg_link_clk_reset(motg, 0);
 	if (ret)
 		return ret;