Merge "ARM: dts: msm: Add firmware update fields for 8226 qrd"
diff --git a/Documentation/devicetree/bindings/platform/msm/qpnp-power-on.txt b/Documentation/devicetree/bindings/platform/msm/qpnp-power-on.txt
index 3095b0a..83237f9 100644
--- a/Documentation/devicetree/bindings/platform/msm/qpnp-power-on.txt
+++ b/Documentation/devicetree/bindings/platform/msm/qpnp-power-on.txt
@@ -56,6 +56,7 @@
0 = Not supported
1 = Supported
This property is set to '0' if not specified.
+- qcom,use-bark Specify if this pon type needs to handle bark irq
- qcom,s1-timer The debounce timer for the BARK interrupt for
that reset source. Value is specified in ms.
Supported values are -
@@ -106,6 +107,7 @@
qcom,s2-timer = <2000>;
qcom,s2-type = <1>;
linux,code = <114>;
+ qcom,use-bark;
};
qcom,pon_3 {
@@ -115,5 +117,6 @@
qcom,s2-timer = <2000>;
qcom,s2-type = <7>;
qcom,pull-up = <1>;
+ qcom,use-bark;
};
};
diff --git a/arch/arm/boot/dts/msm-pm8226.dtsi b/arch/arm/boot/dts/msm-pm8226.dtsi
index 5e0abea..f2ed8b5 100644
--- a/arch/arm/boot/dts/msm-pm8226.dtsi
+++ b/arch/arm/boot/dts/msm-pm8226.dtsi
@@ -50,6 +50,10 @@
qcom,pon-type = <1>;
qcom,pull-up = <1>;
linux,code = <114>;
+ qcom,s1-timer = <6720>;
+ qcom,s2-timer = <2000>;
+ qcom,s2-type = <7>;
+ qcom,support-reset = <1>;
};
qcom,pon_3 {
@@ -59,6 +63,7 @@
qcom,s1-timer = <6720>;
qcom,s2-timer = <2000>;
qcom,s2-type = <7>;
+ qcom,use-bark;
};
};
diff --git a/arch/arm/boot/dts/msm-pm8941.dtsi b/arch/arm/boot/dts/msm-pm8941.dtsi
index 8a239cc..c4de04c 100644
--- a/arch/arm/boot/dts/msm-pm8941.dtsi
+++ b/arch/arm/boot/dts/msm-pm8941.dtsi
@@ -69,6 +69,7 @@
qcom,s2-timer = <2000>;
qcom,s2-type = <1>;
linux,code = <114>;
+ qcom,use-bark;
};
qcom,pon_3 {
@@ -78,6 +79,7 @@
qcom,s2-timer = <2000>;
qcom,s2-type = <7>;
qcom,pull-up = <1>;
+ qcom,use-bark;
};
};
diff --git a/arch/arm/boot/dts/msm8610-v1-qrd-skuab-dvt2.dts b/arch/arm/boot/dts/msm8610-v1-qrd-skuab-dvt2.dts
new file mode 100644
index 0000000..f250c4a
--- /dev/null
+++ b/arch/arm/boot/dts/msm8610-v1-qrd-skuab-dvt2.dts
@@ -0,0 +1,23 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+/include/ "msm8610-v1.dtsi"
+/include/ "msm8610-qrd-skuab.dtsi"
+/include/ "msm8612-qrd-camera-sensor.dtsi"
+
+/ {
+ model = "Qualcomm MSM 8610v1 QRD SKUAB DVT2";
+ compatible = "qcom,msm8610-qrd", "qcom,msm8610", "qcom,qrd";
+ qcom,board-id = <0x2000b 3>;
+};
diff --git a/arch/arm/boot/dts/msm8610-v2-qrd-skuab-dvt2.dts b/arch/arm/boot/dts/msm8610-v2-qrd-skuab-dvt2.dts
new file mode 100644
index 0000000..9867ca6
--- /dev/null
+++ b/arch/arm/boot/dts/msm8610-v2-qrd-skuab-dvt2.dts
@@ -0,0 +1,23 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+/include/ "msm8610-v2.dtsi"
+/include/ "msm8610-qrd-skuab.dtsi"
+/include/ "msm8612-qrd-camera-sensor.dtsi"
+
+/ {
+ model = "Qualcomm MSM 8610v2 QRD SKUAB DVT2";
+ compatible = "qcom,msm8610-qrd", "qcom,msm8610", "qcom,qrd";
+ qcom,board-id = <0x2000b 3>;
+};
diff --git a/arch/arm/configs/msm8226-perf_defconfig b/arch/arm/configs/msm8226-perf_defconfig
index 108907a..03ed61f 100644
--- a/arch/arm/configs/msm8226-perf_defconfig
+++ b/arch/arm/configs/msm8226-perf_defconfig
@@ -449,3 +449,4 @@
CONFIG_MSM_RPM_RBCPR_STATS_V2_LOG=y
CONFIG_TOUCHSCREEN_GT9XX=y
CONFIG_GT9XX_TOUCHPANEL_DRIVER=y
+CONFIG_DEFAULT_ROW=y
diff --git a/arch/arm/configs/msm8226_defconfig b/arch/arm/configs/msm8226_defconfig
index 6d50e8d..f953a70 100644
--- a/arch/arm/configs/msm8226_defconfig
+++ b/arch/arm/configs/msm8226_defconfig
@@ -500,3 +500,4 @@
CONFIG_MSM_RPM_RBCPR_STATS_V2_LOG=y
CONFIG_TOUCHSCREEN_GT9XX=y
CONFIG_GT9XX_TOUCHPANEL_DRIVER=y
+CONFIG_DEFAULT_ROW=y
diff --git a/arch/arm/mach-msm/acpuclock-8974.c b/arch/arm/mach-msm/acpuclock-8974.c
index 7feb30d..66534eb 100644
--- a/arch/arm/mach-msm/acpuclock-8974.c
+++ b/arch/arm/mach-msm/acpuclock-8974.c
@@ -900,219 +900,226 @@
};
static struct acpu_level pro_rev0_2p3g_pvs0[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 72 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 83 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 101 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 780000, 120 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 790000, 139 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 800000, 159 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 810000, 180 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 820000, 200 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 830000, 221 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 840000, 242 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 850000, 264 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 865000, 287 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 875000, 308 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 890000, 333 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 900000, 356 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 915000, 380 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 925000, 404 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 940000, 430 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 955000, 456 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 970000, 482 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 985000, 510 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 1000000, 538 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1015000, 565 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1030000, 596 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1045000, 627 },
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1060000, 659 },
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1075000, 691 },
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 74 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 85 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 104 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 780000, 124 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 790000, 144 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 800000, 164 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 810000, 184 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 820000, 206 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 830000, 227 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 840000, 249 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 850000, 271 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 865000, 295 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 875000, 318 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 890000, 342 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 900000, 365 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 915000, 392 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 925000, 416 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 940000, 442 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 955000, 469 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 970000, 497 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 985000, 525 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 1000000, 554 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1015000, 583 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1030000, 613 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1045000, 642 },
+ { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 1060000, 663 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1060000, 675 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1075000, 708 },
{ 0, { 0 } }
};
static struct acpu_level pro_rev0_2p3g_pvs1[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 72 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 83 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 101 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 120 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 139 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 785000, 159 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 795000, 180 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 805000, 200 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 815000, 221 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 825000, 242 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 835000, 264 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 850000, 287 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 860000, 308 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 870000, 333 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 885000, 356 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 895000, 380 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 905000, 404 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 920000, 430 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 935000, 456 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 950000, 482 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 965000, 510 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 980000, 538 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 995000, 565 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1005000, 596 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1020000, 627 },
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1035000, 659 },
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1050000, 691 },
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 74 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 85 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 104 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 124 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 144 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 785000, 164 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 795000, 184 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 805000, 206 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 815000, 227 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 825000, 249 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 835000, 271 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 850000, 295 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 860000, 318 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 870000, 342 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 885000, 365 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 895000, 392 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 905000, 416 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 920000, 442 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 935000, 469 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 950000, 497 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 965000, 525 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 980000, 554 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 995000, 583 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1005000, 613 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1020000, 642 },
+ { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 1035000, 663 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1035000, 675 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1050000, 708 },
{ 0, { 0 } }
};
static struct acpu_level pro_rev0_2p3g_pvs2[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 750000, 72 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 750000, 83 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 750000, 101 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 750000, 120 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 760000, 139 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 770000, 159 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 780000, 180 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 790000, 200 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 800000, 221 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 810000, 242 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 820000, 264 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 830000, 287 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 840000, 308 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 850000, 333 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 865000, 356 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 875000, 380 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 885000, 404 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 900000, 430 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 915000, 456 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 930000, 482 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 945000, 510 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 955000, 538 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 970000, 565 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 980000, 596 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 995000, 627 },
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1010000, 659 },
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1025000, 691 },
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 750000, 74 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 750000, 85 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 750000, 104 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 750000, 124 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 760000, 144 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 770000, 164 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 780000, 184 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 790000, 206 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 800000, 227 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 810000, 249 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 820000, 271 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 830000, 295 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 840000, 318 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 850000, 342 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 865000, 365 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 875000, 392 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 885000, 416 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 900000, 442 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 915000, 469 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 930000, 497 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 945000, 525 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 955000, 554 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 970000, 583 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 980000, 613 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 995000, 642 },
+ { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 1010000, 663 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1010000, 675 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1025000, 708 },
{ 0, { 0 } }
};
static struct acpu_level pro_rev0_2p3g_pvs3[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 750000, 72 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 750000, 83 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 750000, 101 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 750000, 120 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 750000, 139 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 755000, 159 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 765000, 180 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 775000, 200 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 785000, 221 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 795000, 242 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 805000, 264 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 815000, 287 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 825000, 308 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 835000, 333 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 850000, 356 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 860000, 380 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 870000, 404 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 885000, 430 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 900000, 456 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 910000, 482 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 925000, 510 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 935000, 538 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 945000, 565 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 960000, 596 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 970000, 627 },
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 985000, 659 },
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1000000, 691 },
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 750000, 74 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 750000, 85 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 750000, 104 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 750000, 124 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 750000, 144 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 755000, 164 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 765000, 184 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 775000, 206 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 785000, 227 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 795000, 249 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 805000, 271 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 815000, 295 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 825000, 318 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 835000, 342 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 850000, 365 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 860000, 392 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 870000, 416 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 885000, 442 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 900000, 469 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 910000, 497 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 925000, 525 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 935000, 554 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 945000, 583 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 960000, 613 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 970000, 642 },
+ { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 985000, 663 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 985000, 675 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1000000, 708 },
{ 0, { 0 } }
};
static struct acpu_level pro_rev0_2p3g_pvs4[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 750000, 72 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 750000, 83 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 750000, 101 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 750000, 120 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 750000, 139 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 750000, 159 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 755000, 180 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 765000, 200 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 775000, 221 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 785000, 242 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 795000, 264 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 805000, 287 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 815000, 308 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 825000, 333 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 835000, 356 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 845000, 380 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 855000, 404 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 870000, 430 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 885000, 456 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 895000, 482 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 905000, 510 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 915000, 538 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 925000, 565 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 935000, 596 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 950000, 627 },
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 960000, 659 },
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 975000, 691 },
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 750000, 74 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 750000, 85 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 750000, 104 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 750000, 124 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 750000, 144 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 750000, 164 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 755000, 184 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 765000, 206 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 775000, 227 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 785000, 249 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 795000, 271 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 805000, 295 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 815000, 318 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 825000, 342 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 835000, 365 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 845000, 392 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 855000, 416 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 870000, 442 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 885000, 469 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 895000, 497 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 905000, 525 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 915000, 554 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 925000, 583 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 935000, 613 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 950000, 642 },
+ { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 960000, 663 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 960000, 675 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 975000, 708 },
{ 0, { 0 } }
};
static struct acpu_level pro_rev0_2p3g_pvs5[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 725000, 72 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 725000, 83 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 725000, 101 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 725000, 120 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 725000, 139 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 735000, 159 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 745000, 180 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 755000, 200 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 765000, 221 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 775000, 242 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 785000, 264 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 795000, 287 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 805000, 308 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 815000, 333 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 825000, 356 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 835000, 380 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 845000, 404 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 855000, 430 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 865000, 456 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 875000, 482 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 885000, 510 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 895000, 538 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 905000, 565 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 915000, 596 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 930000, 627 },
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 940000, 659 },
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 950000, 691 },
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 725000, 74 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 725000, 85 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 725000, 104 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 725000, 124 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 725000, 144 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 735000, 164 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 745000, 184 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 755000, 206 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 765000, 227 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 775000, 249 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 785000, 271 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 795000, 295 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 805000, 318 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 815000, 342 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 825000, 365 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 835000, 392 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 845000, 416 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 855000, 442 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 865000, 469 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 875000, 497 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 885000, 525 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 895000, 554 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 905000, 583 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 915000, 613 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 930000, 642 },
+ { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 940000, 663 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 940000, 675 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 950000, 708 },
{ 0, { 0 } }
};
static struct acpu_level pro_rev0_2p3g_pvs6[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 725000, 72 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 725000, 83 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 725000, 101 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 725000, 120 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 725000, 139 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 725000, 159 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 735000, 180 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 745000, 200 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 755000, 221 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 765000, 242 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 775000, 264 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 785000, 287 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 795000, 308 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 805000, 333 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 815000, 356 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 825000, 380 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 835000, 404 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 845000, 430 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 850000, 456 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 860000, 482 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 870000, 510 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 880000, 538 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 890000, 565 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 895000, 596 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 905000, 627 },
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 915000, 659 },
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 925000, 691 },
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 725000, 74 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 725000, 85 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 725000, 104 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 725000, 124 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 725000, 144 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 725000, 164 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 735000, 184 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 745000, 206 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 755000, 227 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 765000, 249 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 775000, 271 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 785000, 295 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 795000, 318 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 805000, 342 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 815000, 365 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 825000, 392 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 835000, 416 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 845000, 442 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 850000, 469 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 860000, 497 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 870000, 525 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 880000, 554 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 890000, 583 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 895000, 613 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 905000, 642 },
+ { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 915000, 663 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 915000, 675 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 925000, 708 },
{ 0, { 0 } }
};
@@ -1122,31 +1129,32 @@
{ 1, { 422400, HFPLL, 2, 44 }, L2(2), 800000, 106 },
{ 0, { 499200, HFPLL, 2, 52 }, L2(2), 800000, 125 },
{ 0, { 576000, HFPLL, 1, 30 }, L2(3), 800000, 145 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 800000, 164 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 800000, 183 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 800000, 202 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 800000, 222 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 800000, 241 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 805000, 261 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 815000, 282 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 825000, 305 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 835000, 327 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 845000, 350 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 855000, 373 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 870000, 398 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 885000, 424 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 900000, 449 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 915000, 476 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 930000, 503 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 945000, 530 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 960000, 559 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 980000, 590 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1000000, 621 },
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1020000, 654 },
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1040000, 686 },
- { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1060000, 723 },
- { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 1080000, 761 },
- { 1, { 2496000, HFPLL, 1, 130 }, L2(19), 1100000, 800 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 810000, 165 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 820000, 186 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 830000, 208 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 840000, 229 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 850000, 251 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 860000, 273 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 870000, 296 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 880000, 319 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 890000, 342 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 900000, 365 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 910000, 390 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 920000, 415 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 930000, 439 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 945000, 465 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 960000, 493 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 975000, 521 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 990000, 549 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1005000, 579 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1020000, 608 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1035000, 638 },
+ { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 1050000, 667 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1050000, 667 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1065000, 700 },
+ { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1080000, 734 },
+ { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 1095000, 769 },
+ { 1, { 2457600, HFPLL, 1, 128 }, L2(19), 1100000, 785 },
{ 0, { 0 } }
};
@@ -1156,31 +1164,32 @@
{ 1, { 422400, HFPLL, 2, 44 }, L2(2), 800000, 106 },
{ 0, { 499200, HFPLL, 2, 52 }, L2(2), 800000, 125 },
{ 0, { 576000, HFPLL, 1, 30 }, L2(3), 800000, 145 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 800000, 164 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 800000, 183 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 800000, 202 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 800000, 222 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 800000, 241 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 800000, 261 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 805000, 282 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 815000, 305 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 825000, 327 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 835000, 350 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 845000, 373 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 855000, 398 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 870000, 424 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 885000, 449 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 900000, 476 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 915000, 503 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 930000, 530 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 945000, 559 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 960000, 590 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 975000, 621 },
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 995000, 654 },
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1015000, 686 },
- { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1035000, 723 },
- { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 1055000, 761 },
- { 1, { 2496000, HFPLL, 1, 130 }, L2(19), 1075000, 800 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 800000, 165 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 800000, 186 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 805000, 208 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 815000, 229 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 825000, 251 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 835000, 273 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 845000, 296 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 855000, 319 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 865000, 342 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 875000, 365 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 885000, 390 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 895000, 415 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 905000, 439 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 920000, 465 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 935000, 493 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 950000, 521 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 965000, 549 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 980000, 579 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 995000, 608 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1010000, 638 },
+ { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 1025000, 667 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1025000, 667 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1040000, 700 },
+ { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1055000, 734 },
+ { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 1070000, 769 },
+ { 1, { 2457600, HFPLL, 1, 128 }, L2(19), 1075000, 785 },
{ 0, { 0 } }
};
@@ -1190,31 +1199,32 @@
{ 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 106 },
{ 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 125 },
{ 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 145 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 775000, 164 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 775000, 183 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 775000, 202 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 775000, 222 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 775000, 241 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 780000, 261 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 790000, 282 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 800000, 305 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 810000, 327 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 820000, 350 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 830000, 373 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 840000, 398 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 850000, 424 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 865000, 449 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 880000, 476 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 895000, 503 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 910000, 530 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 925000, 559 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 940000, 590 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 955000, 621 },
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 970000, 654 },
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 990000, 686 },
- { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1010000, 723 },
- { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 1030000, 761 },
- { 1, { 2496000, HFPLL, 1, 130 }, L2(19), 1050000, 800 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 775000, 165 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 775000, 186 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 780000, 208 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 790000, 229 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 800000, 251 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 810000, 273 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 820000, 296 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 830000, 319 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 840000, 342 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 850000, 365 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 860000, 390 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 870000, 415 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 880000, 439 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 895000, 465 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 910000, 493 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 925000, 521 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 940000, 549 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 955000, 579 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 970000, 608 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 985000, 638 },
+ { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 1000000, 667 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1000000, 667 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1015000, 700 },
+ { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1030000, 734 },
+ { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 1045000, 769 },
+ { 1, { 2457600, HFPLL, 1, 128 }, L2(19), 1050000, 785 },
{ 0, { 0 } }
};
@@ -1224,65 +1234,67 @@
{ 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 106 },
{ 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 125 },
{ 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 145 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 775000, 164 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 775000, 183 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 775000, 202 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 775000, 222 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 775000, 241 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 775000, 261 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 780000, 282 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 790000, 305 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 800000, 327 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 810000, 350 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 820000, 373 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 830000, 398 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 840000, 424 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 850000, 449 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 865000, 476 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 880000, 503 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 895000, 530 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 910000, 559 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 925000, 590 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 940000, 621 },
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 955000, 654 },
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 970000, 686 },
- { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 985000, 723 },
- { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 1005000, 761 },
- { 1, { 2496000, HFPLL, 1, 130 }, L2(19), 1025000, 800 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 775000, 165 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 775000, 186 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 775000, 208 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 775000, 229 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 780000, 251 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 785000, 273 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 795000, 296 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 805000, 319 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 815000, 342 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 825000, 365 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 835000, 390 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 845000, 415 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 855000, 439 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 870000, 465 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 885000, 493 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 900000, 521 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 915000, 549 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 930000, 579 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 945000, 608 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 960000, 638 },
+ { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 975000, 667 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 975000, 667 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 990000, 700 },
+ { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1005000, 734 },
+ { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 1020000, 769 },
+ { 1, { 2457600, HFPLL, 1, 128 }, L2(19), 1025000, 785 },
{ 0, { 0 } }
};
static struct acpu_level pro_rev0_2p5g_pvs4[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 750000, 76 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 750000, 87 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 750000, 106 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 750000, 125 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 750000, 145 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 750000, 164 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 750000, 183 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 750000, 202 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 750000, 222 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 750000, 241 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 760000, 261 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 770000, 282 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 780000, 305 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 790000, 327 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 800000, 350 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 810000, 373 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 820000, 398 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 830000, 424 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 840000, 449 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 850000, 476 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 865000, 503 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 880000, 530 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 895000, 559 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 910000, 590 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 925000, 621 },
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 940000, 654 },
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 955000, 686 },
- { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 970000, 723 },
- { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 985000, 761 },
- { 1, { 2496000, HFPLL, 1, 130 }, L2(19), 1000000, 800 },
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 106 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 125 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 145 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 775000, 165 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 775000, 186 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 775000, 208 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 775000, 229 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 775000, 251 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 775000, 273 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 775000, 296 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 780000, 319 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 790000, 342 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 800000, 365 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 810000, 390 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 820000, 415 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 830000, 439 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 845000, 465 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 860000, 493 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 875000, 521 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 890000, 549 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 905000, 579 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 920000, 608 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 935000, 638 },
+ { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 950000, 667 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 950000, 667 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 965000, 700 },
+ { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 980000, 734 },
+ { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 995000, 769 },
+ { 1, { 2457600, HFPLL, 1, 128 }, L2(19), 1000000, 785 },
{ 0, { 0 } }
};
@@ -1292,65 +1304,67 @@
{ 1, { 422400, HFPLL, 2, 44 }, L2(2), 750000, 106 },
{ 0, { 499200, HFPLL, 2, 52 }, L2(2), 750000, 125 },
{ 0, { 576000, HFPLL, 1, 30 }, L2(3), 750000, 145 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 750000, 164 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 750000, 183 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 750000, 202 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 750000, 222 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 750000, 241 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 750000, 261 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 760000, 282 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 770000, 305 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 780000, 327 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 790000, 350 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 800000, 373 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 810000, 398 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 820000, 424 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 830000, 449 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 840000, 476 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 850000, 503 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 860000, 530 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 870000, 559 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 885000, 590 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 900000, 621 },
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 915000, 654 },
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 930000, 686 },
- { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 945000, 723 },
- { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 960000, 761 },
- { 1, { 2496000, HFPLL, 1, 130 }, L2(19), 975000, 800 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 750000, 165 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 750000, 186 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 750000, 208 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 750000, 229 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 750000, 251 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 750000, 273 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 750000, 296 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 760000, 319 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 770000, 342 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 780000, 365 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 790000, 390 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 800000, 415 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 810000, 439 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 820000, 465 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 835000, 493 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 850000, 521 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 865000, 549 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 880000, 579 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 895000, 608 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 910000, 638 },
+ { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 925000, 667 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 925000, 667 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 940000, 700 },
+ { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 955000, 734 },
+ { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 970000, 769 },
+ { 1, { 2457600, HFPLL, 1, 128 }, L2(19), 975000, 785 },
{ 0, { 0 } }
};
static struct acpu_level pro_rev0_2p5g_pvs6[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 725000, 76 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 725000, 87 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 725000, 106 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 725000, 125 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 725000, 145 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 725000, 164 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 725000, 183 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 725000, 202 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 725000, 222 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 725000, 241 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 735000, 261 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 745000, 282 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 755000, 305 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 765000, 327 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 775000, 350 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 785000, 373 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 795000, 398 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 805000, 424 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 815000, 449 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 825000, 476 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 835000, 503 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 845000, 530 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 855000, 559 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 865000, 590 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 875000, 621 },
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 890000, 654 },
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 905000, 686 },
- { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 920000, 723 },
- { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 935000, 761 },
- { 1, { 2496000, HFPLL, 1, 130 }, L2(19), 950000, 800 },
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 750000, 76 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(1), 750000, 87 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(2), 750000, 106 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(2), 750000, 125 },
+ { 0, { 576000, HFPLL, 1, 30 }, L2(3), 750000, 145 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(3), 750000, 165 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(4), 750000, 186 },
+ { 0, { 806400, HFPLL, 1, 42 }, L2(4), 750000, 208 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(4), 750000, 229 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(9), 750000, 251 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 750000, 273 },
+ { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 750000, 296 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 750000, 319 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 755000, 342 },
+ { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 765000, 365 },
+ { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 775000, 390 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 785000, 415 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 795000, 439 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 805000, 465 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 815000, 493 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 825000, 521 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 840000, 549 },
+ { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 855000, 579 },
+ { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 870000, 608 },
+ { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 885000, 638 },
+ { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 900000, 667 },
+ { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 900000, 667 },
+ { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 915000, 700 },
+ { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 930000, 734 },
+ { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 945000, 769 },
+ { 1, { 2457600, HFPLL, 1, 128 }, L2(19), 950000, 785 },
{ 0, { 0 } }
};
@@ -1380,6 +1394,7 @@
{ 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1025000, 588 },
{ 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1040000, 617 },
{ 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1055000, 649 },
+ { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 1070000, 682 },
{ 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1070000, 682 },
{ 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1085000, 716 },
{ 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1100000, 751 },
@@ -1414,6 +1429,7 @@
{ 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1015000, 588 },
{ 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1030000, 617 },
{ 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1045000, 649 },
+ { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 1060000, 682 },
{ 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1060000, 682 },
{ 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1075000, 716 },
{ 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1090000, 751 },
@@ -1448,6 +1464,7 @@
{ 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1005000, 588 },
{ 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1020000, 617 },
{ 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1035000, 649 },
+ { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 1050000, 682 },
{ 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1050000, 682 },
{ 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1065000, 716 },
{ 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1080000, 751 },
@@ -1482,6 +1499,7 @@
{ 1, { 1958400, HFPLL, 1, 102 }, L2(19), 995000, 588 },
{ 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1010000, 617 },
{ 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1025000, 649 },
+ { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 1040000, 682 },
{ 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1040000, 682 },
{ 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1055000, 716 },
{ 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1070000, 751 },
@@ -1516,6 +1534,7 @@
{ 1, { 1958400, HFPLL, 1, 102 }, L2(19), 985000, 588 },
{ 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1000000, 617 },
{ 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1015000, 649 },
+ { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 1030000, 682 },
{ 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1030000, 682 },
{ 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1045000, 716 },
{ 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1060000, 751 },
@@ -1550,6 +1569,7 @@
{ 1, { 1958400, HFPLL, 1, 102 }, L2(19), 975000, 588 },
{ 0, { 2035200, HFPLL, 1, 106 }, L2(19), 990000, 617 },
{ 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1005000, 649 },
+ { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 1020000, 682 },
{ 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1020000, 682 },
{ 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1035000, 716 },
{ 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1050000, 751 },
@@ -1584,6 +1604,7 @@
{ 1, { 1958400, HFPLL, 1, 102 }, L2(19), 965000, 588 },
{ 0, { 2035200, HFPLL, 1, 106 }, L2(19), 980000, 617 },
{ 0, { 2112000, HFPLL, 1, 110 }, L2(19), 995000, 649 },
+ { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 1010000, 682 },
{ 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1010000, 682 },
{ 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1025000, 716 },
{ 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1040000, 751 },
@@ -1618,6 +1639,7 @@
{ 1, { 1958400, HFPLL, 1, 102 }, L2(19), 955000, 588 },
{ 0, { 2035200, HFPLL, 1, 106 }, L2(19), 970000, 617 },
{ 0, { 2112000, HFPLL, 1, 110 }, L2(19), 985000, 649 },
+ { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 1000000, 682 },
{ 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1000000, 682 },
{ 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1015000, 716 },
{ 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1030000, 751 },
@@ -1652,6 +1674,7 @@
{ 1, { 1958400, HFPLL, 1, 102 }, L2(19), 945000, 588 },
{ 0, { 2035200, HFPLL, 1, 106 }, L2(19), 960000, 617 },
{ 0, { 2112000, HFPLL, 1, 110 }, L2(19), 975000, 649 },
+ { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 990000, 682 },
{ 0, { 2188800, HFPLL, 1, 114 }, L2(19), 990000, 682 },
{ 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1005000, 716 },
{ 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1020000, 751 },
@@ -1686,6 +1709,7 @@
{ 1, { 1958400, HFPLL, 1, 102 }, L2(19), 935000, 588 },
{ 0, { 2035200, HFPLL, 1, 106 }, L2(19), 950000, 617 },
{ 0, { 2112000, HFPLL, 1, 110 }, L2(19), 965000, 649 },
+ { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 980000, 682 },
{ 0, { 2188800, HFPLL, 1, 114 }, L2(19), 980000, 682 },
{ 1, { 2265600, HFPLL, 1, 118 }, L2(19), 995000, 716 },
{ 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1010000, 751 },
@@ -1720,6 +1744,7 @@
{ 1, { 1958400, HFPLL, 1, 102 }, L2(19), 925000, 588 },
{ 0, { 2035200, HFPLL, 1, 106 }, L2(19), 940000, 617 },
{ 0, { 2112000, HFPLL, 1, 110 }, L2(19), 955000, 649 },
+ { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 970000, 682 },
{ 0, { 2188800, HFPLL, 1, 114 }, L2(19), 970000, 682 },
{ 1, { 2265600, HFPLL, 1, 118 }, L2(19), 985000, 716 },
{ 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1000000, 751 },
@@ -1754,6 +1779,7 @@
{ 1, { 1958400, HFPLL, 1, 102 }, L2(19), 915000, 588 },
{ 0, { 2035200, HFPLL, 1, 106 }, L2(19), 930000, 617 },
{ 0, { 2112000, HFPLL, 1, 110 }, L2(19), 945000, 649 },
+ { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 960000, 682 },
{ 0, { 2188800, HFPLL, 1, 114 }, L2(19), 960000, 682 },
{ 1, { 2265600, HFPLL, 1, 118 }, L2(19), 975000, 716 },
{ 0, { 2342400, HFPLL, 1, 122 }, L2(19), 990000, 751 },
@@ -1788,6 +1814,7 @@
{ 1, { 1958400, HFPLL, 1, 102 }, L2(19), 905000, 588 },
{ 0, { 2035200, HFPLL, 1, 106 }, L2(19), 920000, 617 },
{ 0, { 2112000, HFPLL, 1, 110 }, L2(19), 935000, 649 },
+ { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 950000, 682 },
{ 0, { 2188800, HFPLL, 1, 114 }, L2(19), 950000, 682 },
{ 1, { 2265600, HFPLL, 1, 118 }, L2(19), 965000, 716 },
{ 0, { 2342400, HFPLL, 1, 122 }, L2(19), 980000, 751 },
@@ -1822,6 +1849,7 @@
{ 1, { 1958400, HFPLL, 1, 102 }, L2(19), 895000, 588 },
{ 0, { 2035200, HFPLL, 1, 106 }, L2(19), 910000, 617 },
{ 0, { 2112000, HFPLL, 1, 110 }, L2(19), 925000, 649 },
+ { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 940000, 682 },
{ 0, { 2188800, HFPLL, 1, 114 }, L2(19), 940000, 682 },
{ 1, { 2265600, HFPLL, 1, 118 }, L2(19), 955000, 716 },
{ 0, { 2342400, HFPLL, 1, 122 }, L2(19), 970000, 751 },
@@ -1856,6 +1884,7 @@
{ 1, { 1958400, HFPLL, 1, 102 }, L2(19), 885000, 588 },
{ 0, { 2035200, HFPLL, 1, 106 }, L2(19), 900000, 617 },
{ 0, { 2112000, HFPLL, 1, 110 }, L2(19), 915000, 649 },
+ { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 930000, 682 },
{ 0, { 2188800, HFPLL, 1, 114 }, L2(19), 930000, 682 },
{ 1, { 2265600, HFPLL, 1, 118 }, L2(19), 945000, 716 },
{ 0, { 2342400, HFPLL, 1, 122 }, L2(19), 960000, 751 },
@@ -1890,6 +1919,7 @@
{ 1, { 1958400, HFPLL, 1, 102 }, L2(19), 875000, 588 },
{ 0, { 2035200, HFPLL, 1, 106 }, L2(19), 890000, 617 },
{ 0, { 2112000, HFPLL, 1, 110 }, L2(19), 905000, 649 },
+ { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 920000, 682 },
{ 0, { 2188800, HFPLL, 1, 114 }, L2(19), 920000, 682 },
{ 1, { 2265600, HFPLL, 1, 118 }, L2(19), 935000, 716 },
{ 0, { 2342400, HFPLL, 1, 122 }, L2(19), 950000, 751 },
@@ -1924,6 +1954,7 @@
{ 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1060000, 604 },
{ 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1075000, 636 },
{ 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1090000, 669 },
+ { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 1105000, 703 },
{ 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1105000, 703 },
{ 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1120000, 738 },
{ 0, { 0 } }
@@ -1955,6 +1986,7 @@
{ 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1050000, 604 },
{ 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1065000, 636 },
{ 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1080000, 669 },
+ { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 1095000, 703 },
{ 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1095000, 703 },
{ 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1110000, 738 },
{ 0, { 0 } }
@@ -1986,6 +2018,7 @@
{ 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1040000, 604 },
{ 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1055000, 636 },
{ 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1070000, 669 },
+ { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 1085000, 703 },
{ 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1085000, 703 },
{ 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1100000, 738 },
{ 0, { 0 } }
@@ -2017,6 +2050,7 @@
{ 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1030000, 604 },
{ 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1045000, 636 },
{ 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1060000, 669 },
+ { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 1075000, 703 },
{ 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1075000, 703 },
{ 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1090000, 738 },
{ 0, { 0 } }
@@ -2048,6 +2082,7 @@
{ 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1020000, 604 },
{ 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1035000, 636 },
{ 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1050000, 669 },
+ { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 1065000, 703 },
{ 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1065000, 703 },
{ 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1080000, 738 },
{ 0, { 0 } }
@@ -2079,6 +2114,7 @@
{ 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1010000, 604 },
{ 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1025000, 636 },
{ 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1040000, 669 },
+ { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 1055000, 703 },
{ 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1055000, 703 },
{ 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1070000, 738 },
{ 0, { 0 } }
@@ -2110,6 +2146,7 @@
{ 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1000000, 604 },
{ 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1015000, 636 },
{ 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1030000, 669 },
+ { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 1045000, 703 },
{ 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1045000, 703 },
{ 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1060000, 738 },
{ 0, { 0 } }
@@ -2141,6 +2178,7 @@
{ 1, { 1958400, HFPLL, 1, 102 }, L2(19), 990000, 604 },
{ 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1005000, 636 },
{ 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1020000, 669 },
+ { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 1035000, 703 },
{ 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1035000, 703 },
{ 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1050000, 738 },
{ 0, { 0 } }
@@ -2172,6 +2210,7 @@
{ 1, { 1958400, HFPLL, 1, 102 }, L2(19), 980000, 604 },
{ 0, { 2035200, HFPLL, 1, 106 }, L2(19), 995000, 636 },
{ 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1010000, 669 },
+ { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 1025000, 703 },
{ 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1025000, 703 },
{ 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1040000, 738 },
{ 0, { 0 } }
@@ -2203,6 +2242,7 @@
{ 1, { 1958400, HFPLL, 1, 102 }, L2(19), 970000, 604 },
{ 0, { 2035200, HFPLL, 1, 106 }, L2(19), 985000, 636 },
{ 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1000000, 669 },
+ { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 1015000, 703 },
{ 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1015000, 703 },
{ 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1030000, 738 },
{ 0, { 0 } }
@@ -2234,6 +2274,7 @@
{ 1, { 1958400, HFPLL, 1, 102 }, L2(19), 960000, 604 },
{ 0, { 2035200, HFPLL, 1, 106 }, L2(19), 975000, 636 },
{ 0, { 2112000, HFPLL, 1, 110 }, L2(19), 990000, 669 },
+ { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 1005000, 703 },
{ 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1005000, 703 },
{ 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1020000, 738 },
{ 0, { 0 } }
@@ -2265,6 +2306,7 @@
{ 1, { 1958400, HFPLL, 1, 102 }, L2(19), 950000, 604 },
{ 0, { 2035200, HFPLL, 1, 106 }, L2(19), 965000, 636 },
{ 0, { 2112000, HFPLL, 1, 110 }, L2(19), 980000, 669 },
+ { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 995000, 703 },
{ 0, { 2188800, HFPLL, 1, 114 }, L2(19), 995000, 703 },
{ 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1010000, 738 },
{ 0, { 0 } }
@@ -2296,6 +2338,7 @@
{ 1, { 1958400, HFPLL, 1, 102 }, L2(19), 940000, 604 },
{ 0, { 2035200, HFPLL, 1, 106 }, L2(19), 955000, 636 },
{ 0, { 2112000, HFPLL, 1, 110 }, L2(19), 970000, 669 },
+ { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 985000, 703 },
{ 0, { 2188800, HFPLL, 1, 114 }, L2(19), 985000, 703 },
{ 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1000000, 738 },
{ 0, { 0 } }
@@ -2327,6 +2370,7 @@
{ 1, { 1958400, HFPLL, 1, 102 }, L2(19), 930000, 604 },
{ 0, { 2035200, HFPLL, 1, 106 }, L2(19), 945000, 636 },
{ 0, { 2112000, HFPLL, 1, 110 }, L2(19), 960000, 669 },
+ { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 975000, 703 },
{ 0, { 2188800, HFPLL, 1, 114 }, L2(19), 975000, 703 },
{ 1, { 2265600, HFPLL, 1, 118 }, L2(19), 990000, 738 },
{ 0, { 0 } }
@@ -2358,6 +2402,7 @@
{ 1, { 1958400, HFPLL, 1, 102 }, L2(19), 920000, 604 },
{ 0, { 2035200, HFPLL, 1, 106 }, L2(19), 935000, 636 },
{ 0, { 2112000, HFPLL, 1, 110 }, L2(19), 950000, 669 },
+ { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 965000, 703 },
{ 0, { 2188800, HFPLL, 1, 114 }, L2(19), 965000, 703 },
{ 1, { 2265600, HFPLL, 1, 118 }, L2(19), 980000, 738 },
{ 0, { 0 } }
@@ -2389,6 +2434,7 @@
{ 1, { 1958400, HFPLL, 1, 102 }, L2(19), 910000, 604 },
{ 0, { 2035200, HFPLL, 1, 106 }, L2(19), 925000, 636 },
{ 0, { 2112000, HFPLL, 1, 110 }, L2(19), 940000, 669 },
+ { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 955000, 703 },
{ 0, { 2188800, HFPLL, 1, 114 }, L2(19), 955000, 703 },
{ 1, { 2265600, HFPLL, 1, 118 }, L2(19), 970000, 738 },
{ 0, { 0 } }
diff --git a/arch/arm/mach-msm/clock-8974.c b/arch/arm/mach-msm/clock-8974.c
index 32a2617..b0adfa0 100644
--- a/arch/arm/mach-msm/clock-8974.c
+++ b/arch/arm/mach-msm/clock-8974.c
@@ -1545,6 +1545,24 @@
},
};
+/* This table is for MSM8974Pro AC SDCC1 */
+static struct clk_freq_tbl ftbl_gcc_sdcc1_apps_clk_ac[] = {
+ F( 144000, cxo, 16, 3, 25),
+ F( 400000, cxo, 12, 1, 4),
+ F( 20000000, gpll0, 15, 1, 2),
+ F( 25000000, gpll0, 12, 1, 2),
+ F( 50000000, gpll0, 12, 0, 0),
+ F(100000000, gpll0, 6, 0, 0),
+ F(192000000, gpll4, 4, 0, 0),
+ F(384000000, gpll4, 2, 0, 0),
+ F_END
+};
+
+/*
+ * This table is for:
+ * 1) SDCC[1-4] on MSM8974Pro AB, MSM8974 v2 and before
+ * 2) SDCC[2-4] on MSM8974Pro AC
+ */
static struct clk_freq_tbl ftbl_gcc_sdcc1_4_apps_clk[] = {
F( 144000, cxo, 16, 3, 25),
F( 400000, cxo, 12, 1, 4),
@@ -1553,7 +1571,6 @@
F( 50000000, gpll0, 12, 0, 0),
F(100000000, gpll0, 6, 0, 0),
F(200000000, gpll0, 3, 0, 0),
- F(384000000, gpll4, 2, 0, 0),
F_END
};
@@ -5777,6 +5794,7 @@
if (cpu_is_msm8974pro_ac()) {
sdcc1_apps_clk_src.c.fmax[VDD_DIG_LOW] = 200000000;
sdcc1_apps_clk_src.c.fmax[VDD_DIG_NOMINAL] = 400000000;
+ sdcc1_apps_clk_src.freq_tbl = ftbl_gcc_sdcc1_apps_clk_ac;
}
vfe0_clk_src.c.fmax[VDD_DIG_LOW] = 150000000;
diff --git a/drivers/gpu/msm/kgsl.c b/drivers/gpu/msm/kgsl.c
index 06c04d4..298b36e 100644
--- a/drivers/gpu/msm/kgsl.c
+++ b/drivers/gpu/msm/kgsl.c
@@ -909,6 +909,9 @@
private = kgsl_find_process_private(cur_dev_priv);
+ if (!private)
+ return NULL;
+
mutex_lock(&private->process_private_mutex);
if (test_bit(KGSL_PROCESS_INIT, &private->priv))
diff --git a/drivers/media/platform/msm/vidc/msm_venc.c b/drivers/media/platform/msm/vidc/msm_venc.c
index 9e8a639..b94d9db 100644
--- a/drivers/media/platform/msm/vidc/msm_venc.c
+++ b/drivers/media/platform/msm/vidc/msm_venc.c
@@ -25,9 +25,9 @@
#define MAX_BIT_RATE 160000000
#define DEFAULT_BIT_RATE 64000
#define BIT_RATE_STEP 100
-#define MIN_FRAME_RATE 65536
-#define MAX_FRAME_RATE 15728640
-#define DEFAULT_FRAME_RATE 1966080
+#define MIN_FRAME_RATE 1
+#define MAX_FRAME_RATE 240
+#define DEFAULT_FRAME_RATE 15
#define DEFAULT_IR_MBS 30
#define MAX_SLICE_BYTE_SIZE 1024
#define MIN_SLICE_BYTE_SIZE 1024
@@ -1257,8 +1257,9 @@
if (!__temp) { \
dprintk(VIDC_ERR, "Can't find %s (%x) in cluster", \
#__ctrl_id, __ctrl_id); \
- rc = -ENOENT; \
- break; \
+ /* Clusters are hardcoded, if we can't find */ \
+ /* something then things are massively screwed up */ \
+ BUG_ON(1); \
} \
__temp; \
})
@@ -1270,11 +1271,15 @@
idr_period.idr_period = ctrl->val;
pdata = &idr_period;
break;
- case V4L2_CID_MPEG_VIDEO_H264_I_PERIOD: {
- struct v4l2_ctrl *b;
- b = TRY_GET_CTRL(V4L2_CID_MPEG_VIDC_VIDEO_NUM_B_FRAMES);
+ case V4L2_CID_MPEG_VIDEO_H264_I_PERIOD:
+ case V4L2_CID_MPEG_VIDC_VIDEO_NUM_B_FRAMES:
+ case V4L2_CID_MPEG_VIDC_VIDEO_NUM_P_FRAMES:
+ {
+ int num_p, num_b;
+ struct v4l2_ctrl update_ctrl = {.id = 0, .val = 0};
- if (inst->fmts[CAPTURE_PORT]->fourcc != V4L2_PIX_FMT_H264 &&
+ if (ctrl->id == V4L2_CID_MPEG_VIDEO_H264_I_PERIOD &&
+ inst->fmts[CAPTURE_PORT]->fourcc != V4L2_PIX_FMT_H264 &&
inst->fmts[CAPTURE_PORT]->fourcc !=
V4L2_PIX_FMT_H264_NO_SC) {
dprintk(VIDC_ERR, "Control 0x%x only valid for H264",
@@ -1283,110 +1288,115 @@
break;
}
- /*
- * We can't set the I-period explicitly. So set it implicitly
- * by setting the number of P and B frames per I-period
- */
- property_id = HAL_CONFIG_VENC_INTRA_PERIOD;
- intra_period.pframes = (ctrl->val - 1) - b->val;
- intra_period.bframes = b->val;
- pdata = &intra_period;
- break;
- }
- case V4L2_CID_MPEG_VIDC_VIDEO_NUM_P_FRAMES:
- temp_ctrl = TRY_GET_CTRL(V4L2_CID_MPEG_VIDC_VIDEO_NUM_B_FRAMES);
- property_id =
- HAL_CONFIG_VENC_INTRA_PERIOD;
- intra_period.pframes = ctrl->val;
- intra_period.bframes = temp_ctrl->val;
- pdata = &intra_period;
- break;
- case V4L2_CID_MPEG_VIDC_VIDEO_NUM_B_FRAMES:
+ temp_ctrl = TRY_GET_CTRL(V4L2_CID_MPEG_VIDC_VIDEO_NUM_B_FRAMES);
+ num_b = temp_ctrl->val;
+
temp_ctrl = TRY_GET_CTRL(V4L2_CID_MPEG_VIDC_VIDEO_NUM_P_FRAMES);
- intra_period.bframes = ctrl->val;
- intra_period.pframes = temp_ctrl->val;
- if (intra_period.bframes) {
+ num_p = temp_ctrl->val;
+
+ /* V4L2_CID_MPEG_VIDEO_H264_I_PERIOD and _NUM_P_FRAMES are
+ * implicitly tied to each other. If either is adjusted,
+ * the other needs to be adjusted in a complementary manner.
+ * Ideally we adjust _NUM_B_FRAMES as well but we'll leave it
+ * alone for now */
+ if (ctrl->id == V4L2_CID_MPEG_VIDEO_H264_I_PERIOD) {
+ num_p = ctrl->val - 1 - num_b;
+ update_ctrl.id = V4L2_CID_MPEG_VIDC_VIDEO_NUM_P_FRAMES;
+ update_ctrl.val = num_p;
+ } else if (ctrl->id == V4L2_CID_MPEG_VIDC_VIDEO_NUM_P_FRAMES) {
+ num_p = ctrl->val;
+ update_ctrl.id = V4L2_CID_MPEG_VIDEO_H264_I_PERIOD;
+ update_ctrl.val = num_p + num_b;
+ } else if (ctrl->id == V4L2_CID_MPEG_VIDC_VIDEO_NUM_B_FRAMES) {
+ num_b = ctrl->val;
+ update_ctrl.id = V4L2_CID_MPEG_VIDEO_H264_I_PERIOD;
+ update_ctrl.val = num_p + num_b;
+ }
+
+ if (update_ctrl.id) {
+ temp_ctrl = TRY_GET_CTRL(update_ctrl.id);
+ temp_ctrl->val = update_ctrl.val;
+ }
+
+ if (num_b) {
u32 max_num_b_frames = MAX_NUM_B_FRAMES;
- property_id =
- HAL_PARAM_VENC_MAX_NUM_B_FRAMES;
+ property_id = HAL_PARAM_VENC_MAX_NUM_B_FRAMES;
pdata = &max_num_b_frames;
rc = call_hfi_op(hdev, session_set_property,
(void *)inst->session, property_id, pdata);
if (rc) {
dprintk(VIDC_ERR,
- "Failed : Setprop MAX_NUM_B_FRAMES"
- "%d", rc);
+ "Failed : Setprop MAX_NUM_B_FRAMES %d",
+ rc);
break;
}
}
- property_id =
- HAL_CONFIG_VENC_INTRA_PERIOD;
+
+ property_id = HAL_CONFIG_VENC_INTRA_PERIOD;
+ intra_period.pframes = num_p;
+ intra_period.bframes = num_b;
pdata = &intra_period;
+
break;
+ }
case V4L2_CID_MPEG_VIDC_VIDEO_REQUEST_IFRAME:
property_id =
HAL_CONFIG_VENC_REQUEST_IFRAME;
request_iframe.enable = true;
pdata = &request_iframe;
break;
+ case V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL:
case V4L2_CID_MPEG_VIDEO_BITRATE_MODE:
{
- bool cfr = true, cbr = true;
int final_mode = 0;
+ struct v4l2_ctrl update_ctrl = {.id = 0, .val = 0};
- temp_ctrl = TRY_GET_CTRL(
- V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL);
-
- switch (temp_ctrl->val) {
- case V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_OFF:
- /* Let's assume CFR */
- case V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_VBR_CFR:
- case V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_CBR_CFR:
- cfr = true;
- break;
- case V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_VBR_VFR:
- case V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_CBR_VFR:
- cfr = false;
- break;
- default:
- dprintk(VIDC_WARN, "Unknown framerate mode");
- }
-
- switch (ctrl->val) {
- case V4L2_MPEG_VIDEO_BITRATE_MODE_VBR:
- cbr = false;
- break;
- case V4L2_MPEG_VIDEO_BITRATE_MODE_CBR:
- cbr = true;
- break;
- default:
- dprintk(VIDC_WARN, "Unknown bitrate mode");
- }
-
- if (!cfr && !cbr)
- final_mode =
- V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_VBR_VFR;
- else if (!cfr && cbr)
- final_mode =
- V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_CBR_VFR;
- else if (cfr && !cbr)
- final_mode =
+ /* V4L2_CID_MPEG_VIDEO_BITRATE_MODE and _RATE_CONTROL
+ * manipulate the same thing. If one control's state
+ * changes, try to mirror the state in the other control's
+ * value */
+ if (ctrl->id == V4L2_CID_MPEG_VIDEO_BITRATE_MODE) {
+ if (ctrl->val == V4L2_MPEG_VIDEO_BITRATE_MODE_VBR) {
+ final_mode = HAL_RATE_CONTROL_VBR_CFR;
+ update_ctrl.val =
V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_VBR_CFR;
- else /* ... if (cfr && cbr) */
- final_mode =
+ } else {/* ...if (ctrl->val == _BITRATE_MODE_CBR) */
+ final_mode = HAL_RATE_CONTROL_CBR_CFR;
+ update_ctrl.val =
V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_CBR_CFR;
+ }
+
+ update_ctrl.id = V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL;
+
+ } else if (ctrl->id == V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL) {
+ switch (ctrl->val) {
+ case V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_OFF:
+ case V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_VBR_VFR:
+ case V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_VBR_CFR:
+ update_ctrl.val =
+ V4L2_MPEG_VIDEO_BITRATE_MODE_VBR;
+ case V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_CBR_VFR:
+ case V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_CBR_CFR:
+ update_ctrl.val =
+ V4L2_MPEG_VIDEO_BITRATE_MODE_CBR;
+ }
+
+ final_mode = ctrl->val;
+ update_ctrl.id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE;
+ }
+
+ if (update_ctrl.id) {
+ temp_ctrl = TRY_GET_CTRL(update_ctrl.id);
+ temp_ctrl->val = update_ctrl.val;
+ }
property_id = HAL_PARAM_VENC_RATE_CONTROL;
property_val = final_mode;
pdata = &property_val;
+
break;
}
- case V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL:
- property_id = HAL_PARAM_VENC_RATE_CONTROL;
- property_val = ctrl->val;
- pdata = &property_val;
- break;
case V4L2_CID_MPEG_VIDEO_BITRATE:
property_id =
HAL_CONFIG_VENC_TARGET_BITRATE;
diff --git a/drivers/media/platform/msm/vidc/msm_vidc.c b/drivers/media/platform/msm/vidc/msm_vidc.c
index 89fbc2a..f2f0f5d 100644
--- a/drivers/media/platform/msm/vidc/msm_vidc.c
+++ b/drivers/media/platform/msm/vidc/msm_vidc.c
@@ -451,12 +451,12 @@
!b->m.planes[i].length) {
continue;
}
+ mutex_lock(&inst->sync_lock);
temp = get_registered_buf(inst, b, i, &plane);
if (temp && !is_dynamic_output_buffer_mode(b, inst)) {
dprintk(VIDC_DBG,
"This memory region has already been prepared\n");
rc = -EINVAL;
- goto exit;
}
if (temp && is_dynamic_output_buffer_mode(b, inst) &&
@@ -471,12 +471,14 @@
*/
dprintk(VIDC_DBG, "[MAP] Buffer already prepared\n");
rc = buf_ref_get(inst, temp);
- if (rc < 0)
- return rc;
- save_v4l2_buffer(b, temp);
- rc = -EEXIST;
- goto exit;
+ if (rc > 0) {
+ save_v4l2_buffer(b, temp);
+ rc = -EEXIST;
+ }
}
+ mutex_unlock(&inst->sync_lock);
+ if (rc < 0)
+ goto exit;
temp = get_same_fd_buffer(inst, &inst->registered_bufs,
b->m.planes[i].reserved[0], &plane);
diff --git a/drivers/media/platform/msm/vidc/msm_vidc_common.c b/drivers/media/platform/msm/vidc/msm_vidc_common.c
index 780f2c4..bf1c2cf 100644
--- a/drivers/media/platform/msm/vidc/msm_vidc_common.c
+++ b/drivers/media/platform/msm/vidc/msm_vidc_common.c
@@ -510,6 +510,7 @@
"RELEASE REFERENCE EVENT FROM F/W - fd = %d offset = %d\n",
ptr[0], ptr[1]);
+ mutex_lock(&inst->sync_lock);
/* Decrement buffer reference count*/
buf_ref_put(inst, binfo);
@@ -520,6 +521,7 @@
if (unmap_and_deregister_buf(inst, binfo))
dprintk(VIDC_ERR,
"%s: buffer unmap failed\n", __func__);
+ mutex_unlock(&inst->sync_lock);
/*send event to client*/
v4l2_event_queue_fh(&inst->event_handler,
@@ -878,7 +880,7 @@
atomic_inc(&binfo->ref_count);
cnt = atomic_read(&binfo->ref_count);
if (cnt > 2) {
- dprintk(VIDC_ERR, "%s: invalid ref_cnt: %d\n", __func__, cnt);
+ dprintk(VIDC_DBG, "%s: invalid ref_cnt: %d\n", __func__, cnt);
cnt = -EINVAL;
}
dprintk(VIDC_DBG, "REF_GET[%d] fd[0] = %d\n", cnt, binfo->fd[0]);
@@ -905,7 +907,7 @@
else if (cnt == 1)
qbuf_again = true;
else {
- dprintk(VIDC_ERR, "%s: invalid ref_cnt: %d\n", __func__, cnt);
+ dprintk(VIDC_DBG, "%s: invalid ref_cnt: %d\n", __func__, cnt);
cnt = -EINVAL;
}
mutex_unlock(&inst->lock);
@@ -957,12 +959,12 @@
}
if (flags & HAL_BUFFERFLAG_READONLY) {
dprintk(VIDC_DBG,
- "_F_B_D_ fd[0] = %d -> Reference with f/w",
- binfo->fd[0]);
+ "_F_B_D_ fd[0] = %d -> Reference with f/w, addr: 0x%x",
+ binfo->fd[0], device_addr);
} else {
dprintk(VIDC_DBG,
- "_F_B_D_ fd[0] = %d -> FBD_ref_released\n",
- binfo->fd[0]);
+ "_F_B_D_ fd[0] = %d -> FBD_ref_released, addr: 0x%x\n",
+ binfo->fd[0], device_addr);
buf_ref_put(inst, binfo);
}
}
@@ -2616,6 +2618,9 @@
dprintk(VIDC_DBG,
"released buffer held in driver before issuing flush: 0x%x fd[0]: %d\n",
binfo->device_addr[0], binfo->fd[0]);
+ /*delete this buffer info from registered list*/
+ list_del(&binfo->list);
+ kfree(binfo);
/*send event to client*/
v4l2_event_queue_fh(&inst->event_handler,
&buf_event);
@@ -2670,6 +2675,7 @@
}
mutex_lock(&inst->sync_lock);
+ msm_comm_flush_dynamic_buffers(inst);
if (inst->in_reconfig && !ip_flush && op_flush) {
if (!list_empty(&inst->pendingq)) {
/*Execution can never reach here since port reconfig
@@ -2702,8 +2708,6 @@
}
}
- msm_comm_flush_dynamic_buffers(inst);
-
/*Do not send flush in case of session_error */
if (!(inst->state == MSM_VIDC_CORE_INVALID &&
core->state != VIDC_CORE_INVALID))
diff --git a/drivers/mfd/wcd9xxx-core.c b/drivers/mfd/wcd9xxx-core.c
index d8abc6d..907ce7c 100644
--- a/drivers/mfd/wcd9xxx-core.c
+++ b/drivers/mfd/wcd9xxx-core.c
@@ -544,8 +544,10 @@
{WCD9XXX_IRQ_PA2_STARTUP, false},
{WCD9XXX_IRQ_PA3_STARTUP, false},
{WCD9XXX_IRQ_PA4_STARTUP, false},
+ {WCD9306_IRQ_HPH_PA_OCPR_FAULT, false},
{WCD9XXX_IRQ_PA5_STARTUP, false},
{WCD9XXX_IRQ_MICBIAS1_PRECHARGE, false},
+ {WCD9306_IRQ_HPH_PA_OCPL_FAULT, false},
{WCD9XXX_IRQ_MICBIAS2_PRECHARGE, false},
{WCD9XXX_IRQ_MICBIAS3_PRECHARGE, false},
{WCD9XXX_IRQ_HPH_PA_OCPL_FAULT, false},
diff --git a/drivers/platform/msm/qpnp-power-on.c b/drivers/platform/msm/qpnp-power-on.c
index c0371a5..50d5f7b 100644
--- a/drivers/platform/msm/qpnp-power-on.c
+++ b/drivers/platform/msm/qpnp-power-on.c
@@ -107,6 +107,7 @@
u32 bark_irq;
u16 s2_cntl_addr;
u16 s2_cntl2_addr;
+ bool use_bark;
};
struct qpnp_pon {
@@ -614,7 +615,7 @@
cfg->state_irq);
return rc;
}
- if (cfg->support_reset) {
+ if (cfg->use_bark) {
rc = devm_request_irq(&pon->spmi->dev, cfg->bark_irq,
qpnp_kpdpwr_bark_irq,
IRQF_TRIGGER_RISING,
@@ -637,7 +638,7 @@
cfg->state_irq);
return rc;
}
- if (cfg->support_reset) {
+ if (cfg->use_bark) {
rc = devm_request_irq(&pon->spmi->dev, cfg->bark_irq,
qpnp_resin_bark_irq,
IRQF_TRIGGER_RISING,
@@ -662,7 +663,7 @@
}
break;
case PON_KPDPWR_RESIN:
- if (cfg->support_reset) {
+ if (cfg->use_bark) {
rc = devm_request_irq(&pon->spmi->dev, cfg->bark_irq,
qpnp_kpdpwr_resin_bark_irq,
IRQF_TRIGGER_RISING,
@@ -755,7 +756,9 @@
return rc;
}
- if (cfg->support_reset) {
+ cfg->use_bark = of_property_read_bool(pp,
+ "qcom,use-bark");
+ if (cfg->use_bark) {
cfg->bark_irq = spmi_get_irq_byname(pon->spmi,
NULL, "kpdpwr-bark");
if (cfg->bark_irq < 0) {
@@ -793,7 +796,9 @@
return rc;
}
- if (cfg->support_reset) {
+ cfg->use_bark = of_property_read_bool(pp,
+ "qcom,use-bark");
+ if (cfg->use_bark) {
cfg->bark_irq = spmi_get_irq_byname(pon->spmi,
NULL, "resin-bark");
if (cfg->bark_irq < 0) {
@@ -832,7 +837,9 @@
return rc;
}
- if (cfg->support_reset) {
+ cfg->use_bark = of_property_read_bool(pp,
+ "qcom,use-bark");
+ if (cfg->use_bark) {
cfg->bark_irq = spmi_get_irq_byname(pon->spmi,
NULL, "kpdpwr-resin-bark");
if (cfg->bark_irq < 0) {
diff --git a/drivers/video/msm/mdss/mdss_dsi.c b/drivers/video/msm/mdss/mdss_dsi.c
index c94db64..865775a 100644
--- a/drivers/video/msm/mdss/mdss_dsi.c
+++ b/drivers/video/msm/mdss/mdss_dsi.c
@@ -753,6 +753,7 @@
case MDSS_EVENT_DSI_CMDLIST_KOFF:
ctrl_pdata->recovery = (struct mdss_panel_recovery *)arg;
mdss_dsi_cmdlist_commit(ctrl_pdata, 1);
+ break;
case MDSS_EVENT_PANEL_UPDATE_FPS:
if (arg != NULL) {
rc = mdss_dsi_dfps_config(pdata, (int)arg);
diff --git a/drivers/video/msm/mdss/mdss_mdp_intf_video.c b/drivers/video/msm/mdss/mdss_mdp_intf_video.c
index 728269d..a040785 100644
--- a/drivers/video/msm/mdss/mdss_mdp_intf_video.c
+++ b/drivers/video/msm/mdss/mdss_mdp_intf_video.c
@@ -330,6 +330,7 @@
mdss_mdp_set_intr_callback(MDSS_MDP_IRQ_INTF_UNDER_RUN, ctl->intf_num,
NULL, NULL);
+ mdss_mdp_ctl_reset(ctl);
ctx->ref_cnt--;
ctl->priv_data = NULL;
diff --git a/drivers/video/msm/mdss/mdss_mdp_intf_writeback.c b/drivers/video/msm/mdss/mdss_mdp_intf_writeback.c
index 2b07428..7f872b4 100644
--- a/drivers/video/msm/mdss/mdss_mdp_intf_writeback.c
+++ b/drivers/video/msm/mdss/mdss_mdp_intf_writeback.c
@@ -283,9 +283,9 @@
ctx->rot90 = !!(rot->flags & MDP_ROT_90);
if (ctx->bwc_mode || ctx->rot90)
- format = mdss_mdp_get_rotator_dst_format(rot->format);
+ format = mdss_mdp_get_rotator_dst_format(rot->format, 1);
else
- format = rot->format;
+ format = mdss_mdp_get_rotator_dst_format(rot->format, 0);
if (ctx->rot90) {
ctx->opmode |= BIT(5); /* ROT 90 */
diff --git a/drivers/video/msm/mdss/mdss_mdp_overlay.c b/drivers/video/msm/mdss/mdss_mdp_overlay.c
index c2d9965..1584925 100644
--- a/drivers/video/msm/mdss/mdss_mdp_overlay.c
+++ b/drivers/video/msm/mdss/mdss_mdp_overlay.c
@@ -415,7 +415,7 @@
if (req->flags & (MDP_SOURCE_ROTATED_90 | MDP_BWC_EN))
req->src.format =
- mdss_mdp_get_rotator_dst_format(req->src.format);
+ mdss_mdp_get_rotator_dst_format(req->src.format, 1);
fmt = mdss_mdp_get_format_params(req->src.format);
if (!fmt) {
diff --git a/drivers/video/msm/mdss/mdss_mdp_rotator.h b/drivers/video/msm/mdss/mdss_mdp_rotator.h
index 43e77cc..ab7cce1 100644
--- a/drivers/video/msm/mdss/mdss_mdp_rotator.h
+++ b/drivers/video/msm/mdss/mdss_mdp_rotator.h
@@ -51,13 +51,21 @@
struct work_struct commit_work;
};
-static inline u32 mdss_mdp_get_rotator_dst_format(u32 in_format)
+static inline u32 mdss_mdp_get_rotator_dst_format(u32 in_format, u8 in_rot90)
{
switch (in_format) {
case MDP_RGB_565:
case MDP_BGR_565:
- return MDP_RGB_888;
+ if (in_rot90)
+ return MDP_RGB_888;
+ else
+ return in_format;
case MDP_Y_CBCR_H2V2_VENUS:
+ case MDP_Y_CBCR_H2V2:
+ if (in_rot90)
+ return MDP_Y_CRCB_H2V2;
+ else
+ return in_format;
case MDP_Y_CB_CR_H2V2:
case MDP_Y_CR_CB_GH2V2:
case MDP_Y_CR_CB_H2V2:
diff --git a/include/linux/mfd/wcd9xxx/core.h b/include/linux/mfd/wcd9xxx/core.h
index c2ad2b4..85be7c3 100644
--- a/include/linux/mfd/wcd9xxx/core.h
+++ b/include/linux/mfd/wcd9xxx/core.h
@@ -64,8 +64,10 @@
WCD9XXX_IRQ_PA2_STARTUP,
WCD9XXX_IRQ_PA3_STARTUP,
WCD9XXX_IRQ_PA4_STARTUP,
+ WCD9306_IRQ_HPH_PA_OCPR_FAULT = WCD9XXX_IRQ_PA4_STARTUP,
WCD9XXX_IRQ_PA5_STARTUP,
WCD9XXX_IRQ_MICBIAS1_PRECHARGE,
+ WCD9306_IRQ_HPH_PA_OCPL_FAULT = WCD9XXX_IRQ_MICBIAS1_PRECHARGE,
WCD9XXX_IRQ_MICBIAS2_PRECHARGE,
WCD9XXX_IRQ_MICBIAS3_PRECHARGE,
/* INTR_REG 2 */
diff --git a/sound/core/pcm_native.c b/sound/core/pcm_native.c
index 8bba8d7..7504576 100644
--- a/sound/core/pcm_native.c
+++ b/sound/core/pcm_native.c
@@ -448,7 +448,8 @@
runtime->silence_threshold = 0;
runtime->silence_size = 0;
runtime->boundary = runtime->buffer_size;
- while (runtime->boundary * 2 <= LONG_MAX - runtime->buffer_size)
+ while (runtime->boundary * 2 * runtime->channels <=
+ LONG_MAX - runtime->buffer_size)
runtime->boundary *= 2;
snd_pcm_timer_resolution_change(substream);
diff --git a/sound/soc/codecs/msm8x10-wcd.c b/sound/soc/codecs/msm8x10-wcd.c
index 4c20bb9..942d095 100644
--- a/sound/soc/codecs/msm8x10-wcd.c
+++ b/sound/soc/codecs/msm8x10-wcd.c
@@ -2612,12 +2612,6 @@
0xE0, 0xE0);
}
-static int msm8x10_wcd_get_jack_detect_irq(
- struct snd_soc_codec *codec)
-{
- return MSM8X10_WCD_IRQ_MBHC_HS_DET;
-}
-
static struct wcd9xxx_cfilt_mode msm8x10_wcd_switch_cfilt_mode(
struct wcd9xxx_mbhc *mbhc, bool fast)
{
@@ -2642,14 +2636,6 @@
mbhc->mbhc_bias_regs.ctl_reg, 0x60, 0x00);
}
-static void msm8x10_wcd_free_irq(struct wcd9xxx_mbhc *mbhc)
-{
- struct msm8x10_wcd *msm8x10_wcd = mbhc->codec->control_data;
- struct wcd9xxx_core_resource *core_res =
- &msm8x10_wcd->wcd9xxx_res;
- wcd9xxx_free_irq(core_res, MSM8X10_WCD_IRQ_MBHC_HS_DET, mbhc);
-}
-
enum wcd9xxx_cdc_type msm8x10_wcd_get_cdc_type(void)
{
return WCD9XXX_CDC_TYPE_HELICON;
@@ -2707,10 +2693,8 @@
.enable_mux_bias_block = msm8x10_wcd_enable_mux_bias_block,
.cfilt_fast_mode = msm8x10_wcd_put_cfilt_fast_mode,
.codec_specific_cal = msm8x10_wcd_codec_specific_cal_setup,
- .jack_detect_irq = msm8x10_wcd_get_jack_detect_irq,
.switch_cfilt_mode = msm8x10_wcd_switch_cfilt_mode,
.select_cfilt = msm8x10_wcd_select_cfilt,
- .free_irq = msm8x10_wcd_free_irq,
.get_cdc_type = msm8x10_wcd_get_cdc_type,
.enable_clock_gate = msm8x10_wcd_mbhc_clk_gate,
.enable_mbhc_txfe = msm8x10_wcd_mbhc_txfe,
@@ -2819,6 +2803,17 @@
.priority = -INT_MAX,
};
+static const struct wcd9xxx_mbhc_intr cdc_intr_ids = {
+ .poll_plug_rem = MSM8X10_WCD_IRQ_MBHC_REMOVAL,
+ .shortavg_complete = MSM8X10_WCD_IRQ_MBHC_SHORT_TERM,
+ .potential_button_press = MSM8X10_WCD_IRQ_MBHC_PRESS,
+ .button_release = MSM8X10_WCD_IRQ_MBHC_RELEASE,
+ .dce_est_complete = MSM8X10_WCD_IRQ_MBHC_POTENTIAL,
+ .insertion = MSM8X10_WCD_IRQ_MBHC_INSERTION,
+ .hph_left_ocp = MSM8X10_WCD_IRQ_HPH_PA_OCPL_FAULT,
+ .hph_right_ocp = MSM8X10_WCD_IRQ_HPH_PA_OCPR_FAULT,
+ .hs_jack_switch = MSM8X10_WCD_IRQ_MBHC_HS_DET,
+};
static int msm8x10_wcd_codec_probe(struct snd_soc_codec *codec)
{
@@ -2896,7 +2891,7 @@
ret = wcd9xxx_mbhc_init(&msm8x10_wcd_priv->mbhc,
&msm8x10_wcd_priv->resmgr,
- codec, NULL, &mbhc_cb,
+ codec, NULL, &mbhc_cb, &cdc_intr_ids,
HELICON_MCLK_CLK_9P6MHZ, false);
if (ret) {
pr_err("%s: Failed to initialize mbhc\n", __func__);
diff --git a/sound/soc/codecs/wcd9306.c b/sound/soc/codecs/wcd9306.c
index 17ed0d3..4857593 100644
--- a/sound/soc/codecs/wcd9306.c
+++ b/sound/soc/codecs/wcd9306.c
@@ -97,8 +97,6 @@
#define TAPAN_SLIM_IRQ_UNDERFLOW (1 << 1)
#define TAPAN_SLIM_IRQ_PORT_CLOSED (1 << 2)
-#define TAPAN_IRQ_MBHC_JACK_SWITCH 21
-
enum tapan_codec_type {
WCD9306,
WCD9302,
@@ -5086,11 +5084,6 @@
snd_soc_update_bits(codec, WCD9XXX_A_TX_7_MBHC_EN, 0xE0, 0xE0);
}
-static int tapan_get_jack_detect_irq(struct snd_soc_codec *codec)
-{
- return TAPAN_IRQ_MBHC_JACK_SWITCH;
-}
-
static struct wcd9xxx_cfilt_mode tapan_codec_switch_cfilt_mode(
struct wcd9xxx_mbhc *mbhc,
bool fast)
@@ -5116,14 +5109,6 @@
snd_soc_update_bits(codec, mbhc->mbhc_bias_regs.ctl_reg, 0x60, 0x00);
}
-static void tapan_free_irq(struct wcd9xxx_mbhc *mbhc)
-{
- struct wcd9xxx *wcd9xxx = mbhc->codec->control_data;
- struct wcd9xxx_core_resource *core_res =
- &wcd9xxx->core_res;
- wcd9xxx_free_irq(core_res, WCD9306_IRQ_MBHC_JACK_SWITCH, mbhc);
-}
-
enum wcd9xxx_cdc_type tapan_get_cdc_type(void)
{
return WCD9XXX_CDC_TYPE_TAPAN;
@@ -5382,10 +5367,8 @@
.enable_mux_bias_block = tapan_enable_mux_bias_block,
.cfilt_fast_mode = tapan_put_cfilt_fast_mode,
.codec_specific_cal = tapan_codec_specific_cal_setup,
- .jack_detect_irq = tapan_get_jack_detect_irq,
.switch_cfilt_mode = tapan_codec_switch_cfilt_mode,
.select_cfilt = tapan_select_cfilt,
- .free_irq = tapan_free_irq,
.get_cdc_type = tapan_get_cdc_type,
.setup_zdet = tapan_setup_zdet,
.compute_impedance = tapan_compute_impedance,
@@ -5426,6 +5409,18 @@
return 0;
}
+static const struct wcd9xxx_mbhc_intr cdc_intr_ids = {
+ .poll_plug_rem = WCD9XXX_IRQ_MBHC_REMOVAL,
+ .shortavg_complete = WCD9XXX_IRQ_MBHC_SHORT_TERM,
+ .potential_button_press = WCD9XXX_IRQ_MBHC_PRESS,
+ .button_release = WCD9XXX_IRQ_MBHC_RELEASE,
+ .dce_est_complete = WCD9XXX_IRQ_MBHC_POTENTIAL,
+ .insertion = WCD9XXX_IRQ_MBHC_INSERTION,
+ .hph_left_ocp = WCD9306_IRQ_HPH_PA_OCPL_FAULT,
+ .hph_right_ocp = WCD9306_IRQ_HPH_PA_OCPR_FAULT,
+ .hs_jack_switch = WCD9306_IRQ_MBHC_JACK_SWITCH,
+};
+
static int tapan_post_reset_cb(struct wcd9xxx *wcd9xxx)
{
int ret = 0;
@@ -5473,7 +5468,7 @@
rco_clk_rate = TAPAN_MCLK_CLK_9P6MHZ;
ret = wcd9xxx_mbhc_init(&tapan->mbhc, &tapan->resmgr, codec, NULL,
- &mbhc_cb, rco_clk_rate,
+ &mbhc_cb, &cdc_intr_ids, rco_clk_rate,
TAPAN_CDC_ZDET_SUPPORTED);
if (ret)
pr_err("%s: mbhc init failed %d\n", __func__, ret);
@@ -5679,7 +5674,7 @@
rco_clk_rate = TAPAN_MCLK_CLK_9P6MHZ;
ret = wcd9xxx_mbhc_init(&tapan->mbhc, &tapan->resmgr, codec, NULL,
- &mbhc_cb, rco_clk_rate,
+ &mbhc_cb, &cdc_intr_ids, rco_clk_rate,
TAPAN_CDC_ZDET_SUPPORTED);
if (ret) {
diff --git a/sound/soc/codecs/wcd9320.c b/sound/soc/codecs/wcd9320.c
index d2605cb..5656887 100644
--- a/sound/soc/codecs/wcd9320.c
+++ b/sound/soc/codecs/wcd9320.c
@@ -6491,6 +6491,18 @@
.compute_impedance = taiko_compute_impedance,
};
+static const struct wcd9xxx_mbhc_intr cdc_intr_ids = {
+ .poll_plug_rem = WCD9XXX_IRQ_MBHC_REMOVAL,
+ .shortavg_complete = WCD9XXX_IRQ_MBHC_SHORT_TERM,
+ .potential_button_press = WCD9XXX_IRQ_MBHC_PRESS,
+ .button_release = WCD9XXX_IRQ_MBHC_RELEASE,
+ .dce_est_complete = WCD9XXX_IRQ_MBHC_POTENTIAL,
+ .insertion = WCD9XXX_IRQ_MBHC_INSERTION,
+ .hph_left_ocp = WCD9XXX_IRQ_HPH_PA_OCPL_FAULT,
+ .hph_right_ocp = WCD9XXX_IRQ_HPH_PA_OCPR_FAULT,
+ .hs_jack_switch = WCD9320_IRQ_MBHC_JACK_SWITCH,
+};
+
static int taiko_post_reset_cb(struct wcd9xxx *wcd9xxx)
{
int ret = 0;
@@ -6536,7 +6548,8 @@
ret = wcd9xxx_mbhc_init(&taiko->mbhc, &taiko->resmgr, codec,
taiko_enable_mbhc_micbias,
- &mbhc_cb, rco_clk_rate, true);
+ &mbhc_cb, &cdc_intr_ids,
+ rco_clk_rate, true);
if (ret)
pr_err("%s: mbhc init failed %d\n", __func__, ret);
else
@@ -6725,7 +6738,8 @@
/* init and start mbhc */
ret = wcd9xxx_mbhc_init(&taiko->mbhc, &taiko->resmgr, codec,
taiko_enable_mbhc_micbias,
- &mbhc_cb, rco_clk_rate, true);
+ &mbhc_cb, &cdc_intr_ids,
+ rco_clk_rate, true);
if (ret) {
pr_err("%s: mbhc init failed %d\n", __func__, ret);
goto err_init;
diff --git a/sound/soc/codecs/wcd9xxx-mbhc.c b/sound/soc/codecs/wcd9xxx-mbhc.c
index 7b29a11..2ecebcd 100644
--- a/sound/soc/codecs/wcd9xxx-mbhc.c
+++ b/sound/soc/codecs/wcd9xxx-mbhc.c
@@ -118,8 +118,6 @@
/* RX_HPH_CNP_WG_TIME increases by 0.24ms */
#define WCD9XXX_WG_TIME_FACTOR_US 240
-#define WCD9XXX_IRQ_MBHC_JACK_SWITCH_DEFAULT 28
-
#define WCD9XXX_V_CS_HS_MAX 500
#define WCD9XXX_V_CS_NO_MIC 5
#define WCD9XXX_MB_MEAS_DELTA_MAX_MV 80
@@ -570,7 +568,7 @@
* reset retry counter as PA is turned off signifying
* start of new OCP detection session
*/
- if (WCD9XXX_IRQ_HPH_PA_OCPL_FAULT)
+ if (mbhc->intr_ids->hph_left_ocp)
mbhc->hphlocp_cnt = 0;
else
mbhc->hphrocp_cnt = 0;
@@ -581,13 +579,13 @@
static void hphrocp_off_report(struct wcd9xxx_mbhc *mbhc, u32 jack_status)
{
__hphocp_off_report(mbhc, SND_JACK_OC_HPHR,
- WCD9XXX_IRQ_HPH_PA_OCPR_FAULT);
+ mbhc->intr_ids->hph_right_ocp);
}
static void hphlocp_off_report(struct wcd9xxx_mbhc *mbhc, u32 jack_status)
{
__hphocp_off_report(mbhc, SND_JACK_OC_HPHL,
- WCD9XXX_IRQ_HPH_PA_OCPL_FAULT);
+ mbhc->intr_ids->hph_left_ocp);
}
static void wcd9xxx_get_mbhc_micbias_regs(struct wcd9xxx_mbhc *mbhc,
@@ -972,7 +970,8 @@
short bias_value;
struct snd_soc_codec *codec = mbhc->codec;
- wcd9xxx_disable_irq(mbhc->resmgr->core_res, WCD9XXX_IRQ_MBHC_POTENTIAL);
+ wcd9xxx_disable_irq(mbhc->resmgr->core_res,
+ mbhc->intr_ids->dce_est_complete);
if (noreldetection)
wcd9xxx_turn_onoff_rel_detection(codec, false);
@@ -1018,7 +1017,8 @@
if (noreldetection)
wcd9xxx_turn_onoff_rel_detection(codec, true);
- wcd9xxx_enable_irq(mbhc->resmgr->core_res, WCD9XXX_IRQ_MBHC_POTENTIAL);
+ wcd9xxx_enable_irq(mbhc->resmgr->core_res,
+ mbhc->intr_ids->dce_est_complete);
return bias_value;
}
@@ -1957,7 +1957,7 @@
snd_soc_update_bits(codec, mbhc->resmgr->reg_addr->micb_4_mbhc,
0x3, mbhc->mbhc_cfg->micbias);
- wcd9xxx_enable_irq(mbhc->resmgr->core_res, WCD9XXX_IRQ_MBHC_INSERTION);
+ wcd9xxx_enable_irq(mbhc->resmgr->core_res, mbhc->intr_ids->insertion);
snd_soc_update_bits(codec, WCD9XXX_A_CDC_MBHC_INT_CTL, 0x1, 0x1);
pr_debug("%s: leave\n", __func__);
@@ -2432,7 +2432,7 @@
pr_debug("%s: enter\n", __func__);
WCD9XXX_BCL_LOCK(mbhc->resmgr);
- wcd9xxx_disable_irq(mbhc->resmgr->core_res, WCD9XXX_IRQ_MBHC_INSERTION);
+ wcd9xxx_disable_irq(mbhc->resmgr->core_res, mbhc->intr_ids->insertion);
is_mb_trigger = !!(snd_soc_read(codec, mbhc->mbhc_bias_regs.mbhc_reg) &
0x10);
@@ -2499,7 +2499,7 @@
snd_soc_update_bits(codec, mbhc->mbhc_bias_regs.mbhc_reg, 0x90, 0x00);
snd_soc_update_bits(codec, WCD9XXX_A_MBHC_HPH, 0x13, 0x00);
snd_soc_update_bits(codec, mbhc->mbhc_bias_regs.ctl_reg, 0x01, 0x00);
- wcd9xxx_disable_irq_sync(core_res, WCD9XXX_IRQ_MBHC_INSERTION);
+ wcd9xxx_disable_irq_sync(core_res, mbhc->intr_ids->insertion);
wcd9xxx_mbhc_detect_plug_type(mbhc);
wcd9xxx_unlock_sleep(core_res);
}
@@ -3392,7 +3392,7 @@
0x10, 0x10);
} else {
wcd9xxx_disable_irq(mbhc->resmgr->core_res,
- WCD9XXX_IRQ_HPH_PA_OCPL_FAULT);
+ mbhc->intr_ids->hph_left_ocp);
mbhc->hph_status |= SND_JACK_OC_HPHL;
wcd9xxx_jack_report(mbhc, &mbhc->headset_jack,
mbhc->hph_status,
@@ -3422,7 +3422,7 @@
0x10);
} else {
wcd9xxx_disable_irq(mbhc->resmgr->core_res,
- WCD9XXX_IRQ_HPH_PA_OCPR_FAULT);
+ mbhc->intr_ids->hph_right_ocp);
mbhc->hph_status |= SND_JACK_OC_HPHR;
wcd9xxx_jack_report(mbhc, &mbhc->headset_jack,
mbhc->hph_status, WCD9XXX_JACK_MASK);
@@ -3502,7 +3502,8 @@
struct snd_soc_codec *codec = mbhc->codec;
pr_debug("%s: enter\n", __func__);
- wcd9xxx_disable_irq(mbhc->resmgr->core_res, WCD9XXX_IRQ_MBHC_POTENTIAL);
+ wcd9xxx_disable_irq(mbhc->resmgr->core_res,
+ mbhc->intr_ids->dce_est_complete);
wcd9xxx_turn_onoff_rel_detection(codec, false);
/* t_dce and t_sta are updated by wcd9xxx_update_mbhc_clk_rate() */
@@ -3642,7 +3643,8 @@
if (mbhc->mbhc_cb && mbhc->mbhc_cb->enable_mb_source)
mbhc->mbhc_cb->enable_mb_source(codec, false);
- wcd9xxx_enable_irq(mbhc->resmgr->core_res, WCD9XXX_IRQ_MBHC_POTENTIAL);
+ wcd9xxx_enable_irq(mbhc->resmgr->core_res,
+ mbhc->intr_ids->dce_est_complete);
wcd9xxx_turn_onoff_rel_detection(codec, true);
pr_debug("%s: leave\n", __func__);
@@ -3708,14 +3710,7 @@
static int wcd9xxx_setup_jack_detect_irq(struct wcd9xxx_mbhc *mbhc)
{
int ret = 0;
- struct snd_soc_codec *codec = mbhc->codec;
void *core_res = mbhc->resmgr->core_res;
- int jack_irq;
-
- if (mbhc->mbhc_cb && mbhc->mbhc_cb->jack_detect_irq)
- jack_irq = mbhc->mbhc_cb->jack_detect_irq(codec);
- else
- jack_irq = WCD9XXX_IRQ_MBHC_JACK_SWITCH_DEFAULT;
if (mbhc->mbhc_cfg->gpio) {
ret = request_threaded_irq(mbhc->mbhc_cfg->gpio_irq, NULL,
@@ -3738,13 +3733,14 @@
snd_soc_update_bits(mbhc->codec, WCD9XXX_A_RX_HPH_OCP_CTL,
1 << 1, 1 << 1);
- ret = wcd9xxx_request_irq(core_res, jack_irq,
+ ret = wcd9xxx_request_irq(core_res,
+ mbhc->intr_ids->hs_jack_switch,
wcd9xxx_mech_plug_detect_irq,
"Jack Detect",
mbhc);
if (ret)
pr_err("%s: Failed to request insert detect irq %d\n",
- __func__, jack_irq);
+ __func__, mbhc->intr_ids->hs_jack_switch);
}
return ret;
@@ -3774,9 +3770,9 @@
snd_soc_update_bits(codec, WCD9XXX_A_RX_HPH_OCP_CTL, 0x10,
0x10);
wcd9xxx_enable_irq(mbhc->resmgr->core_res,
- WCD9XXX_IRQ_HPH_PA_OCPL_FAULT);
+ mbhc->intr_ids->hph_left_ocp);
wcd9xxx_enable_irq(mbhc->resmgr->core_res,
- WCD9XXX_IRQ_HPH_PA_OCPR_FAULT);
+ mbhc->intr_ids->hph_right_ocp);
/* Initialize mechanical mbhc */
ret = wcd9xxx_setup_jack_detect_irq(mbhc);
@@ -4460,7 +4456,9 @@
int wcd9xxx_mbhc_init(struct wcd9xxx_mbhc *mbhc, struct wcd9xxx_resmgr *resmgr,
struct snd_soc_codec *codec,
int (*micbias_enable_cb) (struct snd_soc_codec*, bool),
- const struct wcd9xxx_mbhc_cb *mbhc_cb, int rco_clk_rate,
+ const struct wcd9xxx_mbhc_cb *mbhc_cb,
+ const struct wcd9xxx_mbhc_intr *mbhc_cdc_intr_ids,
+ int rco_clk_rate,
bool impedance_det_en)
{
int ret;
@@ -4487,9 +4485,15 @@
mbhc->micbias_enable_cb = micbias_enable_cb;
mbhc->rco_clk_rate = rco_clk_rate;
mbhc->mbhc_cb = mbhc_cb;
+ mbhc->intr_ids = mbhc_cdc_intr_ids;
mbhc->impedance_detect = impedance_det_en;
impedance_detect_en = impedance_det_en ? 1 : 0;
+ if (mbhc->intr_ids == NULL) {
+ pr_err("%s: Interrupt mapping not provided\n", __func__);
+ return -EINVAL;
+ }
+
if (mbhc->headset_jack.jack == NULL) {
ret = snd_soc_jack_new(codec, "Headset Jack", WCD9XXX_JACK_MASK,
&mbhc->headset_jack);
@@ -4533,62 +4537,62 @@
wcd9xxx_init_debugfs(mbhc);
core_res = mbhc->resmgr->core_res;
- ret = wcd9xxx_request_irq(core_res, WCD9XXX_IRQ_MBHC_INSERTION,
+ ret = wcd9xxx_request_irq(core_res, mbhc->intr_ids->insertion,
wcd9xxx_hs_insert_irq,
"Headset insert detect", mbhc);
if (ret) {
pr_err("%s: Failed to request irq %d, ret = %d\n", __func__,
- WCD9XXX_IRQ_MBHC_INSERTION, ret);
+ mbhc->intr_ids->insertion, ret);
goto err_insert_irq;
}
- wcd9xxx_disable_irq(core_res, WCD9XXX_IRQ_MBHC_INSERTION);
+ wcd9xxx_disable_irq(core_res, mbhc->intr_ids->insertion);
- ret = wcd9xxx_request_irq(core_res, WCD9XXX_IRQ_MBHC_REMOVAL,
+ ret = wcd9xxx_request_irq(core_res, mbhc->intr_ids->poll_plug_rem,
wcd9xxx_hs_remove_irq,
"Headset remove detect", mbhc);
if (ret) {
pr_err("%s: Failed to request irq %d\n", __func__,
- WCD9XXX_IRQ_MBHC_REMOVAL);
+ mbhc->intr_ids->poll_plug_rem);
goto err_remove_irq;
}
- ret = wcd9xxx_request_irq(core_res, WCD9XXX_IRQ_MBHC_POTENTIAL,
+ ret = wcd9xxx_request_irq(core_res, mbhc->intr_ids->dce_est_complete,
wcd9xxx_dce_handler, "DC Estimation detect",
mbhc);
if (ret) {
pr_err("%s: Failed to request irq %d\n", __func__,
- WCD9XXX_IRQ_MBHC_POTENTIAL);
+ mbhc->intr_ids->dce_est_complete);
goto err_potential_irq;
}
- ret = wcd9xxx_request_irq(core_res, WCD9XXX_IRQ_MBHC_RELEASE,
+ ret = wcd9xxx_request_irq(core_res, mbhc->intr_ids->button_release,
wcd9xxx_release_handler,
"Button Release detect", mbhc);
if (ret) {
pr_err("%s: Failed to request irq %d\n", __func__,
- WCD9XXX_IRQ_MBHC_RELEASE);
+ mbhc->intr_ids->button_release);
goto err_release_irq;
}
- ret = wcd9xxx_request_irq(core_res, WCD9XXX_IRQ_HPH_PA_OCPL_FAULT,
+ ret = wcd9xxx_request_irq(core_res, mbhc->intr_ids->hph_left_ocp,
wcd9xxx_hphl_ocp_irq, "HPH_L OCP detect",
mbhc);
if (ret) {
pr_err("%s: Failed to request irq %d\n", __func__,
- WCD9XXX_IRQ_HPH_PA_OCPL_FAULT);
+ mbhc->intr_ids->hph_left_ocp);
goto err_hphl_ocp_irq;
}
- wcd9xxx_disable_irq(core_res, WCD9XXX_IRQ_HPH_PA_OCPL_FAULT);
+ wcd9xxx_disable_irq(core_res, mbhc->intr_ids->hph_left_ocp);
- ret = wcd9xxx_request_irq(core_res, WCD9XXX_IRQ_HPH_PA_OCPR_FAULT,
+ ret = wcd9xxx_request_irq(core_res, mbhc->intr_ids->hph_right_ocp,
wcd9xxx_hphr_ocp_irq, "HPH_R OCP detect",
mbhc);
if (ret) {
pr_err("%s: Failed to request irq %d\n", __func__,
- WCD9XXX_IRQ_HPH_PA_OCPR_FAULT);
+ mbhc->intr_ids->hph_right_ocp);
goto err_hphr_ocp_irq;
}
- wcd9xxx_disable_irq(core_res, WCD9XXX_IRQ_HPH_PA_OCPR_FAULT);
+ wcd9xxx_disable_irq(core_res, mbhc->intr_ids->hph_right_ocp);
wcd9xxx_regmgr_cond_register(resmgr, 1 << WCD9XXX_COND_HPH_MIC |
1 << WCD9XXX_COND_HPH);
@@ -4597,15 +4601,15 @@
return ret;
err_hphr_ocp_irq:
- wcd9xxx_free_irq(core_res, WCD9XXX_IRQ_HPH_PA_OCPL_FAULT, mbhc);
+ wcd9xxx_free_irq(core_res, mbhc->intr_ids->hph_left_ocp, mbhc);
err_hphl_ocp_irq:
- wcd9xxx_free_irq(core_res, WCD9XXX_IRQ_MBHC_RELEASE, mbhc);
+ wcd9xxx_free_irq(core_res, mbhc->intr_ids->button_release, mbhc);
err_release_irq:
- wcd9xxx_free_irq(core_res, WCD9XXX_IRQ_MBHC_POTENTIAL, mbhc);
+ wcd9xxx_free_irq(core_res, mbhc->intr_ids->dce_est_complete, mbhc);
err_potential_irq:
- wcd9xxx_free_irq(core_res, WCD9XXX_IRQ_MBHC_REMOVAL, mbhc);
+ wcd9xxx_free_irq(core_res, mbhc->intr_ids->poll_plug_rem, mbhc);
err_remove_irq:
- wcd9xxx_free_irq(core_res, WCD9XXX_IRQ_MBHC_INSERTION, mbhc);
+ wcd9xxx_free_irq(core_res, mbhc->intr_ids->insertion, mbhc);
err_insert_irq:
wcd9xxx_resmgr_unregister_notifier(mbhc->resmgr, &mbhc->nblock);
@@ -4622,22 +4626,15 @@
wcd9xxx_regmgr_cond_deregister(mbhc->resmgr, 1 << WCD9XXX_COND_HPH_MIC |
1 << WCD9XXX_COND_HPH);
- wcd9xxx_free_irq(core_res, WCD9XXX_IRQ_MBHC_RELEASE, mbhc);
- wcd9xxx_free_irq(core_res, WCD9XXX_IRQ_MBHC_POTENTIAL, mbhc);
- wcd9xxx_free_irq(core_res, WCD9XXX_IRQ_MBHC_REMOVAL, mbhc);
- wcd9xxx_free_irq(core_res, WCD9XXX_IRQ_MBHC_INSERTION, mbhc);
-
- if (mbhc->mbhc_cb && mbhc->mbhc_cb->free_irq)
- mbhc->mbhc_cb->free_irq(mbhc);
- else
- wcd9xxx_free_irq(core_res, WCD9320_IRQ_MBHC_JACK_SWITCH,
- mbhc);
-
- wcd9xxx_free_irq(core_res, WCD9XXX_IRQ_HPH_PA_OCPL_FAULT, mbhc);
- wcd9xxx_free_irq(core_res, WCD9XXX_IRQ_HPH_PA_OCPR_FAULT, mbhc);
+ wcd9xxx_free_irq(core_res, mbhc->intr_ids->button_release, mbhc);
+ wcd9xxx_free_irq(core_res, mbhc->intr_ids->dce_est_complete, mbhc);
+ wcd9xxx_free_irq(core_res, mbhc->intr_ids->poll_plug_rem, mbhc);
+ wcd9xxx_free_irq(core_res, mbhc->intr_ids->insertion, mbhc);
+ wcd9xxx_free_irq(core_res, mbhc->intr_ids->hs_jack_switch, mbhc);
+ wcd9xxx_free_irq(core_res, mbhc->intr_ids->hph_left_ocp, mbhc);
+ wcd9xxx_free_irq(core_res, mbhc->intr_ids->hph_right_ocp, mbhc);
wcd9xxx_resmgr_unregister_notifier(mbhc->resmgr, &mbhc->nblock);
-
wcd9xxx_cleanup_debugfs(mbhc);
}
EXPORT_SYMBOL(wcd9xxx_mbhc_deinit);
diff --git a/sound/soc/codecs/wcd9xxx-mbhc.h b/sound/soc/codecs/wcd9xxx-mbhc.h
index 91280e4..9d0afe9 100644
--- a/sound/soc/codecs/wcd9xxx-mbhc.h
+++ b/sound/soc/codecs/wcd9xxx-mbhc.h
@@ -236,16 +236,26 @@
u8 reg_mask;
};
+struct wcd9xxx_mbhc_intr {
+ int poll_plug_rem;
+ int shortavg_complete;
+ int potential_button_press;
+ int button_release;
+ int dce_est_complete;
+ int insertion;
+ int hph_left_ocp;
+ int hph_right_ocp;
+ int hs_jack_switch;
+};
+
struct wcd9xxx_mbhc_cb {
void (*enable_mux_bias_block) (struct snd_soc_codec *);
void (*cfilt_fast_mode) (struct snd_soc_codec *, struct wcd9xxx_mbhc *);
void (*codec_specific_cal) (struct snd_soc_codec *,
struct wcd9xxx_mbhc *);
- int (*jack_detect_irq) (struct snd_soc_codec *);
struct wcd9xxx_cfilt_mode (*switch_cfilt_mode) (struct wcd9xxx_mbhc *,
bool);
void (*select_cfilt) (struct snd_soc_codec *, struct wcd9xxx_mbhc *);
- void (*free_irq) (struct wcd9xxx_mbhc *);
enum wcd9xxx_cdc_type (*get_cdc_type) (void);
void (*enable_clock_gate) (struct snd_soc_codec *, bool);
int (*setup_zdet) (struct wcd9xxx_mbhc *,
@@ -327,6 +337,9 @@
bool update_z;
+ /* Holds codec specific interrupt mapping */
+ const struct wcd9xxx_mbhc_intr *intr_ids;
+
#ifdef CONFIG_DEBUG_FS
struct dentry *debugfs_poke;
struct dentry *debugfs_mbhc;
@@ -395,6 +408,7 @@
struct snd_soc_codec *codec,
int (*micbias_enable_cb) (struct snd_soc_codec*, bool),
const struct wcd9xxx_mbhc_cb *mbhc_cb,
+ const struct wcd9xxx_mbhc_intr *mbhc_cdc_intr_ids,
int rco_clk_rate,
bool impedance_det_en);
void wcd9xxx_mbhc_deinit(struct wcd9xxx_mbhc *mbhc);
diff --git a/sound/soc/msm/msm-pcm-hostless.c b/sound/soc/msm/msm-pcm-hostless.c
index 789749f..0f3573b 100644
--- a/sound/soc/msm/msm-pcm-hostless.c
+++ b/sound/soc/msm/msm-pcm-hostless.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2011-2013, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -18,7 +18,21 @@
#include <sound/soc.h>
#include <sound/pcm.h>
-static struct snd_pcm_ops msm_pcm_hostless_ops = {};
+
+static int msm_pcm_hostless_prepare(struct snd_pcm_substream *substream)
+{
+ if (!substream) {
+ pr_err("%s: invalid params\n", __func__);
+ return -EINVAL;
+ }
+ if (pm_qos_request_active(&substream->latency_pm_qos_req))
+ pm_qos_remove_request(&substream->latency_pm_qos_req);
+ return 0;
+}
+
+static struct snd_pcm_ops msm_pcm_hostless_ops = {
+ .prepare = msm_pcm_hostless_prepare
+};
static struct snd_soc_platform_driver msm_soc_hostless_platform = {
.ops = &msm_pcm_hostless_ops,
diff --git a/sound/soc/msm/qdsp6/q6voice.c b/sound/soc/msm/qdsp6/q6voice.c
index 094c58b..d23eee1 100644
--- a/sound/soc/msm/qdsp6/q6voice.c
+++ b/sound/soc/msm/qdsp6/q6voice.c
@@ -1519,7 +1519,8 @@
/* get the cvs cal data */
get_all_vocstrm_cal(&cal_block);
- if (cal_block.cal_size == 0)
+ if (cal_block.cal_size == 0 ||
+ cal_block.cal_size > CVS_CAL_SIZE)
goto fail;
if (v == NULL) {
@@ -1594,7 +1595,8 @@
u16 cvs_handle;
get_all_vocstrm_cal(&cal_block);
- if (cal_block.cal_size == 0)
+ if (cal_block.cal_size == 0 ||
+ cal_block.cal_size > CVS_CAL_SIZE)
return 0;
if (v == NULL) {
@@ -1646,7 +1648,8 @@
struct acdb_cal_block cal_block;
/* get all cvp cal data */
get_all_cvp_cal(&cal_block);
- if (cal_block.cal_size == 0)
+ if (cal_block.cal_size == 0 ||
+ cal_block.cal_size > CVP_CAL_SIZE)
goto fail;
if (is_volte_session(v->session_id) ||
@@ -1787,7 +1790,8 @@
/* get all cvs cal data */
get_all_vocstrm_cal(&cal_block);
- if (cal_block.cal_size == 0)
+ if (cal_block.cal_size == 0 ||
+ cal_block.cal_size > CVS_CAL_SIZE)
goto fail;
if (v == NULL) {
@@ -1859,7 +1863,8 @@
uint32_t cal_paddr = 0;
get_all_vocstrm_cal(&cal_block);
- if (cal_block.cal_size == 0)
+ if (cal_block.cal_size == 0 ||
+ cal_block.cal_size > CVS_CAL_SIZE)
return 0;
if (v == NULL) {
@@ -1928,7 +1933,8 @@
/* get the cvp cal data */
get_all_vocproc_cal(&cal_block);
- if (cal_block.cal_size == 0)
+ if (cal_block.cal_size == 0 ||
+ cal_block.cal_size > CVP_CAL_SIZE)
goto fail;
if (v == NULL) {
@@ -2003,7 +2009,8 @@
u16 cvp_handle;
get_all_vocproc_cal(&cal_block);
- if (cal_block.cal_size == 0)
+ if (cal_block.cal_size == 0 ||
+ cal_block.cal_size > CVP_CAL_SIZE)
return 0;
if (v == NULL) {
@@ -2053,6 +2060,7 @@
struct cvp_register_vol_cal_table_cmd cvp_reg_cal_tbl_cmd;
struct acdb_cal_block vol_block;
struct acdb_cal_block voc_block;
+ struct acdb_cal_block cvp_block;
int ret = 0;
void *apr_cvp;
u16 cvp_handle;
@@ -2062,8 +2070,10 @@
/* get the cvp vol cal data */
get_all_vocvol_cal(&vol_block);
get_all_vocproc_cal(&voc_block);
+ get_all_cvp_cal(&cvp_block);
- if (vol_block.cal_size == 0)
+ if (vol_block.cal_size == 0 ||
+ cvp_block.cal_size > CVP_CAL_SIZE)
goto fail;
if (v == NULL) {
@@ -2135,12 +2145,16 @@
{
struct cvp_deregister_vol_cal_table_cmd cvp_dereg_cal_tbl_cmd;
struct acdb_cal_block cal_block;
+ struct acdb_cal_block voc_block;
int ret = 0;
void *apr_cvp;
u16 cvp_handle;
get_all_vocvol_cal(&cal_block);
- if (cal_block.cal_size == 0)
+ get_all_cvp_cal(&voc_block);
+
+ if (cal_block.cal_size == 0 ||
+ voc_block.cal_size > CVP_CAL_SIZE)
return 0;
if (v == NULL) {
diff --git a/sound/soc/msm/qdsp6v2/audio_acdb.c b/sound/soc/msm/qdsp6v2/audio_acdb.c
index 93defcd..01422cf 100644
--- a/sound/soc/msm/qdsp6v2/audio_acdb.c
+++ b/sound/soc/msm/qdsp6v2/audio_acdb.c
@@ -1508,7 +1508,7 @@
static int acdb_mmap(struct file *file, struct vm_area_struct *vma)
{
int result = 0;
- int size = vma->vm_end - vma->vm_start;
+ uint32_t size = vma->vm_end - vma->vm_start;
pr_debug("%s\n", __func__);
diff --git a/sound/soc/msm/qdsp6v2/q6voice.c b/sound/soc/msm/qdsp6v2/q6voice.c
index c16b14c..673ecff 100644
--- a/sound/soc/msm/qdsp6v2/q6voice.c
+++ b/sound/soc/msm/qdsp6v2/q6voice.c
@@ -1958,20 +1958,22 @@
if (!common.apr_q6_cvs) {
pr_err("%s: apr_cvs is NULL\n", __func__);
- ret = -EPERM;
+ ret = -EINVAL;
goto done;
}
if (!common.cal_mem_handle) {
pr_err("%s: Cal mem handle is NULL\n", __func__);
- ret = -EPERM;
+
+ ret = -EINVAL;
goto done;
}
get_vocstrm_cal(&cal_block);
if (cal_block.cal_size == 0) {
pr_err("%s: CVS cal size is 0\n", __func__);
- ret = -EPERM;
+
+ ret = -EINVAL;
goto done;
}
@@ -1992,6 +1994,15 @@
/* Get the column info corresponding to CVS cal from ACDB. */
get_voice_col_data(VOCSTRM_CAL, &cal_block);
+ if (cal_block.cal_size == 0 ||
+ cal_block.cal_size >
+ sizeof(cvs_reg_cal_cmd.cvs_cal_data.column_info)) {
+ pr_err("%s: Invalid VOCSTRM_CAL size %d\n",
+ __func__, cal_block.cal_size);
+
+ ret = -EINVAL;
+ goto done;
+ }
memcpy(&cvs_reg_cal_cmd.cvs_cal_data.column_info[0],
(void *) cal_block.cal_kvaddr,
cal_block.cal_size);
@@ -2238,20 +2249,22 @@
if (!common.apr_q6_cvp) {
pr_err("%s: apr_cvp is NULL\n", __func__);
- ret = -EPERM;
+ ret = -EINVAL;
goto done;
}
if (!common.cal_mem_handle) {
pr_err("%s: Cal mem handle is NULL\n", __func__);
- ret = -EPERM;
+
+ ret = -EINVAL;
goto done;
}
get_vocproc_cal(&cal_block);
if (cal_block.cal_size == 0) {
pr_err("%s: CVP cal size is 0\n", __func__);
- ret = -EPERM;
+
+ ret = -EINVAL;
goto done;
}
@@ -2272,6 +2285,16 @@
/* Get the column info corresponding to CVP cal from ACDB. */
get_voice_col_data(VOCPROC_CAL, &cal_block);
+ if (cal_block.cal_size == 0 ||
+ cal_block.cal_size >
+ sizeof(cvp_reg_cal_cmd.cvp_cal_data.column_info)) {
+ pr_err("%s: Invalid VOCPROC_CAL size %d\n",
+ __func__, cal_block.cal_size);
+
+ ret = -EINVAL;
+ goto done;
+ }
+
memcpy(&cvp_reg_cal_cmd.cvp_cal_data.column_info[0],
(void *) cal_block.cal_kvaddr,
cal_block.cal_size);
@@ -2378,20 +2401,22 @@
if (!common.apr_q6_cvp) {
pr_err("%s: apr_cvp is NULL\n", __func__);
- ret = -EPERM;
+ ret = -EINVAL;
goto done;
}
if (!common.cal_mem_handle) {
pr_err("%s: Cal mem handle is NULL\n", __func__);
- ret = -EPERM;
+
+ ret = -EINVAL;
goto done;
}
get_vocvol_cal(&cal_block);
if (cal_block.cal_size == 0) {
pr_err("%s: CVP vol cal size is 0\n", __func__);
- ret = -EPERM;
+
+ ret = -EINVAL;
goto done;
}
@@ -2414,6 +2439,16 @@
/* Get the column info corresponding to CVP volume cal from ACDB. */
get_voice_col_data(VOCVOL_CAL, &cal_block);
+ if (cal_block.cal_size == 0 ||
+ cal_block.cal_size >
+ sizeof(cvp_reg_vol_cal_cmd.cvp_vol_cal_data.column_info)) {
+ pr_err("%s: Invalid VOCVOL_CAL size %d\n",
+ __func__, cal_block.cal_size);
+
+ ret = -EINVAL;
+ goto done;
+ }
+
memcpy(&cvp_reg_vol_cal_cmd.cvp_vol_cal_data.column_info[0],
(void *) cal_block.cal_kvaddr,
cal_block.cal_size);