| commit | f213bb937e62614035131373019b89e2b42ecb81 | [log] [tgz] |
|---|---|---|
| author | Ashwin Chaugule <ashwinc@codeaurora.org> | Sat Nov 17 11:32:48 2012 -0500 |
| committer | Ashwin Chaugule <ashwinc@codeaurora.org> | Wed Nov 21 14:12:21 2012 -0500 |
| tree | eebde26fe839d2483bd65481e893799bfede1933 | |
| parent | 4822d74ddbca949520389d341a66e455613a6d06 [diff] |
msm: Perf: Add 9625 L1 PMU support Enable the L1 cache controller performance monitoring unit on the 9625, so that its counters can be controlled via the perfevents framework. Change-Id: I4f7f305a4fb119223494bd0c306e834742904286 Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>