| commit | e1aba3d9b510d34e8309669d811a6f01568858dc | [log] [tgz] |
|---|---|---|
| author | Stepan Moskovchenko <stepanm@codeaurora.org> | Thu Dec 06 18:40:25 2012 -0800 |
| committer | Stepan Moskovchenko <stepanm@codeaurora.org> | Thu Dec 13 12:27:33 2012 -0800 |
| tree | b111db024d4c79bca0782931f73782b86e94f70d | |
| parent | a35d152af82e33acda701966ed3e0cbf01c49006 [diff] |
msm: cache_erp: Handle recoverable L1 errors Some CPU designs may be able to recover from certain types of L1 instruction cache errors. Rather than panicing whenever any kind of L1 error is encountered, add an option to selectively panic on recoverable L1 errors. Change-Id: Id8beb0e58d41fa5319f4ca76c5f35e2162f8b704 Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>