mmc: msm_sdcc: use DATA_PEND bit for write operation
DATA_PEND bit (in MCI_DATA_CTL register) is designed to be used
with CMD24 (WRITE_SINGLE_BLOCK) and CMD25 (WRITE_MULTIPLE_BLOCK) to
automatically start the DPSM (Data Path State Machine) after a normal
(non-error) response is received for CMD24/CMD25. To use this feature,
MCI_DATA_CTL register should be written with the enable bit and the
pending bit asserted before ENABLE bit is set in MCI_CMD register.
As of now SDCC driver is not using the DATA_PEND bit for any of the
write commands which means for write operation, driver first sends the
write command to card and then waits for the CMD_RESPOND_END interrupt
and then configures ADM/BAM and DATA_CTL register (with ENABLE bit set)
in interrupt context.
Instead driver can configure the DPSM (have to set DATA_PEND bit as well)
before configuring CPSM (Command Path State Machine) to send write
commands. So basically this will be the configuration sequence if
we use DATA_PEND bit:
1. Configure ADM/BAM.
2. Configure DATA_CTL with both DATA_PEND and ENABLE bits set.
3. Configure MCI_CMD register for sending the write command.
All of the above configuration will now happen at the same time in thread
context. But note that as DATA_PEND bit only works with CMD24/CMD25
writes, so this change uses the DATA_PEND capability for only for
SD/MMC block write commands (CMD24/CMD25).
Change-Id: Ic1b8cbf625c08c3aec382c713d2e2b0acf3ca041
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
diff --git a/drivers/mmc/host/msm_sdcc.h b/drivers/mmc/host/msm_sdcc.h
index e29ed91..78c12c1 100644
--- a/drivers/mmc/host/msm_sdcc.h
+++ b/drivers/mmc/host/msm_sdcc.h
@@ -78,6 +78,7 @@
#define MCI_DPSM_DIRECTION (1 << 1)
#define MCI_DPSM_MODE (1 << 2)
#define MCI_DPSM_DMAENABLE (1 << 3)
+#define MCI_DATA_PEND (1 << 17)
#define MCI_AUTO_PROG_DONE (1 << 19)
#define MCI_RX_DATA_PEND (1 << 20)
@@ -294,6 +295,7 @@
int got_dataend;
int wait_for_auto_prog_done;
int got_auto_prog_done;
+ bool use_wr_data_pend;
int user_pages;
};