tree 9211554f0542ce636aa1f14ffe58cfa832efa04d
parent 93f5f7f1249e76a5e8afbdab53f90b10c41fdb61
author Zhenyu Wang <zhenyuw@linux.intel.com> 1282878537 +0800
committer Chris Wilson <chris@chris-wilson.co.uk> 1283854603 +0100

agp/intel: Fix cache control for Sandybridge

Sandybridge GTT has new cache control bits in PTE, which controls
graphics page cache in LLC or LLC/MLC, so we need to extend the mask
function to respect the new bits.

And set cache control to always LLC only by default on Gen6.

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Cc: stable@kernel.org
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>